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Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dma
[deliverable/linux.git] / drivers / infiniband / hw / mlx4 / qp.c
1 /*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/log2.h>
35 #include <linux/slab.h>
36 #include <linux/netdevice.h>
37
38 #include <rdma/ib_cache.h>
39 #include <rdma/ib_pack.h>
40 #include <rdma/ib_addr.h>
41
42 #include <linux/mlx4/qp.h>
43
44 #include "mlx4_ib.h"
45 #include "user.h"
46
47 enum {
48 MLX4_IB_ACK_REQ_FREQ = 8,
49 };
50
51 enum {
52 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
53 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
54 MLX4_IB_LINK_TYPE_IB = 0,
55 MLX4_IB_LINK_TYPE_ETH = 1
56 };
57
58 enum {
59 /*
60 * Largest possible UD header: send with GRH and immediate
61 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
62 * tag. (LRH would only use 8 bytes, so Ethernet is the
63 * biggest case)
64 */
65 MLX4_IB_UD_HEADER_SIZE = 82,
66 MLX4_IB_LSO_HEADER_SPARE = 128,
67 };
68
69 enum {
70 MLX4_IB_IBOE_ETHERTYPE = 0x8915
71 };
72
73 struct mlx4_ib_sqp {
74 struct mlx4_ib_qp qp;
75 int pkey_index;
76 u32 qkey;
77 u32 send_psn;
78 struct ib_ud_header ud_header;
79 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
80 };
81
82 enum {
83 MLX4_IB_MIN_SQ_STRIDE = 6,
84 MLX4_IB_CACHE_LINE_SIZE = 64,
85 };
86
87 enum {
88 MLX4_RAW_QP_MTU = 7,
89 MLX4_RAW_QP_MSGMAX = 31,
90 };
91
92 static const __be32 mlx4_ib_opcode[] = {
93 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
94 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
95 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
96 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
97 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
98 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
99 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
100 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
101 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
102 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
103 [IB_WR_FAST_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
104 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
105 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
106 };
107
108 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
109 {
110 return container_of(mqp, struct mlx4_ib_sqp, qp);
111 }
112
113 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
114 {
115 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
116 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
117 }
118
119 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
120 {
121 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
122 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
123 }
124
125 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
126 {
127 return mlx4_buf_offset(&qp->buf, offset);
128 }
129
130 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
131 {
132 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
133 }
134
135 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
136 {
137 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
138 }
139
140 /*
141 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
142 * first four bytes of every 64 byte chunk with
143 * 0x7FFFFFF | (invalid_ownership_value << 31).
144 *
145 * When the max work request size is less than or equal to the WQE
146 * basic block size, as an optimization, we can stamp all WQEs with
147 * 0xffffffff, and skip the very first chunk of each WQE.
148 */
149 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
150 {
151 __be32 *wqe;
152 int i;
153 int s;
154 int ind;
155 void *buf;
156 __be32 stamp;
157 struct mlx4_wqe_ctrl_seg *ctrl;
158
159 if (qp->sq_max_wqes_per_wr > 1) {
160 s = roundup(size, 1U << qp->sq.wqe_shift);
161 for (i = 0; i < s; i += 64) {
162 ind = (i >> qp->sq.wqe_shift) + n;
163 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
164 cpu_to_be32(0xffffffff);
165 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
166 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
167 *wqe = stamp;
168 }
169 } else {
170 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
171 s = (ctrl->fence_size & 0x3f) << 4;
172 for (i = 64; i < s; i += 64) {
173 wqe = buf + i;
174 *wqe = cpu_to_be32(0xffffffff);
175 }
176 }
177 }
178
179 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
180 {
181 struct mlx4_wqe_ctrl_seg *ctrl;
182 struct mlx4_wqe_inline_seg *inl;
183 void *wqe;
184 int s;
185
186 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
187 s = sizeof(struct mlx4_wqe_ctrl_seg);
188
189 if (qp->ibqp.qp_type == IB_QPT_UD) {
190 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
191 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
192 memset(dgram, 0, sizeof *dgram);
193 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
194 s += sizeof(struct mlx4_wqe_datagram_seg);
195 }
196
197 /* Pad the remainder of the WQE with an inline data segment. */
198 if (size > s) {
199 inl = wqe + s;
200 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
201 }
202 ctrl->srcrb_flags = 0;
203 ctrl->fence_size = size / 16;
204 /*
205 * Make sure descriptor is fully written before setting ownership bit
206 * (because HW can start executing as soon as we do).
207 */
208 wmb();
209
210 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
211 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
212
213 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
214 }
215
216 /* Post NOP WQE to prevent wrap-around in the middle of WR */
217 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
218 {
219 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
220 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
221 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
222 ind += s;
223 }
224 return ind;
225 }
226
227 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
228 {
229 struct ib_event event;
230 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
231
232 if (type == MLX4_EVENT_TYPE_PATH_MIG)
233 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
234
235 if (ibqp->event_handler) {
236 event.device = ibqp->device;
237 event.element.qp = ibqp;
238 switch (type) {
239 case MLX4_EVENT_TYPE_PATH_MIG:
240 event.event = IB_EVENT_PATH_MIG;
241 break;
242 case MLX4_EVENT_TYPE_COMM_EST:
243 event.event = IB_EVENT_COMM_EST;
244 break;
245 case MLX4_EVENT_TYPE_SQ_DRAINED:
246 event.event = IB_EVENT_SQ_DRAINED;
247 break;
248 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
249 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
250 break;
251 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
252 event.event = IB_EVENT_QP_FATAL;
253 break;
254 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
255 event.event = IB_EVENT_PATH_MIG_ERR;
256 break;
257 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
258 event.event = IB_EVENT_QP_REQ_ERR;
259 break;
260 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
261 event.event = IB_EVENT_QP_ACCESS_ERR;
262 break;
263 default:
264 pr_warn("Unexpected event type %d "
265 "on QP %06x\n", type, qp->qpn);
266 return;
267 }
268
269 ibqp->event_handler(&event, ibqp->qp_context);
270 }
271 }
272
273 static int send_wqe_overhead(enum ib_qp_type type, u32 flags)
274 {
275 /*
276 * UD WQEs must have a datagram segment.
277 * RC and UC WQEs might have a remote address segment.
278 * MLX WQEs need two extra inline data segments (for the UD
279 * header and space for the ICRC).
280 */
281 switch (type) {
282 case IB_QPT_UD:
283 return sizeof (struct mlx4_wqe_ctrl_seg) +
284 sizeof (struct mlx4_wqe_datagram_seg) +
285 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
286 case IB_QPT_UC:
287 return sizeof (struct mlx4_wqe_ctrl_seg) +
288 sizeof (struct mlx4_wqe_raddr_seg);
289 case IB_QPT_RC:
290 return sizeof (struct mlx4_wqe_ctrl_seg) +
291 sizeof (struct mlx4_wqe_atomic_seg) +
292 sizeof (struct mlx4_wqe_raddr_seg);
293 case IB_QPT_SMI:
294 case IB_QPT_GSI:
295 return sizeof (struct mlx4_wqe_ctrl_seg) +
296 ALIGN(MLX4_IB_UD_HEADER_SIZE +
297 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
298 MLX4_INLINE_ALIGN) *
299 sizeof (struct mlx4_wqe_inline_seg),
300 sizeof (struct mlx4_wqe_data_seg)) +
301 ALIGN(4 +
302 sizeof (struct mlx4_wqe_inline_seg),
303 sizeof (struct mlx4_wqe_data_seg));
304 default:
305 return sizeof (struct mlx4_wqe_ctrl_seg);
306 }
307 }
308
309 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
310 int is_user, int has_rq, struct mlx4_ib_qp *qp)
311 {
312 /* Sanity check RQ size before proceeding */
313 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
314 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
315 return -EINVAL;
316
317 if (!has_rq) {
318 if (cap->max_recv_wr)
319 return -EINVAL;
320
321 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
322 } else {
323 /* HW requires >= 1 RQ entry with >= 1 gather entry */
324 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
325 return -EINVAL;
326
327 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
328 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
329 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
330 }
331
332 /* leave userspace return values as they were, so as not to break ABI */
333 if (is_user) {
334 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
335 cap->max_recv_sge = qp->rq.max_gs;
336 } else {
337 cap->max_recv_wr = qp->rq.max_post =
338 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
339 cap->max_recv_sge = min(qp->rq.max_gs,
340 min(dev->dev->caps.max_sq_sg,
341 dev->dev->caps.max_rq_sg));
342 }
343
344 return 0;
345 }
346
347 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
348 enum ib_qp_type type, struct mlx4_ib_qp *qp)
349 {
350 int s;
351
352 /* Sanity check SQ size before proceeding */
353 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
354 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
355 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
356 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
357 return -EINVAL;
358
359 /*
360 * For MLX transport we need 2 extra S/G entries:
361 * one for the header and one for the checksum at the end
362 */
363 if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
364 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
365 return -EINVAL;
366
367 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
368 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
369 send_wqe_overhead(type, qp->flags);
370
371 if (s > dev->dev->caps.max_sq_desc_sz)
372 return -EINVAL;
373
374 /*
375 * Hermon supports shrinking WQEs, such that a single work
376 * request can include multiple units of 1 << wqe_shift. This
377 * way, work requests can differ in size, and do not have to
378 * be a power of 2 in size, saving memory and speeding up send
379 * WR posting. Unfortunately, if we do this then the
380 * wqe_index field in CQEs can't be used to look up the WR ID
381 * anymore, so we do this only if selective signaling is off.
382 *
383 * Further, on 32-bit platforms, we can't use vmap() to make
384 * the QP buffer virtually contiguous. Thus we have to use
385 * constant-sized WRs to make sure a WR is always fully within
386 * a single page-sized chunk.
387 *
388 * Finally, we use NOP work requests to pad the end of the
389 * work queue, to avoid wrap-around in the middle of WR. We
390 * set NEC bit to avoid getting completions with error for
391 * these NOP WRs, but since NEC is only supported starting
392 * with firmware 2.2.232, we use constant-sized WRs for older
393 * firmware.
394 *
395 * And, since MLX QPs only support SEND, we use constant-sized
396 * WRs in this case.
397 *
398 * We look for the smallest value of wqe_shift such that the
399 * resulting number of wqes does not exceed device
400 * capabilities.
401 *
402 * We set WQE size to at least 64 bytes, this way stamping
403 * invalidates each WQE.
404 */
405 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
406 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
407 type != IB_QPT_SMI && type != IB_QPT_GSI)
408 qp->sq.wqe_shift = ilog2(64);
409 else
410 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
411
412 for (;;) {
413 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
414
415 /*
416 * We need to leave 2 KB + 1 WR of headroom in the SQ to
417 * allow HW to prefetch.
418 */
419 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
420 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
421 qp->sq_max_wqes_per_wr +
422 qp->sq_spare_wqes);
423
424 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
425 break;
426
427 if (qp->sq_max_wqes_per_wr <= 1)
428 return -EINVAL;
429
430 ++qp->sq.wqe_shift;
431 }
432
433 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
434 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
435 send_wqe_overhead(type, qp->flags)) /
436 sizeof (struct mlx4_wqe_data_seg);
437
438 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
439 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
440 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
441 qp->rq.offset = 0;
442 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
443 } else {
444 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
445 qp->sq.offset = 0;
446 }
447
448 cap->max_send_wr = qp->sq.max_post =
449 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
450 cap->max_send_sge = min(qp->sq.max_gs,
451 min(dev->dev->caps.max_sq_sg,
452 dev->dev->caps.max_rq_sg));
453 /* We don't support inline sends for kernel QPs (yet) */
454 cap->max_inline_data = 0;
455
456 return 0;
457 }
458
459 static int set_user_sq_size(struct mlx4_ib_dev *dev,
460 struct mlx4_ib_qp *qp,
461 struct mlx4_ib_create_qp *ucmd)
462 {
463 /* Sanity check SQ size before proceeding */
464 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
465 ucmd->log_sq_stride >
466 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
467 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
468 return -EINVAL;
469
470 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
471 qp->sq.wqe_shift = ucmd->log_sq_stride;
472
473 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
474 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
475
476 return 0;
477 }
478
479 static int qp_has_rq(struct ib_qp_init_attr *attr)
480 {
481 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
482 return 0;
483
484 return !attr->srq;
485 }
486
487 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
488 struct ib_qp_init_attr *init_attr,
489 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
490 {
491 int qpn;
492 int err;
493
494 mutex_init(&qp->mutex);
495 spin_lock_init(&qp->sq.lock);
496 spin_lock_init(&qp->rq.lock);
497 INIT_LIST_HEAD(&qp->gid_list);
498
499 qp->state = IB_QPS_RESET;
500 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
501 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
502
503 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
504 if (err)
505 goto err;
506
507 if (pd->uobject) {
508 struct mlx4_ib_create_qp ucmd;
509
510 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
511 err = -EFAULT;
512 goto err;
513 }
514
515 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
516
517 err = set_user_sq_size(dev, qp, &ucmd);
518 if (err)
519 goto err;
520
521 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
522 qp->buf_size, 0, 0);
523 if (IS_ERR(qp->umem)) {
524 err = PTR_ERR(qp->umem);
525 goto err;
526 }
527
528 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
529 ilog2(qp->umem->page_size), &qp->mtt);
530 if (err)
531 goto err_buf;
532
533 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
534 if (err)
535 goto err_mtt;
536
537 if (qp_has_rq(init_attr)) {
538 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
539 ucmd.db_addr, &qp->db);
540 if (err)
541 goto err_mtt;
542 }
543 } else {
544 qp->sq_no_prefetch = 0;
545
546 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
547 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
548
549 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
550 qp->flags |= MLX4_IB_QP_LSO;
551
552 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
553 if (err)
554 goto err;
555
556 if (qp_has_rq(init_attr)) {
557 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
558 if (err)
559 goto err;
560
561 *qp->db.db = 0;
562 }
563
564 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
565 err = -ENOMEM;
566 goto err_db;
567 }
568
569 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
570 &qp->mtt);
571 if (err)
572 goto err_buf;
573
574 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
575 if (err)
576 goto err_mtt;
577
578 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
579 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
580
581 if (!qp->sq.wrid || !qp->rq.wrid) {
582 err = -ENOMEM;
583 goto err_wrid;
584 }
585 }
586
587 if (sqpn) {
588 qpn = sqpn;
589 } else {
590 /* Raw packet QPNs must be aligned to 8 bits. If not, the WQE
591 * BlueFlame setup flow wrongly causes VLAN insertion. */
592 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
593 err = mlx4_qp_reserve_range(dev->dev, 1, 1 << 8, &qpn);
594 else
595 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn);
596 if (err)
597 goto err_wrid;
598 }
599
600 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
601 if (err)
602 goto err_qpn;
603
604 if (init_attr->qp_type == IB_QPT_XRC_TGT)
605 qp->mqp.qpn |= (1 << 23);
606
607 /*
608 * Hardware wants QPN written in big-endian order (after
609 * shifting) for send doorbell. Precompute this value to save
610 * a little bit when posting sends.
611 */
612 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
613
614 qp->mqp.event = mlx4_ib_qp_event;
615
616 return 0;
617
618 err_qpn:
619 if (!sqpn)
620 mlx4_qp_release_range(dev->dev, qpn, 1);
621
622 err_wrid:
623 if (pd->uobject) {
624 if (qp_has_rq(init_attr))
625 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
626 } else {
627 kfree(qp->sq.wrid);
628 kfree(qp->rq.wrid);
629 }
630
631 err_mtt:
632 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
633
634 err_buf:
635 if (pd->uobject)
636 ib_umem_release(qp->umem);
637 else
638 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
639
640 err_db:
641 if (!pd->uobject && qp_has_rq(init_attr))
642 mlx4_db_free(dev->dev, &qp->db);
643
644 err:
645 return err;
646 }
647
648 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
649 {
650 switch (state) {
651 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
652 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
653 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
654 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
655 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
656 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
657 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
658 default: return -1;
659 }
660 }
661
662 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
663 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
664 {
665 if (send_cq == recv_cq) {
666 spin_lock_irq(&send_cq->lock);
667 __acquire(&recv_cq->lock);
668 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
669 spin_lock_irq(&send_cq->lock);
670 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
671 } else {
672 spin_lock_irq(&recv_cq->lock);
673 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
674 }
675 }
676
677 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
678 __releases(&send_cq->lock) __releases(&recv_cq->lock)
679 {
680 if (send_cq == recv_cq) {
681 __release(&recv_cq->lock);
682 spin_unlock_irq(&send_cq->lock);
683 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
684 spin_unlock(&recv_cq->lock);
685 spin_unlock_irq(&send_cq->lock);
686 } else {
687 spin_unlock(&send_cq->lock);
688 spin_unlock_irq(&recv_cq->lock);
689 }
690 }
691
692 static void del_gid_entries(struct mlx4_ib_qp *qp)
693 {
694 struct mlx4_ib_gid_entry *ge, *tmp;
695
696 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
697 list_del(&ge->list);
698 kfree(ge);
699 }
700 }
701
702 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
703 {
704 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
705 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
706 else
707 return to_mpd(qp->ibqp.pd);
708 }
709
710 static void get_cqs(struct mlx4_ib_qp *qp,
711 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
712 {
713 switch (qp->ibqp.qp_type) {
714 case IB_QPT_XRC_TGT:
715 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
716 *recv_cq = *send_cq;
717 break;
718 case IB_QPT_XRC_INI:
719 *send_cq = to_mcq(qp->ibqp.send_cq);
720 *recv_cq = *send_cq;
721 break;
722 default:
723 *send_cq = to_mcq(qp->ibqp.send_cq);
724 *recv_cq = to_mcq(qp->ibqp.recv_cq);
725 break;
726 }
727 }
728
729 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
730 int is_user)
731 {
732 struct mlx4_ib_cq *send_cq, *recv_cq;
733
734 if (qp->state != IB_QPS_RESET)
735 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
736 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
737 pr_warn("modify QP %06x to RESET failed.\n",
738 qp->mqp.qpn);
739
740 get_cqs(qp, &send_cq, &recv_cq);
741
742 mlx4_ib_lock_cqs(send_cq, recv_cq);
743
744 if (!is_user) {
745 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
746 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
747 if (send_cq != recv_cq)
748 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
749 }
750
751 mlx4_qp_remove(dev->dev, &qp->mqp);
752
753 mlx4_ib_unlock_cqs(send_cq, recv_cq);
754
755 mlx4_qp_free(dev->dev, &qp->mqp);
756
757 if (!is_sqp(dev, qp))
758 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
759
760 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
761
762 if (is_user) {
763 if (qp->rq.wqe_cnt)
764 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
765 &qp->db);
766 ib_umem_release(qp->umem);
767 } else {
768 kfree(qp->sq.wrid);
769 kfree(qp->rq.wrid);
770 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
771 if (qp->rq.wqe_cnt)
772 mlx4_db_free(dev->dev, &qp->db);
773 }
774
775 del_gid_entries(qp);
776 }
777
778 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
779 struct ib_qp_init_attr *init_attr,
780 struct ib_udata *udata)
781 {
782 struct mlx4_ib_sqp *sqp;
783 struct mlx4_ib_qp *qp;
784 int err;
785 u16 xrcdn = 0;
786
787 /*
788 * We only support LSO and multicast loopback blocking, and
789 * only for kernel UD QPs.
790 */
791 if (init_attr->create_flags & ~(IB_QP_CREATE_IPOIB_UD_LSO |
792 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
793 return ERR_PTR(-EINVAL);
794
795 if (init_attr->create_flags &&
796 (udata || init_attr->qp_type != IB_QPT_UD))
797 return ERR_PTR(-EINVAL);
798
799 switch (init_attr->qp_type) {
800 case IB_QPT_XRC_TGT:
801 pd = to_mxrcd(init_attr->xrcd)->pd;
802 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
803 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
804 /* fall through */
805 case IB_QPT_XRC_INI:
806 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
807 return ERR_PTR(-ENOSYS);
808 init_attr->recv_cq = init_attr->send_cq;
809 /* fall through */
810 case IB_QPT_RC:
811 case IB_QPT_UC:
812 case IB_QPT_UD:
813 case IB_QPT_RAW_PACKET:
814 {
815 qp = kzalloc(sizeof *qp, GFP_KERNEL);
816 if (!qp)
817 return ERR_PTR(-ENOMEM);
818
819 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata, 0, qp);
820 if (err) {
821 kfree(qp);
822 return ERR_PTR(err);
823 }
824
825 qp->ibqp.qp_num = qp->mqp.qpn;
826 qp->xrcdn = xrcdn;
827
828 break;
829 }
830 case IB_QPT_SMI:
831 case IB_QPT_GSI:
832 {
833 /* Userspace is not allowed to create special QPs: */
834 if (udata)
835 return ERR_PTR(-EINVAL);
836
837 sqp = kzalloc(sizeof *sqp, GFP_KERNEL);
838 if (!sqp)
839 return ERR_PTR(-ENOMEM);
840
841 qp = &sqp->qp;
842
843 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
844 to_mdev(pd->device)->dev->caps.sqp_start +
845 (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
846 init_attr->port_num - 1,
847 qp);
848 if (err) {
849 kfree(sqp);
850 return ERR_PTR(err);
851 }
852
853 qp->port = init_attr->port_num;
854 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
855
856 break;
857 }
858 default:
859 /* Don't support raw QPs */
860 return ERR_PTR(-EINVAL);
861 }
862
863 return &qp->ibqp;
864 }
865
866 int mlx4_ib_destroy_qp(struct ib_qp *qp)
867 {
868 struct mlx4_ib_dev *dev = to_mdev(qp->device);
869 struct mlx4_ib_qp *mqp = to_mqp(qp);
870 struct mlx4_ib_pd *pd;
871
872 if (is_qp0(dev, mqp))
873 mlx4_CLOSE_PORT(dev->dev, mqp->port);
874
875 pd = get_pd(mqp);
876 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
877
878 if (is_sqp(dev, mqp))
879 kfree(to_msqp(mqp));
880 else
881 kfree(mqp);
882
883 return 0;
884 }
885
886 static int to_mlx4_st(enum ib_qp_type type)
887 {
888 switch (type) {
889 case IB_QPT_RC: return MLX4_QP_ST_RC;
890 case IB_QPT_UC: return MLX4_QP_ST_UC;
891 case IB_QPT_UD: return MLX4_QP_ST_UD;
892 case IB_QPT_XRC_INI:
893 case IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
894 case IB_QPT_SMI:
895 case IB_QPT_GSI:
896 case IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
897 default: return -1;
898 }
899 }
900
901 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
902 int attr_mask)
903 {
904 u8 dest_rd_atomic;
905 u32 access_flags;
906 u32 hw_access_flags = 0;
907
908 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
909 dest_rd_atomic = attr->max_dest_rd_atomic;
910 else
911 dest_rd_atomic = qp->resp_depth;
912
913 if (attr_mask & IB_QP_ACCESS_FLAGS)
914 access_flags = attr->qp_access_flags;
915 else
916 access_flags = qp->atomic_rd_en;
917
918 if (!dest_rd_atomic)
919 access_flags &= IB_ACCESS_REMOTE_WRITE;
920
921 if (access_flags & IB_ACCESS_REMOTE_READ)
922 hw_access_flags |= MLX4_QP_BIT_RRE;
923 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
924 hw_access_flags |= MLX4_QP_BIT_RAE;
925 if (access_flags & IB_ACCESS_REMOTE_WRITE)
926 hw_access_flags |= MLX4_QP_BIT_RWE;
927
928 return cpu_to_be32(hw_access_flags);
929 }
930
931 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
932 int attr_mask)
933 {
934 if (attr_mask & IB_QP_PKEY_INDEX)
935 sqp->pkey_index = attr->pkey_index;
936 if (attr_mask & IB_QP_QKEY)
937 sqp->qkey = attr->qkey;
938 if (attr_mask & IB_QP_SQ_PSN)
939 sqp->send_psn = attr->sq_psn;
940 }
941
942 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
943 {
944 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
945 }
946
947 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
948 struct mlx4_qp_path *path, u8 port)
949 {
950 int err;
951 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
952 IB_LINK_LAYER_ETHERNET;
953 u8 mac[6];
954 int is_mcast;
955 u16 vlan_tag;
956 int vidx;
957
958 path->grh_mylmc = ah->src_path_bits & 0x7f;
959 path->rlid = cpu_to_be16(ah->dlid);
960 if (ah->static_rate) {
961 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
962 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
963 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
964 --path->static_rate;
965 } else
966 path->static_rate = 0;
967
968 if (ah->ah_flags & IB_AH_GRH) {
969 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
970 pr_err("sgid_index (%u) too large. max is %d\n",
971 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
972 return -1;
973 }
974
975 path->grh_mylmc |= 1 << 7;
976 path->mgid_index = ah->grh.sgid_index;
977 path->hop_limit = ah->grh.hop_limit;
978 path->tclass_flowlabel =
979 cpu_to_be32((ah->grh.traffic_class << 20) |
980 (ah->grh.flow_label));
981 memcpy(path->rgid, ah->grh.dgid.raw, 16);
982 }
983
984 if (is_eth) {
985 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
986 ((port - 1) << 6) | ((ah->sl & 7) << 3);
987
988 if (!(ah->ah_flags & IB_AH_GRH))
989 return -1;
990
991 err = mlx4_ib_resolve_grh(dev, ah, mac, &is_mcast, port);
992 if (err)
993 return err;
994
995 memcpy(path->dmac, mac, 6);
996 path->ackto = MLX4_IB_LINK_TYPE_ETH;
997 /* use index 0 into MAC table for IBoE */
998 path->grh_mylmc &= 0x80;
999
1000 vlan_tag = rdma_get_vlan_id(&dev->iboe.gid_table[port - 1][ah->grh.sgid_index]);
1001 if (vlan_tag < 0x1000) {
1002 if (mlx4_find_cached_vlan(dev->dev, port, vlan_tag, &vidx))
1003 return -ENOENT;
1004
1005 path->vlan_index = vidx;
1006 path->fl = 1 << 6;
1007 }
1008 } else
1009 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1010 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1011
1012 return 0;
1013 }
1014
1015 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1016 {
1017 struct mlx4_ib_gid_entry *ge, *tmp;
1018
1019 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1020 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1021 ge->added = 1;
1022 ge->port = qp->port;
1023 }
1024 }
1025 }
1026
1027 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1028 const struct ib_qp_attr *attr, int attr_mask,
1029 enum ib_qp_state cur_state, enum ib_qp_state new_state)
1030 {
1031 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1032 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1033 struct mlx4_ib_pd *pd;
1034 struct mlx4_ib_cq *send_cq, *recv_cq;
1035 struct mlx4_qp_context *context;
1036 enum mlx4_qp_optpar optpar = 0;
1037 int sqd_event;
1038 int err = -EINVAL;
1039
1040 context = kzalloc(sizeof *context, GFP_KERNEL);
1041 if (!context)
1042 return -ENOMEM;
1043
1044 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1045 (to_mlx4_st(ibqp->qp_type) << 16));
1046
1047 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1048 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1049 else {
1050 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1051 switch (attr->path_mig_state) {
1052 case IB_MIG_MIGRATED:
1053 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1054 break;
1055 case IB_MIG_REARM:
1056 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1057 break;
1058 case IB_MIG_ARMED:
1059 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1060 break;
1061 }
1062 }
1063
1064 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1065 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1066 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1067 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1068 else if (ibqp->qp_type == IB_QPT_UD) {
1069 if (qp->flags & MLX4_IB_QP_LSO)
1070 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1071 ilog2(dev->dev->caps.max_gso_sz);
1072 else
1073 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1074 } else if (attr_mask & IB_QP_PATH_MTU) {
1075 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1076 pr_err("path MTU (%u) is invalid\n",
1077 attr->path_mtu);
1078 goto out;
1079 }
1080 context->mtu_msgmax = (attr->path_mtu << 5) |
1081 ilog2(dev->dev->caps.max_msg_sz);
1082 }
1083
1084 if (qp->rq.wqe_cnt)
1085 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1086 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1087
1088 if (qp->sq.wqe_cnt)
1089 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1090 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1091
1092 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1093 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1094 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1095 }
1096
1097 if (qp->ibqp.uobject)
1098 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1099 else
1100 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1101
1102 if (attr_mask & IB_QP_DEST_QPN)
1103 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1104
1105 if (attr_mask & IB_QP_PORT) {
1106 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1107 !(attr_mask & IB_QP_AV)) {
1108 mlx4_set_sched(&context->pri_path, attr->port_num);
1109 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1110 }
1111 }
1112
1113 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1114 if (dev->counters[qp->port - 1] != -1) {
1115 context->pri_path.counter_index =
1116 dev->counters[qp->port - 1];
1117 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1118 } else
1119 context->pri_path.counter_index = 0xff;
1120 }
1121
1122 if (attr_mask & IB_QP_PKEY_INDEX) {
1123 context->pri_path.pkey_index = attr->pkey_index;
1124 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1125 }
1126
1127 if (attr_mask & IB_QP_AV) {
1128 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
1129 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
1130 goto out;
1131
1132 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1133 MLX4_QP_OPTPAR_SCHED_QUEUE);
1134 }
1135
1136 if (attr_mask & IB_QP_TIMEOUT) {
1137 context->pri_path.ackto |= attr->timeout << 3;
1138 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1139 }
1140
1141 if (attr_mask & IB_QP_ALT_PATH) {
1142 if (attr->alt_port_num == 0 ||
1143 attr->alt_port_num > dev->dev->caps.num_ports)
1144 goto out;
1145
1146 if (attr->alt_pkey_index >=
1147 dev->dev->caps.pkey_table_len[attr->alt_port_num])
1148 goto out;
1149
1150 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1151 attr->alt_port_num))
1152 goto out;
1153
1154 context->alt_path.pkey_index = attr->alt_pkey_index;
1155 context->alt_path.ackto = attr->alt_timeout << 3;
1156 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1157 }
1158
1159 pd = get_pd(qp);
1160 get_cqs(qp, &send_cq, &recv_cq);
1161 context->pd = cpu_to_be32(pd->pdn);
1162 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1163 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1164 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1165
1166 /* Set "fast registration enabled" for all kernel QPs */
1167 if (!qp->ibqp.uobject)
1168 context->params1 |= cpu_to_be32(1 << 11);
1169
1170 if (attr_mask & IB_QP_RNR_RETRY) {
1171 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1172 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1173 }
1174
1175 if (attr_mask & IB_QP_RETRY_CNT) {
1176 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1177 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1178 }
1179
1180 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1181 if (attr->max_rd_atomic)
1182 context->params1 |=
1183 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1184 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1185 }
1186
1187 if (attr_mask & IB_QP_SQ_PSN)
1188 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1189
1190 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1191 if (attr->max_dest_rd_atomic)
1192 context->params2 |=
1193 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1194 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1195 }
1196
1197 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1198 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1199 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1200 }
1201
1202 if (ibqp->srq)
1203 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1204
1205 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1206 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1207 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1208 }
1209 if (attr_mask & IB_QP_RQ_PSN)
1210 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1211
1212 if (attr_mask & IB_QP_QKEY) {
1213 context->qkey = cpu_to_be32(attr->qkey);
1214 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1215 }
1216
1217 if (ibqp->srq)
1218 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1219
1220 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1221 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1222
1223 if (cur_state == IB_QPS_INIT &&
1224 new_state == IB_QPS_RTR &&
1225 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1226 ibqp->qp_type == IB_QPT_UD ||
1227 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1228 context->pri_path.sched_queue = (qp->port - 1) << 6;
1229 if (is_qp0(dev, qp))
1230 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1231 else
1232 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1233 }
1234
1235 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1236 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1237 sqd_event = 1;
1238 else
1239 sqd_event = 0;
1240
1241 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1242 context->rlkey |= (1 << 4);
1243
1244 /*
1245 * Before passing a kernel QP to the HW, make sure that the
1246 * ownership bits of the send queue are set and the SQ
1247 * headroom is stamped so that the hardware doesn't start
1248 * processing stale work requests.
1249 */
1250 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1251 struct mlx4_wqe_ctrl_seg *ctrl;
1252 int i;
1253
1254 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1255 ctrl = get_send_wqe(qp, i);
1256 ctrl->owner_opcode = cpu_to_be32(1 << 31);
1257 if (qp->sq_max_wqes_per_wr == 1)
1258 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1259
1260 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1261 }
1262 }
1263
1264 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1265 to_mlx4_state(new_state), context, optpar,
1266 sqd_event, &qp->mqp);
1267 if (err)
1268 goto out;
1269
1270 qp->state = new_state;
1271
1272 if (attr_mask & IB_QP_ACCESS_FLAGS)
1273 qp->atomic_rd_en = attr->qp_access_flags;
1274 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1275 qp->resp_depth = attr->max_dest_rd_atomic;
1276 if (attr_mask & IB_QP_PORT) {
1277 qp->port = attr->port_num;
1278 update_mcg_macs(dev, qp);
1279 }
1280 if (attr_mask & IB_QP_ALT_PATH)
1281 qp->alt_port = attr->alt_port_num;
1282
1283 if (is_sqp(dev, qp))
1284 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1285
1286 /*
1287 * If we moved QP0 to RTR, bring the IB link up; if we moved
1288 * QP0 to RESET or ERROR, bring the link back down.
1289 */
1290 if (is_qp0(dev, qp)) {
1291 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1292 if (mlx4_INIT_PORT(dev->dev, qp->port))
1293 pr_warn("INIT_PORT failed for port %d\n",
1294 qp->port);
1295
1296 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1297 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1298 mlx4_CLOSE_PORT(dev->dev, qp->port);
1299 }
1300
1301 /*
1302 * If we moved a kernel QP to RESET, clean up all old CQ
1303 * entries and reinitialize the QP.
1304 */
1305 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1306 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1307 ibqp->srq ? to_msrq(ibqp->srq): NULL);
1308 if (send_cq != recv_cq)
1309 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1310
1311 qp->rq.head = 0;
1312 qp->rq.tail = 0;
1313 qp->sq.head = 0;
1314 qp->sq.tail = 0;
1315 qp->sq_next_wqe = 0;
1316 if (qp->rq.wqe_cnt)
1317 *qp->db.db = 0;
1318 }
1319
1320 out:
1321 kfree(context);
1322 return err;
1323 }
1324
1325 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1326 int attr_mask, struct ib_udata *udata)
1327 {
1328 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1329 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1330 enum ib_qp_state cur_state, new_state;
1331 int err = -EINVAL;
1332
1333 mutex_lock(&qp->mutex);
1334
1335 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1336 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1337
1338 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1339 goto out;
1340
1341 if ((attr_mask & IB_QP_PORT) &&
1342 (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1343 goto out;
1344 }
1345
1346 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1347 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1348 IB_LINK_LAYER_ETHERNET))
1349 goto out;
1350
1351 if (attr_mask & IB_QP_PKEY_INDEX) {
1352 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1353 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1354 goto out;
1355 }
1356
1357 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1358 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1359 goto out;
1360 }
1361
1362 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1363 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1364 goto out;
1365 }
1366
1367 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1368 err = 0;
1369 goto out;
1370 }
1371
1372 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1373
1374 out:
1375 mutex_unlock(&qp->mutex);
1376 return err;
1377 }
1378
1379 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1380 void *wqe, unsigned *mlx_seg_len)
1381 {
1382 struct ib_device *ib_dev = sqp->qp.ibqp.device;
1383 struct mlx4_wqe_mlx_seg *mlx = wqe;
1384 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1385 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1386 union ib_gid sgid;
1387 u16 pkey;
1388 int send_size;
1389 int header_size;
1390 int spc;
1391 int i;
1392 int is_eth;
1393 int is_vlan = 0;
1394 int is_grh;
1395 u16 vlan;
1396
1397 send_size = 0;
1398 for (i = 0; i < wr->num_sge; ++i)
1399 send_size += wr->sg_list[i].length;
1400
1401 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
1402 is_grh = mlx4_ib_ah_grh_present(ah);
1403 if (is_eth) {
1404 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.ib.port_pd) >> 24,
1405 ah->av.ib.gid_index, &sgid);
1406 vlan = rdma_get_vlan_id(&sgid);
1407 is_vlan = vlan < 0x1000;
1408 }
1409 ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
1410
1411 if (!is_eth) {
1412 sqp->ud_header.lrh.service_level =
1413 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1414 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
1415 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1416 }
1417
1418 if (is_grh) {
1419 sqp->ud_header.grh.traffic_class =
1420 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
1421 sqp->ud_header.grh.flow_label =
1422 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1423 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
1424 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.ib.port_pd) >> 24,
1425 ah->av.ib.gid_index, &sqp->ud_header.grh.source_gid);
1426 memcpy(sqp->ud_header.grh.destination_gid.raw,
1427 ah->av.ib.dgid, 16);
1428 }
1429
1430 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1431
1432 if (!is_eth) {
1433 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1434 (sqp->ud_header.lrh.destination_lid ==
1435 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1436 (sqp->ud_header.lrh.service_level << 8));
1437 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1438 }
1439
1440 switch (wr->opcode) {
1441 case IB_WR_SEND:
1442 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1443 sqp->ud_header.immediate_present = 0;
1444 break;
1445 case IB_WR_SEND_WITH_IMM:
1446 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1447 sqp->ud_header.immediate_present = 1;
1448 sqp->ud_header.immediate_data = wr->ex.imm_data;
1449 break;
1450 default:
1451 return -EINVAL;
1452 }
1453
1454 if (is_eth) {
1455 u8 *smac;
1456 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
1457
1458 mlx->sched_prio = cpu_to_be16(pcp);
1459
1460 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
1461 /* FIXME: cache smac value? */
1462 smac = to_mdev(sqp->qp.ibqp.device)->iboe.netdevs[sqp->qp.port - 1]->dev_addr;
1463 memcpy(sqp->ud_header.eth.smac_h, smac, 6);
1464 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
1465 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
1466 if (!is_vlan) {
1467 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
1468 } else {
1469 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
1470 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
1471 }
1472 } else {
1473 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1474 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1475 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1476 }
1477 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1478 if (!sqp->qp.ibqp.qp_num)
1479 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1480 else
1481 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1482 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1483 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1484 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1485 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1486 sqp->qkey : wr->wr.ud.remote_qkey);
1487 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1488
1489 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1490
1491 if (0) {
1492 pr_err("built UD header of size %d:\n", header_size);
1493 for (i = 0; i < header_size / 4; ++i) {
1494 if (i % 8 == 0)
1495 pr_err(" [%02x] ", i * 4);
1496 pr_cont(" %08x",
1497 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1498 if ((i + 1) % 8 == 0)
1499 pr_cont("\n");
1500 }
1501 pr_err("\n");
1502 }
1503
1504 /*
1505 * Inline data segments may not cross a 64 byte boundary. If
1506 * our UD header is bigger than the space available up to the
1507 * next 64 byte boundary in the WQE, use two inline data
1508 * segments to hold the UD header.
1509 */
1510 spc = MLX4_INLINE_ALIGN -
1511 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1512 if (header_size <= spc) {
1513 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1514 memcpy(inl + 1, sqp->header_buf, header_size);
1515 i = 1;
1516 } else {
1517 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1518 memcpy(inl + 1, sqp->header_buf, spc);
1519
1520 inl = (void *) (inl + 1) + spc;
1521 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1522 /*
1523 * Need a barrier here to make sure all the data is
1524 * visible before the byte_count field is set.
1525 * Otherwise the HCA prefetcher could grab the 64-byte
1526 * chunk with this inline segment and get a valid (!=
1527 * 0xffffffff) byte count but stale data, and end up
1528 * generating a packet with bad headers.
1529 *
1530 * The first inline segment's byte_count field doesn't
1531 * need a barrier, because it comes after a
1532 * control/MLX segment and therefore is at an offset
1533 * of 16 mod 64.
1534 */
1535 wmb();
1536 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1537 i = 2;
1538 }
1539
1540 *mlx_seg_len =
1541 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1542 return 0;
1543 }
1544
1545 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1546 {
1547 unsigned cur;
1548 struct mlx4_ib_cq *cq;
1549
1550 cur = wq->head - wq->tail;
1551 if (likely(cur + nreq < wq->max_post))
1552 return 0;
1553
1554 cq = to_mcq(ib_cq);
1555 spin_lock(&cq->lock);
1556 cur = wq->head - wq->tail;
1557 spin_unlock(&cq->lock);
1558
1559 return cur + nreq >= wq->max_post;
1560 }
1561
1562 static __be32 convert_access(int acc)
1563 {
1564 return (acc & IB_ACCESS_REMOTE_ATOMIC ? cpu_to_be32(MLX4_WQE_FMR_PERM_ATOMIC) : 0) |
1565 (acc & IB_ACCESS_REMOTE_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_WRITE) : 0) |
1566 (acc & IB_ACCESS_REMOTE_READ ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_READ) : 0) |
1567 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
1568 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
1569 }
1570
1571 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
1572 {
1573 struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
1574 int i;
1575
1576 for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
1577 mfrpl->mapped_page_list[i] =
1578 cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
1579 MLX4_MTT_FLAG_PRESENT);
1580
1581 fseg->flags = convert_access(wr->wr.fast_reg.access_flags);
1582 fseg->mem_key = cpu_to_be32(wr->wr.fast_reg.rkey);
1583 fseg->buf_list = cpu_to_be64(mfrpl->map);
1584 fseg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1585 fseg->reg_len = cpu_to_be64(wr->wr.fast_reg.length);
1586 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
1587 fseg->page_size = cpu_to_be32(wr->wr.fast_reg.page_shift);
1588 fseg->reserved[0] = 0;
1589 fseg->reserved[1] = 0;
1590 }
1591
1592 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
1593 {
1594 iseg->flags = 0;
1595 iseg->mem_key = cpu_to_be32(rkey);
1596 iseg->guest_id = 0;
1597 iseg->pa = 0;
1598 }
1599
1600 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1601 u64 remote_addr, u32 rkey)
1602 {
1603 rseg->raddr = cpu_to_be64(remote_addr);
1604 rseg->rkey = cpu_to_be32(rkey);
1605 rseg->reserved = 0;
1606 }
1607
1608 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1609 {
1610 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1611 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1612 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
1613 } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
1614 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1615 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add_mask);
1616 } else {
1617 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1618 aseg->compare = 0;
1619 }
1620
1621 }
1622
1623 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
1624 struct ib_send_wr *wr)
1625 {
1626 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1627 aseg->swap_add_mask = cpu_to_be64(wr->wr.atomic.swap_mask);
1628 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
1629 aseg->compare_mask = cpu_to_be64(wr->wr.atomic.compare_add_mask);
1630 }
1631
1632 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1633 struct ib_send_wr *wr)
1634 {
1635 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1636 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1637 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1638 dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
1639 memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
1640 }
1641
1642 static void set_mlx_icrc_seg(void *dseg)
1643 {
1644 u32 *t = dseg;
1645 struct mlx4_wqe_inline_seg *iseg = dseg;
1646
1647 t[1] = 0;
1648
1649 /*
1650 * Need a barrier here before writing the byte_count field to
1651 * make sure that all the data is visible before the
1652 * byte_count field is set. Otherwise, if the segment begins
1653 * a new cacheline, the HCA prefetcher could grab the 64-byte
1654 * chunk and get a valid (!= * 0xffffffff) byte count but
1655 * stale data, and end up sending the wrong data.
1656 */
1657 wmb();
1658
1659 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1660 }
1661
1662 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1663 {
1664 dseg->lkey = cpu_to_be32(sg->lkey);
1665 dseg->addr = cpu_to_be64(sg->addr);
1666
1667 /*
1668 * Need a barrier here before writing the byte_count field to
1669 * make sure that all the data is visible before the
1670 * byte_count field is set. Otherwise, if the segment begins
1671 * a new cacheline, the HCA prefetcher could grab the 64-byte
1672 * chunk and get a valid (!= * 0xffffffff) byte count but
1673 * stale data, and end up sending the wrong data.
1674 */
1675 wmb();
1676
1677 dseg->byte_count = cpu_to_be32(sg->length);
1678 }
1679
1680 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1681 {
1682 dseg->byte_count = cpu_to_be32(sg->length);
1683 dseg->lkey = cpu_to_be32(sg->lkey);
1684 dseg->addr = cpu_to_be64(sg->addr);
1685 }
1686
1687 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
1688 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
1689 __be32 *lso_hdr_sz, __be32 *blh)
1690 {
1691 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
1692
1693 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
1694 *blh = cpu_to_be32(1 << 6);
1695
1696 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
1697 wr->num_sge > qp->sq.max_gs - (halign >> 4)))
1698 return -EINVAL;
1699
1700 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
1701
1702 *lso_hdr_sz = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
1703 wr->wr.ud.hlen);
1704 *lso_seg_len = halign;
1705 return 0;
1706 }
1707
1708 static __be32 send_ieth(struct ib_send_wr *wr)
1709 {
1710 switch (wr->opcode) {
1711 case IB_WR_SEND_WITH_IMM:
1712 case IB_WR_RDMA_WRITE_WITH_IMM:
1713 return wr->ex.imm_data;
1714
1715 case IB_WR_SEND_WITH_INV:
1716 return cpu_to_be32(wr->ex.invalidate_rkey);
1717
1718 default:
1719 return 0;
1720 }
1721 }
1722
1723 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1724 struct ib_send_wr **bad_wr)
1725 {
1726 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1727 void *wqe;
1728 struct mlx4_wqe_ctrl_seg *ctrl;
1729 struct mlx4_wqe_data_seg *dseg;
1730 unsigned long flags;
1731 int nreq;
1732 int err = 0;
1733 unsigned ind;
1734 int uninitialized_var(stamp);
1735 int uninitialized_var(size);
1736 unsigned uninitialized_var(seglen);
1737 __be32 dummy;
1738 __be32 *lso_wqe;
1739 __be32 uninitialized_var(lso_hdr_sz);
1740 __be32 blh;
1741 int i;
1742
1743 spin_lock_irqsave(&qp->sq.lock, flags);
1744
1745 ind = qp->sq_next_wqe;
1746
1747 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1748 lso_wqe = &dummy;
1749 blh = 0;
1750
1751 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1752 err = -ENOMEM;
1753 *bad_wr = wr;
1754 goto out;
1755 }
1756
1757 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1758 err = -EINVAL;
1759 *bad_wr = wr;
1760 goto out;
1761 }
1762
1763 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1764 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
1765
1766 ctrl->srcrb_flags =
1767 (wr->send_flags & IB_SEND_SIGNALED ?
1768 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1769 (wr->send_flags & IB_SEND_SOLICITED ?
1770 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1771 ((wr->send_flags & IB_SEND_IP_CSUM) ?
1772 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
1773 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
1774 qp->sq_signal_bits;
1775
1776 ctrl->imm = send_ieth(wr);
1777
1778 wqe += sizeof *ctrl;
1779 size = sizeof *ctrl / 16;
1780
1781 switch (ibqp->qp_type) {
1782 case IB_QPT_RC:
1783 case IB_QPT_UC:
1784 switch (wr->opcode) {
1785 case IB_WR_ATOMIC_CMP_AND_SWP:
1786 case IB_WR_ATOMIC_FETCH_AND_ADD:
1787 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
1788 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1789 wr->wr.atomic.rkey);
1790 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1791
1792 set_atomic_seg(wqe, wr);
1793 wqe += sizeof (struct mlx4_wqe_atomic_seg);
1794
1795 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1796 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1797
1798 break;
1799
1800 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
1801 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1802 wr->wr.atomic.rkey);
1803 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1804
1805 set_masked_atomic_seg(wqe, wr);
1806 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
1807
1808 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1809 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
1810
1811 break;
1812
1813 case IB_WR_RDMA_READ:
1814 case IB_WR_RDMA_WRITE:
1815 case IB_WR_RDMA_WRITE_WITH_IMM:
1816 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1817 wr->wr.rdma.rkey);
1818 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1819 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1820 break;
1821
1822 case IB_WR_LOCAL_INV:
1823 ctrl->srcrb_flags |=
1824 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
1825 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
1826 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
1827 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
1828 break;
1829
1830 case IB_WR_FAST_REG_MR:
1831 ctrl->srcrb_flags |=
1832 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
1833 set_fmr_seg(wqe, wr);
1834 wqe += sizeof (struct mlx4_wqe_fmr_seg);
1835 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
1836 break;
1837
1838 default:
1839 /* No extra segments required for sends */
1840 break;
1841 }
1842 break;
1843
1844 case IB_QPT_UD:
1845 set_datagram_seg(wqe, wr);
1846 wqe += sizeof (struct mlx4_wqe_datagram_seg);
1847 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1848
1849 if (wr->opcode == IB_WR_LSO) {
1850 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
1851 if (unlikely(err)) {
1852 *bad_wr = wr;
1853 goto out;
1854 }
1855 lso_wqe = (__be32 *) wqe;
1856 wqe += seglen;
1857 size += seglen / 16;
1858 }
1859 break;
1860
1861 case IB_QPT_SMI:
1862 case IB_QPT_GSI:
1863 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
1864 if (unlikely(err)) {
1865 *bad_wr = wr;
1866 goto out;
1867 }
1868 wqe += seglen;
1869 size += seglen / 16;
1870 break;
1871
1872 default:
1873 break;
1874 }
1875
1876 /*
1877 * Write data segments in reverse order, so as to
1878 * overwrite cacheline stamp last within each
1879 * cacheline. This avoids issues with WQE
1880 * prefetching.
1881 */
1882
1883 dseg = wqe;
1884 dseg += wr->num_sge - 1;
1885 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
1886
1887 /* Add one more inline data segment for ICRC for MLX sends */
1888 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1889 qp->ibqp.qp_type == IB_QPT_GSI)) {
1890 set_mlx_icrc_seg(dseg + 1);
1891 size += sizeof (struct mlx4_wqe_data_seg) / 16;
1892 }
1893
1894 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1895 set_data_seg(dseg, wr->sg_list + i);
1896
1897 /*
1898 * Possibly overwrite stamping in cacheline with LSO
1899 * segment only after making sure all data segments
1900 * are written.
1901 */
1902 wmb();
1903 *lso_wqe = lso_hdr_sz;
1904
1905 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1906 MLX4_WQE_CTRL_FENCE : 0) | size;
1907
1908 /*
1909 * Make sure descriptor is fully written before
1910 * setting ownership bit (because HW can start
1911 * executing as soon as we do).
1912 */
1913 wmb();
1914
1915 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1916 *bad_wr = wr;
1917 err = -EINVAL;
1918 goto out;
1919 }
1920
1921 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1922 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
1923
1924 stamp = ind + qp->sq_spare_wqes;
1925 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
1926
1927 /*
1928 * We can improve latency by not stamping the last
1929 * send queue WQE until after ringing the doorbell, so
1930 * only stamp here if there are still more WQEs to post.
1931 *
1932 * Same optimization applies to padding with NOP wqe
1933 * in case of WQE shrinking (used to prevent wrap-around
1934 * in the middle of WR).
1935 */
1936 if (wr->next) {
1937 stamp_send_wqe(qp, stamp, size * 16);
1938 ind = pad_wraparound(qp, ind);
1939 }
1940 }
1941
1942 out:
1943 if (likely(nreq)) {
1944 qp->sq.head += nreq;
1945
1946 /*
1947 * Make sure that descriptors are written before
1948 * doorbell record.
1949 */
1950 wmb();
1951
1952 writel(qp->doorbell_qpn,
1953 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1954
1955 /*
1956 * Make sure doorbells don't leak out of SQ spinlock
1957 * and reach the HCA out of order.
1958 */
1959 mmiowb();
1960
1961 stamp_send_wqe(qp, stamp, size * 16);
1962
1963 ind = pad_wraparound(qp, ind);
1964 qp->sq_next_wqe = ind;
1965 }
1966
1967 spin_unlock_irqrestore(&qp->sq.lock, flags);
1968
1969 return err;
1970 }
1971
1972 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1973 struct ib_recv_wr **bad_wr)
1974 {
1975 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1976 struct mlx4_wqe_data_seg *scat;
1977 unsigned long flags;
1978 int err = 0;
1979 int nreq;
1980 int ind;
1981 int i;
1982
1983 spin_lock_irqsave(&qp->rq.lock, flags);
1984
1985 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
1986
1987 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1988 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1989 err = -ENOMEM;
1990 *bad_wr = wr;
1991 goto out;
1992 }
1993
1994 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1995 err = -EINVAL;
1996 *bad_wr = wr;
1997 goto out;
1998 }
1999
2000 scat = get_recv_wqe(qp, ind);
2001
2002 for (i = 0; i < wr->num_sge; ++i)
2003 __set_data_seg(scat + i, wr->sg_list + i);
2004
2005 if (i < qp->rq.max_gs) {
2006 scat[i].byte_count = 0;
2007 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
2008 scat[i].addr = 0;
2009 }
2010
2011 qp->rq.wrid[ind] = wr->wr_id;
2012
2013 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2014 }
2015
2016 out:
2017 if (likely(nreq)) {
2018 qp->rq.head += nreq;
2019
2020 /*
2021 * Make sure that descriptors are written before
2022 * doorbell record.
2023 */
2024 wmb();
2025
2026 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2027 }
2028
2029 spin_unlock_irqrestore(&qp->rq.lock, flags);
2030
2031 return err;
2032 }
2033
2034 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
2035 {
2036 switch (mlx4_state) {
2037 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
2038 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
2039 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
2040 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
2041 case MLX4_QP_STATE_SQ_DRAINING:
2042 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
2043 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
2044 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
2045 default: return -1;
2046 }
2047 }
2048
2049 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
2050 {
2051 switch (mlx4_mig_state) {
2052 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
2053 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
2054 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
2055 default: return -1;
2056 }
2057 }
2058
2059 static int to_ib_qp_access_flags(int mlx4_flags)
2060 {
2061 int ib_flags = 0;
2062
2063 if (mlx4_flags & MLX4_QP_BIT_RRE)
2064 ib_flags |= IB_ACCESS_REMOTE_READ;
2065 if (mlx4_flags & MLX4_QP_BIT_RWE)
2066 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2067 if (mlx4_flags & MLX4_QP_BIT_RAE)
2068 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2069
2070 return ib_flags;
2071 }
2072
2073 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2074 struct mlx4_qp_path *path)
2075 {
2076 struct mlx4_dev *dev = ibdev->dev;
2077 int is_eth;
2078
2079 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
2080 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
2081
2082 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2083 return;
2084
2085 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
2086 IB_LINK_LAYER_ETHERNET;
2087 if (is_eth)
2088 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
2089 ((path->sched_queue & 4) << 1);
2090 else
2091 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
2092
2093 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
2094 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
2095 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
2096 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
2097 if (ib_ah_attr->ah_flags) {
2098 ib_ah_attr->grh.sgid_index = path->mgid_index;
2099 ib_ah_attr->grh.hop_limit = path->hop_limit;
2100 ib_ah_attr->grh.traffic_class =
2101 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2102 ib_ah_attr->grh.flow_label =
2103 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2104 memcpy(ib_ah_attr->grh.dgid.raw,
2105 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
2106 }
2107 }
2108
2109 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2110 struct ib_qp_init_attr *qp_init_attr)
2111 {
2112 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2113 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2114 struct mlx4_qp_context context;
2115 int mlx4_state;
2116 int err = 0;
2117
2118 mutex_lock(&qp->mutex);
2119
2120 if (qp->state == IB_QPS_RESET) {
2121 qp_attr->qp_state = IB_QPS_RESET;
2122 goto done;
2123 }
2124
2125 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
2126 if (err) {
2127 err = -EINVAL;
2128 goto out;
2129 }
2130
2131 mlx4_state = be32_to_cpu(context.flags) >> 28;
2132
2133 qp->state = to_ib_qp_state(mlx4_state);
2134 qp_attr->qp_state = qp->state;
2135 qp_attr->path_mtu = context.mtu_msgmax >> 5;
2136 qp_attr->path_mig_state =
2137 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
2138 qp_attr->qkey = be32_to_cpu(context.qkey);
2139 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
2140 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
2141 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
2142 qp_attr->qp_access_flags =
2143 to_ib_qp_access_flags(be32_to_cpu(context.params2));
2144
2145 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
2146 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
2147 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
2148 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
2149 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
2150 }
2151
2152 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
2153 if (qp_attr->qp_state == IB_QPS_INIT)
2154 qp_attr->port_num = qp->port;
2155 else
2156 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
2157
2158 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2159 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
2160
2161 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
2162
2163 qp_attr->max_dest_rd_atomic =
2164 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
2165 qp_attr->min_rnr_timer =
2166 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
2167 qp_attr->timeout = context.pri_path.ackto >> 3;
2168 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
2169 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
2170 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
2171
2172 done:
2173 qp_attr->cur_qp_state = qp_attr->qp_state;
2174 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
2175 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
2176
2177 if (!ibqp->uobject) {
2178 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
2179 qp_attr->cap.max_send_sge = qp->sq.max_gs;
2180 } else {
2181 qp_attr->cap.max_send_wr = 0;
2182 qp_attr->cap.max_send_sge = 0;
2183 }
2184
2185 /*
2186 * We don't support inline sends for kernel QPs (yet), and we
2187 * don't know what userspace's value should be.
2188 */
2189 qp_attr->cap.max_inline_data = 0;
2190
2191 qp_init_attr->cap = qp_attr->cap;
2192
2193 qp_init_attr->create_flags = 0;
2194 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2195 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
2196
2197 if (qp->flags & MLX4_IB_QP_LSO)
2198 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
2199
2200 out:
2201 mutex_unlock(&qp->mutex);
2202 return err;
2203 }
2204
Linux kernel - Deliverables
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