2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/log2.h>
35 #include <linux/slab.h>
36 #include <linux/netdevice.h>
38 #include <rdma/ib_cache.h>
39 #include <rdma/ib_pack.h>
40 #include <rdma/ib_addr.h>
42 #include <linux/mlx4/qp.h>
48 MLX4_IB_ACK_REQ_FREQ
= 8,
52 MLX4_IB_DEFAULT_SCHED_QUEUE
= 0x83,
53 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE
= 0x3f,
54 MLX4_IB_LINK_TYPE_IB
= 0,
55 MLX4_IB_LINK_TYPE_ETH
= 1
60 * Largest possible UD header: send with GRH and immediate
61 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
62 * tag. (LRH would only use 8 bytes, so Ethernet is the
65 MLX4_IB_UD_HEADER_SIZE
= 82,
66 MLX4_IB_LSO_HEADER_SPARE
= 128,
70 MLX4_IB_IBOE_ETHERTYPE
= 0x8915
78 struct ib_ud_header ud_header
;
79 u8 header_buf
[MLX4_IB_UD_HEADER_SIZE
];
83 MLX4_IB_MIN_SQ_STRIDE
= 6,
84 MLX4_IB_CACHE_LINE_SIZE
= 64,
89 MLX4_RAW_QP_MSGMAX
= 31,
92 static const __be32 mlx4_ib_opcode
[] = {
93 [IB_WR_SEND
] = cpu_to_be32(MLX4_OPCODE_SEND
),
94 [IB_WR_LSO
] = cpu_to_be32(MLX4_OPCODE_LSO
),
95 [IB_WR_SEND_WITH_IMM
] = cpu_to_be32(MLX4_OPCODE_SEND_IMM
),
96 [IB_WR_RDMA_WRITE
] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE
),
97 [IB_WR_RDMA_WRITE_WITH_IMM
] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM
),
98 [IB_WR_RDMA_READ
] = cpu_to_be32(MLX4_OPCODE_RDMA_READ
),
99 [IB_WR_ATOMIC_CMP_AND_SWP
] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS
),
100 [IB_WR_ATOMIC_FETCH_AND_ADD
] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA
),
101 [IB_WR_SEND_WITH_INV
] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL
),
102 [IB_WR_LOCAL_INV
] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL
),
103 [IB_WR_FAST_REG_MR
] = cpu_to_be32(MLX4_OPCODE_FMR
),
104 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP
] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS
),
105 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD
] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA
),
108 static struct mlx4_ib_sqp
*to_msqp(struct mlx4_ib_qp
*mqp
)
110 return container_of(mqp
, struct mlx4_ib_sqp
, qp
);
113 static int is_sqp(struct mlx4_ib_dev
*dev
, struct mlx4_ib_qp
*qp
)
115 return qp
->mqp
.qpn
>= dev
->dev
->caps
.sqp_start
&&
116 qp
->mqp
.qpn
<= dev
->dev
->caps
.sqp_start
+ 3;
119 static int is_qp0(struct mlx4_ib_dev
*dev
, struct mlx4_ib_qp
*qp
)
121 return qp
->mqp
.qpn
>= dev
->dev
->caps
.sqp_start
&&
122 qp
->mqp
.qpn
<= dev
->dev
->caps
.sqp_start
+ 1;
125 static void *get_wqe(struct mlx4_ib_qp
*qp
, int offset
)
127 return mlx4_buf_offset(&qp
->buf
, offset
);
130 static void *get_recv_wqe(struct mlx4_ib_qp
*qp
, int n
)
132 return get_wqe(qp
, qp
->rq
.offset
+ (n
<< qp
->rq
.wqe_shift
));
135 static void *get_send_wqe(struct mlx4_ib_qp
*qp
, int n
)
137 return get_wqe(qp
, qp
->sq
.offset
+ (n
<< qp
->sq
.wqe_shift
));
141 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
142 * first four bytes of every 64 byte chunk with
143 * 0x7FFFFFF | (invalid_ownership_value << 31).
145 * When the max work request size is less than or equal to the WQE
146 * basic block size, as an optimization, we can stamp all WQEs with
147 * 0xffffffff, and skip the very first chunk of each WQE.
149 static void stamp_send_wqe(struct mlx4_ib_qp
*qp
, int n
, int size
)
157 struct mlx4_wqe_ctrl_seg
*ctrl
;
159 if (qp
->sq_max_wqes_per_wr
> 1) {
160 s
= roundup(size
, 1U << qp
->sq
.wqe_shift
);
161 for (i
= 0; i
< s
; i
+= 64) {
162 ind
= (i
>> qp
->sq
.wqe_shift
) + n
;
163 stamp
= ind
& qp
->sq
.wqe_cnt
? cpu_to_be32(0x7fffffff) :
164 cpu_to_be32(0xffffffff);
165 buf
= get_send_wqe(qp
, ind
& (qp
->sq
.wqe_cnt
- 1));
166 wqe
= buf
+ (i
& ((1 << qp
->sq
.wqe_shift
) - 1));
170 ctrl
= buf
= get_send_wqe(qp
, n
& (qp
->sq
.wqe_cnt
- 1));
171 s
= (ctrl
->fence_size
& 0x3f) << 4;
172 for (i
= 64; i
< s
; i
+= 64) {
174 *wqe
= cpu_to_be32(0xffffffff);
179 static void post_nop_wqe(struct mlx4_ib_qp
*qp
, int n
, int size
)
181 struct mlx4_wqe_ctrl_seg
*ctrl
;
182 struct mlx4_wqe_inline_seg
*inl
;
186 ctrl
= wqe
= get_send_wqe(qp
, n
& (qp
->sq
.wqe_cnt
- 1));
187 s
= sizeof(struct mlx4_wqe_ctrl_seg
);
189 if (qp
->ibqp
.qp_type
== IB_QPT_UD
) {
190 struct mlx4_wqe_datagram_seg
*dgram
= wqe
+ sizeof *ctrl
;
191 struct mlx4_av
*av
= (struct mlx4_av
*)dgram
->av
;
192 memset(dgram
, 0, sizeof *dgram
);
193 av
->port_pd
= cpu_to_be32((qp
->port
<< 24) | to_mpd(qp
->ibqp
.pd
)->pdn
);
194 s
+= sizeof(struct mlx4_wqe_datagram_seg
);
197 /* Pad the remainder of the WQE with an inline data segment. */
200 inl
->byte_count
= cpu_to_be32(1 << 31 | (size
- s
- sizeof *inl
));
202 ctrl
->srcrb_flags
= 0;
203 ctrl
->fence_size
= size
/ 16;
205 * Make sure descriptor is fully written before setting ownership bit
206 * (because HW can start executing as soon as we do).
210 ctrl
->owner_opcode
= cpu_to_be32(MLX4_OPCODE_NOP
| MLX4_WQE_CTRL_NEC
) |
211 (n
& qp
->sq
.wqe_cnt
? cpu_to_be32(1 << 31) : 0);
213 stamp_send_wqe(qp
, n
+ qp
->sq_spare_wqes
, size
);
216 /* Post NOP WQE to prevent wrap-around in the middle of WR */
217 static inline unsigned pad_wraparound(struct mlx4_ib_qp
*qp
, int ind
)
219 unsigned s
= qp
->sq
.wqe_cnt
- (ind
& (qp
->sq
.wqe_cnt
- 1));
220 if (unlikely(s
< qp
->sq_max_wqes_per_wr
)) {
221 post_nop_wqe(qp
, ind
, s
<< qp
->sq
.wqe_shift
);
227 static void mlx4_ib_qp_event(struct mlx4_qp
*qp
, enum mlx4_event type
)
229 struct ib_event event
;
230 struct ib_qp
*ibqp
= &to_mibqp(qp
)->ibqp
;
232 if (type
== MLX4_EVENT_TYPE_PATH_MIG
)
233 to_mibqp(qp
)->port
= to_mibqp(qp
)->alt_port
;
235 if (ibqp
->event_handler
) {
236 event
.device
= ibqp
->device
;
237 event
.element
.qp
= ibqp
;
239 case MLX4_EVENT_TYPE_PATH_MIG
:
240 event
.event
= IB_EVENT_PATH_MIG
;
242 case MLX4_EVENT_TYPE_COMM_EST
:
243 event
.event
= IB_EVENT_COMM_EST
;
245 case MLX4_EVENT_TYPE_SQ_DRAINED
:
246 event
.event
= IB_EVENT_SQ_DRAINED
;
248 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
:
249 event
.event
= IB_EVENT_QP_LAST_WQE_REACHED
;
251 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR
:
252 event
.event
= IB_EVENT_QP_FATAL
;
254 case MLX4_EVENT_TYPE_PATH_MIG_FAILED
:
255 event
.event
= IB_EVENT_PATH_MIG_ERR
;
257 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
:
258 event
.event
= IB_EVENT_QP_REQ_ERR
;
260 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
:
261 event
.event
= IB_EVENT_QP_ACCESS_ERR
;
264 pr_warn("Unexpected event type %d "
265 "on QP %06x\n", type
, qp
->qpn
);
269 ibqp
->event_handler(&event
, ibqp
->qp_context
);
273 static int send_wqe_overhead(enum ib_qp_type type
, u32 flags
)
276 * UD WQEs must have a datagram segment.
277 * RC and UC WQEs might have a remote address segment.
278 * MLX WQEs need two extra inline data segments (for the UD
279 * header and space for the ICRC).
283 return sizeof (struct mlx4_wqe_ctrl_seg
) +
284 sizeof (struct mlx4_wqe_datagram_seg
) +
285 ((flags
& MLX4_IB_QP_LSO
) ? MLX4_IB_LSO_HEADER_SPARE
: 0);
287 return sizeof (struct mlx4_wqe_ctrl_seg
) +
288 sizeof (struct mlx4_wqe_raddr_seg
);
290 return sizeof (struct mlx4_wqe_ctrl_seg
) +
291 sizeof (struct mlx4_wqe_atomic_seg
) +
292 sizeof (struct mlx4_wqe_raddr_seg
);
295 return sizeof (struct mlx4_wqe_ctrl_seg
) +
296 ALIGN(MLX4_IB_UD_HEADER_SIZE
+
297 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE
,
299 sizeof (struct mlx4_wqe_inline_seg
),
300 sizeof (struct mlx4_wqe_data_seg
)) +
302 sizeof (struct mlx4_wqe_inline_seg
),
303 sizeof (struct mlx4_wqe_data_seg
));
305 return sizeof (struct mlx4_wqe_ctrl_seg
);
309 static int set_rq_size(struct mlx4_ib_dev
*dev
, struct ib_qp_cap
*cap
,
310 int is_user
, int has_rq
, struct mlx4_ib_qp
*qp
)
312 /* Sanity check RQ size before proceeding */
313 if (cap
->max_recv_wr
> dev
->dev
->caps
.max_wqes
||
314 cap
->max_recv_sge
> dev
->dev
->caps
.max_rq_sg
)
318 if (cap
->max_recv_wr
)
321 qp
->rq
.wqe_cnt
= qp
->rq
.max_gs
= 0;
323 /* HW requires >= 1 RQ entry with >= 1 gather entry */
324 if (is_user
&& (!cap
->max_recv_wr
|| !cap
->max_recv_sge
))
327 qp
->rq
.wqe_cnt
= roundup_pow_of_two(max(1U, cap
->max_recv_wr
));
328 qp
->rq
.max_gs
= roundup_pow_of_two(max(1U, cap
->max_recv_sge
));
329 qp
->rq
.wqe_shift
= ilog2(qp
->rq
.max_gs
* sizeof (struct mlx4_wqe_data_seg
));
332 cap
->max_recv_wr
= qp
->rq
.max_post
= qp
->rq
.wqe_cnt
;
333 cap
->max_recv_sge
= qp
->rq
.max_gs
;
338 static int set_kernel_sq_size(struct mlx4_ib_dev
*dev
, struct ib_qp_cap
*cap
,
339 enum ib_qp_type type
, struct mlx4_ib_qp
*qp
)
343 /* Sanity check SQ size before proceeding */
344 if (cap
->max_send_wr
> dev
->dev
->caps
.max_wqes
||
345 cap
->max_send_sge
> dev
->dev
->caps
.max_sq_sg
||
346 cap
->max_inline_data
+ send_wqe_overhead(type
, qp
->flags
) +
347 sizeof (struct mlx4_wqe_inline_seg
) > dev
->dev
->caps
.max_sq_desc_sz
)
351 * For MLX transport we need 2 extra S/G entries:
352 * one for the header and one for the checksum at the end
354 if ((type
== IB_QPT_SMI
|| type
== IB_QPT_GSI
) &&
355 cap
->max_send_sge
+ 2 > dev
->dev
->caps
.max_sq_sg
)
358 s
= max(cap
->max_send_sge
* sizeof (struct mlx4_wqe_data_seg
),
359 cap
->max_inline_data
+ sizeof (struct mlx4_wqe_inline_seg
)) +
360 send_wqe_overhead(type
, qp
->flags
);
362 if (s
> dev
->dev
->caps
.max_sq_desc_sz
)
366 * Hermon supports shrinking WQEs, such that a single work
367 * request can include multiple units of 1 << wqe_shift. This
368 * way, work requests can differ in size, and do not have to
369 * be a power of 2 in size, saving memory and speeding up send
370 * WR posting. Unfortunately, if we do this then the
371 * wqe_index field in CQEs can't be used to look up the WR ID
372 * anymore, so we do this only if selective signaling is off.
374 * Further, on 32-bit platforms, we can't use vmap() to make
375 * the QP buffer virtually contiguous. Thus we have to use
376 * constant-sized WRs to make sure a WR is always fully within
377 * a single page-sized chunk.
379 * Finally, we use NOP work requests to pad the end of the
380 * work queue, to avoid wrap-around in the middle of WR. We
381 * set NEC bit to avoid getting completions with error for
382 * these NOP WRs, but since NEC is only supported starting
383 * with firmware 2.2.232, we use constant-sized WRs for older
386 * And, since MLX QPs only support SEND, we use constant-sized
389 * We look for the smallest value of wqe_shift such that the
390 * resulting number of wqes does not exceed device
393 * We set WQE size to at least 64 bytes, this way stamping
394 * invalidates each WQE.
396 if (dev
->dev
->caps
.fw_ver
>= MLX4_FW_VER_WQE_CTRL_NEC
&&
397 qp
->sq_signal_bits
&& BITS_PER_LONG
== 64 &&
398 type
!= IB_QPT_SMI
&& type
!= IB_QPT_GSI
)
399 qp
->sq
.wqe_shift
= ilog2(64);
401 qp
->sq
.wqe_shift
= ilog2(roundup_pow_of_two(s
));
404 qp
->sq_max_wqes_per_wr
= DIV_ROUND_UP(s
, 1U << qp
->sq
.wqe_shift
);
407 * We need to leave 2 KB + 1 WR of headroom in the SQ to
408 * allow HW to prefetch.
410 qp
->sq_spare_wqes
= (2048 >> qp
->sq
.wqe_shift
) + qp
->sq_max_wqes_per_wr
;
411 qp
->sq
.wqe_cnt
= roundup_pow_of_two(cap
->max_send_wr
*
412 qp
->sq_max_wqes_per_wr
+
415 if (qp
->sq
.wqe_cnt
<= dev
->dev
->caps
.max_wqes
)
418 if (qp
->sq_max_wqes_per_wr
<= 1)
424 qp
->sq
.max_gs
= (min(dev
->dev
->caps
.max_sq_desc_sz
,
425 (qp
->sq_max_wqes_per_wr
<< qp
->sq
.wqe_shift
)) -
426 send_wqe_overhead(type
, qp
->flags
)) /
427 sizeof (struct mlx4_wqe_data_seg
);
429 qp
->buf_size
= (qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
) +
430 (qp
->sq
.wqe_cnt
<< qp
->sq
.wqe_shift
);
431 if (qp
->rq
.wqe_shift
> qp
->sq
.wqe_shift
) {
433 qp
->sq
.offset
= qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
;
435 qp
->rq
.offset
= qp
->sq
.wqe_cnt
<< qp
->sq
.wqe_shift
;
439 cap
->max_send_wr
= qp
->sq
.max_post
=
440 (qp
->sq
.wqe_cnt
- qp
->sq_spare_wqes
) / qp
->sq_max_wqes_per_wr
;
441 cap
->max_send_sge
= min(qp
->sq
.max_gs
,
442 min(dev
->dev
->caps
.max_sq_sg
,
443 dev
->dev
->caps
.max_rq_sg
));
444 /* We don't support inline sends for kernel QPs (yet) */
445 cap
->max_inline_data
= 0;
450 static int set_user_sq_size(struct mlx4_ib_dev
*dev
,
451 struct mlx4_ib_qp
*qp
,
452 struct mlx4_ib_create_qp
*ucmd
)
454 /* Sanity check SQ size before proceeding */
455 if ((1 << ucmd
->log_sq_bb_count
) > dev
->dev
->caps
.max_wqes
||
456 ucmd
->log_sq_stride
>
457 ilog2(roundup_pow_of_two(dev
->dev
->caps
.max_sq_desc_sz
)) ||
458 ucmd
->log_sq_stride
< MLX4_IB_MIN_SQ_STRIDE
)
461 qp
->sq
.wqe_cnt
= 1 << ucmd
->log_sq_bb_count
;
462 qp
->sq
.wqe_shift
= ucmd
->log_sq_stride
;
464 qp
->buf_size
= (qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
) +
465 (qp
->sq
.wqe_cnt
<< qp
->sq
.wqe_shift
);
470 static int qp_has_rq(struct ib_qp_init_attr
*attr
)
472 if (attr
->qp_type
== IB_QPT_XRC_INI
|| attr
->qp_type
== IB_QPT_XRC_TGT
)
478 static int create_qp_common(struct mlx4_ib_dev
*dev
, struct ib_pd
*pd
,
479 struct ib_qp_init_attr
*init_attr
,
480 struct ib_udata
*udata
, int sqpn
, struct mlx4_ib_qp
*qp
)
485 mutex_init(&qp
->mutex
);
486 spin_lock_init(&qp
->sq
.lock
);
487 spin_lock_init(&qp
->rq
.lock
);
488 INIT_LIST_HEAD(&qp
->gid_list
);
490 qp
->state
= IB_QPS_RESET
;
491 if (init_attr
->sq_sig_type
== IB_SIGNAL_ALL_WR
)
492 qp
->sq_signal_bits
= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE
);
494 err
= set_rq_size(dev
, &init_attr
->cap
, !!pd
->uobject
, qp_has_rq(init_attr
), qp
);
499 struct mlx4_ib_create_qp ucmd
;
501 if (ib_copy_from_udata(&ucmd
, udata
, sizeof ucmd
)) {
506 qp
->sq_no_prefetch
= ucmd
.sq_no_prefetch
;
508 err
= set_user_sq_size(dev
, qp
, &ucmd
);
512 qp
->umem
= ib_umem_get(pd
->uobject
->context
, ucmd
.buf_addr
,
514 if (IS_ERR(qp
->umem
)) {
515 err
= PTR_ERR(qp
->umem
);
519 err
= mlx4_mtt_init(dev
->dev
, ib_umem_page_count(qp
->umem
),
520 ilog2(qp
->umem
->page_size
), &qp
->mtt
);
524 err
= mlx4_ib_umem_write_mtt(dev
, &qp
->mtt
, qp
->umem
);
528 if (qp_has_rq(init_attr
)) {
529 err
= mlx4_ib_db_map_user(to_mucontext(pd
->uobject
->context
),
530 ucmd
.db_addr
, &qp
->db
);
535 qp
->sq_no_prefetch
= 0;
537 if (init_attr
->create_flags
& IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
)
538 qp
->flags
|= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK
;
540 if (init_attr
->create_flags
& IB_QP_CREATE_IPOIB_UD_LSO
)
541 qp
->flags
|= MLX4_IB_QP_LSO
;
543 err
= set_kernel_sq_size(dev
, &init_attr
->cap
, init_attr
->qp_type
, qp
);
547 if (qp_has_rq(init_attr
)) {
548 err
= mlx4_db_alloc(dev
->dev
, &qp
->db
, 0);
555 if (mlx4_buf_alloc(dev
->dev
, qp
->buf_size
, PAGE_SIZE
* 2, &qp
->buf
)) {
560 err
= mlx4_mtt_init(dev
->dev
, qp
->buf
.npages
, qp
->buf
.page_shift
,
565 err
= mlx4_buf_write_mtt(dev
->dev
, &qp
->mtt
, &qp
->buf
);
569 qp
->sq
.wrid
= kmalloc(qp
->sq
.wqe_cnt
* sizeof (u64
), GFP_KERNEL
);
570 qp
->rq
.wrid
= kmalloc(qp
->rq
.wqe_cnt
* sizeof (u64
), GFP_KERNEL
);
572 if (!qp
->sq
.wrid
|| !qp
->rq
.wrid
) {
581 /* Raw packet QPNs must be aligned to 8 bits. If not, the WQE
582 * BlueFlame setup flow wrongly causes VLAN insertion. */
583 if (init_attr
->qp_type
== IB_QPT_RAW_PACKET
)
584 err
= mlx4_qp_reserve_range(dev
->dev
, 1, 1 << 8, &qpn
);
586 err
= mlx4_qp_reserve_range(dev
->dev
, 1, 1, &qpn
);
591 err
= mlx4_qp_alloc(dev
->dev
, qpn
, &qp
->mqp
);
595 if (init_attr
->qp_type
== IB_QPT_XRC_TGT
)
596 qp
->mqp
.qpn
|= (1 << 23);
599 * Hardware wants QPN written in big-endian order (after
600 * shifting) for send doorbell. Precompute this value to save
601 * a little bit when posting sends.
603 qp
->doorbell_qpn
= swab32(qp
->mqp
.qpn
<< 8);
605 qp
->mqp
.event
= mlx4_ib_qp_event
;
611 mlx4_qp_release_range(dev
->dev
, qpn
, 1);
615 if (qp_has_rq(init_attr
))
616 mlx4_ib_db_unmap_user(to_mucontext(pd
->uobject
->context
), &qp
->db
);
623 mlx4_mtt_cleanup(dev
->dev
, &qp
->mtt
);
627 ib_umem_release(qp
->umem
);
629 mlx4_buf_free(dev
->dev
, qp
->buf_size
, &qp
->buf
);
632 if (!pd
->uobject
&& qp_has_rq(init_attr
))
633 mlx4_db_free(dev
->dev
, &qp
->db
);
639 static enum mlx4_qp_state
to_mlx4_state(enum ib_qp_state state
)
642 case IB_QPS_RESET
: return MLX4_QP_STATE_RST
;
643 case IB_QPS_INIT
: return MLX4_QP_STATE_INIT
;
644 case IB_QPS_RTR
: return MLX4_QP_STATE_RTR
;
645 case IB_QPS_RTS
: return MLX4_QP_STATE_RTS
;
646 case IB_QPS_SQD
: return MLX4_QP_STATE_SQD
;
647 case IB_QPS_SQE
: return MLX4_QP_STATE_SQER
;
648 case IB_QPS_ERR
: return MLX4_QP_STATE_ERR
;
653 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq
*send_cq
, struct mlx4_ib_cq
*recv_cq
)
654 __acquires(&send_cq
->lock
) __acquires(&recv_cq
->lock
)
656 if (send_cq
== recv_cq
) {
657 spin_lock_irq(&send_cq
->lock
);
658 __acquire(&recv_cq
->lock
);
659 } else if (send_cq
->mcq
.cqn
< recv_cq
->mcq
.cqn
) {
660 spin_lock_irq(&send_cq
->lock
);
661 spin_lock_nested(&recv_cq
->lock
, SINGLE_DEPTH_NESTING
);
663 spin_lock_irq(&recv_cq
->lock
);
664 spin_lock_nested(&send_cq
->lock
, SINGLE_DEPTH_NESTING
);
668 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq
*send_cq
, struct mlx4_ib_cq
*recv_cq
)
669 __releases(&send_cq
->lock
) __releases(&recv_cq
->lock
)
671 if (send_cq
== recv_cq
) {
672 __release(&recv_cq
->lock
);
673 spin_unlock_irq(&send_cq
->lock
);
674 } else if (send_cq
->mcq
.cqn
< recv_cq
->mcq
.cqn
) {
675 spin_unlock(&recv_cq
->lock
);
676 spin_unlock_irq(&send_cq
->lock
);
678 spin_unlock(&send_cq
->lock
);
679 spin_unlock_irq(&recv_cq
->lock
);
683 static void del_gid_entries(struct mlx4_ib_qp
*qp
)
685 struct mlx4_ib_gid_entry
*ge
, *tmp
;
687 list_for_each_entry_safe(ge
, tmp
, &qp
->gid_list
, list
) {
693 static struct mlx4_ib_pd
*get_pd(struct mlx4_ib_qp
*qp
)
695 if (qp
->ibqp
.qp_type
== IB_QPT_XRC_TGT
)
696 return to_mpd(to_mxrcd(qp
->ibqp
.xrcd
)->pd
);
698 return to_mpd(qp
->ibqp
.pd
);
701 static void get_cqs(struct mlx4_ib_qp
*qp
,
702 struct mlx4_ib_cq
**send_cq
, struct mlx4_ib_cq
**recv_cq
)
704 switch (qp
->ibqp
.qp_type
) {
706 *send_cq
= to_mcq(to_mxrcd(qp
->ibqp
.xrcd
)->cq
);
710 *send_cq
= to_mcq(qp
->ibqp
.send_cq
);
714 *send_cq
= to_mcq(qp
->ibqp
.send_cq
);
715 *recv_cq
= to_mcq(qp
->ibqp
.recv_cq
);
720 static void destroy_qp_common(struct mlx4_ib_dev
*dev
, struct mlx4_ib_qp
*qp
,
723 struct mlx4_ib_cq
*send_cq
, *recv_cq
;
725 if (qp
->state
!= IB_QPS_RESET
)
726 if (mlx4_qp_modify(dev
->dev
, NULL
, to_mlx4_state(qp
->state
),
727 MLX4_QP_STATE_RST
, NULL
, 0, 0, &qp
->mqp
))
728 pr_warn("modify QP %06x to RESET failed.\n",
731 get_cqs(qp
, &send_cq
, &recv_cq
);
733 mlx4_ib_lock_cqs(send_cq
, recv_cq
);
736 __mlx4_ib_cq_clean(recv_cq
, qp
->mqp
.qpn
,
737 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
): NULL
);
738 if (send_cq
!= recv_cq
)
739 __mlx4_ib_cq_clean(send_cq
, qp
->mqp
.qpn
, NULL
);
742 mlx4_qp_remove(dev
->dev
, &qp
->mqp
);
744 mlx4_ib_unlock_cqs(send_cq
, recv_cq
);
746 mlx4_qp_free(dev
->dev
, &qp
->mqp
);
748 if (!is_sqp(dev
, qp
))
749 mlx4_qp_release_range(dev
->dev
, qp
->mqp
.qpn
, 1);
751 mlx4_mtt_cleanup(dev
->dev
, &qp
->mtt
);
755 mlx4_ib_db_unmap_user(to_mucontext(qp
->ibqp
.uobject
->context
),
757 ib_umem_release(qp
->umem
);
761 mlx4_buf_free(dev
->dev
, qp
->buf_size
, &qp
->buf
);
763 mlx4_db_free(dev
->dev
, &qp
->db
);
769 struct ib_qp
*mlx4_ib_create_qp(struct ib_pd
*pd
,
770 struct ib_qp_init_attr
*init_attr
,
771 struct ib_udata
*udata
)
773 struct mlx4_ib_sqp
*sqp
;
774 struct mlx4_ib_qp
*qp
;
779 * We only support LSO and multicast loopback blocking, and
780 * only for kernel UD QPs.
782 if (init_attr
->create_flags
& ~(IB_QP_CREATE_IPOIB_UD_LSO
|
783 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
))
784 return ERR_PTR(-EINVAL
);
786 if (init_attr
->create_flags
&&
787 (udata
|| init_attr
->qp_type
!= IB_QPT_UD
))
788 return ERR_PTR(-EINVAL
);
790 switch (init_attr
->qp_type
) {
792 pd
= to_mxrcd(init_attr
->xrcd
)->pd
;
793 xrcdn
= to_mxrcd(init_attr
->xrcd
)->xrcdn
;
794 init_attr
->send_cq
= to_mxrcd(init_attr
->xrcd
)->cq
;
797 if (!(to_mdev(pd
->device
)->dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
))
798 return ERR_PTR(-ENOSYS
);
799 init_attr
->recv_cq
= init_attr
->send_cq
;
804 case IB_QPT_RAW_PACKET
:
806 qp
= kzalloc(sizeof *qp
, GFP_KERNEL
);
808 return ERR_PTR(-ENOMEM
);
810 err
= create_qp_common(to_mdev(pd
->device
), pd
, init_attr
, udata
, 0, qp
);
816 qp
->ibqp
.qp_num
= qp
->mqp
.qpn
;
824 /* Userspace is not allowed to create special QPs: */
826 return ERR_PTR(-EINVAL
);
828 sqp
= kzalloc(sizeof *sqp
, GFP_KERNEL
);
830 return ERR_PTR(-ENOMEM
);
834 err
= create_qp_common(to_mdev(pd
->device
), pd
, init_attr
, udata
,
835 to_mdev(pd
->device
)->dev
->caps
.sqp_start
+
836 (init_attr
->qp_type
== IB_QPT_SMI
? 0 : 2) +
837 init_attr
->port_num
- 1,
844 qp
->port
= init_attr
->port_num
;
845 qp
->ibqp
.qp_num
= init_attr
->qp_type
== IB_QPT_SMI
? 0 : 1;
850 /* Don't support raw QPs */
851 return ERR_PTR(-EINVAL
);
857 int mlx4_ib_destroy_qp(struct ib_qp
*qp
)
859 struct mlx4_ib_dev
*dev
= to_mdev(qp
->device
);
860 struct mlx4_ib_qp
*mqp
= to_mqp(qp
);
861 struct mlx4_ib_pd
*pd
;
863 if (is_qp0(dev
, mqp
))
864 mlx4_CLOSE_PORT(dev
->dev
, mqp
->port
);
867 destroy_qp_common(dev
, mqp
, !!pd
->ibpd
.uobject
);
869 if (is_sqp(dev
, mqp
))
877 static int to_mlx4_st(enum ib_qp_type type
)
880 case IB_QPT_RC
: return MLX4_QP_ST_RC
;
881 case IB_QPT_UC
: return MLX4_QP_ST_UC
;
882 case IB_QPT_UD
: return MLX4_QP_ST_UD
;
884 case IB_QPT_XRC_TGT
: return MLX4_QP_ST_XRC
;
887 case IB_QPT_RAW_PACKET
: return MLX4_QP_ST_MLX
;
892 static __be32
to_mlx4_access_flags(struct mlx4_ib_qp
*qp
, const struct ib_qp_attr
*attr
,
897 u32 hw_access_flags
= 0;
899 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
900 dest_rd_atomic
= attr
->max_dest_rd_atomic
;
902 dest_rd_atomic
= qp
->resp_depth
;
904 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
905 access_flags
= attr
->qp_access_flags
;
907 access_flags
= qp
->atomic_rd_en
;
910 access_flags
&= IB_ACCESS_REMOTE_WRITE
;
912 if (access_flags
& IB_ACCESS_REMOTE_READ
)
913 hw_access_flags
|= MLX4_QP_BIT_RRE
;
914 if (access_flags
& IB_ACCESS_REMOTE_ATOMIC
)
915 hw_access_flags
|= MLX4_QP_BIT_RAE
;
916 if (access_flags
& IB_ACCESS_REMOTE_WRITE
)
917 hw_access_flags
|= MLX4_QP_BIT_RWE
;
919 return cpu_to_be32(hw_access_flags
);
922 static void store_sqp_attrs(struct mlx4_ib_sqp
*sqp
, const struct ib_qp_attr
*attr
,
925 if (attr_mask
& IB_QP_PKEY_INDEX
)
926 sqp
->pkey_index
= attr
->pkey_index
;
927 if (attr_mask
& IB_QP_QKEY
)
928 sqp
->qkey
= attr
->qkey
;
929 if (attr_mask
& IB_QP_SQ_PSN
)
930 sqp
->send_psn
= attr
->sq_psn
;
933 static void mlx4_set_sched(struct mlx4_qp_path
*path
, u8 port
)
935 path
->sched_queue
= (path
->sched_queue
& 0xbf) | ((port
- 1) << 6);
938 static int mlx4_set_path(struct mlx4_ib_dev
*dev
, const struct ib_ah_attr
*ah
,
939 struct mlx4_qp_path
*path
, u8 port
)
942 int is_eth
= rdma_port_get_link_layer(&dev
->ib_dev
, port
) ==
943 IB_LINK_LAYER_ETHERNET
;
949 path
->grh_mylmc
= ah
->src_path_bits
& 0x7f;
950 path
->rlid
= cpu_to_be16(ah
->dlid
);
951 if (ah
->static_rate
) {
952 path
->static_rate
= ah
->static_rate
+ MLX4_STAT_RATE_OFFSET
;
953 while (path
->static_rate
> IB_RATE_2_5_GBPS
+ MLX4_STAT_RATE_OFFSET
&&
954 !(1 << path
->static_rate
& dev
->dev
->caps
.stat_rate_support
))
957 path
->static_rate
= 0;
959 if (ah
->ah_flags
& IB_AH_GRH
) {
960 if (ah
->grh
.sgid_index
>= dev
->dev
->caps
.gid_table_len
[port
]) {
961 pr_err("sgid_index (%u) too large. max is %d\n",
962 ah
->grh
.sgid_index
, dev
->dev
->caps
.gid_table_len
[port
] - 1);
966 path
->grh_mylmc
|= 1 << 7;
967 path
->mgid_index
= ah
->grh
.sgid_index
;
968 path
->hop_limit
= ah
->grh
.hop_limit
;
969 path
->tclass_flowlabel
=
970 cpu_to_be32((ah
->grh
.traffic_class
<< 20) |
971 (ah
->grh
.flow_label
));
972 memcpy(path
->rgid
, ah
->grh
.dgid
.raw
, 16);
976 path
->sched_queue
= MLX4_IB_DEFAULT_SCHED_QUEUE
|
977 ((port
- 1) << 6) | ((ah
->sl
& 7) << 3);
979 if (!(ah
->ah_flags
& IB_AH_GRH
))
982 err
= mlx4_ib_resolve_grh(dev
, ah
, mac
, &is_mcast
, port
);
986 memcpy(path
->dmac
, mac
, 6);
987 path
->ackto
= MLX4_IB_LINK_TYPE_ETH
;
988 /* use index 0 into MAC table for IBoE */
989 path
->grh_mylmc
&= 0x80;
991 vlan_tag
= rdma_get_vlan_id(&dev
->iboe
.gid_table
[port
- 1][ah
->grh
.sgid_index
]);
992 if (vlan_tag
< 0x1000) {
993 if (mlx4_find_cached_vlan(dev
->dev
, port
, vlan_tag
, &vidx
))
996 path
->vlan_index
= vidx
;
1000 path
->sched_queue
= MLX4_IB_DEFAULT_SCHED_QUEUE
|
1001 ((port
- 1) << 6) | ((ah
->sl
& 0xf) << 2);
1006 static void update_mcg_macs(struct mlx4_ib_dev
*dev
, struct mlx4_ib_qp
*qp
)
1008 struct mlx4_ib_gid_entry
*ge
, *tmp
;
1010 list_for_each_entry_safe(ge
, tmp
, &qp
->gid_list
, list
) {
1011 if (!ge
->added
&& mlx4_ib_add_mc(dev
, qp
, &ge
->gid
)) {
1013 ge
->port
= qp
->port
;
1018 static int __mlx4_ib_modify_qp(struct ib_qp
*ibqp
,
1019 const struct ib_qp_attr
*attr
, int attr_mask
,
1020 enum ib_qp_state cur_state
, enum ib_qp_state new_state
)
1022 struct mlx4_ib_dev
*dev
= to_mdev(ibqp
->device
);
1023 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
1024 struct mlx4_ib_pd
*pd
;
1025 struct mlx4_ib_cq
*send_cq
, *recv_cq
;
1026 struct mlx4_qp_context
*context
;
1027 enum mlx4_qp_optpar optpar
= 0;
1031 context
= kzalloc(sizeof *context
, GFP_KERNEL
);
1035 context
->flags
= cpu_to_be32((to_mlx4_state(new_state
) << 28) |
1036 (to_mlx4_st(ibqp
->qp_type
) << 16));
1038 if (!(attr_mask
& IB_QP_PATH_MIG_STATE
))
1039 context
->flags
|= cpu_to_be32(MLX4_QP_PM_MIGRATED
<< 11);
1041 optpar
|= MLX4_QP_OPTPAR_PM_STATE
;
1042 switch (attr
->path_mig_state
) {
1043 case IB_MIG_MIGRATED
:
1044 context
->flags
|= cpu_to_be32(MLX4_QP_PM_MIGRATED
<< 11);
1047 context
->flags
|= cpu_to_be32(MLX4_QP_PM_REARM
<< 11);
1050 context
->flags
|= cpu_to_be32(MLX4_QP_PM_ARMED
<< 11);
1055 if (ibqp
->qp_type
== IB_QPT_GSI
|| ibqp
->qp_type
== IB_QPT_SMI
)
1056 context
->mtu_msgmax
= (IB_MTU_4096
<< 5) | 11;
1057 else if (ibqp
->qp_type
== IB_QPT_RAW_PACKET
)
1058 context
->mtu_msgmax
= (MLX4_RAW_QP_MTU
<< 5) | MLX4_RAW_QP_MSGMAX
;
1059 else if (ibqp
->qp_type
== IB_QPT_UD
) {
1060 if (qp
->flags
& MLX4_IB_QP_LSO
)
1061 context
->mtu_msgmax
= (IB_MTU_4096
<< 5) |
1062 ilog2(dev
->dev
->caps
.max_gso_sz
);
1064 context
->mtu_msgmax
= (IB_MTU_4096
<< 5) | 12;
1065 } else if (attr_mask
& IB_QP_PATH_MTU
) {
1066 if (attr
->path_mtu
< IB_MTU_256
|| attr
->path_mtu
> IB_MTU_4096
) {
1067 pr_err("path MTU (%u) is invalid\n",
1071 context
->mtu_msgmax
= (attr
->path_mtu
<< 5) |
1072 ilog2(dev
->dev
->caps
.max_msg_sz
);
1076 context
->rq_size_stride
= ilog2(qp
->rq
.wqe_cnt
) << 3;
1077 context
->rq_size_stride
|= qp
->rq
.wqe_shift
- 4;
1080 context
->sq_size_stride
= ilog2(qp
->sq
.wqe_cnt
) << 3;
1081 context
->sq_size_stride
|= qp
->sq
.wqe_shift
- 4;
1083 if (cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
) {
1084 context
->sq_size_stride
|= !!qp
->sq_no_prefetch
<< 7;
1085 context
->xrcd
= cpu_to_be32((u32
) qp
->xrcdn
);
1088 if (qp
->ibqp
.uobject
)
1089 context
->usr_page
= cpu_to_be32(to_mucontext(ibqp
->uobject
->context
)->uar
.index
);
1091 context
->usr_page
= cpu_to_be32(dev
->priv_uar
.index
);
1093 if (attr_mask
& IB_QP_DEST_QPN
)
1094 context
->remote_qpn
= cpu_to_be32(attr
->dest_qp_num
);
1096 if (attr_mask
& IB_QP_PORT
) {
1097 if (cur_state
== IB_QPS_SQD
&& new_state
== IB_QPS_SQD
&&
1098 !(attr_mask
& IB_QP_AV
)) {
1099 mlx4_set_sched(&context
->pri_path
, attr
->port_num
);
1100 optpar
|= MLX4_QP_OPTPAR_SCHED_QUEUE
;
1104 if (cur_state
== IB_QPS_INIT
&& new_state
== IB_QPS_RTR
) {
1105 if (dev
->counters
[qp
->port
- 1] != -1) {
1106 context
->pri_path
.counter_index
=
1107 dev
->counters
[qp
->port
- 1];
1108 optpar
|= MLX4_QP_OPTPAR_COUNTER_INDEX
;
1110 context
->pri_path
.counter_index
= 0xff;
1113 if (attr_mask
& IB_QP_PKEY_INDEX
) {
1114 context
->pri_path
.pkey_index
= attr
->pkey_index
;
1115 optpar
|= MLX4_QP_OPTPAR_PKEY_INDEX
;
1118 if (attr_mask
& IB_QP_AV
) {
1119 if (mlx4_set_path(dev
, &attr
->ah_attr
, &context
->pri_path
,
1120 attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
))
1123 optpar
|= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH
|
1124 MLX4_QP_OPTPAR_SCHED_QUEUE
);
1127 if (attr_mask
& IB_QP_TIMEOUT
) {
1128 context
->pri_path
.ackto
|= attr
->timeout
<< 3;
1129 optpar
|= MLX4_QP_OPTPAR_ACK_TIMEOUT
;
1132 if (attr_mask
& IB_QP_ALT_PATH
) {
1133 if (attr
->alt_port_num
== 0 ||
1134 attr
->alt_port_num
> dev
->dev
->caps
.num_ports
)
1137 if (attr
->alt_pkey_index
>=
1138 dev
->dev
->caps
.pkey_table_len
[attr
->alt_port_num
])
1141 if (mlx4_set_path(dev
, &attr
->alt_ah_attr
, &context
->alt_path
,
1142 attr
->alt_port_num
))
1145 context
->alt_path
.pkey_index
= attr
->alt_pkey_index
;
1146 context
->alt_path
.ackto
= attr
->alt_timeout
<< 3;
1147 optpar
|= MLX4_QP_OPTPAR_ALT_ADDR_PATH
;
1151 get_cqs(qp
, &send_cq
, &recv_cq
);
1152 context
->pd
= cpu_to_be32(pd
->pdn
);
1153 context
->cqn_send
= cpu_to_be32(send_cq
->mcq
.cqn
);
1154 context
->cqn_recv
= cpu_to_be32(recv_cq
->mcq
.cqn
);
1155 context
->params1
= cpu_to_be32(MLX4_IB_ACK_REQ_FREQ
<< 28);
1157 /* Set "fast registration enabled" for all kernel QPs */
1158 if (!qp
->ibqp
.uobject
)
1159 context
->params1
|= cpu_to_be32(1 << 11);
1161 if (attr_mask
& IB_QP_RNR_RETRY
) {
1162 context
->params1
|= cpu_to_be32(attr
->rnr_retry
<< 13);
1163 optpar
|= MLX4_QP_OPTPAR_RNR_RETRY
;
1166 if (attr_mask
& IB_QP_RETRY_CNT
) {
1167 context
->params1
|= cpu_to_be32(attr
->retry_cnt
<< 16);
1168 optpar
|= MLX4_QP_OPTPAR_RETRY_COUNT
;
1171 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
) {
1172 if (attr
->max_rd_atomic
)
1174 cpu_to_be32(fls(attr
->max_rd_atomic
- 1) << 21);
1175 optpar
|= MLX4_QP_OPTPAR_SRA_MAX
;
1178 if (attr_mask
& IB_QP_SQ_PSN
)
1179 context
->next_send_psn
= cpu_to_be32(attr
->sq_psn
);
1181 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
) {
1182 if (attr
->max_dest_rd_atomic
)
1184 cpu_to_be32(fls(attr
->max_dest_rd_atomic
- 1) << 21);
1185 optpar
|= MLX4_QP_OPTPAR_RRA_MAX
;
1188 if (attr_mask
& (IB_QP_ACCESS_FLAGS
| IB_QP_MAX_DEST_RD_ATOMIC
)) {
1189 context
->params2
|= to_mlx4_access_flags(qp
, attr
, attr_mask
);
1190 optpar
|= MLX4_QP_OPTPAR_RWE
| MLX4_QP_OPTPAR_RRE
| MLX4_QP_OPTPAR_RAE
;
1194 context
->params2
|= cpu_to_be32(MLX4_QP_BIT_RIC
);
1196 if (attr_mask
& IB_QP_MIN_RNR_TIMER
) {
1197 context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->min_rnr_timer
<< 24);
1198 optpar
|= MLX4_QP_OPTPAR_RNR_TIMEOUT
;
1200 if (attr_mask
& IB_QP_RQ_PSN
)
1201 context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->rq_psn
);
1203 if (attr_mask
& IB_QP_QKEY
) {
1204 context
->qkey
= cpu_to_be32(attr
->qkey
);
1205 optpar
|= MLX4_QP_OPTPAR_Q_KEY
;
1209 context
->srqn
= cpu_to_be32(1 << 24 | to_msrq(ibqp
->srq
)->msrq
.srqn
);
1211 if (qp
->rq
.wqe_cnt
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
)
1212 context
->db_rec_addr
= cpu_to_be64(qp
->db
.dma
);
1214 if (cur_state
== IB_QPS_INIT
&&
1215 new_state
== IB_QPS_RTR
&&
1216 (ibqp
->qp_type
== IB_QPT_GSI
|| ibqp
->qp_type
== IB_QPT_SMI
||
1217 ibqp
->qp_type
== IB_QPT_UD
||
1218 ibqp
->qp_type
== IB_QPT_RAW_PACKET
)) {
1219 context
->pri_path
.sched_queue
= (qp
->port
- 1) << 6;
1220 if (is_qp0(dev
, qp
))
1221 context
->pri_path
.sched_queue
|= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE
;
1223 context
->pri_path
.sched_queue
|= MLX4_IB_DEFAULT_SCHED_QUEUE
;
1226 if (cur_state
== IB_QPS_RTS
&& new_state
== IB_QPS_SQD
&&
1227 attr_mask
& IB_QP_EN_SQD_ASYNC_NOTIFY
&& attr
->en_sqd_async_notify
)
1232 if (!ibqp
->uobject
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
)
1233 context
->rlkey
|= (1 << 4);
1236 * Before passing a kernel QP to the HW, make sure that the
1237 * ownership bits of the send queue are set and the SQ
1238 * headroom is stamped so that the hardware doesn't start
1239 * processing stale work requests.
1241 if (!ibqp
->uobject
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
) {
1242 struct mlx4_wqe_ctrl_seg
*ctrl
;
1245 for (i
= 0; i
< qp
->sq
.wqe_cnt
; ++i
) {
1246 ctrl
= get_send_wqe(qp
, i
);
1247 ctrl
->owner_opcode
= cpu_to_be32(1 << 31);
1248 if (qp
->sq_max_wqes_per_wr
== 1)
1249 ctrl
->fence_size
= 1 << (qp
->sq
.wqe_shift
- 4);
1251 stamp_send_wqe(qp
, i
, 1 << qp
->sq
.wqe_shift
);
1255 err
= mlx4_qp_modify(dev
->dev
, &qp
->mtt
, to_mlx4_state(cur_state
),
1256 to_mlx4_state(new_state
), context
, optpar
,
1257 sqd_event
, &qp
->mqp
);
1261 qp
->state
= new_state
;
1263 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
1264 qp
->atomic_rd_en
= attr
->qp_access_flags
;
1265 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
1266 qp
->resp_depth
= attr
->max_dest_rd_atomic
;
1267 if (attr_mask
& IB_QP_PORT
) {
1268 qp
->port
= attr
->port_num
;
1269 update_mcg_macs(dev
, qp
);
1271 if (attr_mask
& IB_QP_ALT_PATH
)
1272 qp
->alt_port
= attr
->alt_port_num
;
1274 if (is_sqp(dev
, qp
))
1275 store_sqp_attrs(to_msqp(qp
), attr
, attr_mask
);
1278 * If we moved QP0 to RTR, bring the IB link up; if we moved
1279 * QP0 to RESET or ERROR, bring the link back down.
1281 if (is_qp0(dev
, qp
)) {
1282 if (cur_state
!= IB_QPS_RTR
&& new_state
== IB_QPS_RTR
)
1283 if (mlx4_INIT_PORT(dev
->dev
, qp
->port
))
1284 pr_warn("INIT_PORT failed for port %d\n",
1287 if (cur_state
!= IB_QPS_RESET
&& cur_state
!= IB_QPS_ERR
&&
1288 (new_state
== IB_QPS_RESET
|| new_state
== IB_QPS_ERR
))
1289 mlx4_CLOSE_PORT(dev
->dev
, qp
->port
);
1293 * If we moved a kernel QP to RESET, clean up all old CQ
1294 * entries and reinitialize the QP.
1296 if (new_state
== IB_QPS_RESET
&& !ibqp
->uobject
) {
1297 mlx4_ib_cq_clean(recv_cq
, qp
->mqp
.qpn
,
1298 ibqp
->srq
? to_msrq(ibqp
->srq
): NULL
);
1299 if (send_cq
!= recv_cq
)
1300 mlx4_ib_cq_clean(send_cq
, qp
->mqp
.qpn
, NULL
);
1306 qp
->sq_next_wqe
= 0;
1316 int mlx4_ib_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
1317 int attr_mask
, struct ib_udata
*udata
)
1319 struct mlx4_ib_dev
*dev
= to_mdev(ibqp
->device
);
1320 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
1321 enum ib_qp_state cur_state
, new_state
;
1324 mutex_lock(&qp
->mutex
);
1326 cur_state
= attr_mask
& IB_QP_CUR_STATE
? attr
->cur_qp_state
: qp
->state
;
1327 new_state
= attr_mask
& IB_QP_STATE
? attr
->qp_state
: cur_state
;
1329 if (!ib_modify_qp_is_ok(cur_state
, new_state
, ibqp
->qp_type
, attr_mask
))
1332 if ((attr_mask
& IB_QP_PORT
) &&
1333 (attr
->port_num
== 0 || attr
->port_num
> dev
->dev
->caps
.num_ports
)) {
1337 if ((attr_mask
& IB_QP_PORT
) && (ibqp
->qp_type
== IB_QPT_RAW_PACKET
) &&
1338 (rdma_port_get_link_layer(&dev
->ib_dev
, attr
->port_num
) !=
1339 IB_LINK_LAYER_ETHERNET
))
1342 if (attr_mask
& IB_QP_PKEY_INDEX
) {
1343 int p
= attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
;
1344 if (attr
->pkey_index
>= dev
->dev
->caps
.pkey_table_len
[p
])
1348 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
&&
1349 attr
->max_rd_atomic
> dev
->dev
->caps
.max_qp_init_rdma
) {
1353 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
&&
1354 attr
->max_dest_rd_atomic
> dev
->dev
->caps
.max_qp_dest_rdma
) {
1358 if (cur_state
== new_state
&& cur_state
== IB_QPS_RESET
) {
1363 err
= __mlx4_ib_modify_qp(ibqp
, attr
, attr_mask
, cur_state
, new_state
);
1366 mutex_unlock(&qp
->mutex
);
1370 static int build_mlx_header(struct mlx4_ib_sqp
*sqp
, struct ib_send_wr
*wr
,
1371 void *wqe
, unsigned *mlx_seg_len
)
1373 struct ib_device
*ib_dev
= sqp
->qp
.ibqp
.device
;
1374 struct mlx4_wqe_mlx_seg
*mlx
= wqe
;
1375 struct mlx4_wqe_inline_seg
*inl
= wqe
+ sizeof *mlx
;
1376 struct mlx4_ib_ah
*ah
= to_mah(wr
->wr
.ud
.ah
);
1389 for (i
= 0; i
< wr
->num_sge
; ++i
)
1390 send_size
+= wr
->sg_list
[i
].length
;
1392 is_eth
= rdma_port_get_link_layer(sqp
->qp
.ibqp
.device
, sqp
->qp
.port
) == IB_LINK_LAYER_ETHERNET
;
1393 is_grh
= mlx4_ib_ah_grh_present(ah
);
1395 ib_get_cached_gid(ib_dev
, be32_to_cpu(ah
->av
.ib
.port_pd
) >> 24,
1396 ah
->av
.ib
.gid_index
, &sgid
);
1397 vlan
= rdma_get_vlan_id(&sgid
);
1398 is_vlan
= vlan
< 0x1000;
1400 ib_ud_header_init(send_size
, !is_eth
, is_eth
, is_vlan
, is_grh
, 0, &sqp
->ud_header
);
1403 sqp
->ud_header
.lrh
.service_level
=
1404 be32_to_cpu(ah
->av
.ib
.sl_tclass_flowlabel
) >> 28;
1405 sqp
->ud_header
.lrh
.destination_lid
= ah
->av
.ib
.dlid
;
1406 sqp
->ud_header
.lrh
.source_lid
= cpu_to_be16(ah
->av
.ib
.g_slid
& 0x7f);
1410 sqp
->ud_header
.grh
.traffic_class
=
1411 (be32_to_cpu(ah
->av
.ib
.sl_tclass_flowlabel
) >> 20) & 0xff;
1412 sqp
->ud_header
.grh
.flow_label
=
1413 ah
->av
.ib
.sl_tclass_flowlabel
& cpu_to_be32(0xfffff);
1414 sqp
->ud_header
.grh
.hop_limit
= ah
->av
.ib
.hop_limit
;
1415 ib_get_cached_gid(ib_dev
, be32_to_cpu(ah
->av
.ib
.port_pd
) >> 24,
1416 ah
->av
.ib
.gid_index
, &sqp
->ud_header
.grh
.source_gid
);
1417 memcpy(sqp
->ud_header
.grh
.destination_gid
.raw
,
1418 ah
->av
.ib
.dgid
, 16);
1421 mlx
->flags
&= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE
);
1424 mlx
->flags
|= cpu_to_be32((!sqp
->qp
.ibqp
.qp_num
? MLX4_WQE_MLX_VL15
: 0) |
1425 (sqp
->ud_header
.lrh
.destination_lid
==
1426 IB_LID_PERMISSIVE
? MLX4_WQE_MLX_SLR
: 0) |
1427 (sqp
->ud_header
.lrh
.service_level
<< 8));
1428 mlx
->rlid
= sqp
->ud_header
.lrh
.destination_lid
;
1431 switch (wr
->opcode
) {
1433 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY
;
1434 sqp
->ud_header
.immediate_present
= 0;
1436 case IB_WR_SEND_WITH_IMM
:
1437 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE
;
1438 sqp
->ud_header
.immediate_present
= 1;
1439 sqp
->ud_header
.immediate_data
= wr
->ex
.imm_data
;
1447 u16 pcp
= (be32_to_cpu(ah
->av
.ib
.sl_tclass_flowlabel
) >> 29) << 13;
1449 mlx
->sched_prio
= cpu_to_be16(pcp
);
1451 memcpy(sqp
->ud_header
.eth
.dmac_h
, ah
->av
.eth
.mac
, 6);
1452 /* FIXME: cache smac value? */
1453 smac
= to_mdev(sqp
->qp
.ibqp
.device
)->iboe
.netdevs
[sqp
->qp
.port
- 1]->dev_addr
;
1454 memcpy(sqp
->ud_header
.eth
.smac_h
, smac
, 6);
1455 if (!memcmp(sqp
->ud_header
.eth
.smac_h
, sqp
->ud_header
.eth
.dmac_h
, 6))
1456 mlx
->flags
|= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK
);
1458 sqp
->ud_header
.eth
.type
= cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE
);
1460 sqp
->ud_header
.vlan
.type
= cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE
);
1461 sqp
->ud_header
.vlan
.tag
= cpu_to_be16(vlan
| pcp
);
1464 sqp
->ud_header
.lrh
.virtual_lane
= !sqp
->qp
.ibqp
.qp_num
? 15 : 0;
1465 if (sqp
->ud_header
.lrh
.destination_lid
== IB_LID_PERMISSIVE
)
1466 sqp
->ud_header
.lrh
.source_lid
= IB_LID_PERMISSIVE
;
1468 sqp
->ud_header
.bth
.solicited_event
= !!(wr
->send_flags
& IB_SEND_SOLICITED
);
1469 if (!sqp
->qp
.ibqp
.qp_num
)
1470 ib_get_cached_pkey(ib_dev
, sqp
->qp
.port
, sqp
->pkey_index
, &pkey
);
1472 ib_get_cached_pkey(ib_dev
, sqp
->qp
.port
, wr
->wr
.ud
.pkey_index
, &pkey
);
1473 sqp
->ud_header
.bth
.pkey
= cpu_to_be16(pkey
);
1474 sqp
->ud_header
.bth
.destination_qpn
= cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1475 sqp
->ud_header
.bth
.psn
= cpu_to_be32((sqp
->send_psn
++) & ((1 << 24) - 1));
1476 sqp
->ud_header
.deth
.qkey
= cpu_to_be32(wr
->wr
.ud
.remote_qkey
& 0x80000000 ?
1477 sqp
->qkey
: wr
->wr
.ud
.remote_qkey
);
1478 sqp
->ud_header
.deth
.source_qpn
= cpu_to_be32(sqp
->qp
.ibqp
.qp_num
);
1480 header_size
= ib_ud_header_pack(&sqp
->ud_header
, sqp
->header_buf
);
1483 pr_err("built UD header of size %d:\n", header_size
);
1484 for (i
= 0; i
< header_size
/ 4; ++i
) {
1486 pr_err(" [%02x] ", i
* 4);
1488 be32_to_cpu(((__be32
*) sqp
->header_buf
)[i
]));
1489 if ((i
+ 1) % 8 == 0)
1496 * Inline data segments may not cross a 64 byte boundary. If
1497 * our UD header is bigger than the space available up to the
1498 * next 64 byte boundary in the WQE, use two inline data
1499 * segments to hold the UD header.
1501 spc
= MLX4_INLINE_ALIGN
-
1502 ((unsigned long) (inl
+ 1) & (MLX4_INLINE_ALIGN
- 1));
1503 if (header_size
<= spc
) {
1504 inl
->byte_count
= cpu_to_be32(1 << 31 | header_size
);
1505 memcpy(inl
+ 1, sqp
->header_buf
, header_size
);
1508 inl
->byte_count
= cpu_to_be32(1 << 31 | spc
);
1509 memcpy(inl
+ 1, sqp
->header_buf
, spc
);
1511 inl
= (void *) (inl
+ 1) + spc
;
1512 memcpy(inl
+ 1, sqp
->header_buf
+ spc
, header_size
- spc
);
1514 * Need a barrier here to make sure all the data is
1515 * visible before the byte_count field is set.
1516 * Otherwise the HCA prefetcher could grab the 64-byte
1517 * chunk with this inline segment and get a valid (!=
1518 * 0xffffffff) byte count but stale data, and end up
1519 * generating a packet with bad headers.
1521 * The first inline segment's byte_count field doesn't
1522 * need a barrier, because it comes after a
1523 * control/MLX segment and therefore is at an offset
1527 inl
->byte_count
= cpu_to_be32(1 << 31 | (header_size
- spc
));
1532 ALIGN(i
* sizeof (struct mlx4_wqe_inline_seg
) + header_size
, 16);
1536 static int mlx4_wq_overflow(struct mlx4_ib_wq
*wq
, int nreq
, struct ib_cq
*ib_cq
)
1539 struct mlx4_ib_cq
*cq
;
1541 cur
= wq
->head
- wq
->tail
;
1542 if (likely(cur
+ nreq
< wq
->max_post
))
1546 spin_lock(&cq
->lock
);
1547 cur
= wq
->head
- wq
->tail
;
1548 spin_unlock(&cq
->lock
);
1550 return cur
+ nreq
>= wq
->max_post
;
1553 static __be32
convert_access(int acc
)
1555 return (acc
& IB_ACCESS_REMOTE_ATOMIC
? cpu_to_be32(MLX4_WQE_FMR_PERM_ATOMIC
) : 0) |
1556 (acc
& IB_ACCESS_REMOTE_WRITE
? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_WRITE
) : 0) |
1557 (acc
& IB_ACCESS_REMOTE_READ
? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_READ
) : 0) |
1558 (acc
& IB_ACCESS_LOCAL_WRITE
? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE
) : 0) |
1559 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ
);
1562 static void set_fmr_seg(struct mlx4_wqe_fmr_seg
*fseg
, struct ib_send_wr
*wr
)
1564 struct mlx4_ib_fast_reg_page_list
*mfrpl
= to_mfrpl(wr
->wr
.fast_reg
.page_list
);
1567 for (i
= 0; i
< wr
->wr
.fast_reg
.page_list_len
; ++i
)
1568 mfrpl
->mapped_page_list
[i
] =
1569 cpu_to_be64(wr
->wr
.fast_reg
.page_list
->page_list
[i
] |
1570 MLX4_MTT_FLAG_PRESENT
);
1572 fseg
->flags
= convert_access(wr
->wr
.fast_reg
.access_flags
);
1573 fseg
->mem_key
= cpu_to_be32(wr
->wr
.fast_reg
.rkey
);
1574 fseg
->buf_list
= cpu_to_be64(mfrpl
->map
);
1575 fseg
->start_addr
= cpu_to_be64(wr
->wr
.fast_reg
.iova_start
);
1576 fseg
->reg_len
= cpu_to_be64(wr
->wr
.fast_reg
.length
);
1577 fseg
->offset
= 0; /* XXX -- is this just for ZBVA? */
1578 fseg
->page_size
= cpu_to_be32(wr
->wr
.fast_reg
.page_shift
);
1579 fseg
->reserved
[0] = 0;
1580 fseg
->reserved
[1] = 0;
1583 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg
*iseg
, u32 rkey
)
1586 iseg
->mem_key
= cpu_to_be32(rkey
);
1591 static __always_inline
void set_raddr_seg(struct mlx4_wqe_raddr_seg
*rseg
,
1592 u64 remote_addr
, u32 rkey
)
1594 rseg
->raddr
= cpu_to_be64(remote_addr
);
1595 rseg
->rkey
= cpu_to_be32(rkey
);
1599 static void set_atomic_seg(struct mlx4_wqe_atomic_seg
*aseg
, struct ib_send_wr
*wr
)
1601 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1602 aseg
->swap_add
= cpu_to_be64(wr
->wr
.atomic
.swap
);
1603 aseg
->compare
= cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1604 } else if (wr
->opcode
== IB_WR_MASKED_ATOMIC_FETCH_AND_ADD
) {
1605 aseg
->swap_add
= cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1606 aseg
->compare
= cpu_to_be64(wr
->wr
.atomic
.compare_add_mask
);
1608 aseg
->swap_add
= cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1614 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg
*aseg
,
1615 struct ib_send_wr
*wr
)
1617 aseg
->swap_add
= cpu_to_be64(wr
->wr
.atomic
.swap
);
1618 aseg
->swap_add_mask
= cpu_to_be64(wr
->wr
.atomic
.swap_mask
);
1619 aseg
->compare
= cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1620 aseg
->compare_mask
= cpu_to_be64(wr
->wr
.atomic
.compare_add_mask
);
1623 static void set_datagram_seg(struct mlx4_wqe_datagram_seg
*dseg
,
1624 struct ib_send_wr
*wr
)
1626 memcpy(dseg
->av
, &to_mah(wr
->wr
.ud
.ah
)->av
, sizeof (struct mlx4_av
));
1627 dseg
->dqpn
= cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1628 dseg
->qkey
= cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1629 dseg
->vlan
= to_mah(wr
->wr
.ud
.ah
)->av
.eth
.vlan
;
1630 memcpy(dseg
->mac
, to_mah(wr
->wr
.ud
.ah
)->av
.eth
.mac
, 6);
1633 static void set_mlx_icrc_seg(void *dseg
)
1636 struct mlx4_wqe_inline_seg
*iseg
= dseg
;
1641 * Need a barrier here before writing the byte_count field to
1642 * make sure that all the data is visible before the
1643 * byte_count field is set. Otherwise, if the segment begins
1644 * a new cacheline, the HCA prefetcher could grab the 64-byte
1645 * chunk and get a valid (!= * 0xffffffff) byte count but
1646 * stale data, and end up sending the wrong data.
1650 iseg
->byte_count
= cpu_to_be32((1 << 31) | 4);
1653 static void set_data_seg(struct mlx4_wqe_data_seg
*dseg
, struct ib_sge
*sg
)
1655 dseg
->lkey
= cpu_to_be32(sg
->lkey
);
1656 dseg
->addr
= cpu_to_be64(sg
->addr
);
1659 * Need a barrier here before writing the byte_count field to
1660 * make sure that all the data is visible before the
1661 * byte_count field is set. Otherwise, if the segment begins
1662 * a new cacheline, the HCA prefetcher could grab the 64-byte
1663 * chunk and get a valid (!= * 0xffffffff) byte count but
1664 * stale data, and end up sending the wrong data.
1668 dseg
->byte_count
= cpu_to_be32(sg
->length
);
1671 static void __set_data_seg(struct mlx4_wqe_data_seg
*dseg
, struct ib_sge
*sg
)
1673 dseg
->byte_count
= cpu_to_be32(sg
->length
);
1674 dseg
->lkey
= cpu_to_be32(sg
->lkey
);
1675 dseg
->addr
= cpu_to_be64(sg
->addr
);
1678 static int build_lso_seg(struct mlx4_wqe_lso_seg
*wqe
, struct ib_send_wr
*wr
,
1679 struct mlx4_ib_qp
*qp
, unsigned *lso_seg_len
,
1680 __be32
*lso_hdr_sz
, __be32
*blh
)
1682 unsigned halign
= ALIGN(sizeof *wqe
+ wr
->wr
.ud
.hlen
, 16);
1684 if (unlikely(halign
> MLX4_IB_CACHE_LINE_SIZE
))
1685 *blh
= cpu_to_be32(1 << 6);
1687 if (unlikely(!(qp
->flags
& MLX4_IB_QP_LSO
) &&
1688 wr
->num_sge
> qp
->sq
.max_gs
- (halign
>> 4)))
1691 memcpy(wqe
->header
, wr
->wr
.ud
.header
, wr
->wr
.ud
.hlen
);
1693 *lso_hdr_sz
= cpu_to_be32((wr
->wr
.ud
.mss
- wr
->wr
.ud
.hlen
) << 16 |
1695 *lso_seg_len
= halign
;
1699 static __be32
send_ieth(struct ib_send_wr
*wr
)
1701 switch (wr
->opcode
) {
1702 case IB_WR_SEND_WITH_IMM
:
1703 case IB_WR_RDMA_WRITE_WITH_IMM
:
1704 return wr
->ex
.imm_data
;
1706 case IB_WR_SEND_WITH_INV
:
1707 return cpu_to_be32(wr
->ex
.invalidate_rkey
);
1714 int mlx4_ib_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1715 struct ib_send_wr
**bad_wr
)
1717 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
1719 struct mlx4_wqe_ctrl_seg
*ctrl
;
1720 struct mlx4_wqe_data_seg
*dseg
;
1721 unsigned long flags
;
1725 int uninitialized_var(stamp
);
1726 int uninitialized_var(size
);
1727 unsigned uninitialized_var(seglen
);
1730 __be32
uninitialized_var(lso_hdr_sz
);
1734 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1736 ind
= qp
->sq_next_wqe
;
1738 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1742 if (mlx4_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1748 if (unlikely(wr
->num_sge
> qp
->sq
.max_gs
)) {
1754 ctrl
= wqe
= get_send_wqe(qp
, ind
& (qp
->sq
.wqe_cnt
- 1));
1755 qp
->sq
.wrid
[(qp
->sq
.head
+ nreq
) & (qp
->sq
.wqe_cnt
- 1)] = wr
->wr_id
;
1758 (wr
->send_flags
& IB_SEND_SIGNALED
?
1759 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE
) : 0) |
1760 (wr
->send_flags
& IB_SEND_SOLICITED
?
1761 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED
) : 0) |
1762 ((wr
->send_flags
& IB_SEND_IP_CSUM
) ?
1763 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM
|
1764 MLX4_WQE_CTRL_TCP_UDP_CSUM
) : 0) |
1767 ctrl
->imm
= send_ieth(wr
);
1769 wqe
+= sizeof *ctrl
;
1770 size
= sizeof *ctrl
/ 16;
1772 switch (ibqp
->qp_type
) {
1775 switch (wr
->opcode
) {
1776 case IB_WR_ATOMIC_CMP_AND_SWP
:
1777 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1778 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD
:
1779 set_raddr_seg(wqe
, wr
->wr
.atomic
.remote_addr
,
1780 wr
->wr
.atomic
.rkey
);
1781 wqe
+= sizeof (struct mlx4_wqe_raddr_seg
);
1783 set_atomic_seg(wqe
, wr
);
1784 wqe
+= sizeof (struct mlx4_wqe_atomic_seg
);
1786 size
+= (sizeof (struct mlx4_wqe_raddr_seg
) +
1787 sizeof (struct mlx4_wqe_atomic_seg
)) / 16;
1791 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP
:
1792 set_raddr_seg(wqe
, wr
->wr
.atomic
.remote_addr
,
1793 wr
->wr
.atomic
.rkey
);
1794 wqe
+= sizeof (struct mlx4_wqe_raddr_seg
);
1796 set_masked_atomic_seg(wqe
, wr
);
1797 wqe
+= sizeof (struct mlx4_wqe_masked_atomic_seg
);
1799 size
+= (sizeof (struct mlx4_wqe_raddr_seg
) +
1800 sizeof (struct mlx4_wqe_masked_atomic_seg
)) / 16;
1804 case IB_WR_RDMA_READ
:
1805 case IB_WR_RDMA_WRITE
:
1806 case IB_WR_RDMA_WRITE_WITH_IMM
:
1807 set_raddr_seg(wqe
, wr
->wr
.rdma
.remote_addr
,
1809 wqe
+= sizeof (struct mlx4_wqe_raddr_seg
);
1810 size
+= sizeof (struct mlx4_wqe_raddr_seg
) / 16;
1813 case IB_WR_LOCAL_INV
:
1814 ctrl
->srcrb_flags
|=
1815 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER
);
1816 set_local_inv_seg(wqe
, wr
->ex
.invalidate_rkey
);
1817 wqe
+= sizeof (struct mlx4_wqe_local_inval_seg
);
1818 size
+= sizeof (struct mlx4_wqe_local_inval_seg
) / 16;
1821 case IB_WR_FAST_REG_MR
:
1822 ctrl
->srcrb_flags
|=
1823 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER
);
1824 set_fmr_seg(wqe
, wr
);
1825 wqe
+= sizeof (struct mlx4_wqe_fmr_seg
);
1826 size
+= sizeof (struct mlx4_wqe_fmr_seg
) / 16;
1830 /* No extra segments required for sends */
1836 set_datagram_seg(wqe
, wr
);
1837 wqe
+= sizeof (struct mlx4_wqe_datagram_seg
);
1838 size
+= sizeof (struct mlx4_wqe_datagram_seg
) / 16;
1840 if (wr
->opcode
== IB_WR_LSO
) {
1841 err
= build_lso_seg(wqe
, wr
, qp
, &seglen
, &lso_hdr_sz
, &blh
);
1842 if (unlikely(err
)) {
1846 lso_wqe
= (__be32
*) wqe
;
1848 size
+= seglen
/ 16;
1854 err
= build_mlx_header(to_msqp(qp
), wr
, ctrl
, &seglen
);
1855 if (unlikely(err
)) {
1860 size
+= seglen
/ 16;
1868 * Write data segments in reverse order, so as to
1869 * overwrite cacheline stamp last within each
1870 * cacheline. This avoids issues with WQE
1875 dseg
+= wr
->num_sge
- 1;
1876 size
+= wr
->num_sge
* (sizeof (struct mlx4_wqe_data_seg
) / 16);
1878 /* Add one more inline data segment for ICRC for MLX sends */
1879 if (unlikely(qp
->ibqp
.qp_type
== IB_QPT_SMI
||
1880 qp
->ibqp
.qp_type
== IB_QPT_GSI
)) {
1881 set_mlx_icrc_seg(dseg
+ 1);
1882 size
+= sizeof (struct mlx4_wqe_data_seg
) / 16;
1885 for (i
= wr
->num_sge
- 1; i
>= 0; --i
, --dseg
)
1886 set_data_seg(dseg
, wr
->sg_list
+ i
);
1889 * Possibly overwrite stamping in cacheline with LSO
1890 * segment only after making sure all data segments
1894 *lso_wqe
= lso_hdr_sz
;
1896 ctrl
->fence_size
= (wr
->send_flags
& IB_SEND_FENCE
?
1897 MLX4_WQE_CTRL_FENCE
: 0) | size
;
1900 * Make sure descriptor is fully written before
1901 * setting ownership bit (because HW can start
1902 * executing as soon as we do).
1906 if (wr
->opcode
< 0 || wr
->opcode
>= ARRAY_SIZE(mlx4_ib_opcode
)) {
1912 ctrl
->owner_opcode
= mlx4_ib_opcode
[wr
->opcode
] |
1913 (ind
& qp
->sq
.wqe_cnt
? cpu_to_be32(1 << 31) : 0) | blh
;
1915 stamp
= ind
+ qp
->sq_spare_wqes
;
1916 ind
+= DIV_ROUND_UP(size
* 16, 1U << qp
->sq
.wqe_shift
);
1919 * We can improve latency by not stamping the last
1920 * send queue WQE until after ringing the doorbell, so
1921 * only stamp here if there are still more WQEs to post.
1923 * Same optimization applies to padding with NOP wqe
1924 * in case of WQE shrinking (used to prevent wrap-around
1925 * in the middle of WR).
1928 stamp_send_wqe(qp
, stamp
, size
* 16);
1929 ind
= pad_wraparound(qp
, ind
);
1935 qp
->sq
.head
+= nreq
;
1938 * Make sure that descriptors are written before
1943 writel(qp
->doorbell_qpn
,
1944 to_mdev(ibqp
->device
)->uar_map
+ MLX4_SEND_DOORBELL
);
1947 * Make sure doorbells don't leak out of SQ spinlock
1948 * and reach the HCA out of order.
1952 stamp_send_wqe(qp
, stamp
, size
* 16);
1954 ind
= pad_wraparound(qp
, ind
);
1955 qp
->sq_next_wqe
= ind
;
1958 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
1963 int mlx4_ib_post_recv(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
1964 struct ib_recv_wr
**bad_wr
)
1966 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
1967 struct mlx4_wqe_data_seg
*scat
;
1968 unsigned long flags
;
1974 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
1976 ind
= qp
->rq
.head
& (qp
->rq
.wqe_cnt
- 1);
1978 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1979 if (mlx4_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
1985 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
1991 scat
= get_recv_wqe(qp
, ind
);
1993 for (i
= 0; i
< wr
->num_sge
; ++i
)
1994 __set_data_seg(scat
+ i
, wr
->sg_list
+ i
);
1996 if (i
< qp
->rq
.max_gs
) {
1997 scat
[i
].byte_count
= 0;
1998 scat
[i
].lkey
= cpu_to_be32(MLX4_INVALID_LKEY
);
2002 qp
->rq
.wrid
[ind
] = wr
->wr_id
;
2004 ind
= (ind
+ 1) & (qp
->rq
.wqe_cnt
- 1);
2009 qp
->rq
.head
+= nreq
;
2012 * Make sure that descriptors are written before
2017 *qp
->db
.db
= cpu_to_be32(qp
->rq
.head
& 0xffff);
2020 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
2025 static inline enum ib_qp_state
to_ib_qp_state(enum mlx4_qp_state mlx4_state
)
2027 switch (mlx4_state
) {
2028 case MLX4_QP_STATE_RST
: return IB_QPS_RESET
;
2029 case MLX4_QP_STATE_INIT
: return IB_QPS_INIT
;
2030 case MLX4_QP_STATE_RTR
: return IB_QPS_RTR
;
2031 case MLX4_QP_STATE_RTS
: return IB_QPS_RTS
;
2032 case MLX4_QP_STATE_SQ_DRAINING
:
2033 case MLX4_QP_STATE_SQD
: return IB_QPS_SQD
;
2034 case MLX4_QP_STATE_SQER
: return IB_QPS_SQE
;
2035 case MLX4_QP_STATE_ERR
: return IB_QPS_ERR
;
2040 static inline enum ib_mig_state
to_ib_mig_state(int mlx4_mig_state
)
2042 switch (mlx4_mig_state
) {
2043 case MLX4_QP_PM_ARMED
: return IB_MIG_ARMED
;
2044 case MLX4_QP_PM_REARM
: return IB_MIG_REARM
;
2045 case MLX4_QP_PM_MIGRATED
: return IB_MIG_MIGRATED
;
2050 static int to_ib_qp_access_flags(int mlx4_flags
)
2054 if (mlx4_flags
& MLX4_QP_BIT_RRE
)
2055 ib_flags
|= IB_ACCESS_REMOTE_READ
;
2056 if (mlx4_flags
& MLX4_QP_BIT_RWE
)
2057 ib_flags
|= IB_ACCESS_REMOTE_WRITE
;
2058 if (mlx4_flags
& MLX4_QP_BIT_RAE
)
2059 ib_flags
|= IB_ACCESS_REMOTE_ATOMIC
;
2064 static void to_ib_ah_attr(struct mlx4_ib_dev
*ibdev
, struct ib_ah_attr
*ib_ah_attr
,
2065 struct mlx4_qp_path
*path
)
2067 struct mlx4_dev
*dev
= ibdev
->dev
;
2070 memset(ib_ah_attr
, 0, sizeof *ib_ah_attr
);
2071 ib_ah_attr
->port_num
= path
->sched_queue
& 0x40 ? 2 : 1;
2073 if (ib_ah_attr
->port_num
== 0 || ib_ah_attr
->port_num
> dev
->caps
.num_ports
)
2076 is_eth
= rdma_port_get_link_layer(&ibdev
->ib_dev
, ib_ah_attr
->port_num
) ==
2077 IB_LINK_LAYER_ETHERNET
;
2079 ib_ah_attr
->sl
= ((path
->sched_queue
>> 3) & 0x7) |
2080 ((path
->sched_queue
& 4) << 1);
2082 ib_ah_attr
->sl
= (path
->sched_queue
>> 2) & 0xf;
2084 ib_ah_attr
->dlid
= be16_to_cpu(path
->rlid
);
2085 ib_ah_attr
->src_path_bits
= path
->grh_mylmc
& 0x7f;
2086 ib_ah_attr
->static_rate
= path
->static_rate
? path
->static_rate
- 5 : 0;
2087 ib_ah_attr
->ah_flags
= (path
->grh_mylmc
& (1 << 7)) ? IB_AH_GRH
: 0;
2088 if (ib_ah_attr
->ah_flags
) {
2089 ib_ah_attr
->grh
.sgid_index
= path
->mgid_index
;
2090 ib_ah_attr
->grh
.hop_limit
= path
->hop_limit
;
2091 ib_ah_attr
->grh
.traffic_class
=
2092 (be32_to_cpu(path
->tclass_flowlabel
) >> 20) & 0xff;
2093 ib_ah_attr
->grh
.flow_label
=
2094 be32_to_cpu(path
->tclass_flowlabel
) & 0xfffff;
2095 memcpy(ib_ah_attr
->grh
.dgid
.raw
,
2096 path
->rgid
, sizeof ib_ah_attr
->grh
.dgid
.raw
);
2100 int mlx4_ib_query_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*qp_attr
, int qp_attr_mask
,
2101 struct ib_qp_init_attr
*qp_init_attr
)
2103 struct mlx4_ib_dev
*dev
= to_mdev(ibqp
->device
);
2104 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
2105 struct mlx4_qp_context context
;
2109 mutex_lock(&qp
->mutex
);
2111 if (qp
->state
== IB_QPS_RESET
) {
2112 qp_attr
->qp_state
= IB_QPS_RESET
;
2116 err
= mlx4_qp_query(dev
->dev
, &qp
->mqp
, &context
);
2122 mlx4_state
= be32_to_cpu(context
.flags
) >> 28;
2124 qp
->state
= to_ib_qp_state(mlx4_state
);
2125 qp_attr
->qp_state
= qp
->state
;
2126 qp_attr
->path_mtu
= context
.mtu_msgmax
>> 5;
2127 qp_attr
->path_mig_state
=
2128 to_ib_mig_state((be32_to_cpu(context
.flags
) >> 11) & 0x3);
2129 qp_attr
->qkey
= be32_to_cpu(context
.qkey
);
2130 qp_attr
->rq_psn
= be32_to_cpu(context
.rnr_nextrecvpsn
) & 0xffffff;
2131 qp_attr
->sq_psn
= be32_to_cpu(context
.next_send_psn
) & 0xffffff;
2132 qp_attr
->dest_qp_num
= be32_to_cpu(context
.remote_qpn
) & 0xffffff;
2133 qp_attr
->qp_access_flags
=
2134 to_ib_qp_access_flags(be32_to_cpu(context
.params2
));
2136 if (qp
->ibqp
.qp_type
== IB_QPT_RC
|| qp
->ibqp
.qp_type
== IB_QPT_UC
) {
2137 to_ib_ah_attr(dev
, &qp_attr
->ah_attr
, &context
.pri_path
);
2138 to_ib_ah_attr(dev
, &qp_attr
->alt_ah_attr
, &context
.alt_path
);
2139 qp_attr
->alt_pkey_index
= context
.alt_path
.pkey_index
& 0x7f;
2140 qp_attr
->alt_port_num
= qp_attr
->alt_ah_attr
.port_num
;
2143 qp_attr
->pkey_index
= context
.pri_path
.pkey_index
& 0x7f;
2144 if (qp_attr
->qp_state
== IB_QPS_INIT
)
2145 qp_attr
->port_num
= qp
->port
;
2147 qp_attr
->port_num
= context
.pri_path
.sched_queue
& 0x40 ? 2 : 1;
2149 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2150 qp_attr
->sq_draining
= mlx4_state
== MLX4_QP_STATE_SQ_DRAINING
;
2152 qp_attr
->max_rd_atomic
= 1 << ((be32_to_cpu(context
.params1
) >> 21) & 0x7);
2154 qp_attr
->max_dest_rd_atomic
=
2155 1 << ((be32_to_cpu(context
.params2
) >> 21) & 0x7);
2156 qp_attr
->min_rnr_timer
=
2157 (be32_to_cpu(context
.rnr_nextrecvpsn
) >> 24) & 0x1f;
2158 qp_attr
->timeout
= context
.pri_path
.ackto
>> 3;
2159 qp_attr
->retry_cnt
= (be32_to_cpu(context
.params1
) >> 16) & 0x7;
2160 qp_attr
->rnr_retry
= (be32_to_cpu(context
.params1
) >> 13) & 0x7;
2161 qp_attr
->alt_timeout
= context
.alt_path
.ackto
>> 3;
2164 qp_attr
->cur_qp_state
= qp_attr
->qp_state
;
2165 qp_attr
->cap
.max_recv_wr
= qp
->rq
.wqe_cnt
;
2166 qp_attr
->cap
.max_recv_sge
= qp
->rq
.max_gs
;
2168 if (!ibqp
->uobject
) {
2169 qp_attr
->cap
.max_send_wr
= qp
->sq
.wqe_cnt
;
2170 qp_attr
->cap
.max_send_sge
= qp
->sq
.max_gs
;
2172 qp_attr
->cap
.max_send_wr
= 0;
2173 qp_attr
->cap
.max_send_sge
= 0;
2177 * We don't support inline sends for kernel QPs (yet), and we
2178 * don't know what userspace's value should be.
2180 qp_attr
->cap
.max_inline_data
= 0;
2182 qp_init_attr
->cap
= qp_attr
->cap
;
2184 qp_init_attr
->create_flags
= 0;
2185 if (qp
->flags
& MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK
)
2186 qp_init_attr
->create_flags
|= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
;
2188 if (qp
->flags
& MLX4_IB_QP_LSO
)
2189 qp_init_attr
->create_flags
|= IB_QP_CREATE_IPOIB_UD_LSO
;
2192 mutex_unlock(&qp
->mutex
);