2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/sched.h>
42 #include <rdma/ib_user_verbs.h>
43 #include <rdma/ib_addr.h>
44 #include <rdma/ib_cache.h>
45 #include <linux/mlx5/vport.h>
46 #include <rdma/ib_smi.h>
47 #include <rdma/ib_umem.h>
51 #define DRIVER_NAME "mlx5_ib"
52 #define DRIVER_VERSION "2.2-1"
53 #define DRIVER_RELDATE "Feb 2014"
55 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
56 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
57 MODULE_LICENSE("Dual BSD/GPL");
58 MODULE_VERSION(DRIVER_VERSION
);
60 static int deprecated_prof_sel
= 2;
61 module_param_named(prof_sel
, deprecated_prof_sel
, int, 0444);
62 MODULE_PARM_DESC(prof_sel
, "profile selector. Deprecated here. Moved to module mlx5_core");
64 static char mlx5_version
[] =
65 DRIVER_NAME
": Mellanox Connect-IB Infiniband driver v"
66 DRIVER_VERSION
" (" DRIVER_RELDATE
")\n";
69 MLX5_ATOMIC_SIZE_QP_8BYTES
= 1 << 3,
72 static enum rdma_link_layer
73 mlx5_port_type_cap_to_rdma_ll(int port_type_cap
)
75 switch (port_type_cap
) {
76 case MLX5_CAP_PORT_TYPE_IB
:
77 return IB_LINK_LAYER_INFINIBAND
;
78 case MLX5_CAP_PORT_TYPE_ETH
:
79 return IB_LINK_LAYER_ETHERNET
;
81 return IB_LINK_LAYER_UNSPECIFIED
;
85 static enum rdma_link_layer
86 mlx5_ib_port_link_layer(struct ib_device
*device
, u8 port_num
)
88 struct mlx5_ib_dev
*dev
= to_mdev(device
);
89 int port_type_cap
= MLX5_CAP_GEN(dev
->mdev
, port_type
);
91 return mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
94 static int mlx5_netdev_event(struct notifier_block
*this,
95 unsigned long event
, void *ptr
)
97 struct net_device
*ndev
= netdev_notifier_info_to_dev(ptr
);
98 struct mlx5_ib_dev
*ibdev
= container_of(this, struct mlx5_ib_dev
,
101 if ((event
!= NETDEV_UNREGISTER
) && (event
!= NETDEV_REGISTER
))
104 write_lock(&ibdev
->roce
.netdev_lock
);
105 if (ndev
->dev
.parent
== &ibdev
->mdev
->pdev
->dev
)
106 ibdev
->roce
.netdev
= (event
== NETDEV_UNREGISTER
) ? NULL
: ndev
;
107 write_unlock(&ibdev
->roce
.netdev_lock
);
112 static struct net_device
*mlx5_ib_get_netdev(struct ib_device
*device
,
115 struct mlx5_ib_dev
*ibdev
= to_mdev(device
);
116 struct net_device
*ndev
;
118 /* Ensure ndev does not disappear before we invoke dev_hold()
120 read_lock(&ibdev
->roce
.netdev_lock
);
121 ndev
= ibdev
->roce
.netdev
;
124 read_unlock(&ibdev
->roce
.netdev_lock
);
129 static int mlx5_query_port_roce(struct ib_device
*device
, u8 port_num
,
130 struct ib_port_attr
*props
)
132 struct mlx5_ib_dev
*dev
= to_mdev(device
);
133 struct net_device
*ndev
;
134 enum ib_mtu ndev_ib_mtu
;
137 memset(props
, 0, sizeof(*props
));
139 props
->port_cap_flags
|= IB_PORT_CM_SUP
;
140 props
->port_cap_flags
|= IB_PORT_IP_BASED_GIDS
;
142 props
->gid_tbl_len
= MLX5_CAP_ROCE(dev
->mdev
,
143 roce_address_table_size
);
144 props
->max_mtu
= IB_MTU_4096
;
145 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_msg
);
146 props
->pkey_tbl_len
= 1;
147 props
->state
= IB_PORT_DOWN
;
148 props
->phys_state
= 3;
150 mlx5_query_nic_vport_qkey_viol_cntr(dev
->mdev
, &qkey_viol_cntr
);
151 props
->qkey_viol_cntr
= qkey_viol_cntr
;
153 ndev
= mlx5_ib_get_netdev(device
, port_num
);
157 if (netif_running(ndev
) && netif_carrier_ok(ndev
)) {
158 props
->state
= IB_PORT_ACTIVE
;
159 props
->phys_state
= 5;
162 ndev_ib_mtu
= iboe_get_mtu(ndev
->mtu
);
166 props
->active_mtu
= min(props
->max_mtu
, ndev_ib_mtu
);
168 props
->active_width
= IB_WIDTH_4X
; /* TODO */
169 props
->active_speed
= IB_SPEED_QDR
; /* TODO */
174 static void ib_gid_to_mlx5_roce_addr(const union ib_gid
*gid
,
175 const struct ib_gid_attr
*attr
,
178 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
179 char *mlx5_addr_l3_addr
= MLX5_ADDR_OF(roce_addr_layout
, mlx5_addr
,
181 void *mlx5_addr_mac
= MLX5_ADDR_OF(roce_addr_layout
, mlx5_addr
,
187 ether_addr_copy(mlx5_addr_mac
, attr
->ndev
->dev_addr
);
189 if (is_vlan_dev(attr
->ndev
)) {
190 MLX5_SET_RA(mlx5_addr
, vlan_valid
, 1);
191 MLX5_SET_RA(mlx5_addr
, vlan_id
, vlan_dev_vlan_id(attr
->ndev
));
194 switch (attr
->gid_type
) {
196 MLX5_SET_RA(mlx5_addr
, roce_version
, MLX5_ROCE_VERSION_1
);
198 case IB_GID_TYPE_ROCE_UDP_ENCAP
:
199 MLX5_SET_RA(mlx5_addr
, roce_version
, MLX5_ROCE_VERSION_2
);
206 if (attr
->gid_type
!= IB_GID_TYPE_IB
) {
207 if (ipv6_addr_v4mapped((void *)gid
))
208 MLX5_SET_RA(mlx5_addr
, roce_l3_type
,
209 MLX5_ROCE_L3_TYPE_IPV4
);
211 MLX5_SET_RA(mlx5_addr
, roce_l3_type
,
212 MLX5_ROCE_L3_TYPE_IPV6
);
215 if ((attr
->gid_type
== IB_GID_TYPE_IB
) ||
216 !ipv6_addr_v4mapped((void *)gid
))
217 memcpy(mlx5_addr_l3_addr
, gid
, sizeof(*gid
));
219 memcpy(&mlx5_addr_l3_addr
[12], &gid
->raw
[12], 4);
222 static int set_roce_addr(struct ib_device
*device
, u8 port_num
,
224 const union ib_gid
*gid
,
225 const struct ib_gid_attr
*attr
)
227 struct mlx5_ib_dev
*dev
= to_mdev(device
);
228 u32 in
[MLX5_ST_SZ_DW(set_roce_address_in
)];
229 u32 out
[MLX5_ST_SZ_DW(set_roce_address_out
)];
230 void *in_addr
= MLX5_ADDR_OF(set_roce_address_in
, in
, roce_address
);
231 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(device
, port_num
);
233 if (ll
!= IB_LINK_LAYER_ETHERNET
)
236 memset(in
, 0, sizeof(in
));
238 ib_gid_to_mlx5_roce_addr(gid
, attr
, in_addr
);
240 MLX5_SET(set_roce_address_in
, in
, roce_address_index
, index
);
241 MLX5_SET(set_roce_address_in
, in
, opcode
, MLX5_CMD_OP_SET_ROCE_ADDRESS
);
243 memset(out
, 0, sizeof(out
));
244 return mlx5_cmd_exec(dev
->mdev
, in
, sizeof(in
), out
, sizeof(out
));
247 static int mlx5_ib_add_gid(struct ib_device
*device
, u8 port_num
,
248 unsigned int index
, const union ib_gid
*gid
,
249 const struct ib_gid_attr
*attr
,
250 __always_unused
void **context
)
252 return set_roce_addr(device
, port_num
, index
, gid
, attr
);
255 static int mlx5_ib_del_gid(struct ib_device
*device
, u8 port_num
,
256 unsigned int index
, __always_unused
void **context
)
258 return set_roce_addr(device
, port_num
, index
, NULL
, NULL
);
261 __be16
mlx5_get_roce_udp_sport(struct mlx5_ib_dev
*dev
, u8 port_num
,
264 struct ib_gid_attr attr
;
267 if (ib_get_cached_gid(&dev
->ib_dev
, port_num
, index
, &gid
, &attr
))
275 if (attr
.gid_type
!= IB_GID_TYPE_ROCE_UDP_ENCAP
)
278 return cpu_to_be16(MLX5_CAP_ROCE(dev
->mdev
, r_roce_min_src_udp_port
));
281 static int mlx5_use_mad_ifc(struct mlx5_ib_dev
*dev
)
283 return !dev
->mdev
->issi
;
287 MLX5_VPORT_ACCESS_METHOD_MAD
,
288 MLX5_VPORT_ACCESS_METHOD_HCA
,
289 MLX5_VPORT_ACCESS_METHOD_NIC
,
292 static int mlx5_get_vport_access_method(struct ib_device
*ibdev
)
294 if (mlx5_use_mad_ifc(to_mdev(ibdev
)))
295 return MLX5_VPORT_ACCESS_METHOD_MAD
;
297 if (mlx5_ib_port_link_layer(ibdev
, 1) ==
298 IB_LINK_LAYER_ETHERNET
)
299 return MLX5_VPORT_ACCESS_METHOD_NIC
;
301 return MLX5_VPORT_ACCESS_METHOD_HCA
;
304 static void get_atomic_caps(struct mlx5_ib_dev
*dev
,
305 struct ib_device_attr
*props
)
308 u8 atomic_operations
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_operations
);
309 u8 atomic_size_qp
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_size_qp
);
310 u8 atomic_req_8B_endianness_mode
=
311 MLX5_CAP_ATOMIC(dev
->mdev
, atomic_req_8B_endianess_mode
);
313 /* Check if HW supports 8 bytes standard atomic operations and capable
314 * of host endianness respond
316 tmp
= MLX5_ATOMIC_OPS_CMP_SWAP
| MLX5_ATOMIC_OPS_FETCH_ADD
;
317 if (((atomic_operations
& tmp
) == tmp
) &&
318 (atomic_size_qp
& MLX5_ATOMIC_SIZE_QP_8BYTES
) &&
319 (atomic_req_8B_endianness_mode
)) {
320 props
->atomic_cap
= IB_ATOMIC_HCA
;
322 props
->atomic_cap
= IB_ATOMIC_NONE
;
326 static int mlx5_query_system_image_guid(struct ib_device
*ibdev
,
327 __be64
*sys_image_guid
)
329 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
330 struct mlx5_core_dev
*mdev
= dev
->mdev
;
334 switch (mlx5_get_vport_access_method(ibdev
)) {
335 case MLX5_VPORT_ACCESS_METHOD_MAD
:
336 return mlx5_query_mad_ifc_system_image_guid(ibdev
,
339 case MLX5_VPORT_ACCESS_METHOD_HCA
:
340 err
= mlx5_query_hca_vport_system_image_guid(mdev
, &tmp
);
343 case MLX5_VPORT_ACCESS_METHOD_NIC
:
344 err
= mlx5_query_nic_vport_system_image_guid(mdev
, &tmp
);
352 *sys_image_guid
= cpu_to_be64(tmp
);
358 static int mlx5_query_max_pkeys(struct ib_device
*ibdev
,
361 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
362 struct mlx5_core_dev
*mdev
= dev
->mdev
;
364 switch (mlx5_get_vport_access_method(ibdev
)) {
365 case MLX5_VPORT_ACCESS_METHOD_MAD
:
366 return mlx5_query_mad_ifc_max_pkeys(ibdev
, max_pkeys
);
368 case MLX5_VPORT_ACCESS_METHOD_HCA
:
369 case MLX5_VPORT_ACCESS_METHOD_NIC
:
370 *max_pkeys
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
,
379 static int mlx5_query_vendor_id(struct ib_device
*ibdev
,
382 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
384 switch (mlx5_get_vport_access_method(ibdev
)) {
385 case MLX5_VPORT_ACCESS_METHOD_MAD
:
386 return mlx5_query_mad_ifc_vendor_id(ibdev
, vendor_id
);
388 case MLX5_VPORT_ACCESS_METHOD_HCA
:
389 case MLX5_VPORT_ACCESS_METHOD_NIC
:
390 return mlx5_core_query_vendor_id(dev
->mdev
, vendor_id
);
397 static int mlx5_query_node_guid(struct mlx5_ib_dev
*dev
,
403 switch (mlx5_get_vport_access_method(&dev
->ib_dev
)) {
404 case MLX5_VPORT_ACCESS_METHOD_MAD
:
405 return mlx5_query_mad_ifc_node_guid(dev
, node_guid
);
407 case MLX5_VPORT_ACCESS_METHOD_HCA
:
408 err
= mlx5_query_hca_vport_node_guid(dev
->mdev
, &tmp
);
411 case MLX5_VPORT_ACCESS_METHOD_NIC
:
412 err
= mlx5_query_nic_vport_node_guid(dev
->mdev
, &tmp
);
420 *node_guid
= cpu_to_be64(tmp
);
425 struct mlx5_reg_node_desc
{
429 static int mlx5_query_node_desc(struct mlx5_ib_dev
*dev
, char *node_desc
)
431 struct mlx5_reg_node_desc in
;
433 if (mlx5_use_mad_ifc(dev
))
434 return mlx5_query_mad_ifc_node_desc(dev
, node_desc
);
436 memset(&in
, 0, sizeof(in
));
438 return mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), node_desc
,
439 sizeof(struct mlx5_reg_node_desc
),
440 MLX5_REG_NODE_DESC
, 0, 0);
443 static int mlx5_ib_query_device(struct ib_device
*ibdev
,
444 struct ib_device_attr
*props
,
445 struct ib_udata
*uhw
)
447 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
448 struct mlx5_core_dev
*mdev
= dev
->mdev
;
452 u64 min_page_size
= 1ull << MLX5_CAP_GEN(mdev
, log_pg_sz
);
454 if (uhw
->inlen
|| uhw
->outlen
)
457 memset(props
, 0, sizeof(*props
));
458 err
= mlx5_query_system_image_guid(ibdev
,
459 &props
->sys_image_guid
);
463 err
= mlx5_query_max_pkeys(ibdev
, &props
->max_pkeys
);
467 err
= mlx5_query_vendor_id(ibdev
, &props
->vendor_id
);
471 props
->fw_ver
= ((u64
)fw_rev_maj(dev
->mdev
) << 32) |
472 (fw_rev_min(dev
->mdev
) << 16) |
473 fw_rev_sub(dev
->mdev
);
474 props
->device_cap_flags
= IB_DEVICE_CHANGE_PHY_PORT
|
475 IB_DEVICE_PORT_ACTIVE_EVENT
|
476 IB_DEVICE_SYS_IMAGE_GUID
|
477 IB_DEVICE_RC_RNR_NAK_GEN
;
479 if (MLX5_CAP_GEN(mdev
, pkv
))
480 props
->device_cap_flags
|= IB_DEVICE_BAD_PKEY_CNTR
;
481 if (MLX5_CAP_GEN(mdev
, qkv
))
482 props
->device_cap_flags
|= IB_DEVICE_BAD_QKEY_CNTR
;
483 if (MLX5_CAP_GEN(mdev
, apm
))
484 props
->device_cap_flags
|= IB_DEVICE_AUTO_PATH_MIG
;
485 if (MLX5_CAP_GEN(mdev
, xrc
))
486 props
->device_cap_flags
|= IB_DEVICE_XRC
;
487 props
->device_cap_flags
|= IB_DEVICE_MEM_MGT_EXTENSIONS
;
488 if (MLX5_CAP_GEN(mdev
, sho
)) {
489 props
->device_cap_flags
|= IB_DEVICE_SIGNATURE_HANDOVER
;
490 /* At this stage no support for signature handover */
491 props
->sig_prot_cap
= IB_PROT_T10DIF_TYPE_1
|
492 IB_PROT_T10DIF_TYPE_2
|
493 IB_PROT_T10DIF_TYPE_3
;
494 props
->sig_guard_cap
= IB_GUARD_T10DIF_CRC
|
495 IB_GUARD_T10DIF_CSUM
;
497 if (MLX5_CAP_GEN(mdev
, block_lb_mc
))
498 props
->device_cap_flags
|= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK
;
500 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) &&
501 (MLX5_CAP_ETH(dev
->mdev
, csum_cap
)))
502 props
->device_cap_flags
|= IB_DEVICE_RAW_IP_CSUM
;
504 props
->vendor_part_id
= mdev
->pdev
->device
;
505 props
->hw_ver
= mdev
->pdev
->revision
;
507 props
->max_mr_size
= ~0ull;
508 props
->page_size_cap
= ~(min_page_size
- 1);
509 props
->max_qp
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp
);
510 props
->max_qp_wr
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp_sz
);
511 max_rq_sg
= MLX5_CAP_GEN(mdev
, max_wqe_sz_rq
) /
512 sizeof(struct mlx5_wqe_data_seg
);
513 max_sq_sg
= (MLX5_CAP_GEN(mdev
, max_wqe_sz_sq
) -
514 sizeof(struct mlx5_wqe_ctrl_seg
)) /
515 sizeof(struct mlx5_wqe_data_seg
);
516 props
->max_sge
= min(max_rq_sg
, max_sq_sg
);
517 props
->max_sge_rd
= props
->max_sge
;
518 props
->max_cq
= 1 << MLX5_CAP_GEN(mdev
, log_max_cq
);
519 props
->max_cqe
= (1 << MLX5_CAP_GEN(mdev
, log_max_cq_sz
)) - 1;
520 props
->max_mr
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
521 props
->max_pd
= 1 << MLX5_CAP_GEN(mdev
, log_max_pd
);
522 props
->max_qp_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_req_qp
);
523 props
->max_qp_init_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_res_qp
);
524 props
->max_srq
= 1 << MLX5_CAP_GEN(mdev
, log_max_srq
);
525 props
->max_srq_wr
= (1 << MLX5_CAP_GEN(mdev
, log_max_srq_sz
)) - 1;
526 props
->local_ca_ack_delay
= MLX5_CAP_GEN(mdev
, local_ca_ack_delay
);
527 props
->max_res_rd_atom
= props
->max_qp_rd_atom
* props
->max_qp
;
528 props
->max_srq_sge
= max_rq_sg
- 1;
529 props
->max_fast_reg_page_list_len
= (unsigned int)-1;
530 get_atomic_caps(dev
, props
);
531 props
->masked_atomic_cap
= IB_ATOMIC_NONE
;
532 props
->max_mcast_grp
= 1 << MLX5_CAP_GEN(mdev
, log_max_mcg
);
533 props
->max_mcast_qp_attach
= MLX5_CAP_GEN(mdev
, max_qp_mcg
);
534 props
->max_total_mcast_qp_attach
= props
->max_mcast_qp_attach
*
535 props
->max_mcast_grp
;
536 props
->max_map_per_fmr
= INT_MAX
; /* no limit in ConnectIB */
537 props
->hca_core_clock
= MLX5_CAP_GEN(mdev
, device_frequency_khz
);
538 props
->timestamp_mask
= 0x7FFFFFFFFFFFFFFFULL
;
540 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
541 if (MLX5_CAP_GEN(mdev
, pg
))
542 props
->device_cap_flags
|= IB_DEVICE_ON_DEMAND_PAGING
;
543 props
->odp_caps
= dev
->odp_caps
;
546 if (MLX5_CAP_GEN(mdev
, cd
))
547 props
->device_cap_flags
|= IB_DEVICE_CROSS_CHANNEL
;
553 MLX5_IB_WIDTH_1X
= 1 << 0,
554 MLX5_IB_WIDTH_2X
= 1 << 1,
555 MLX5_IB_WIDTH_4X
= 1 << 2,
556 MLX5_IB_WIDTH_8X
= 1 << 3,
557 MLX5_IB_WIDTH_12X
= 1 << 4
560 static int translate_active_width(struct ib_device
*ibdev
, u8 active_width
,
563 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
566 if (active_width
& MLX5_IB_WIDTH_1X
) {
567 *ib_width
= IB_WIDTH_1X
;
568 } else if (active_width
& MLX5_IB_WIDTH_2X
) {
569 mlx5_ib_dbg(dev
, "active_width %d is not supported by IB spec\n",
572 } else if (active_width
& MLX5_IB_WIDTH_4X
) {
573 *ib_width
= IB_WIDTH_4X
;
574 } else if (active_width
& MLX5_IB_WIDTH_8X
) {
575 *ib_width
= IB_WIDTH_8X
;
576 } else if (active_width
& MLX5_IB_WIDTH_12X
) {
577 *ib_width
= IB_WIDTH_12X
;
579 mlx5_ib_dbg(dev
, "Invalid active_width %d\n",
587 static int mlx5_mtu_to_ib_mtu(int mtu
)
596 pr_warn("invalid mtu\n");
606 __IB_MAX_VL_0_14
= 5,
609 enum mlx5_vl_hw_cap
{
621 static int translate_max_vl_num(struct ib_device
*ibdev
, u8 vl_hw_cap
,
626 *max_vl_num
= __IB_MAX_VL_0
;
629 *max_vl_num
= __IB_MAX_VL_0_1
;
632 *max_vl_num
= __IB_MAX_VL_0_3
;
635 *max_vl_num
= __IB_MAX_VL_0_7
;
637 case MLX5_VL_HW_0_14
:
638 *max_vl_num
= __IB_MAX_VL_0_14
;
648 static int mlx5_query_hca_port(struct ib_device
*ibdev
, u8 port
,
649 struct ib_port_attr
*props
)
651 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
652 struct mlx5_core_dev
*mdev
= dev
->mdev
;
653 struct mlx5_hca_vport_context
*rep
;
657 u8 ib_link_width_oper
;
660 rep
= kzalloc(sizeof(*rep
), GFP_KERNEL
);
666 memset(props
, 0, sizeof(*props
));
668 err
= mlx5_query_hca_vport_context(mdev
, 0, port
, 0, rep
);
672 props
->lid
= rep
->lid
;
673 props
->lmc
= rep
->lmc
;
674 props
->sm_lid
= rep
->sm_lid
;
675 props
->sm_sl
= rep
->sm_sl
;
676 props
->state
= rep
->vport_state
;
677 props
->phys_state
= rep
->port_physical_state
;
678 props
->port_cap_flags
= rep
->cap_mask1
;
679 props
->gid_tbl_len
= mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev
, gid_table_size
));
680 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(mdev
, log_max_msg
);
681 props
->pkey_tbl_len
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
, pkey_table_size
));
682 props
->bad_pkey_cntr
= rep
->pkey_violation_counter
;
683 props
->qkey_viol_cntr
= rep
->qkey_violation_counter
;
684 props
->subnet_timeout
= rep
->subnet_timeout
;
685 props
->init_type_reply
= rep
->init_type_reply
;
687 err
= mlx5_query_port_link_width_oper(mdev
, &ib_link_width_oper
, port
);
691 err
= translate_active_width(ibdev
, ib_link_width_oper
,
692 &props
->active_width
);
695 err
= mlx5_query_port_proto_oper(mdev
, &props
->active_speed
, MLX5_PTYS_IB
,
700 mlx5_query_port_max_mtu(mdev
, &max_mtu
, port
);
702 props
->max_mtu
= mlx5_mtu_to_ib_mtu(max_mtu
);
704 mlx5_query_port_oper_mtu(mdev
, &oper_mtu
, port
);
706 props
->active_mtu
= mlx5_mtu_to_ib_mtu(oper_mtu
);
708 err
= mlx5_query_port_vl_hw_cap(mdev
, &vl_hw_cap
, port
);
712 err
= translate_max_vl_num(ibdev
, vl_hw_cap
,
719 int mlx5_ib_query_port(struct ib_device
*ibdev
, u8 port
,
720 struct ib_port_attr
*props
)
722 switch (mlx5_get_vport_access_method(ibdev
)) {
723 case MLX5_VPORT_ACCESS_METHOD_MAD
:
724 return mlx5_query_mad_ifc_port(ibdev
, port
, props
);
726 case MLX5_VPORT_ACCESS_METHOD_HCA
:
727 return mlx5_query_hca_port(ibdev
, port
, props
);
729 case MLX5_VPORT_ACCESS_METHOD_NIC
:
730 return mlx5_query_port_roce(ibdev
, port
, props
);
737 static int mlx5_ib_query_gid(struct ib_device
*ibdev
, u8 port
, int index
,
740 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
741 struct mlx5_core_dev
*mdev
= dev
->mdev
;
743 switch (mlx5_get_vport_access_method(ibdev
)) {
744 case MLX5_VPORT_ACCESS_METHOD_MAD
:
745 return mlx5_query_mad_ifc_gids(ibdev
, port
, index
, gid
);
747 case MLX5_VPORT_ACCESS_METHOD_HCA
:
748 return mlx5_query_hca_vport_gid(mdev
, 0, port
, 0, index
, gid
);
756 static int mlx5_ib_query_pkey(struct ib_device
*ibdev
, u8 port
, u16 index
,
759 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
760 struct mlx5_core_dev
*mdev
= dev
->mdev
;
762 switch (mlx5_get_vport_access_method(ibdev
)) {
763 case MLX5_VPORT_ACCESS_METHOD_MAD
:
764 return mlx5_query_mad_ifc_pkey(ibdev
, port
, index
, pkey
);
766 case MLX5_VPORT_ACCESS_METHOD_HCA
:
767 case MLX5_VPORT_ACCESS_METHOD_NIC
:
768 return mlx5_query_hca_vport_pkey(mdev
, 0, port
, 0, index
,
775 static int mlx5_ib_modify_device(struct ib_device
*ibdev
, int mask
,
776 struct ib_device_modify
*props
)
778 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
779 struct mlx5_reg_node_desc in
;
780 struct mlx5_reg_node_desc out
;
783 if (mask
& ~IB_DEVICE_MODIFY_NODE_DESC
)
786 if (!(mask
& IB_DEVICE_MODIFY_NODE_DESC
))
790 * If possible, pass node desc to FW, so it can generate
791 * a 144 trap. If cmd fails, just ignore.
793 memcpy(&in
, props
->node_desc
, 64);
794 err
= mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), &out
,
795 sizeof(out
), MLX5_REG_NODE_DESC
, 0, 1);
799 memcpy(ibdev
->node_desc
, props
->node_desc
, 64);
804 static int mlx5_ib_modify_port(struct ib_device
*ibdev
, u8 port
, int mask
,
805 struct ib_port_modify
*props
)
807 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
808 struct ib_port_attr attr
;
812 mutex_lock(&dev
->cap_mask_mutex
);
814 err
= mlx5_ib_query_port(ibdev
, port
, &attr
);
818 tmp
= (attr
.port_cap_flags
| props
->set_port_cap_mask
) &
819 ~props
->clr_port_cap_mask
;
821 err
= mlx5_set_port_caps(dev
->mdev
, port
, tmp
);
824 mutex_unlock(&dev
->cap_mask_mutex
);
828 static struct ib_ucontext
*mlx5_ib_alloc_ucontext(struct ib_device
*ibdev
,
829 struct ib_udata
*udata
)
831 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
832 struct mlx5_ib_alloc_ucontext_req_v2 req
= {};
833 struct mlx5_ib_alloc_ucontext_resp resp
= {};
834 struct mlx5_ib_ucontext
*context
;
835 struct mlx5_uuar_info
*uuari
;
836 struct mlx5_uar
*uars
;
846 return ERR_PTR(-EAGAIN
);
848 if (udata
->inlen
< sizeof(struct ib_uverbs_cmd_hdr
))
849 return ERR_PTR(-EINVAL
);
851 reqlen
= udata
->inlen
- sizeof(struct ib_uverbs_cmd_hdr
);
852 if (reqlen
== sizeof(struct mlx5_ib_alloc_ucontext_req
))
854 else if (reqlen
>= sizeof(struct mlx5_ib_alloc_ucontext_req_v2
))
857 return ERR_PTR(-EINVAL
);
859 err
= ib_copy_from_udata(&req
, udata
, min(reqlen
, sizeof(req
)));
864 return ERR_PTR(-EINVAL
);
866 if (req
.total_num_uuars
> MLX5_MAX_UUARS
)
867 return ERR_PTR(-ENOMEM
);
869 if (req
.total_num_uuars
== 0)
870 return ERR_PTR(-EINVAL
);
872 if (req
.comp_mask
|| req
.reserved0
|| req
.reserved1
|| req
.reserved2
)
873 return ERR_PTR(-EOPNOTSUPP
);
875 if (reqlen
> sizeof(req
) &&
876 !ib_is_udata_cleared(udata
, sizeof(req
),
877 reqlen
- sizeof(req
)))
878 return ERR_PTR(-EOPNOTSUPP
);
880 req
.total_num_uuars
= ALIGN(req
.total_num_uuars
,
881 MLX5_NON_FP_BF_REGS_PER_PAGE
);
882 if (req
.num_low_latency_uuars
> req
.total_num_uuars
- 1)
883 return ERR_PTR(-EINVAL
);
885 num_uars
= req
.total_num_uuars
/ MLX5_NON_FP_BF_REGS_PER_PAGE
;
886 gross_uuars
= num_uars
* MLX5_BF_REGS_PER_PAGE
;
887 resp
.qp_tab_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp
);
888 resp
.bf_reg_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_bf_reg_size
);
889 resp
.cache_line_size
= L1_CACHE_BYTES
;
890 resp
.max_sq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
);
891 resp
.max_rq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_rq
);
892 resp
.max_send_wqebb
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
893 resp
.max_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
894 resp
.max_srq_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_srq_sz
);
895 resp
.cqe_version
= min_t(__u8
,
896 (__u8
)MLX5_CAP_GEN(dev
->mdev
, cqe_version
),
897 req
.max_cqe_version
);
898 resp
.response_length
= min(offsetof(typeof(resp
), response_length
) +
899 sizeof(resp
.response_length
), udata
->outlen
);
901 context
= kzalloc(sizeof(*context
), GFP_KERNEL
);
903 return ERR_PTR(-ENOMEM
);
905 uuari
= &context
->uuari
;
906 mutex_init(&uuari
->lock
);
907 uars
= kcalloc(num_uars
, sizeof(*uars
), GFP_KERNEL
);
913 uuari
->bitmap
= kcalloc(BITS_TO_LONGS(gross_uuars
),
914 sizeof(*uuari
->bitmap
),
916 if (!uuari
->bitmap
) {
921 * clear all fast path uuars
923 for (i
= 0; i
< gross_uuars
; i
++) {
925 if (uuarn
== 2 || uuarn
== 3)
926 set_bit(i
, uuari
->bitmap
);
929 uuari
->count
= kcalloc(gross_uuars
, sizeof(*uuari
->count
), GFP_KERNEL
);
935 for (i
= 0; i
< num_uars
; i
++) {
936 err
= mlx5_cmd_alloc_uar(dev
->mdev
, &uars
[i
].index
);
941 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
942 context
->ibucontext
.invalidate_range
= &mlx5_ib_invalidate_range
;
945 INIT_LIST_HEAD(&context
->db_page_list
);
946 mutex_init(&context
->db_page_mutex
);
948 resp
.tot_uuars
= req
.total_num_uuars
;
949 resp
.num_ports
= MLX5_CAP_GEN(dev
->mdev
, num_ports
);
951 if (field_avail(typeof(resp
), cqe_version
, udata
->outlen
))
952 resp
.response_length
+= sizeof(resp
.cqe_version
);
954 if (field_avail(typeof(resp
), hca_core_clock_offset
, udata
->outlen
)) {
956 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET
;
957 resp
.hca_core_clock_offset
=
958 offsetof(struct mlx5_init_seg
, internal_timer_h
) %
960 resp
.response_length
+= sizeof(resp
.hca_core_clock_offset
) +
961 sizeof(resp
.reserved2
) +
962 sizeof(resp
.reserved3
);
965 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
970 uuari
->num_low_latency_uuars
= req
.num_low_latency_uuars
;
972 uuari
->num_uars
= num_uars
;
973 context
->cqe_version
= resp
.cqe_version
;
975 return &context
->ibucontext
;
978 for (i
--; i
>= 0; i
--)
979 mlx5_cmd_free_uar(dev
->mdev
, uars
[i
].index
);
984 kfree(uuari
->bitmap
);
994 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext
*ibcontext
)
996 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
997 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
998 struct mlx5_uuar_info
*uuari
= &context
->uuari
;
1001 for (i
= 0; i
< uuari
->num_uars
; i
++) {
1002 if (mlx5_cmd_free_uar(dev
->mdev
, uuari
->uars
[i
].index
))
1003 mlx5_ib_warn(dev
, "failed to free UAR 0x%x\n", uuari
->uars
[i
].index
);
1006 kfree(uuari
->count
);
1007 kfree(uuari
->bitmap
);
1014 static phys_addr_t
uar_index2pfn(struct mlx5_ib_dev
*dev
, int index
)
1016 return (pci_resource_start(dev
->mdev
->pdev
, 0) >> PAGE_SHIFT
) + index
;
1019 static int get_command(unsigned long offset
)
1021 return (offset
>> MLX5_IB_MMAP_CMD_SHIFT
) & MLX5_IB_MMAP_CMD_MASK
;
1024 static int get_arg(unsigned long offset
)
1026 return offset
& ((1 << MLX5_IB_MMAP_CMD_SHIFT
) - 1);
1029 static int get_index(unsigned long offset
)
1031 return get_arg(offset
);
1034 static int mlx5_ib_mmap(struct ib_ucontext
*ibcontext
, struct vm_area_struct
*vma
)
1036 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1037 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
1038 struct mlx5_uuar_info
*uuari
= &context
->uuari
;
1039 unsigned long command
;
1043 command
= get_command(vma
->vm_pgoff
);
1045 case MLX5_IB_MMAP_REGULAR_PAGE
:
1046 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
1049 idx
= get_index(vma
->vm_pgoff
);
1050 if (idx
>= uuari
->num_uars
)
1053 pfn
= uar_index2pfn(dev
, uuari
->uars
[idx
].index
);
1054 mlx5_ib_dbg(dev
, "uar idx 0x%lx, pfn 0x%llx\n", idx
,
1055 (unsigned long long)pfn
);
1057 vma
->vm_page_prot
= pgprot_writecombine(vma
->vm_page_prot
);
1058 if (io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
1059 PAGE_SIZE
, vma
->vm_page_prot
))
1062 mlx5_ib_dbg(dev
, "mapped WC at 0x%lx, PA 0x%llx\n",
1064 (unsigned long long)pfn
<< PAGE_SHIFT
);
1067 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES
:
1070 case MLX5_IB_MMAP_CORE_CLOCK
:
1071 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
1074 if (vma
->vm_flags
& (VM_WRITE
| VM_EXEC
))
1077 /* Don't expose to user-space information it shouldn't have */
1078 if (PAGE_SIZE
> 4096)
1081 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
1082 pfn
= (dev
->mdev
->iseg_base
+
1083 offsetof(struct mlx5_init_seg
, internal_timer_h
)) >>
1085 if (io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
1086 PAGE_SIZE
, vma
->vm_page_prot
))
1089 mlx5_ib_dbg(dev
, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1091 (unsigned long long)pfn
<< PAGE_SHIFT
);
1101 static struct ib_pd
*mlx5_ib_alloc_pd(struct ib_device
*ibdev
,
1102 struct ib_ucontext
*context
,
1103 struct ib_udata
*udata
)
1105 struct mlx5_ib_alloc_pd_resp resp
;
1106 struct mlx5_ib_pd
*pd
;
1109 pd
= kmalloc(sizeof(*pd
), GFP_KERNEL
);
1111 return ERR_PTR(-ENOMEM
);
1113 err
= mlx5_core_alloc_pd(to_mdev(ibdev
)->mdev
, &pd
->pdn
);
1116 return ERR_PTR(err
);
1121 if (ib_copy_to_udata(udata
, &resp
, sizeof(resp
))) {
1122 mlx5_core_dealloc_pd(to_mdev(ibdev
)->mdev
, pd
->pdn
);
1124 return ERR_PTR(-EFAULT
);
1131 static int mlx5_ib_dealloc_pd(struct ib_pd
*pd
)
1133 struct mlx5_ib_dev
*mdev
= to_mdev(pd
->device
);
1134 struct mlx5_ib_pd
*mpd
= to_mpd(pd
);
1136 mlx5_core_dealloc_pd(mdev
->mdev
, mpd
->pdn
);
1142 static int mlx5_ib_mcg_attach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
1144 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
1147 err
= mlx5_core_attach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
1149 mlx5_ib_warn(dev
, "failed attaching QPN 0x%x, MGID %pI6\n",
1150 ibqp
->qp_num
, gid
->raw
);
1155 static int mlx5_ib_mcg_detach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
1157 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
1160 err
= mlx5_core_detach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
1162 mlx5_ib_warn(dev
, "failed detaching QPN 0x%x, MGID %pI6\n",
1163 ibqp
->qp_num
, gid
->raw
);
1168 static int init_node_data(struct mlx5_ib_dev
*dev
)
1172 err
= mlx5_query_node_desc(dev
, dev
->ib_dev
.node_desc
);
1176 dev
->mdev
->rev_id
= dev
->mdev
->pdev
->revision
;
1178 return mlx5_query_node_guid(dev
, &dev
->ib_dev
.node_guid
);
1181 static ssize_t
show_fw_pages(struct device
*device
, struct device_attribute
*attr
,
1184 struct mlx5_ib_dev
*dev
=
1185 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1187 return sprintf(buf
, "%d\n", dev
->mdev
->priv
.fw_pages
);
1190 static ssize_t
show_reg_pages(struct device
*device
,
1191 struct device_attribute
*attr
, char *buf
)
1193 struct mlx5_ib_dev
*dev
=
1194 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1196 return sprintf(buf
, "%d\n", atomic_read(&dev
->mdev
->priv
.reg_pages
));
1199 static ssize_t
show_hca(struct device
*device
, struct device_attribute
*attr
,
1202 struct mlx5_ib_dev
*dev
=
1203 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1204 return sprintf(buf
, "MT%d\n", dev
->mdev
->pdev
->device
);
1207 static ssize_t
show_fw_ver(struct device
*device
, struct device_attribute
*attr
,
1210 struct mlx5_ib_dev
*dev
=
1211 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1212 return sprintf(buf
, "%d.%d.%d\n", fw_rev_maj(dev
->mdev
),
1213 fw_rev_min(dev
->mdev
), fw_rev_sub(dev
->mdev
));
1216 static ssize_t
show_rev(struct device
*device
, struct device_attribute
*attr
,
1219 struct mlx5_ib_dev
*dev
=
1220 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1221 return sprintf(buf
, "%x\n", dev
->mdev
->rev_id
);
1224 static ssize_t
show_board(struct device
*device
, struct device_attribute
*attr
,
1227 struct mlx5_ib_dev
*dev
=
1228 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1229 return sprintf(buf
, "%.*s\n", MLX5_BOARD_ID_LEN
,
1230 dev
->mdev
->board_id
);
1233 static DEVICE_ATTR(hw_rev
, S_IRUGO
, show_rev
, NULL
);
1234 static DEVICE_ATTR(fw_ver
, S_IRUGO
, show_fw_ver
, NULL
);
1235 static DEVICE_ATTR(hca_type
, S_IRUGO
, show_hca
, NULL
);
1236 static DEVICE_ATTR(board_id
, S_IRUGO
, show_board
, NULL
);
1237 static DEVICE_ATTR(fw_pages
, S_IRUGO
, show_fw_pages
, NULL
);
1238 static DEVICE_ATTR(reg_pages
, S_IRUGO
, show_reg_pages
, NULL
);
1240 static struct device_attribute
*mlx5_class_attributes
[] = {
1246 &dev_attr_reg_pages
,
1249 static void mlx5_ib_event(struct mlx5_core_dev
*dev
, void *context
,
1250 enum mlx5_dev_event event
, unsigned long param
)
1252 struct mlx5_ib_dev
*ibdev
= (struct mlx5_ib_dev
*)context
;
1253 struct ib_event ibev
;
1258 case MLX5_DEV_EVENT_SYS_ERROR
:
1259 ibdev
->ib_active
= false;
1260 ibev
.event
= IB_EVENT_DEVICE_FATAL
;
1263 case MLX5_DEV_EVENT_PORT_UP
:
1264 ibev
.event
= IB_EVENT_PORT_ACTIVE
;
1268 case MLX5_DEV_EVENT_PORT_DOWN
:
1269 ibev
.event
= IB_EVENT_PORT_ERR
;
1273 case MLX5_DEV_EVENT_PORT_INITIALIZED
:
1274 /* not used by ULPs */
1277 case MLX5_DEV_EVENT_LID_CHANGE
:
1278 ibev
.event
= IB_EVENT_LID_CHANGE
;
1282 case MLX5_DEV_EVENT_PKEY_CHANGE
:
1283 ibev
.event
= IB_EVENT_PKEY_CHANGE
;
1287 case MLX5_DEV_EVENT_GUID_CHANGE
:
1288 ibev
.event
= IB_EVENT_GID_CHANGE
;
1292 case MLX5_DEV_EVENT_CLIENT_REREG
:
1293 ibev
.event
= IB_EVENT_CLIENT_REREGISTER
;
1298 ibev
.device
= &ibdev
->ib_dev
;
1299 ibev
.element
.port_num
= port
;
1301 if (port
< 1 || port
> ibdev
->num_ports
) {
1302 mlx5_ib_warn(ibdev
, "warning: event on port %d\n", port
);
1306 if (ibdev
->ib_active
)
1307 ib_dispatch_event(&ibev
);
1310 static void get_ext_port_caps(struct mlx5_ib_dev
*dev
)
1314 for (port
= 1; port
<= MLX5_CAP_GEN(dev
->mdev
, num_ports
); port
++)
1315 mlx5_query_ext_port_caps(dev
, port
);
1318 static int get_port_caps(struct mlx5_ib_dev
*dev
)
1320 struct ib_device_attr
*dprops
= NULL
;
1321 struct ib_port_attr
*pprops
= NULL
;
1324 struct ib_udata uhw
= {.inlen
= 0, .outlen
= 0};
1326 pprops
= kmalloc(sizeof(*pprops
), GFP_KERNEL
);
1330 dprops
= kmalloc(sizeof(*dprops
), GFP_KERNEL
);
1334 err
= mlx5_ib_query_device(&dev
->ib_dev
, dprops
, &uhw
);
1336 mlx5_ib_warn(dev
, "query_device failed %d\n", err
);
1340 for (port
= 1; port
<= MLX5_CAP_GEN(dev
->mdev
, num_ports
); port
++) {
1341 err
= mlx5_ib_query_port(&dev
->ib_dev
, port
, pprops
);
1343 mlx5_ib_warn(dev
, "query_port %d failed %d\n",
1347 dev
->mdev
->port_caps
[port
- 1].pkey_table_len
=
1349 dev
->mdev
->port_caps
[port
- 1].gid_table_len
=
1350 pprops
->gid_tbl_len
;
1351 mlx5_ib_dbg(dev
, "pkey_table_len %d, gid_table_len %d\n",
1352 dprops
->max_pkeys
, pprops
->gid_tbl_len
);
1362 static void destroy_umrc_res(struct mlx5_ib_dev
*dev
)
1366 err
= mlx5_mr_cache_cleanup(dev
);
1368 mlx5_ib_warn(dev
, "mr cache cleanup failed\n");
1370 mlx5_ib_destroy_qp(dev
->umrc
.qp
);
1371 ib_destroy_cq(dev
->umrc
.cq
);
1372 ib_dealloc_pd(dev
->umrc
.pd
);
1379 static int create_umr_res(struct mlx5_ib_dev
*dev
)
1381 struct ib_qp_init_attr
*init_attr
= NULL
;
1382 struct ib_qp_attr
*attr
= NULL
;
1386 struct ib_cq_init_attr cq_attr
= {};
1389 attr
= kzalloc(sizeof(*attr
), GFP_KERNEL
);
1390 init_attr
= kzalloc(sizeof(*init_attr
), GFP_KERNEL
);
1391 if (!attr
|| !init_attr
) {
1396 pd
= ib_alloc_pd(&dev
->ib_dev
);
1398 mlx5_ib_dbg(dev
, "Couldn't create PD for sync UMR QP\n");
1404 cq
= ib_create_cq(&dev
->ib_dev
, mlx5_umr_cq_handler
, NULL
, NULL
,
1407 mlx5_ib_dbg(dev
, "Couldn't create CQ for sync UMR QP\n");
1411 ib_req_notify_cq(cq
, IB_CQ_NEXT_COMP
);
1413 init_attr
->send_cq
= cq
;
1414 init_attr
->recv_cq
= cq
;
1415 init_attr
->sq_sig_type
= IB_SIGNAL_ALL_WR
;
1416 init_attr
->cap
.max_send_wr
= MAX_UMR_WR
;
1417 init_attr
->cap
.max_send_sge
= 1;
1418 init_attr
->qp_type
= MLX5_IB_QPT_REG_UMR
;
1419 init_attr
->port_num
= 1;
1420 qp
= mlx5_ib_create_qp(pd
, init_attr
, NULL
);
1422 mlx5_ib_dbg(dev
, "Couldn't create sync UMR QP\n");
1426 qp
->device
= &dev
->ib_dev
;
1429 qp
->qp_type
= MLX5_IB_QPT_REG_UMR
;
1431 attr
->qp_state
= IB_QPS_INIT
;
1433 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
| IB_QP_PKEY_INDEX
|
1436 mlx5_ib_dbg(dev
, "Couldn't modify UMR QP\n");
1440 memset(attr
, 0, sizeof(*attr
));
1441 attr
->qp_state
= IB_QPS_RTR
;
1442 attr
->path_mtu
= IB_MTU_256
;
1444 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
1446 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rtr\n");
1450 memset(attr
, 0, sizeof(*attr
));
1451 attr
->qp_state
= IB_QPS_RTS
;
1452 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
1454 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rts\n");
1462 sema_init(&dev
->umrc
.sem
, MAX_UMR_WR
);
1463 ret
= mlx5_mr_cache_init(dev
);
1465 mlx5_ib_warn(dev
, "mr cache init failed %d\n", ret
);
1475 mlx5_ib_destroy_qp(qp
);
1489 static int create_dev_resources(struct mlx5_ib_resources
*devr
)
1491 struct ib_srq_init_attr attr
;
1492 struct mlx5_ib_dev
*dev
;
1493 struct ib_cq_init_attr cq_attr
= {.cqe
= 1};
1496 dev
= container_of(devr
, struct mlx5_ib_dev
, devr
);
1498 devr
->p0
= mlx5_ib_alloc_pd(&dev
->ib_dev
, NULL
, NULL
);
1499 if (IS_ERR(devr
->p0
)) {
1500 ret
= PTR_ERR(devr
->p0
);
1503 devr
->p0
->device
= &dev
->ib_dev
;
1504 devr
->p0
->uobject
= NULL
;
1505 atomic_set(&devr
->p0
->usecnt
, 0);
1507 devr
->c0
= mlx5_ib_create_cq(&dev
->ib_dev
, &cq_attr
, NULL
, NULL
);
1508 if (IS_ERR(devr
->c0
)) {
1509 ret
= PTR_ERR(devr
->c0
);
1512 devr
->c0
->device
= &dev
->ib_dev
;
1513 devr
->c0
->uobject
= NULL
;
1514 devr
->c0
->comp_handler
= NULL
;
1515 devr
->c0
->event_handler
= NULL
;
1516 devr
->c0
->cq_context
= NULL
;
1517 atomic_set(&devr
->c0
->usecnt
, 0);
1519 devr
->x0
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
1520 if (IS_ERR(devr
->x0
)) {
1521 ret
= PTR_ERR(devr
->x0
);
1524 devr
->x0
->device
= &dev
->ib_dev
;
1525 devr
->x0
->inode
= NULL
;
1526 atomic_set(&devr
->x0
->usecnt
, 0);
1527 mutex_init(&devr
->x0
->tgt_qp_mutex
);
1528 INIT_LIST_HEAD(&devr
->x0
->tgt_qp_list
);
1530 devr
->x1
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
1531 if (IS_ERR(devr
->x1
)) {
1532 ret
= PTR_ERR(devr
->x1
);
1535 devr
->x1
->device
= &dev
->ib_dev
;
1536 devr
->x1
->inode
= NULL
;
1537 atomic_set(&devr
->x1
->usecnt
, 0);
1538 mutex_init(&devr
->x1
->tgt_qp_mutex
);
1539 INIT_LIST_HEAD(&devr
->x1
->tgt_qp_list
);
1541 memset(&attr
, 0, sizeof(attr
));
1542 attr
.attr
.max_sge
= 1;
1543 attr
.attr
.max_wr
= 1;
1544 attr
.srq_type
= IB_SRQT_XRC
;
1545 attr
.ext
.xrc
.cq
= devr
->c0
;
1546 attr
.ext
.xrc
.xrcd
= devr
->x0
;
1548 devr
->s0
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
1549 if (IS_ERR(devr
->s0
)) {
1550 ret
= PTR_ERR(devr
->s0
);
1553 devr
->s0
->device
= &dev
->ib_dev
;
1554 devr
->s0
->pd
= devr
->p0
;
1555 devr
->s0
->uobject
= NULL
;
1556 devr
->s0
->event_handler
= NULL
;
1557 devr
->s0
->srq_context
= NULL
;
1558 devr
->s0
->srq_type
= IB_SRQT_XRC
;
1559 devr
->s0
->ext
.xrc
.xrcd
= devr
->x0
;
1560 devr
->s0
->ext
.xrc
.cq
= devr
->c0
;
1561 atomic_inc(&devr
->s0
->ext
.xrc
.xrcd
->usecnt
);
1562 atomic_inc(&devr
->s0
->ext
.xrc
.cq
->usecnt
);
1563 atomic_inc(&devr
->p0
->usecnt
);
1564 atomic_set(&devr
->s0
->usecnt
, 0);
1566 memset(&attr
, 0, sizeof(attr
));
1567 attr
.attr
.max_sge
= 1;
1568 attr
.attr
.max_wr
= 1;
1569 attr
.srq_type
= IB_SRQT_BASIC
;
1570 devr
->s1
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
1571 if (IS_ERR(devr
->s1
)) {
1572 ret
= PTR_ERR(devr
->s1
);
1575 devr
->s1
->device
= &dev
->ib_dev
;
1576 devr
->s1
->pd
= devr
->p0
;
1577 devr
->s1
->uobject
= NULL
;
1578 devr
->s1
->event_handler
= NULL
;
1579 devr
->s1
->srq_context
= NULL
;
1580 devr
->s1
->srq_type
= IB_SRQT_BASIC
;
1581 devr
->s1
->ext
.xrc
.cq
= devr
->c0
;
1582 atomic_inc(&devr
->p0
->usecnt
);
1583 atomic_set(&devr
->s0
->usecnt
, 0);
1588 mlx5_ib_destroy_srq(devr
->s0
);
1590 mlx5_ib_dealloc_xrcd(devr
->x1
);
1592 mlx5_ib_dealloc_xrcd(devr
->x0
);
1594 mlx5_ib_destroy_cq(devr
->c0
);
1596 mlx5_ib_dealloc_pd(devr
->p0
);
1601 static void destroy_dev_resources(struct mlx5_ib_resources
*devr
)
1603 mlx5_ib_destroy_srq(devr
->s1
);
1604 mlx5_ib_destroy_srq(devr
->s0
);
1605 mlx5_ib_dealloc_xrcd(devr
->x0
);
1606 mlx5_ib_dealloc_xrcd(devr
->x1
);
1607 mlx5_ib_destroy_cq(devr
->c0
);
1608 mlx5_ib_dealloc_pd(devr
->p0
);
1611 static u32
get_core_cap_flags(struct ib_device
*ibdev
)
1613 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1614 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(ibdev
, 1);
1615 u8 l3_type_cap
= MLX5_CAP_ROCE(dev
->mdev
, l3_type
);
1616 u8 roce_version_cap
= MLX5_CAP_ROCE(dev
->mdev
, roce_version
);
1619 if (ll
== IB_LINK_LAYER_INFINIBAND
)
1620 return RDMA_CORE_PORT_IBA_IB
;
1622 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV4_CAP
))
1625 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV6_CAP
))
1628 if (roce_version_cap
& MLX5_ROCE_VERSION_1_CAP
)
1629 ret
|= RDMA_CORE_PORT_IBA_ROCE
;
1631 if (roce_version_cap
& MLX5_ROCE_VERSION_2_CAP
)
1632 ret
|= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP
;
1637 static int mlx5_port_immutable(struct ib_device
*ibdev
, u8 port_num
,
1638 struct ib_port_immutable
*immutable
)
1640 struct ib_port_attr attr
;
1643 err
= mlx5_ib_query_port(ibdev
, port_num
, &attr
);
1647 immutable
->pkey_tbl_len
= attr
.pkey_tbl_len
;
1648 immutable
->gid_tbl_len
= attr
.gid_tbl_len
;
1649 immutable
->core_cap_flags
= get_core_cap_flags(ibdev
);
1650 immutable
->max_mad_size
= IB_MGMT_MAD_SIZE
;
1655 static int mlx5_enable_roce(struct mlx5_ib_dev
*dev
)
1659 dev
->roce
.nb
.notifier_call
= mlx5_netdev_event
;
1660 err
= register_netdevice_notifier(&dev
->roce
.nb
);
1664 err
= mlx5_nic_vport_enable_roce(dev
->mdev
);
1666 goto err_unregister_netdevice_notifier
;
1670 err_unregister_netdevice_notifier
:
1671 unregister_netdevice_notifier(&dev
->roce
.nb
);
1675 static void mlx5_disable_roce(struct mlx5_ib_dev
*dev
)
1677 mlx5_nic_vport_disable_roce(dev
->mdev
);
1678 unregister_netdevice_notifier(&dev
->roce
.nb
);
1681 static void *mlx5_ib_add(struct mlx5_core_dev
*mdev
)
1683 struct mlx5_ib_dev
*dev
;
1684 enum rdma_link_layer ll
;
1689 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
1690 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
1692 if ((ll
== IB_LINK_LAYER_ETHERNET
) && !MLX5_CAP_GEN(mdev
, roce
))
1695 printk_once(KERN_INFO
"%s", mlx5_version
);
1697 dev
= (struct mlx5_ib_dev
*)ib_alloc_device(sizeof(*dev
));
1703 rwlock_init(&dev
->roce
.netdev_lock
);
1704 err
= get_port_caps(dev
);
1708 if (mlx5_use_mad_ifc(dev
))
1709 get_ext_port_caps(dev
);
1711 MLX5_INIT_DOORBELL_LOCK(&dev
->uar_lock
);
1713 strlcpy(dev
->ib_dev
.name
, "mlx5_%d", IB_DEVICE_NAME_MAX
);
1714 dev
->ib_dev
.owner
= THIS_MODULE
;
1715 dev
->ib_dev
.node_type
= RDMA_NODE_IB_CA
;
1716 dev
->ib_dev
.local_dma_lkey
= 0 /* not supported for now */;
1717 dev
->num_ports
= MLX5_CAP_GEN(mdev
, num_ports
);
1718 dev
->ib_dev
.phys_port_cnt
= dev
->num_ports
;
1719 dev
->ib_dev
.num_comp_vectors
=
1720 dev
->mdev
->priv
.eq_table
.num_comp_vectors
;
1721 dev
->ib_dev
.dma_device
= &mdev
->pdev
->dev
;
1723 dev
->ib_dev
.uverbs_abi_ver
= MLX5_IB_UVERBS_ABI_VERSION
;
1724 dev
->ib_dev
.uverbs_cmd_mask
=
1725 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT
) |
1726 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE
) |
1727 (1ull << IB_USER_VERBS_CMD_QUERY_PORT
) |
1728 (1ull << IB_USER_VERBS_CMD_ALLOC_PD
) |
1729 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD
) |
1730 (1ull << IB_USER_VERBS_CMD_REG_MR
) |
1731 (1ull << IB_USER_VERBS_CMD_DEREG_MR
) |
1732 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL
) |
1733 (1ull << IB_USER_VERBS_CMD_CREATE_CQ
) |
1734 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ
) |
1735 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ
) |
1736 (1ull << IB_USER_VERBS_CMD_CREATE_QP
) |
1737 (1ull << IB_USER_VERBS_CMD_MODIFY_QP
) |
1738 (1ull << IB_USER_VERBS_CMD_QUERY_QP
) |
1739 (1ull << IB_USER_VERBS_CMD_DESTROY_QP
) |
1740 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST
) |
1741 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST
) |
1742 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ
) |
1743 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ
) |
1744 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ
) |
1745 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ
) |
1746 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ
) |
1747 (1ull << IB_USER_VERBS_CMD_OPEN_QP
);
1748 dev
->ib_dev
.uverbs_ex_cmd_mask
=
1749 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE
);
1751 dev
->ib_dev
.query_device
= mlx5_ib_query_device
;
1752 dev
->ib_dev
.query_port
= mlx5_ib_query_port
;
1753 dev
->ib_dev
.get_link_layer
= mlx5_ib_port_link_layer
;
1754 if (ll
== IB_LINK_LAYER_ETHERNET
)
1755 dev
->ib_dev
.get_netdev
= mlx5_ib_get_netdev
;
1756 dev
->ib_dev
.query_gid
= mlx5_ib_query_gid
;
1757 dev
->ib_dev
.add_gid
= mlx5_ib_add_gid
;
1758 dev
->ib_dev
.del_gid
= mlx5_ib_del_gid
;
1759 dev
->ib_dev
.query_pkey
= mlx5_ib_query_pkey
;
1760 dev
->ib_dev
.modify_device
= mlx5_ib_modify_device
;
1761 dev
->ib_dev
.modify_port
= mlx5_ib_modify_port
;
1762 dev
->ib_dev
.alloc_ucontext
= mlx5_ib_alloc_ucontext
;
1763 dev
->ib_dev
.dealloc_ucontext
= mlx5_ib_dealloc_ucontext
;
1764 dev
->ib_dev
.mmap
= mlx5_ib_mmap
;
1765 dev
->ib_dev
.alloc_pd
= mlx5_ib_alloc_pd
;
1766 dev
->ib_dev
.dealloc_pd
= mlx5_ib_dealloc_pd
;
1767 dev
->ib_dev
.create_ah
= mlx5_ib_create_ah
;
1768 dev
->ib_dev
.query_ah
= mlx5_ib_query_ah
;
1769 dev
->ib_dev
.destroy_ah
= mlx5_ib_destroy_ah
;
1770 dev
->ib_dev
.create_srq
= mlx5_ib_create_srq
;
1771 dev
->ib_dev
.modify_srq
= mlx5_ib_modify_srq
;
1772 dev
->ib_dev
.query_srq
= mlx5_ib_query_srq
;
1773 dev
->ib_dev
.destroy_srq
= mlx5_ib_destroy_srq
;
1774 dev
->ib_dev
.post_srq_recv
= mlx5_ib_post_srq_recv
;
1775 dev
->ib_dev
.create_qp
= mlx5_ib_create_qp
;
1776 dev
->ib_dev
.modify_qp
= mlx5_ib_modify_qp
;
1777 dev
->ib_dev
.query_qp
= mlx5_ib_query_qp
;
1778 dev
->ib_dev
.destroy_qp
= mlx5_ib_destroy_qp
;
1779 dev
->ib_dev
.post_send
= mlx5_ib_post_send
;
1780 dev
->ib_dev
.post_recv
= mlx5_ib_post_recv
;
1781 dev
->ib_dev
.create_cq
= mlx5_ib_create_cq
;
1782 dev
->ib_dev
.modify_cq
= mlx5_ib_modify_cq
;
1783 dev
->ib_dev
.resize_cq
= mlx5_ib_resize_cq
;
1784 dev
->ib_dev
.destroy_cq
= mlx5_ib_destroy_cq
;
1785 dev
->ib_dev
.poll_cq
= mlx5_ib_poll_cq
;
1786 dev
->ib_dev
.req_notify_cq
= mlx5_ib_arm_cq
;
1787 dev
->ib_dev
.get_dma_mr
= mlx5_ib_get_dma_mr
;
1788 dev
->ib_dev
.reg_user_mr
= mlx5_ib_reg_user_mr
;
1789 dev
->ib_dev
.dereg_mr
= mlx5_ib_dereg_mr
;
1790 dev
->ib_dev
.attach_mcast
= mlx5_ib_mcg_attach
;
1791 dev
->ib_dev
.detach_mcast
= mlx5_ib_mcg_detach
;
1792 dev
->ib_dev
.process_mad
= mlx5_ib_process_mad
;
1793 dev
->ib_dev
.alloc_mr
= mlx5_ib_alloc_mr
;
1794 dev
->ib_dev
.map_mr_sg
= mlx5_ib_map_mr_sg
;
1795 dev
->ib_dev
.check_mr_status
= mlx5_ib_check_mr_status
;
1796 dev
->ib_dev
.get_port_immutable
= mlx5_port_immutable
;
1798 mlx5_ib_internal_fill_odp_caps(dev
);
1800 if (MLX5_CAP_GEN(mdev
, xrc
)) {
1801 dev
->ib_dev
.alloc_xrcd
= mlx5_ib_alloc_xrcd
;
1802 dev
->ib_dev
.dealloc_xrcd
= mlx5_ib_dealloc_xrcd
;
1803 dev
->ib_dev
.uverbs_cmd_mask
|=
1804 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD
) |
1805 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD
);
1808 err
= init_node_data(dev
);
1812 mutex_init(&dev
->cap_mask_mutex
);
1814 if (ll
== IB_LINK_LAYER_ETHERNET
) {
1815 err
= mlx5_enable_roce(dev
);
1820 err
= create_dev_resources(&dev
->devr
);
1822 goto err_disable_roce
;
1824 err
= mlx5_ib_odp_init_one(dev
);
1828 err
= ib_register_device(&dev
->ib_dev
, NULL
);
1832 err
= create_umr_res(dev
);
1836 for (i
= 0; i
< ARRAY_SIZE(mlx5_class_attributes
); i
++) {
1837 err
= device_create_file(&dev
->ib_dev
.dev
,
1838 mlx5_class_attributes
[i
]);
1843 dev
->ib_active
= true;
1848 destroy_umrc_res(dev
);
1851 ib_unregister_device(&dev
->ib_dev
);
1854 mlx5_ib_odp_remove_one(dev
);
1857 destroy_dev_resources(&dev
->devr
);
1860 if (ll
== IB_LINK_LAYER_ETHERNET
)
1861 mlx5_disable_roce(dev
);
1864 ib_dealloc_device((struct ib_device
*)dev
);
1869 static void mlx5_ib_remove(struct mlx5_core_dev
*mdev
, void *context
)
1871 struct mlx5_ib_dev
*dev
= context
;
1872 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&dev
->ib_dev
, 1);
1874 ib_unregister_device(&dev
->ib_dev
);
1875 destroy_umrc_res(dev
);
1876 mlx5_ib_odp_remove_one(dev
);
1877 destroy_dev_resources(&dev
->devr
);
1878 if (ll
== IB_LINK_LAYER_ETHERNET
)
1879 mlx5_disable_roce(dev
);
1880 ib_dealloc_device(&dev
->ib_dev
);
1883 static struct mlx5_interface mlx5_ib_interface
= {
1885 .remove
= mlx5_ib_remove
,
1886 .event
= mlx5_ib_event
,
1887 .protocol
= MLX5_INTERFACE_PROTOCOL_IB
,
1890 static int __init
mlx5_ib_init(void)
1894 if (deprecated_prof_sel
!= 2)
1895 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
1897 err
= mlx5_ib_odp_init();
1901 err
= mlx5_register_interface(&mlx5_ib_interface
);
1908 mlx5_ib_odp_cleanup();
1912 static void __exit
mlx5_ib_cleanup(void)
1914 mlx5_unregister_interface(&mlx5_ib_interface
);
1915 mlx5_ib_odp_cleanup();
1918 module_init(mlx5_ib_init
);
1919 module_exit(mlx5_ib_cleanup
);