2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #if defined(CONFIG_X86)
44 #include <linux/sched.h>
45 #include <rdma/ib_user_verbs.h>
46 #include <rdma/ib_addr.h>
47 #include <rdma/ib_cache.h>
48 #include <linux/mlx5/port.h>
49 #include <linux/mlx5/vport.h>
50 #include <rdma/ib_smi.h>
51 #include <rdma/ib_umem.h>
53 #include <linux/etherdevice.h>
54 #include <linux/mlx5/fs.h>
58 #define DRIVER_NAME "mlx5_ib"
59 #define DRIVER_VERSION "2.2-1"
60 #define DRIVER_RELDATE "Feb 2014"
62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_VERSION(DRIVER_VERSION
);
67 static int deprecated_prof_sel
= 2;
68 module_param_named(prof_sel
, deprecated_prof_sel
, int, 0444);
69 MODULE_PARM_DESC(prof_sel
, "profile selector. Deprecated here. Moved to module mlx5_core");
71 static char mlx5_version
[] =
72 DRIVER_NAME
": Mellanox Connect-IB Infiniband driver v"
73 DRIVER_VERSION
" (" DRIVER_RELDATE
")\n";
76 MLX5_ATOMIC_SIZE_QP_8BYTES
= 1 << 3,
79 static enum rdma_link_layer
80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap
)
82 switch (port_type_cap
) {
83 case MLX5_CAP_PORT_TYPE_IB
:
84 return IB_LINK_LAYER_INFINIBAND
;
85 case MLX5_CAP_PORT_TYPE_ETH
:
86 return IB_LINK_LAYER_ETHERNET
;
88 return IB_LINK_LAYER_UNSPECIFIED
;
92 static enum rdma_link_layer
93 mlx5_ib_port_link_layer(struct ib_device
*device
, u8 port_num
)
95 struct mlx5_ib_dev
*dev
= to_mdev(device
);
96 int port_type_cap
= MLX5_CAP_GEN(dev
->mdev
, port_type
);
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
101 static int mlx5_netdev_event(struct notifier_block
*this,
102 unsigned long event
, void *ptr
)
104 struct net_device
*ndev
= netdev_notifier_info_to_dev(ptr
);
105 struct mlx5_ib_dev
*ibdev
= container_of(this, struct mlx5_ib_dev
,
108 if ((event
!= NETDEV_UNREGISTER
) && (event
!= NETDEV_REGISTER
))
111 write_lock(&ibdev
->roce
.netdev_lock
);
112 if (ndev
->dev
.parent
== &ibdev
->mdev
->pdev
->dev
)
113 ibdev
->roce
.netdev
= (event
== NETDEV_UNREGISTER
) ? NULL
: ndev
;
114 write_unlock(&ibdev
->roce
.netdev_lock
);
119 static struct net_device
*mlx5_ib_get_netdev(struct ib_device
*device
,
122 struct mlx5_ib_dev
*ibdev
= to_mdev(device
);
123 struct net_device
*ndev
;
125 /* Ensure ndev does not disappear before we invoke dev_hold()
127 read_lock(&ibdev
->roce
.netdev_lock
);
128 ndev
= ibdev
->roce
.netdev
;
131 read_unlock(&ibdev
->roce
.netdev_lock
);
136 static int mlx5_query_port_roce(struct ib_device
*device
, u8 port_num
,
137 struct ib_port_attr
*props
)
139 struct mlx5_ib_dev
*dev
= to_mdev(device
);
140 struct net_device
*ndev
;
141 enum ib_mtu ndev_ib_mtu
;
144 memset(props
, 0, sizeof(*props
));
146 props
->port_cap_flags
|= IB_PORT_CM_SUP
;
147 props
->port_cap_flags
|= IB_PORT_IP_BASED_GIDS
;
149 props
->gid_tbl_len
= MLX5_CAP_ROCE(dev
->mdev
,
150 roce_address_table_size
);
151 props
->max_mtu
= IB_MTU_4096
;
152 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_msg
);
153 props
->pkey_tbl_len
= 1;
154 props
->state
= IB_PORT_DOWN
;
155 props
->phys_state
= 3;
157 mlx5_query_nic_vport_qkey_viol_cntr(dev
->mdev
, &qkey_viol_cntr
);
158 props
->qkey_viol_cntr
= qkey_viol_cntr
;
160 ndev
= mlx5_ib_get_netdev(device
, port_num
);
164 if (netif_running(ndev
) && netif_carrier_ok(ndev
)) {
165 props
->state
= IB_PORT_ACTIVE
;
166 props
->phys_state
= 5;
169 ndev_ib_mtu
= iboe_get_mtu(ndev
->mtu
);
173 props
->active_mtu
= min(props
->max_mtu
, ndev_ib_mtu
);
175 props
->active_width
= IB_WIDTH_4X
; /* TODO */
176 props
->active_speed
= IB_SPEED_QDR
; /* TODO */
181 static void ib_gid_to_mlx5_roce_addr(const union ib_gid
*gid
,
182 const struct ib_gid_attr
*attr
,
185 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
186 char *mlx5_addr_l3_addr
= MLX5_ADDR_OF(roce_addr_layout
, mlx5_addr
,
188 void *mlx5_addr_mac
= MLX5_ADDR_OF(roce_addr_layout
, mlx5_addr
,
194 ether_addr_copy(mlx5_addr_mac
, attr
->ndev
->dev_addr
);
196 if (is_vlan_dev(attr
->ndev
)) {
197 MLX5_SET_RA(mlx5_addr
, vlan_valid
, 1);
198 MLX5_SET_RA(mlx5_addr
, vlan_id
, vlan_dev_vlan_id(attr
->ndev
));
201 switch (attr
->gid_type
) {
203 MLX5_SET_RA(mlx5_addr
, roce_version
, MLX5_ROCE_VERSION_1
);
205 case IB_GID_TYPE_ROCE_UDP_ENCAP
:
206 MLX5_SET_RA(mlx5_addr
, roce_version
, MLX5_ROCE_VERSION_2
);
213 if (attr
->gid_type
!= IB_GID_TYPE_IB
) {
214 if (ipv6_addr_v4mapped((void *)gid
))
215 MLX5_SET_RA(mlx5_addr
, roce_l3_type
,
216 MLX5_ROCE_L3_TYPE_IPV4
);
218 MLX5_SET_RA(mlx5_addr
, roce_l3_type
,
219 MLX5_ROCE_L3_TYPE_IPV6
);
222 if ((attr
->gid_type
== IB_GID_TYPE_IB
) ||
223 !ipv6_addr_v4mapped((void *)gid
))
224 memcpy(mlx5_addr_l3_addr
, gid
, sizeof(*gid
));
226 memcpy(&mlx5_addr_l3_addr
[12], &gid
->raw
[12], 4);
229 static int set_roce_addr(struct ib_device
*device
, u8 port_num
,
231 const union ib_gid
*gid
,
232 const struct ib_gid_attr
*attr
)
234 struct mlx5_ib_dev
*dev
= to_mdev(device
);
235 u32 in
[MLX5_ST_SZ_DW(set_roce_address_in
)];
236 u32 out
[MLX5_ST_SZ_DW(set_roce_address_out
)];
237 void *in_addr
= MLX5_ADDR_OF(set_roce_address_in
, in
, roce_address
);
238 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(device
, port_num
);
240 if (ll
!= IB_LINK_LAYER_ETHERNET
)
243 memset(in
, 0, sizeof(in
));
245 ib_gid_to_mlx5_roce_addr(gid
, attr
, in_addr
);
247 MLX5_SET(set_roce_address_in
, in
, roce_address_index
, index
);
248 MLX5_SET(set_roce_address_in
, in
, opcode
, MLX5_CMD_OP_SET_ROCE_ADDRESS
);
250 memset(out
, 0, sizeof(out
));
251 return mlx5_cmd_exec(dev
->mdev
, in
, sizeof(in
), out
, sizeof(out
));
254 static int mlx5_ib_add_gid(struct ib_device
*device
, u8 port_num
,
255 unsigned int index
, const union ib_gid
*gid
,
256 const struct ib_gid_attr
*attr
,
257 __always_unused
void **context
)
259 return set_roce_addr(device
, port_num
, index
, gid
, attr
);
262 static int mlx5_ib_del_gid(struct ib_device
*device
, u8 port_num
,
263 unsigned int index
, __always_unused
void **context
)
265 return set_roce_addr(device
, port_num
, index
, NULL
, NULL
);
268 __be16
mlx5_get_roce_udp_sport(struct mlx5_ib_dev
*dev
, u8 port_num
,
271 struct ib_gid_attr attr
;
274 if (ib_get_cached_gid(&dev
->ib_dev
, port_num
, index
, &gid
, &attr
))
282 if (attr
.gid_type
!= IB_GID_TYPE_ROCE_UDP_ENCAP
)
285 return cpu_to_be16(MLX5_CAP_ROCE(dev
->mdev
, r_roce_min_src_udp_port
));
288 static int mlx5_use_mad_ifc(struct mlx5_ib_dev
*dev
)
290 return !MLX5_CAP_GEN(dev
->mdev
, ib_virt
);
294 MLX5_VPORT_ACCESS_METHOD_MAD
,
295 MLX5_VPORT_ACCESS_METHOD_HCA
,
296 MLX5_VPORT_ACCESS_METHOD_NIC
,
299 static int mlx5_get_vport_access_method(struct ib_device
*ibdev
)
301 if (mlx5_use_mad_ifc(to_mdev(ibdev
)))
302 return MLX5_VPORT_ACCESS_METHOD_MAD
;
304 if (mlx5_ib_port_link_layer(ibdev
, 1) ==
305 IB_LINK_LAYER_ETHERNET
)
306 return MLX5_VPORT_ACCESS_METHOD_NIC
;
308 return MLX5_VPORT_ACCESS_METHOD_HCA
;
311 static void get_atomic_caps(struct mlx5_ib_dev
*dev
,
312 struct ib_device_attr
*props
)
315 u8 atomic_operations
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_operations
);
316 u8 atomic_size_qp
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_size_qp
);
317 u8 atomic_req_8B_endianness_mode
=
318 MLX5_CAP_ATOMIC(dev
->mdev
, atomic_req_8B_endianess_mode
);
320 /* Check if HW supports 8 bytes standard atomic operations and capable
321 * of host endianness respond
323 tmp
= MLX5_ATOMIC_OPS_CMP_SWAP
| MLX5_ATOMIC_OPS_FETCH_ADD
;
324 if (((atomic_operations
& tmp
) == tmp
) &&
325 (atomic_size_qp
& MLX5_ATOMIC_SIZE_QP_8BYTES
) &&
326 (atomic_req_8B_endianness_mode
)) {
327 props
->atomic_cap
= IB_ATOMIC_HCA
;
329 props
->atomic_cap
= IB_ATOMIC_NONE
;
333 static int mlx5_query_system_image_guid(struct ib_device
*ibdev
,
334 __be64
*sys_image_guid
)
336 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
337 struct mlx5_core_dev
*mdev
= dev
->mdev
;
341 switch (mlx5_get_vport_access_method(ibdev
)) {
342 case MLX5_VPORT_ACCESS_METHOD_MAD
:
343 return mlx5_query_mad_ifc_system_image_guid(ibdev
,
346 case MLX5_VPORT_ACCESS_METHOD_HCA
:
347 err
= mlx5_query_hca_vport_system_image_guid(mdev
, &tmp
);
350 case MLX5_VPORT_ACCESS_METHOD_NIC
:
351 err
= mlx5_query_nic_vport_system_image_guid(mdev
, &tmp
);
359 *sys_image_guid
= cpu_to_be64(tmp
);
365 static int mlx5_query_max_pkeys(struct ib_device
*ibdev
,
368 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
369 struct mlx5_core_dev
*mdev
= dev
->mdev
;
371 switch (mlx5_get_vport_access_method(ibdev
)) {
372 case MLX5_VPORT_ACCESS_METHOD_MAD
:
373 return mlx5_query_mad_ifc_max_pkeys(ibdev
, max_pkeys
);
375 case MLX5_VPORT_ACCESS_METHOD_HCA
:
376 case MLX5_VPORT_ACCESS_METHOD_NIC
:
377 *max_pkeys
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
,
386 static int mlx5_query_vendor_id(struct ib_device
*ibdev
,
389 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
391 switch (mlx5_get_vport_access_method(ibdev
)) {
392 case MLX5_VPORT_ACCESS_METHOD_MAD
:
393 return mlx5_query_mad_ifc_vendor_id(ibdev
, vendor_id
);
395 case MLX5_VPORT_ACCESS_METHOD_HCA
:
396 case MLX5_VPORT_ACCESS_METHOD_NIC
:
397 return mlx5_core_query_vendor_id(dev
->mdev
, vendor_id
);
404 static int mlx5_query_node_guid(struct mlx5_ib_dev
*dev
,
410 switch (mlx5_get_vport_access_method(&dev
->ib_dev
)) {
411 case MLX5_VPORT_ACCESS_METHOD_MAD
:
412 return mlx5_query_mad_ifc_node_guid(dev
, node_guid
);
414 case MLX5_VPORT_ACCESS_METHOD_HCA
:
415 err
= mlx5_query_hca_vport_node_guid(dev
->mdev
, &tmp
);
418 case MLX5_VPORT_ACCESS_METHOD_NIC
:
419 err
= mlx5_query_nic_vport_node_guid(dev
->mdev
, &tmp
);
427 *node_guid
= cpu_to_be64(tmp
);
432 struct mlx5_reg_node_desc
{
436 static int mlx5_query_node_desc(struct mlx5_ib_dev
*dev
, char *node_desc
)
438 struct mlx5_reg_node_desc in
;
440 if (mlx5_use_mad_ifc(dev
))
441 return mlx5_query_mad_ifc_node_desc(dev
, node_desc
);
443 memset(&in
, 0, sizeof(in
));
445 return mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), node_desc
,
446 sizeof(struct mlx5_reg_node_desc
),
447 MLX5_REG_NODE_DESC
, 0, 0);
450 static int mlx5_ib_query_device(struct ib_device
*ibdev
,
451 struct ib_device_attr
*props
,
452 struct ib_udata
*uhw
)
454 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
455 struct mlx5_core_dev
*mdev
= dev
->mdev
;
459 u64 min_page_size
= 1ull << MLX5_CAP_GEN(mdev
, log_pg_sz
);
461 if (uhw
->inlen
|| uhw
->outlen
)
464 memset(props
, 0, sizeof(*props
));
465 err
= mlx5_query_system_image_guid(ibdev
,
466 &props
->sys_image_guid
);
470 err
= mlx5_query_max_pkeys(ibdev
, &props
->max_pkeys
);
474 err
= mlx5_query_vendor_id(ibdev
, &props
->vendor_id
);
478 props
->fw_ver
= ((u64
)fw_rev_maj(dev
->mdev
) << 32) |
479 (fw_rev_min(dev
->mdev
) << 16) |
480 fw_rev_sub(dev
->mdev
);
481 props
->device_cap_flags
= IB_DEVICE_CHANGE_PHY_PORT
|
482 IB_DEVICE_PORT_ACTIVE_EVENT
|
483 IB_DEVICE_SYS_IMAGE_GUID
|
484 IB_DEVICE_RC_RNR_NAK_GEN
;
486 if (MLX5_CAP_GEN(mdev
, pkv
))
487 props
->device_cap_flags
|= IB_DEVICE_BAD_PKEY_CNTR
;
488 if (MLX5_CAP_GEN(mdev
, qkv
))
489 props
->device_cap_flags
|= IB_DEVICE_BAD_QKEY_CNTR
;
490 if (MLX5_CAP_GEN(mdev
, apm
))
491 props
->device_cap_flags
|= IB_DEVICE_AUTO_PATH_MIG
;
492 if (MLX5_CAP_GEN(mdev
, xrc
))
493 props
->device_cap_flags
|= IB_DEVICE_XRC
;
494 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
495 props
->device_cap_flags
|= IB_DEVICE_MEM_WINDOW
|
496 IB_DEVICE_MEM_WINDOW_TYPE_2B
;
497 props
->max_mw
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
498 /* We support 'Gappy' memory registration too */
499 props
->device_cap_flags
|= IB_DEVICE_SG_GAPS_REG
;
501 props
->device_cap_flags
|= IB_DEVICE_MEM_MGT_EXTENSIONS
;
502 if (MLX5_CAP_GEN(mdev
, sho
)) {
503 props
->device_cap_flags
|= IB_DEVICE_SIGNATURE_HANDOVER
;
504 /* At this stage no support for signature handover */
505 props
->sig_prot_cap
= IB_PROT_T10DIF_TYPE_1
|
506 IB_PROT_T10DIF_TYPE_2
|
507 IB_PROT_T10DIF_TYPE_3
;
508 props
->sig_guard_cap
= IB_GUARD_T10DIF_CRC
|
509 IB_GUARD_T10DIF_CSUM
;
511 if (MLX5_CAP_GEN(mdev
, block_lb_mc
))
512 props
->device_cap_flags
|= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK
;
514 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) &&
515 (MLX5_CAP_ETH(dev
->mdev
, csum_cap
)))
516 props
->device_cap_flags
|= IB_DEVICE_RAW_IP_CSUM
;
518 if (MLX5_CAP_GEN(mdev
, ipoib_basic_offloads
)) {
519 props
->device_cap_flags
|= IB_DEVICE_UD_IP_CSUM
;
520 props
->device_cap_flags
|= IB_DEVICE_UD_TSO
;
523 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) &&
524 MLX5_CAP_ETH(dev
->mdev
, scatter_fcs
))
525 props
->device_cap_flags
|= IB_DEVICE_RAW_SCATTER_FCS
;
527 if (mlx5_get_flow_namespace(dev
->mdev
, MLX5_FLOW_NAMESPACE_BYPASS
))
528 props
->device_cap_flags
|= IB_DEVICE_MANAGED_FLOW_STEERING
;
530 props
->vendor_part_id
= mdev
->pdev
->device
;
531 props
->hw_ver
= mdev
->pdev
->revision
;
533 props
->max_mr_size
= ~0ull;
534 props
->page_size_cap
= ~(min_page_size
- 1);
535 props
->max_qp
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp
);
536 props
->max_qp_wr
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp_sz
);
537 max_rq_sg
= MLX5_CAP_GEN(mdev
, max_wqe_sz_rq
) /
538 sizeof(struct mlx5_wqe_data_seg
);
539 max_sq_sg
= (MLX5_CAP_GEN(mdev
, max_wqe_sz_sq
) -
540 sizeof(struct mlx5_wqe_ctrl_seg
)) /
541 sizeof(struct mlx5_wqe_data_seg
);
542 props
->max_sge
= min(max_rq_sg
, max_sq_sg
);
543 props
->max_sge_rd
= MLX5_MAX_SGE_RD
;
544 props
->max_cq
= 1 << MLX5_CAP_GEN(mdev
, log_max_cq
);
545 props
->max_cqe
= (1 << MLX5_CAP_GEN(mdev
, log_max_cq_sz
)) - 1;
546 props
->max_mr
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
547 props
->max_pd
= 1 << MLX5_CAP_GEN(mdev
, log_max_pd
);
548 props
->max_qp_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_req_qp
);
549 props
->max_qp_init_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_res_qp
);
550 props
->max_srq
= 1 << MLX5_CAP_GEN(mdev
, log_max_srq
);
551 props
->max_srq_wr
= (1 << MLX5_CAP_GEN(mdev
, log_max_srq_sz
)) - 1;
552 props
->local_ca_ack_delay
= MLX5_CAP_GEN(mdev
, local_ca_ack_delay
);
553 props
->max_res_rd_atom
= props
->max_qp_rd_atom
* props
->max_qp
;
554 props
->max_srq_sge
= max_rq_sg
- 1;
555 props
->max_fast_reg_page_list_len
=
556 1 << MLX5_CAP_GEN(mdev
, log_max_klm_list_size
);
557 get_atomic_caps(dev
, props
);
558 props
->masked_atomic_cap
= IB_ATOMIC_NONE
;
559 props
->max_mcast_grp
= 1 << MLX5_CAP_GEN(mdev
, log_max_mcg
);
560 props
->max_mcast_qp_attach
= MLX5_CAP_GEN(mdev
, max_qp_mcg
);
561 props
->max_total_mcast_qp_attach
= props
->max_mcast_qp_attach
*
562 props
->max_mcast_grp
;
563 props
->max_map_per_fmr
= INT_MAX
; /* no limit in ConnectIB */
564 props
->hca_core_clock
= MLX5_CAP_GEN(mdev
, device_frequency_khz
);
565 props
->timestamp_mask
= 0x7FFFFFFFFFFFFFFFULL
;
567 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
568 if (MLX5_CAP_GEN(mdev
, pg
))
569 props
->device_cap_flags
|= IB_DEVICE_ON_DEMAND_PAGING
;
570 props
->odp_caps
= dev
->odp_caps
;
573 if (MLX5_CAP_GEN(mdev
, cd
))
574 props
->device_cap_flags
|= IB_DEVICE_CROSS_CHANNEL
;
576 if (!mlx5_core_is_pf(mdev
))
577 props
->device_cap_flags
|= IB_DEVICE_VIRTUAL_FUNCTION
;
583 MLX5_IB_WIDTH_1X
= 1 << 0,
584 MLX5_IB_WIDTH_2X
= 1 << 1,
585 MLX5_IB_WIDTH_4X
= 1 << 2,
586 MLX5_IB_WIDTH_8X
= 1 << 3,
587 MLX5_IB_WIDTH_12X
= 1 << 4
590 static int translate_active_width(struct ib_device
*ibdev
, u8 active_width
,
593 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
596 if (active_width
& MLX5_IB_WIDTH_1X
) {
597 *ib_width
= IB_WIDTH_1X
;
598 } else if (active_width
& MLX5_IB_WIDTH_2X
) {
599 mlx5_ib_dbg(dev
, "active_width %d is not supported by IB spec\n",
602 } else if (active_width
& MLX5_IB_WIDTH_4X
) {
603 *ib_width
= IB_WIDTH_4X
;
604 } else if (active_width
& MLX5_IB_WIDTH_8X
) {
605 *ib_width
= IB_WIDTH_8X
;
606 } else if (active_width
& MLX5_IB_WIDTH_12X
) {
607 *ib_width
= IB_WIDTH_12X
;
609 mlx5_ib_dbg(dev
, "Invalid active_width %d\n",
617 static int mlx5_mtu_to_ib_mtu(int mtu
)
626 pr_warn("invalid mtu\n");
636 __IB_MAX_VL_0_14
= 5,
639 enum mlx5_vl_hw_cap
{
651 static int translate_max_vl_num(struct ib_device
*ibdev
, u8 vl_hw_cap
,
656 *max_vl_num
= __IB_MAX_VL_0
;
659 *max_vl_num
= __IB_MAX_VL_0_1
;
662 *max_vl_num
= __IB_MAX_VL_0_3
;
665 *max_vl_num
= __IB_MAX_VL_0_7
;
667 case MLX5_VL_HW_0_14
:
668 *max_vl_num
= __IB_MAX_VL_0_14
;
678 static int mlx5_query_hca_port(struct ib_device
*ibdev
, u8 port
,
679 struct ib_port_attr
*props
)
681 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
682 struct mlx5_core_dev
*mdev
= dev
->mdev
;
683 struct mlx5_hca_vport_context
*rep
;
687 u8 ib_link_width_oper
;
690 rep
= kzalloc(sizeof(*rep
), GFP_KERNEL
);
696 memset(props
, 0, sizeof(*props
));
698 err
= mlx5_query_hca_vport_context(mdev
, 0, port
, 0, rep
);
702 props
->lid
= rep
->lid
;
703 props
->lmc
= rep
->lmc
;
704 props
->sm_lid
= rep
->sm_lid
;
705 props
->sm_sl
= rep
->sm_sl
;
706 props
->state
= rep
->vport_state
;
707 props
->phys_state
= rep
->port_physical_state
;
708 props
->port_cap_flags
= rep
->cap_mask1
;
709 props
->gid_tbl_len
= mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev
, gid_table_size
));
710 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(mdev
, log_max_msg
);
711 props
->pkey_tbl_len
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
, pkey_table_size
));
712 props
->bad_pkey_cntr
= rep
->pkey_violation_counter
;
713 props
->qkey_viol_cntr
= rep
->qkey_violation_counter
;
714 props
->subnet_timeout
= rep
->subnet_timeout
;
715 props
->init_type_reply
= rep
->init_type_reply
;
716 props
->grh_required
= rep
->grh_required
;
718 err
= mlx5_query_port_link_width_oper(mdev
, &ib_link_width_oper
, port
);
722 err
= translate_active_width(ibdev
, ib_link_width_oper
,
723 &props
->active_width
);
726 err
= mlx5_query_port_proto_oper(mdev
, &props
->active_speed
, MLX5_PTYS_IB
,
731 mlx5_query_port_max_mtu(mdev
, &max_mtu
, port
);
733 props
->max_mtu
= mlx5_mtu_to_ib_mtu(max_mtu
);
735 mlx5_query_port_oper_mtu(mdev
, &oper_mtu
, port
);
737 props
->active_mtu
= mlx5_mtu_to_ib_mtu(oper_mtu
);
739 err
= mlx5_query_port_vl_hw_cap(mdev
, &vl_hw_cap
, port
);
743 err
= translate_max_vl_num(ibdev
, vl_hw_cap
,
750 int mlx5_ib_query_port(struct ib_device
*ibdev
, u8 port
,
751 struct ib_port_attr
*props
)
753 switch (mlx5_get_vport_access_method(ibdev
)) {
754 case MLX5_VPORT_ACCESS_METHOD_MAD
:
755 return mlx5_query_mad_ifc_port(ibdev
, port
, props
);
757 case MLX5_VPORT_ACCESS_METHOD_HCA
:
758 return mlx5_query_hca_port(ibdev
, port
, props
);
760 case MLX5_VPORT_ACCESS_METHOD_NIC
:
761 return mlx5_query_port_roce(ibdev
, port
, props
);
768 static int mlx5_ib_query_gid(struct ib_device
*ibdev
, u8 port
, int index
,
771 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
772 struct mlx5_core_dev
*mdev
= dev
->mdev
;
774 switch (mlx5_get_vport_access_method(ibdev
)) {
775 case MLX5_VPORT_ACCESS_METHOD_MAD
:
776 return mlx5_query_mad_ifc_gids(ibdev
, port
, index
, gid
);
778 case MLX5_VPORT_ACCESS_METHOD_HCA
:
779 return mlx5_query_hca_vport_gid(mdev
, 0, port
, 0, index
, gid
);
787 static int mlx5_ib_query_pkey(struct ib_device
*ibdev
, u8 port
, u16 index
,
790 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
791 struct mlx5_core_dev
*mdev
= dev
->mdev
;
793 switch (mlx5_get_vport_access_method(ibdev
)) {
794 case MLX5_VPORT_ACCESS_METHOD_MAD
:
795 return mlx5_query_mad_ifc_pkey(ibdev
, port
, index
, pkey
);
797 case MLX5_VPORT_ACCESS_METHOD_HCA
:
798 case MLX5_VPORT_ACCESS_METHOD_NIC
:
799 return mlx5_query_hca_vport_pkey(mdev
, 0, port
, 0, index
,
806 static int mlx5_ib_modify_device(struct ib_device
*ibdev
, int mask
,
807 struct ib_device_modify
*props
)
809 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
810 struct mlx5_reg_node_desc in
;
811 struct mlx5_reg_node_desc out
;
814 if (mask
& ~IB_DEVICE_MODIFY_NODE_DESC
)
817 if (!(mask
& IB_DEVICE_MODIFY_NODE_DESC
))
821 * If possible, pass node desc to FW, so it can generate
822 * a 144 trap. If cmd fails, just ignore.
824 memcpy(&in
, props
->node_desc
, 64);
825 err
= mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), &out
,
826 sizeof(out
), MLX5_REG_NODE_DESC
, 0, 1);
830 memcpy(ibdev
->node_desc
, props
->node_desc
, 64);
835 static int mlx5_ib_modify_port(struct ib_device
*ibdev
, u8 port
, int mask
,
836 struct ib_port_modify
*props
)
838 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
839 struct ib_port_attr attr
;
843 mutex_lock(&dev
->cap_mask_mutex
);
845 err
= mlx5_ib_query_port(ibdev
, port
, &attr
);
849 tmp
= (attr
.port_cap_flags
| props
->set_port_cap_mask
) &
850 ~props
->clr_port_cap_mask
;
852 err
= mlx5_set_port_caps(dev
->mdev
, port
, tmp
);
855 mutex_unlock(&dev
->cap_mask_mutex
);
859 static struct ib_ucontext
*mlx5_ib_alloc_ucontext(struct ib_device
*ibdev
,
860 struct ib_udata
*udata
)
862 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
863 struct mlx5_ib_alloc_ucontext_req_v2 req
= {};
864 struct mlx5_ib_alloc_ucontext_resp resp
= {};
865 struct mlx5_ib_ucontext
*context
;
866 struct mlx5_uuar_info
*uuari
;
867 struct mlx5_uar
*uars
;
875 size_t min_req_v2
= offsetof(struct mlx5_ib_alloc_ucontext_req_v2
,
879 return ERR_PTR(-EAGAIN
);
881 if (udata
->inlen
< sizeof(struct ib_uverbs_cmd_hdr
))
882 return ERR_PTR(-EINVAL
);
884 reqlen
= udata
->inlen
- sizeof(struct ib_uverbs_cmd_hdr
);
885 if (reqlen
== sizeof(struct mlx5_ib_alloc_ucontext_req
))
887 else if (reqlen
>= min_req_v2
)
890 return ERR_PTR(-EINVAL
);
892 err
= ib_copy_from_udata(&req
, udata
, min(reqlen
, sizeof(req
)));
897 return ERR_PTR(-EINVAL
);
899 if (req
.total_num_uuars
> MLX5_MAX_UUARS
)
900 return ERR_PTR(-ENOMEM
);
902 if (req
.total_num_uuars
== 0)
903 return ERR_PTR(-EINVAL
);
905 if (req
.comp_mask
|| req
.reserved0
|| req
.reserved1
|| req
.reserved2
)
906 return ERR_PTR(-EOPNOTSUPP
);
908 if (reqlen
> sizeof(req
) &&
909 !ib_is_udata_cleared(udata
, sizeof(req
),
910 reqlen
- sizeof(req
)))
911 return ERR_PTR(-EOPNOTSUPP
);
913 req
.total_num_uuars
= ALIGN(req
.total_num_uuars
,
914 MLX5_NON_FP_BF_REGS_PER_PAGE
);
915 if (req
.num_low_latency_uuars
> req
.total_num_uuars
- 1)
916 return ERR_PTR(-EINVAL
);
918 num_uars
= req
.total_num_uuars
/ MLX5_NON_FP_BF_REGS_PER_PAGE
;
919 gross_uuars
= num_uars
* MLX5_BF_REGS_PER_PAGE
;
920 resp
.qp_tab_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp
);
921 if (mlx5_core_is_pf(dev
->mdev
) && MLX5_CAP_GEN(dev
->mdev
, bf
))
922 resp
.bf_reg_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_bf_reg_size
);
923 resp
.cache_line_size
= L1_CACHE_BYTES
;
924 resp
.max_sq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
);
925 resp
.max_rq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_rq
);
926 resp
.max_send_wqebb
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
927 resp
.max_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
928 resp
.max_srq_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_srq_sz
);
929 resp
.cqe_version
= min_t(__u8
,
930 (__u8
)MLX5_CAP_GEN(dev
->mdev
, cqe_version
),
931 req
.max_cqe_version
);
932 resp
.response_length
= min(offsetof(typeof(resp
), response_length
) +
933 sizeof(resp
.response_length
), udata
->outlen
);
935 context
= kzalloc(sizeof(*context
), GFP_KERNEL
);
937 return ERR_PTR(-ENOMEM
);
939 uuari
= &context
->uuari
;
940 mutex_init(&uuari
->lock
);
941 uars
= kcalloc(num_uars
, sizeof(*uars
), GFP_KERNEL
);
947 uuari
->bitmap
= kcalloc(BITS_TO_LONGS(gross_uuars
),
948 sizeof(*uuari
->bitmap
),
950 if (!uuari
->bitmap
) {
955 * clear all fast path uuars
957 for (i
= 0; i
< gross_uuars
; i
++) {
959 if (uuarn
== 2 || uuarn
== 3)
960 set_bit(i
, uuari
->bitmap
);
963 uuari
->count
= kcalloc(gross_uuars
, sizeof(*uuari
->count
), GFP_KERNEL
);
969 for (i
= 0; i
< num_uars
; i
++) {
970 err
= mlx5_cmd_alloc_uar(dev
->mdev
, &uars
[i
].index
);
975 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
976 context
->ibucontext
.invalidate_range
= &mlx5_ib_invalidate_range
;
979 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
)) {
980 err
= mlx5_core_alloc_transport_domain(dev
->mdev
,
986 INIT_LIST_HEAD(&context
->db_page_list
);
987 mutex_init(&context
->db_page_mutex
);
989 resp
.tot_uuars
= req
.total_num_uuars
;
990 resp
.num_ports
= MLX5_CAP_GEN(dev
->mdev
, num_ports
);
992 if (field_avail(typeof(resp
), cqe_version
, udata
->outlen
))
993 resp
.response_length
+= sizeof(resp
.cqe_version
);
996 * We don't want to expose information from the PCI bar that is located
997 * after 4096 bytes, so if the arch only supports larger pages, let's
998 * pretend we don't support reading the HCA's core clock. This is also
999 * forced by mmap function.
1001 if (PAGE_SIZE
<= 4096 &&
1002 field_avail(typeof(resp
), hca_core_clock_offset
, udata
->outlen
)) {
1004 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET
;
1005 resp
.hca_core_clock_offset
=
1006 offsetof(struct mlx5_init_seg
, internal_timer_h
) %
1008 resp
.response_length
+= sizeof(resp
.hca_core_clock_offset
) +
1009 sizeof(resp
.reserved2
) +
1010 sizeof(resp
.reserved3
);
1013 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
1018 uuari
->num_low_latency_uuars
= req
.num_low_latency_uuars
;
1020 uuari
->num_uars
= num_uars
;
1021 context
->cqe_version
= resp
.cqe_version
;
1023 return &context
->ibucontext
;
1026 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1027 mlx5_core_dealloc_transport_domain(dev
->mdev
, context
->tdn
);
1030 for (i
--; i
>= 0; i
--)
1031 mlx5_cmd_free_uar(dev
->mdev
, uars
[i
].index
);
1033 kfree(uuari
->count
);
1036 kfree(uuari
->bitmap
);
1043 return ERR_PTR(err
);
1046 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext
*ibcontext
)
1048 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1049 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
1050 struct mlx5_uuar_info
*uuari
= &context
->uuari
;
1053 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1054 mlx5_core_dealloc_transport_domain(dev
->mdev
, context
->tdn
);
1056 for (i
= 0; i
< uuari
->num_uars
; i
++) {
1057 if (mlx5_cmd_free_uar(dev
->mdev
, uuari
->uars
[i
].index
))
1058 mlx5_ib_warn(dev
, "failed to free UAR 0x%x\n", uuari
->uars
[i
].index
);
1061 kfree(uuari
->count
);
1062 kfree(uuari
->bitmap
);
1069 static phys_addr_t
uar_index2pfn(struct mlx5_ib_dev
*dev
, int index
)
1071 return (pci_resource_start(dev
->mdev
->pdev
, 0) >> PAGE_SHIFT
) + index
;
1074 static int get_command(unsigned long offset
)
1076 return (offset
>> MLX5_IB_MMAP_CMD_SHIFT
) & MLX5_IB_MMAP_CMD_MASK
;
1079 static int get_arg(unsigned long offset
)
1081 return offset
& ((1 << MLX5_IB_MMAP_CMD_SHIFT
) - 1);
1084 static int get_index(unsigned long offset
)
1086 return get_arg(offset
);
1089 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd
)
1092 case MLX5_IB_MMAP_WC_PAGE
:
1094 case MLX5_IB_MMAP_REGULAR_PAGE
:
1095 return "best effort WC";
1096 case MLX5_IB_MMAP_NC_PAGE
:
1103 static int uar_mmap(struct mlx5_ib_dev
*dev
, enum mlx5_ib_mmap_cmd cmd
,
1104 struct vm_area_struct
*vma
, struct mlx5_uuar_info
*uuari
)
1108 phys_addr_t pfn
, pa
;
1112 case MLX5_IB_MMAP_WC_PAGE
:
1113 /* Some architectures don't support WC memory */
1114 #if defined(CONFIG_X86)
1117 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1121 case MLX5_IB_MMAP_REGULAR_PAGE
:
1122 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1123 prot
= pgprot_writecombine(vma
->vm_page_prot
);
1125 case MLX5_IB_MMAP_NC_PAGE
:
1126 prot
= pgprot_noncached(vma
->vm_page_prot
);
1132 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
1135 idx
= get_index(vma
->vm_pgoff
);
1136 if (idx
>= uuari
->num_uars
)
1139 pfn
= uar_index2pfn(dev
, uuari
->uars
[idx
].index
);
1140 mlx5_ib_dbg(dev
, "uar idx 0x%lx, pfn %pa\n", idx
, &pfn
);
1142 vma
->vm_page_prot
= prot
;
1143 err
= io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
1144 PAGE_SIZE
, vma
->vm_page_prot
);
1146 mlx5_ib_err(dev
, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1147 err
, vma
->vm_start
, &pfn
, mmap_cmd2str(cmd
));
1151 pa
= pfn
<< PAGE_SHIFT
;
1152 mlx5_ib_dbg(dev
, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd
),
1153 vma
->vm_start
, &pa
);
1158 static int mlx5_ib_mmap(struct ib_ucontext
*ibcontext
, struct vm_area_struct
*vma
)
1160 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1161 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
1162 struct mlx5_uuar_info
*uuari
= &context
->uuari
;
1163 unsigned long command
;
1166 command
= get_command(vma
->vm_pgoff
);
1168 case MLX5_IB_MMAP_WC_PAGE
:
1169 case MLX5_IB_MMAP_NC_PAGE
:
1170 case MLX5_IB_MMAP_REGULAR_PAGE
:
1171 return uar_mmap(dev
, command
, vma
, uuari
);
1173 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES
:
1176 case MLX5_IB_MMAP_CORE_CLOCK
:
1177 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
1180 if (vma
->vm_flags
& VM_WRITE
)
1183 /* Don't expose to user-space information it shouldn't have */
1184 if (PAGE_SIZE
> 4096)
1187 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
1188 pfn
= (dev
->mdev
->iseg_base
+
1189 offsetof(struct mlx5_init_seg
, internal_timer_h
)) >>
1191 if (io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
1192 PAGE_SIZE
, vma
->vm_page_prot
))
1195 mlx5_ib_dbg(dev
, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1197 (unsigned long long)pfn
<< PAGE_SHIFT
);
1207 static struct ib_pd
*mlx5_ib_alloc_pd(struct ib_device
*ibdev
,
1208 struct ib_ucontext
*context
,
1209 struct ib_udata
*udata
)
1211 struct mlx5_ib_alloc_pd_resp resp
;
1212 struct mlx5_ib_pd
*pd
;
1215 pd
= kmalloc(sizeof(*pd
), GFP_KERNEL
);
1217 return ERR_PTR(-ENOMEM
);
1219 err
= mlx5_core_alloc_pd(to_mdev(ibdev
)->mdev
, &pd
->pdn
);
1222 return ERR_PTR(err
);
1227 if (ib_copy_to_udata(udata
, &resp
, sizeof(resp
))) {
1228 mlx5_core_dealloc_pd(to_mdev(ibdev
)->mdev
, pd
->pdn
);
1230 return ERR_PTR(-EFAULT
);
1237 static int mlx5_ib_dealloc_pd(struct ib_pd
*pd
)
1239 struct mlx5_ib_dev
*mdev
= to_mdev(pd
->device
);
1240 struct mlx5_ib_pd
*mpd
= to_mpd(pd
);
1242 mlx5_core_dealloc_pd(mdev
->mdev
, mpd
->pdn
);
1248 static bool outer_header_zero(u32
*match_criteria
)
1250 int size
= MLX5_ST_SZ_BYTES(fte_match_param
);
1251 char *outer_headers_c
= MLX5_ADDR_OF(fte_match_param
, match_criteria
,
1254 return outer_headers_c
[0] == 0 && !memcmp(outer_headers_c
,
1255 outer_headers_c
+ 1,
1259 static int parse_flow_attr(u32
*match_c
, u32
*match_v
,
1260 union ib_flow_spec
*ib_spec
)
1262 void *outer_headers_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
1264 void *outer_headers_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
1266 switch (ib_spec
->type
) {
1267 case IB_FLOW_SPEC_ETH
:
1268 if (ib_spec
->size
!= sizeof(ib_spec
->eth
))
1271 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_c
,
1273 ib_spec
->eth
.mask
.dst_mac
);
1274 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_v
,
1276 ib_spec
->eth
.val
.dst_mac
);
1278 if (ib_spec
->eth
.mask
.vlan_tag
) {
1279 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1281 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1284 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1285 first_vid
, ntohs(ib_spec
->eth
.mask
.vlan_tag
));
1286 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1287 first_vid
, ntohs(ib_spec
->eth
.val
.vlan_tag
));
1289 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1291 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 12);
1292 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1294 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 12);
1296 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1298 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 13);
1299 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1301 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 13);
1303 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1304 ethertype
, ntohs(ib_spec
->eth
.mask
.ether_type
));
1305 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1306 ethertype
, ntohs(ib_spec
->eth
.val
.ether_type
));
1308 case IB_FLOW_SPEC_IPV4
:
1309 if (ib_spec
->size
!= sizeof(ib_spec
->ipv4
))
1312 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
,
1314 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
,
1315 ethertype
, ETH_P_IP
);
1317 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_c
,
1318 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
1319 &ib_spec
->ipv4
.mask
.src_ip
,
1320 sizeof(ib_spec
->ipv4
.mask
.src_ip
));
1321 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_v
,
1322 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
1323 &ib_spec
->ipv4
.val
.src_ip
,
1324 sizeof(ib_spec
->ipv4
.val
.src_ip
));
1325 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_c
,
1326 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
1327 &ib_spec
->ipv4
.mask
.dst_ip
,
1328 sizeof(ib_spec
->ipv4
.mask
.dst_ip
));
1329 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, outer_headers_v
,
1330 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
1331 &ib_spec
->ipv4
.val
.dst_ip
,
1332 sizeof(ib_spec
->ipv4
.val
.dst_ip
));
1334 case IB_FLOW_SPEC_TCP
:
1335 if (ib_spec
->size
!= sizeof(ib_spec
->tcp_udp
))
1338 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, ip_protocol
,
1340 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, ip_protocol
,
1343 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, tcp_sport
,
1344 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
1345 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, tcp_sport
,
1346 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
1348 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, tcp_dport
,
1349 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
1350 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, tcp_dport
,
1351 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
1353 case IB_FLOW_SPEC_UDP
:
1354 if (ib_spec
->size
!= sizeof(ib_spec
->tcp_udp
))
1357 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, ip_protocol
,
1359 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, ip_protocol
,
1362 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, udp_sport
,
1363 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
1364 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, udp_sport
,
1365 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
1367 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_c
, udp_dport
,
1368 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
1369 MLX5_SET(fte_match_set_lyr_2_4
, outer_headers_v
, udp_dport
,
1370 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
1379 /* If a flow could catch both multicast and unicast packets,
1380 * it won't fall into the multicast flow steering table and this rule
1381 * could steal other multicast packets.
1383 static bool flow_is_multicast_only(struct ib_flow_attr
*ib_attr
)
1385 struct ib_flow_spec_eth
*eth_spec
;
1387 if (ib_attr
->type
!= IB_FLOW_ATTR_NORMAL
||
1388 ib_attr
->size
< sizeof(struct ib_flow_attr
) +
1389 sizeof(struct ib_flow_spec_eth
) ||
1390 ib_attr
->num_of_specs
< 1)
1393 eth_spec
= (struct ib_flow_spec_eth
*)(ib_attr
+ 1);
1394 if (eth_spec
->type
!= IB_FLOW_SPEC_ETH
||
1395 eth_spec
->size
!= sizeof(*eth_spec
))
1398 return is_multicast_ether_addr(eth_spec
->mask
.dst_mac
) &&
1399 is_multicast_ether_addr(eth_spec
->val
.dst_mac
);
1402 static bool is_valid_attr(struct ib_flow_attr
*flow_attr
)
1404 union ib_flow_spec
*ib_spec
= (union ib_flow_spec
*)(flow_attr
+ 1);
1405 bool has_ipv4_spec
= false;
1406 bool eth_type_ipv4
= true;
1407 unsigned int spec_index
;
1409 /* Validate that ethertype is correct */
1410 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
1411 if (ib_spec
->type
== IB_FLOW_SPEC_ETH
&&
1412 ib_spec
->eth
.mask
.ether_type
) {
1413 if (!((ib_spec
->eth
.mask
.ether_type
== htons(0xffff)) &&
1414 ib_spec
->eth
.val
.ether_type
== htons(ETH_P_IP
)))
1415 eth_type_ipv4
= false;
1416 } else if (ib_spec
->type
== IB_FLOW_SPEC_IPV4
) {
1417 has_ipv4_spec
= true;
1419 ib_spec
= (void *)ib_spec
+ ib_spec
->size
;
1421 return !has_ipv4_spec
|| eth_type_ipv4
;
1424 static void put_flow_table(struct mlx5_ib_dev
*dev
,
1425 struct mlx5_ib_flow_prio
*prio
, bool ft_added
)
1427 prio
->refcount
-= !!ft_added
;
1428 if (!prio
->refcount
) {
1429 mlx5_destroy_flow_table(prio
->flow_table
);
1430 prio
->flow_table
= NULL
;
1434 static int mlx5_ib_destroy_flow(struct ib_flow
*flow_id
)
1436 struct mlx5_ib_dev
*dev
= to_mdev(flow_id
->qp
->device
);
1437 struct mlx5_ib_flow_handler
*handler
= container_of(flow_id
,
1438 struct mlx5_ib_flow_handler
,
1440 struct mlx5_ib_flow_handler
*iter
, *tmp
;
1442 mutex_lock(&dev
->flow_db
.lock
);
1444 list_for_each_entry_safe(iter
, tmp
, &handler
->list
, list
) {
1445 mlx5_del_flow_rule(iter
->rule
);
1446 list_del(&iter
->list
);
1450 mlx5_del_flow_rule(handler
->rule
);
1451 put_flow_table(dev
, &dev
->flow_db
.prios
[handler
->prio
], true);
1452 mutex_unlock(&dev
->flow_db
.lock
);
1459 static int ib_prio_to_core_prio(unsigned int priority
, bool dont_trap
)
1467 #define MLX5_FS_MAX_TYPES 10
1468 #define MLX5_FS_MAX_ENTRIES 32000UL
1469 static struct mlx5_ib_flow_prio
*get_flow_table(struct mlx5_ib_dev
*dev
,
1470 struct ib_flow_attr
*flow_attr
)
1472 bool dont_trap
= flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
;
1473 struct mlx5_flow_namespace
*ns
= NULL
;
1474 struct mlx5_ib_flow_prio
*prio
;
1475 struct mlx5_flow_table
*ft
;
1481 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
1482 if (flow_is_multicast_only(flow_attr
) &&
1484 priority
= MLX5_IB_FLOW_MCAST_PRIO
;
1486 priority
= ib_prio_to_core_prio(flow_attr
->priority
,
1488 ns
= mlx5_get_flow_namespace(dev
->mdev
,
1489 MLX5_FLOW_NAMESPACE_BYPASS
);
1490 num_entries
= MLX5_FS_MAX_ENTRIES
;
1491 num_groups
= MLX5_FS_MAX_TYPES
;
1492 prio
= &dev
->flow_db
.prios
[priority
];
1493 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
1494 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
1495 ns
= mlx5_get_flow_namespace(dev
->mdev
,
1496 MLX5_FLOW_NAMESPACE_LEFTOVERS
);
1497 build_leftovers_ft_param(&priority
,
1500 prio
= &dev
->flow_db
.prios
[MLX5_IB_FLOW_LEFTOVERS_PRIO
];
1504 return ERR_PTR(-ENOTSUPP
);
1506 ft
= prio
->flow_table
;
1508 ft
= mlx5_create_auto_grouped_flow_table(ns
, priority
,
1515 prio
->flow_table
= ft
;
1521 return err
? ERR_PTR(err
) : prio
;
1524 static struct mlx5_ib_flow_handler
*create_flow_rule(struct mlx5_ib_dev
*dev
,
1525 struct mlx5_ib_flow_prio
*ft_prio
,
1526 struct ib_flow_attr
*flow_attr
,
1527 struct mlx5_flow_destination
*dst
)
1529 struct mlx5_flow_table
*ft
= ft_prio
->flow_table
;
1530 struct mlx5_ib_flow_handler
*handler
;
1531 void *ib_flow
= flow_attr
+ 1;
1532 u8 match_criteria_enable
= 0;
1533 unsigned int spec_index
;
1539 if (!is_valid_attr(flow_attr
))
1540 return ERR_PTR(-EINVAL
);
1542 match_c
= kzalloc(MLX5_ST_SZ_BYTES(fte_match_param
), GFP_KERNEL
);
1543 match_v
= kzalloc(MLX5_ST_SZ_BYTES(fte_match_param
), GFP_KERNEL
);
1544 handler
= kzalloc(sizeof(*handler
), GFP_KERNEL
);
1545 if (!handler
|| !match_c
|| !match_v
) {
1550 INIT_LIST_HEAD(&handler
->list
);
1552 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
1553 err
= parse_flow_attr(match_c
, match_v
, ib_flow
);
1557 ib_flow
+= ((union ib_flow_spec
*)ib_flow
)->size
;
1560 /* Outer header support only */
1561 match_criteria_enable
= (!outer_header_zero(match_c
)) << 0;
1562 action
= dst
? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
:
1563 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO
;
1564 handler
->rule
= mlx5_add_flow_rule(ft
, match_criteria_enable
,
1567 MLX5_FS_DEFAULT_FLOW_TAG
,
1570 if (IS_ERR(handler
->rule
)) {
1571 err
= PTR_ERR(handler
->rule
);
1575 handler
->prio
= ft_prio
- dev
->flow_db
.prios
;
1577 ft_prio
->flow_table
= ft
;
1583 return err
? ERR_PTR(err
) : handler
;
1586 static struct mlx5_ib_flow_handler
*create_dont_trap_rule(struct mlx5_ib_dev
*dev
,
1587 struct mlx5_ib_flow_prio
*ft_prio
,
1588 struct ib_flow_attr
*flow_attr
,
1589 struct mlx5_flow_destination
*dst
)
1591 struct mlx5_ib_flow_handler
*handler_dst
= NULL
;
1592 struct mlx5_ib_flow_handler
*handler
= NULL
;
1594 handler
= create_flow_rule(dev
, ft_prio
, flow_attr
, NULL
);
1595 if (!IS_ERR(handler
)) {
1596 handler_dst
= create_flow_rule(dev
, ft_prio
,
1598 if (IS_ERR(handler_dst
)) {
1599 mlx5_del_flow_rule(handler
->rule
);
1601 handler
= handler_dst
;
1603 list_add(&handler_dst
->list
, &handler
->list
);
1614 static struct mlx5_ib_flow_handler
*create_leftovers_rule(struct mlx5_ib_dev
*dev
,
1615 struct mlx5_ib_flow_prio
*ft_prio
,
1616 struct ib_flow_attr
*flow_attr
,
1617 struct mlx5_flow_destination
*dst
)
1619 struct mlx5_ib_flow_handler
*handler_ucast
= NULL
;
1620 struct mlx5_ib_flow_handler
*handler
= NULL
;
1623 struct ib_flow_attr flow_attr
;
1624 struct ib_flow_spec_eth eth_flow
;
1625 } leftovers_specs
[] = {
1629 .size
= sizeof(leftovers_specs
[0])
1632 .type
= IB_FLOW_SPEC_ETH
,
1633 .size
= sizeof(struct ib_flow_spec_eth
),
1634 .mask
= {.dst_mac
= {0x1} },
1635 .val
= {.dst_mac
= {0x1} }
1641 .size
= sizeof(leftovers_specs
[0])
1644 .type
= IB_FLOW_SPEC_ETH
,
1645 .size
= sizeof(struct ib_flow_spec_eth
),
1646 .mask
= {.dst_mac
= {0x1} },
1647 .val
= {.dst_mac
= {} }
1652 handler
= create_flow_rule(dev
, ft_prio
,
1653 &leftovers_specs
[LEFTOVERS_MC
].flow_attr
,
1655 if (!IS_ERR(handler
) &&
1656 flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
) {
1657 handler_ucast
= create_flow_rule(dev
, ft_prio
,
1658 &leftovers_specs
[LEFTOVERS_UC
].flow_attr
,
1660 if (IS_ERR(handler_ucast
)) {
1662 handler
= handler_ucast
;
1664 list_add(&handler_ucast
->list
, &handler
->list
);
1671 static struct ib_flow
*mlx5_ib_create_flow(struct ib_qp
*qp
,
1672 struct ib_flow_attr
*flow_attr
,
1675 struct mlx5_ib_dev
*dev
= to_mdev(qp
->device
);
1676 struct mlx5_ib_flow_handler
*handler
= NULL
;
1677 struct mlx5_flow_destination
*dst
= NULL
;
1678 struct mlx5_ib_flow_prio
*ft_prio
;
1681 if (flow_attr
->priority
> MLX5_IB_FLOW_LAST_PRIO
)
1682 return ERR_PTR(-ENOSPC
);
1684 if (domain
!= IB_FLOW_DOMAIN_USER
||
1685 flow_attr
->port
> MLX5_CAP_GEN(dev
->mdev
, num_ports
) ||
1686 (flow_attr
->flags
& ~IB_FLOW_ATTR_FLAGS_DONT_TRAP
))
1687 return ERR_PTR(-EINVAL
);
1689 dst
= kzalloc(sizeof(*dst
), GFP_KERNEL
);
1691 return ERR_PTR(-ENOMEM
);
1693 mutex_lock(&dev
->flow_db
.lock
);
1695 ft_prio
= get_flow_table(dev
, flow_attr
);
1696 if (IS_ERR(ft_prio
)) {
1697 err
= PTR_ERR(ft_prio
);
1701 dst
->type
= MLX5_FLOW_DESTINATION_TYPE_TIR
;
1702 dst
->tir_num
= to_mqp(qp
)->raw_packet_qp
.rq
.tirn
;
1704 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
1705 if (flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
) {
1706 handler
= create_dont_trap_rule(dev
, ft_prio
,
1709 handler
= create_flow_rule(dev
, ft_prio
, flow_attr
,
1712 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
1713 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
1714 handler
= create_leftovers_rule(dev
, ft_prio
, flow_attr
,
1721 if (IS_ERR(handler
)) {
1722 err
= PTR_ERR(handler
);
1727 ft_prio
->refcount
++;
1728 mutex_unlock(&dev
->flow_db
.lock
);
1731 return &handler
->ibflow
;
1734 put_flow_table(dev
, ft_prio
, false);
1736 mutex_unlock(&dev
->flow_db
.lock
);
1739 return ERR_PTR(err
);
1742 static int mlx5_ib_mcg_attach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
1744 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
1747 err
= mlx5_core_attach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
1749 mlx5_ib_warn(dev
, "failed attaching QPN 0x%x, MGID %pI6\n",
1750 ibqp
->qp_num
, gid
->raw
);
1755 static int mlx5_ib_mcg_detach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
1757 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
1760 err
= mlx5_core_detach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
1762 mlx5_ib_warn(dev
, "failed detaching QPN 0x%x, MGID %pI6\n",
1763 ibqp
->qp_num
, gid
->raw
);
1768 static int init_node_data(struct mlx5_ib_dev
*dev
)
1772 err
= mlx5_query_node_desc(dev
, dev
->ib_dev
.node_desc
);
1776 dev
->mdev
->rev_id
= dev
->mdev
->pdev
->revision
;
1778 return mlx5_query_node_guid(dev
, &dev
->ib_dev
.node_guid
);
1781 static ssize_t
show_fw_pages(struct device
*device
, struct device_attribute
*attr
,
1784 struct mlx5_ib_dev
*dev
=
1785 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1787 return sprintf(buf
, "%d\n", dev
->mdev
->priv
.fw_pages
);
1790 static ssize_t
show_reg_pages(struct device
*device
,
1791 struct device_attribute
*attr
, char *buf
)
1793 struct mlx5_ib_dev
*dev
=
1794 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1796 return sprintf(buf
, "%d\n", atomic_read(&dev
->mdev
->priv
.reg_pages
));
1799 static ssize_t
show_hca(struct device
*device
, struct device_attribute
*attr
,
1802 struct mlx5_ib_dev
*dev
=
1803 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1804 return sprintf(buf
, "MT%d\n", dev
->mdev
->pdev
->device
);
1807 static ssize_t
show_fw_ver(struct device
*device
, struct device_attribute
*attr
,
1810 struct mlx5_ib_dev
*dev
=
1811 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1812 return sprintf(buf
, "%d.%d.%04d\n", fw_rev_maj(dev
->mdev
),
1813 fw_rev_min(dev
->mdev
), fw_rev_sub(dev
->mdev
));
1816 static ssize_t
show_rev(struct device
*device
, struct device_attribute
*attr
,
1819 struct mlx5_ib_dev
*dev
=
1820 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1821 return sprintf(buf
, "%x\n", dev
->mdev
->rev_id
);
1824 static ssize_t
show_board(struct device
*device
, struct device_attribute
*attr
,
1827 struct mlx5_ib_dev
*dev
=
1828 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
1829 return sprintf(buf
, "%.*s\n", MLX5_BOARD_ID_LEN
,
1830 dev
->mdev
->board_id
);
1833 static DEVICE_ATTR(hw_rev
, S_IRUGO
, show_rev
, NULL
);
1834 static DEVICE_ATTR(fw_ver
, S_IRUGO
, show_fw_ver
, NULL
);
1835 static DEVICE_ATTR(hca_type
, S_IRUGO
, show_hca
, NULL
);
1836 static DEVICE_ATTR(board_id
, S_IRUGO
, show_board
, NULL
);
1837 static DEVICE_ATTR(fw_pages
, S_IRUGO
, show_fw_pages
, NULL
);
1838 static DEVICE_ATTR(reg_pages
, S_IRUGO
, show_reg_pages
, NULL
);
1840 static struct device_attribute
*mlx5_class_attributes
[] = {
1846 &dev_attr_reg_pages
,
1849 static void pkey_change_handler(struct work_struct
*work
)
1851 struct mlx5_ib_port_resources
*ports
=
1852 container_of(work
, struct mlx5_ib_port_resources
,
1855 mutex_lock(&ports
->devr
->mutex
);
1856 mlx5_ib_gsi_pkey_change(ports
->gsi
);
1857 mutex_unlock(&ports
->devr
->mutex
);
1860 static void mlx5_ib_event(struct mlx5_core_dev
*dev
, void *context
,
1861 enum mlx5_dev_event event
, unsigned long param
)
1863 struct mlx5_ib_dev
*ibdev
= (struct mlx5_ib_dev
*)context
;
1864 struct ib_event ibev
;
1869 case MLX5_DEV_EVENT_SYS_ERROR
:
1870 ibdev
->ib_active
= false;
1871 ibev
.event
= IB_EVENT_DEVICE_FATAL
;
1874 case MLX5_DEV_EVENT_PORT_UP
:
1875 ibev
.event
= IB_EVENT_PORT_ACTIVE
;
1879 case MLX5_DEV_EVENT_PORT_DOWN
:
1880 case MLX5_DEV_EVENT_PORT_INITIALIZED
:
1881 ibev
.event
= IB_EVENT_PORT_ERR
;
1885 case MLX5_DEV_EVENT_LID_CHANGE
:
1886 ibev
.event
= IB_EVENT_LID_CHANGE
;
1890 case MLX5_DEV_EVENT_PKEY_CHANGE
:
1891 ibev
.event
= IB_EVENT_PKEY_CHANGE
;
1894 schedule_work(&ibdev
->devr
.ports
[port
- 1].pkey_change_work
);
1897 case MLX5_DEV_EVENT_GUID_CHANGE
:
1898 ibev
.event
= IB_EVENT_GID_CHANGE
;
1902 case MLX5_DEV_EVENT_CLIENT_REREG
:
1903 ibev
.event
= IB_EVENT_CLIENT_REREGISTER
;
1908 ibev
.device
= &ibdev
->ib_dev
;
1909 ibev
.element
.port_num
= port
;
1911 if (port
< 1 || port
> ibdev
->num_ports
) {
1912 mlx5_ib_warn(ibdev
, "warning: event on port %d\n", port
);
1916 if (ibdev
->ib_active
)
1917 ib_dispatch_event(&ibev
);
1920 static void get_ext_port_caps(struct mlx5_ib_dev
*dev
)
1924 for (port
= 1; port
<= MLX5_CAP_GEN(dev
->mdev
, num_ports
); port
++)
1925 mlx5_query_ext_port_caps(dev
, port
);
1928 static int get_port_caps(struct mlx5_ib_dev
*dev
)
1930 struct ib_device_attr
*dprops
= NULL
;
1931 struct ib_port_attr
*pprops
= NULL
;
1934 struct ib_udata uhw
= {.inlen
= 0, .outlen
= 0};
1936 pprops
= kmalloc(sizeof(*pprops
), GFP_KERNEL
);
1940 dprops
= kmalloc(sizeof(*dprops
), GFP_KERNEL
);
1944 err
= mlx5_ib_query_device(&dev
->ib_dev
, dprops
, &uhw
);
1946 mlx5_ib_warn(dev
, "query_device failed %d\n", err
);
1950 for (port
= 1; port
<= MLX5_CAP_GEN(dev
->mdev
, num_ports
); port
++) {
1951 err
= mlx5_ib_query_port(&dev
->ib_dev
, port
, pprops
);
1953 mlx5_ib_warn(dev
, "query_port %d failed %d\n",
1957 dev
->mdev
->port_caps
[port
- 1].pkey_table_len
=
1959 dev
->mdev
->port_caps
[port
- 1].gid_table_len
=
1960 pprops
->gid_tbl_len
;
1961 mlx5_ib_dbg(dev
, "pkey_table_len %d, gid_table_len %d\n",
1962 dprops
->max_pkeys
, pprops
->gid_tbl_len
);
1972 static void destroy_umrc_res(struct mlx5_ib_dev
*dev
)
1976 err
= mlx5_mr_cache_cleanup(dev
);
1978 mlx5_ib_warn(dev
, "mr cache cleanup failed\n");
1980 mlx5_ib_destroy_qp(dev
->umrc
.qp
);
1981 ib_free_cq(dev
->umrc
.cq
);
1982 ib_dealloc_pd(dev
->umrc
.pd
);
1989 static int create_umr_res(struct mlx5_ib_dev
*dev
)
1991 struct ib_qp_init_attr
*init_attr
= NULL
;
1992 struct ib_qp_attr
*attr
= NULL
;
1998 attr
= kzalloc(sizeof(*attr
), GFP_KERNEL
);
1999 init_attr
= kzalloc(sizeof(*init_attr
), GFP_KERNEL
);
2000 if (!attr
|| !init_attr
) {
2005 pd
= ib_alloc_pd(&dev
->ib_dev
);
2007 mlx5_ib_dbg(dev
, "Couldn't create PD for sync UMR QP\n");
2012 cq
= ib_alloc_cq(&dev
->ib_dev
, NULL
, 128, 0, IB_POLL_SOFTIRQ
);
2014 mlx5_ib_dbg(dev
, "Couldn't create CQ for sync UMR QP\n");
2019 init_attr
->send_cq
= cq
;
2020 init_attr
->recv_cq
= cq
;
2021 init_attr
->sq_sig_type
= IB_SIGNAL_ALL_WR
;
2022 init_attr
->cap
.max_send_wr
= MAX_UMR_WR
;
2023 init_attr
->cap
.max_send_sge
= 1;
2024 init_attr
->qp_type
= MLX5_IB_QPT_REG_UMR
;
2025 init_attr
->port_num
= 1;
2026 qp
= mlx5_ib_create_qp(pd
, init_attr
, NULL
);
2028 mlx5_ib_dbg(dev
, "Couldn't create sync UMR QP\n");
2032 qp
->device
= &dev
->ib_dev
;
2035 qp
->qp_type
= MLX5_IB_QPT_REG_UMR
;
2037 attr
->qp_state
= IB_QPS_INIT
;
2039 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
| IB_QP_PKEY_INDEX
|
2042 mlx5_ib_dbg(dev
, "Couldn't modify UMR QP\n");
2046 memset(attr
, 0, sizeof(*attr
));
2047 attr
->qp_state
= IB_QPS_RTR
;
2048 attr
->path_mtu
= IB_MTU_256
;
2050 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
2052 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rtr\n");
2056 memset(attr
, 0, sizeof(*attr
));
2057 attr
->qp_state
= IB_QPS_RTS
;
2058 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
2060 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rts\n");
2068 sema_init(&dev
->umrc
.sem
, MAX_UMR_WR
);
2069 ret
= mlx5_mr_cache_init(dev
);
2071 mlx5_ib_warn(dev
, "mr cache init failed %d\n", ret
);
2081 mlx5_ib_destroy_qp(qp
);
2095 static int create_dev_resources(struct mlx5_ib_resources
*devr
)
2097 struct ib_srq_init_attr attr
;
2098 struct mlx5_ib_dev
*dev
;
2099 struct ib_cq_init_attr cq_attr
= {.cqe
= 1};
2103 dev
= container_of(devr
, struct mlx5_ib_dev
, devr
);
2105 mutex_init(&devr
->mutex
);
2107 devr
->p0
= mlx5_ib_alloc_pd(&dev
->ib_dev
, NULL
, NULL
);
2108 if (IS_ERR(devr
->p0
)) {
2109 ret
= PTR_ERR(devr
->p0
);
2112 devr
->p0
->device
= &dev
->ib_dev
;
2113 devr
->p0
->uobject
= NULL
;
2114 atomic_set(&devr
->p0
->usecnt
, 0);
2116 devr
->c0
= mlx5_ib_create_cq(&dev
->ib_dev
, &cq_attr
, NULL
, NULL
);
2117 if (IS_ERR(devr
->c0
)) {
2118 ret
= PTR_ERR(devr
->c0
);
2121 devr
->c0
->device
= &dev
->ib_dev
;
2122 devr
->c0
->uobject
= NULL
;
2123 devr
->c0
->comp_handler
= NULL
;
2124 devr
->c0
->event_handler
= NULL
;
2125 devr
->c0
->cq_context
= NULL
;
2126 atomic_set(&devr
->c0
->usecnt
, 0);
2128 devr
->x0
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
2129 if (IS_ERR(devr
->x0
)) {
2130 ret
= PTR_ERR(devr
->x0
);
2133 devr
->x0
->device
= &dev
->ib_dev
;
2134 devr
->x0
->inode
= NULL
;
2135 atomic_set(&devr
->x0
->usecnt
, 0);
2136 mutex_init(&devr
->x0
->tgt_qp_mutex
);
2137 INIT_LIST_HEAD(&devr
->x0
->tgt_qp_list
);
2139 devr
->x1
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
2140 if (IS_ERR(devr
->x1
)) {
2141 ret
= PTR_ERR(devr
->x1
);
2144 devr
->x1
->device
= &dev
->ib_dev
;
2145 devr
->x1
->inode
= NULL
;
2146 atomic_set(&devr
->x1
->usecnt
, 0);
2147 mutex_init(&devr
->x1
->tgt_qp_mutex
);
2148 INIT_LIST_HEAD(&devr
->x1
->tgt_qp_list
);
2150 memset(&attr
, 0, sizeof(attr
));
2151 attr
.attr
.max_sge
= 1;
2152 attr
.attr
.max_wr
= 1;
2153 attr
.srq_type
= IB_SRQT_XRC
;
2154 attr
.ext
.xrc
.cq
= devr
->c0
;
2155 attr
.ext
.xrc
.xrcd
= devr
->x0
;
2157 devr
->s0
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
2158 if (IS_ERR(devr
->s0
)) {
2159 ret
= PTR_ERR(devr
->s0
);
2162 devr
->s0
->device
= &dev
->ib_dev
;
2163 devr
->s0
->pd
= devr
->p0
;
2164 devr
->s0
->uobject
= NULL
;
2165 devr
->s0
->event_handler
= NULL
;
2166 devr
->s0
->srq_context
= NULL
;
2167 devr
->s0
->srq_type
= IB_SRQT_XRC
;
2168 devr
->s0
->ext
.xrc
.xrcd
= devr
->x0
;
2169 devr
->s0
->ext
.xrc
.cq
= devr
->c0
;
2170 atomic_inc(&devr
->s0
->ext
.xrc
.xrcd
->usecnt
);
2171 atomic_inc(&devr
->s0
->ext
.xrc
.cq
->usecnt
);
2172 atomic_inc(&devr
->p0
->usecnt
);
2173 atomic_set(&devr
->s0
->usecnt
, 0);
2175 memset(&attr
, 0, sizeof(attr
));
2176 attr
.attr
.max_sge
= 1;
2177 attr
.attr
.max_wr
= 1;
2178 attr
.srq_type
= IB_SRQT_BASIC
;
2179 devr
->s1
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
2180 if (IS_ERR(devr
->s1
)) {
2181 ret
= PTR_ERR(devr
->s1
);
2184 devr
->s1
->device
= &dev
->ib_dev
;
2185 devr
->s1
->pd
= devr
->p0
;
2186 devr
->s1
->uobject
= NULL
;
2187 devr
->s1
->event_handler
= NULL
;
2188 devr
->s1
->srq_context
= NULL
;
2189 devr
->s1
->srq_type
= IB_SRQT_BASIC
;
2190 devr
->s1
->ext
.xrc
.cq
= devr
->c0
;
2191 atomic_inc(&devr
->p0
->usecnt
);
2192 atomic_set(&devr
->s0
->usecnt
, 0);
2194 for (port
= 0; port
< ARRAY_SIZE(devr
->ports
); ++port
) {
2195 INIT_WORK(&devr
->ports
[port
].pkey_change_work
,
2196 pkey_change_handler
);
2197 devr
->ports
[port
].devr
= devr
;
2203 mlx5_ib_destroy_srq(devr
->s0
);
2205 mlx5_ib_dealloc_xrcd(devr
->x1
);
2207 mlx5_ib_dealloc_xrcd(devr
->x0
);
2209 mlx5_ib_destroy_cq(devr
->c0
);
2211 mlx5_ib_dealloc_pd(devr
->p0
);
2216 static void destroy_dev_resources(struct mlx5_ib_resources
*devr
)
2218 struct mlx5_ib_dev
*dev
=
2219 container_of(devr
, struct mlx5_ib_dev
, devr
);
2222 mlx5_ib_destroy_srq(devr
->s1
);
2223 mlx5_ib_destroy_srq(devr
->s0
);
2224 mlx5_ib_dealloc_xrcd(devr
->x0
);
2225 mlx5_ib_dealloc_xrcd(devr
->x1
);
2226 mlx5_ib_destroy_cq(devr
->c0
);
2227 mlx5_ib_dealloc_pd(devr
->p0
);
2229 /* Make sure no change P_Key work items are still executing */
2230 for (port
= 0; port
< dev
->num_ports
; ++port
)
2231 cancel_work_sync(&devr
->ports
[port
].pkey_change_work
);
2234 static u32
get_core_cap_flags(struct ib_device
*ibdev
)
2236 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
2237 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(ibdev
, 1);
2238 u8 l3_type_cap
= MLX5_CAP_ROCE(dev
->mdev
, l3_type
);
2239 u8 roce_version_cap
= MLX5_CAP_ROCE(dev
->mdev
, roce_version
);
2242 if (ll
== IB_LINK_LAYER_INFINIBAND
)
2243 return RDMA_CORE_PORT_IBA_IB
;
2245 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV4_CAP
))
2248 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV6_CAP
))
2251 if (roce_version_cap
& MLX5_ROCE_VERSION_1_CAP
)
2252 ret
|= RDMA_CORE_PORT_IBA_ROCE
;
2254 if (roce_version_cap
& MLX5_ROCE_VERSION_2_CAP
)
2255 ret
|= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP
;
2260 static int mlx5_port_immutable(struct ib_device
*ibdev
, u8 port_num
,
2261 struct ib_port_immutable
*immutable
)
2263 struct ib_port_attr attr
;
2266 err
= mlx5_ib_query_port(ibdev
, port_num
, &attr
);
2270 immutable
->pkey_tbl_len
= attr
.pkey_tbl_len
;
2271 immutable
->gid_tbl_len
= attr
.gid_tbl_len
;
2272 immutable
->core_cap_flags
= get_core_cap_flags(ibdev
);
2273 immutable
->max_mad_size
= IB_MGMT_MAD_SIZE
;
2278 static int mlx5_enable_roce(struct mlx5_ib_dev
*dev
)
2282 dev
->roce
.nb
.notifier_call
= mlx5_netdev_event
;
2283 err
= register_netdevice_notifier(&dev
->roce
.nb
);
2287 err
= mlx5_nic_vport_enable_roce(dev
->mdev
);
2289 goto err_unregister_netdevice_notifier
;
2293 err_unregister_netdevice_notifier
:
2294 unregister_netdevice_notifier(&dev
->roce
.nb
);
2298 static void mlx5_disable_roce(struct mlx5_ib_dev
*dev
)
2300 mlx5_nic_vport_disable_roce(dev
->mdev
);
2301 unregister_netdevice_notifier(&dev
->roce
.nb
);
2304 static void *mlx5_ib_add(struct mlx5_core_dev
*mdev
)
2306 struct mlx5_ib_dev
*dev
;
2307 enum rdma_link_layer ll
;
2312 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
2313 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
2315 if ((ll
== IB_LINK_LAYER_ETHERNET
) && !MLX5_CAP_GEN(mdev
, roce
))
2318 printk_once(KERN_INFO
"%s", mlx5_version
);
2320 dev
= (struct mlx5_ib_dev
*)ib_alloc_device(sizeof(*dev
));
2326 rwlock_init(&dev
->roce
.netdev_lock
);
2327 err
= get_port_caps(dev
);
2331 if (mlx5_use_mad_ifc(dev
))
2332 get_ext_port_caps(dev
);
2334 MLX5_INIT_DOORBELL_LOCK(&dev
->uar_lock
);
2336 strlcpy(dev
->ib_dev
.name
, "mlx5_%d", IB_DEVICE_NAME_MAX
);
2337 dev
->ib_dev
.owner
= THIS_MODULE
;
2338 dev
->ib_dev
.node_type
= RDMA_NODE_IB_CA
;
2339 dev
->ib_dev
.local_dma_lkey
= 0 /* not supported for now */;
2340 dev
->num_ports
= MLX5_CAP_GEN(mdev
, num_ports
);
2341 dev
->ib_dev
.phys_port_cnt
= dev
->num_ports
;
2342 dev
->ib_dev
.num_comp_vectors
=
2343 dev
->mdev
->priv
.eq_table
.num_comp_vectors
;
2344 dev
->ib_dev
.dma_device
= &mdev
->pdev
->dev
;
2346 dev
->ib_dev
.uverbs_abi_ver
= MLX5_IB_UVERBS_ABI_VERSION
;
2347 dev
->ib_dev
.uverbs_cmd_mask
=
2348 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT
) |
2349 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE
) |
2350 (1ull << IB_USER_VERBS_CMD_QUERY_PORT
) |
2351 (1ull << IB_USER_VERBS_CMD_ALLOC_PD
) |
2352 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD
) |
2353 (1ull << IB_USER_VERBS_CMD_REG_MR
) |
2354 (1ull << IB_USER_VERBS_CMD_REREG_MR
) |
2355 (1ull << IB_USER_VERBS_CMD_DEREG_MR
) |
2356 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL
) |
2357 (1ull << IB_USER_VERBS_CMD_CREATE_CQ
) |
2358 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ
) |
2359 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ
) |
2360 (1ull << IB_USER_VERBS_CMD_CREATE_QP
) |
2361 (1ull << IB_USER_VERBS_CMD_MODIFY_QP
) |
2362 (1ull << IB_USER_VERBS_CMD_QUERY_QP
) |
2363 (1ull << IB_USER_VERBS_CMD_DESTROY_QP
) |
2364 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST
) |
2365 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST
) |
2366 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ
) |
2367 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ
) |
2368 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ
) |
2369 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ
) |
2370 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ
) |
2371 (1ull << IB_USER_VERBS_CMD_OPEN_QP
);
2372 dev
->ib_dev
.uverbs_ex_cmd_mask
=
2373 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE
) |
2374 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ
) |
2375 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP
);
2377 dev
->ib_dev
.query_device
= mlx5_ib_query_device
;
2378 dev
->ib_dev
.query_port
= mlx5_ib_query_port
;
2379 dev
->ib_dev
.get_link_layer
= mlx5_ib_port_link_layer
;
2380 if (ll
== IB_LINK_LAYER_ETHERNET
)
2381 dev
->ib_dev
.get_netdev
= mlx5_ib_get_netdev
;
2382 dev
->ib_dev
.query_gid
= mlx5_ib_query_gid
;
2383 dev
->ib_dev
.add_gid
= mlx5_ib_add_gid
;
2384 dev
->ib_dev
.del_gid
= mlx5_ib_del_gid
;
2385 dev
->ib_dev
.query_pkey
= mlx5_ib_query_pkey
;
2386 dev
->ib_dev
.modify_device
= mlx5_ib_modify_device
;
2387 dev
->ib_dev
.modify_port
= mlx5_ib_modify_port
;
2388 dev
->ib_dev
.alloc_ucontext
= mlx5_ib_alloc_ucontext
;
2389 dev
->ib_dev
.dealloc_ucontext
= mlx5_ib_dealloc_ucontext
;
2390 dev
->ib_dev
.mmap
= mlx5_ib_mmap
;
2391 dev
->ib_dev
.alloc_pd
= mlx5_ib_alloc_pd
;
2392 dev
->ib_dev
.dealloc_pd
= mlx5_ib_dealloc_pd
;
2393 dev
->ib_dev
.create_ah
= mlx5_ib_create_ah
;
2394 dev
->ib_dev
.query_ah
= mlx5_ib_query_ah
;
2395 dev
->ib_dev
.destroy_ah
= mlx5_ib_destroy_ah
;
2396 dev
->ib_dev
.create_srq
= mlx5_ib_create_srq
;
2397 dev
->ib_dev
.modify_srq
= mlx5_ib_modify_srq
;
2398 dev
->ib_dev
.query_srq
= mlx5_ib_query_srq
;
2399 dev
->ib_dev
.destroy_srq
= mlx5_ib_destroy_srq
;
2400 dev
->ib_dev
.post_srq_recv
= mlx5_ib_post_srq_recv
;
2401 dev
->ib_dev
.create_qp
= mlx5_ib_create_qp
;
2402 dev
->ib_dev
.modify_qp
= mlx5_ib_modify_qp
;
2403 dev
->ib_dev
.query_qp
= mlx5_ib_query_qp
;
2404 dev
->ib_dev
.destroy_qp
= mlx5_ib_destroy_qp
;
2405 dev
->ib_dev
.post_send
= mlx5_ib_post_send
;
2406 dev
->ib_dev
.post_recv
= mlx5_ib_post_recv
;
2407 dev
->ib_dev
.create_cq
= mlx5_ib_create_cq
;
2408 dev
->ib_dev
.modify_cq
= mlx5_ib_modify_cq
;
2409 dev
->ib_dev
.resize_cq
= mlx5_ib_resize_cq
;
2410 dev
->ib_dev
.destroy_cq
= mlx5_ib_destroy_cq
;
2411 dev
->ib_dev
.poll_cq
= mlx5_ib_poll_cq
;
2412 dev
->ib_dev
.req_notify_cq
= mlx5_ib_arm_cq
;
2413 dev
->ib_dev
.get_dma_mr
= mlx5_ib_get_dma_mr
;
2414 dev
->ib_dev
.reg_user_mr
= mlx5_ib_reg_user_mr
;
2415 dev
->ib_dev
.rereg_user_mr
= mlx5_ib_rereg_user_mr
;
2416 dev
->ib_dev
.dereg_mr
= mlx5_ib_dereg_mr
;
2417 dev
->ib_dev
.attach_mcast
= mlx5_ib_mcg_attach
;
2418 dev
->ib_dev
.detach_mcast
= mlx5_ib_mcg_detach
;
2419 dev
->ib_dev
.process_mad
= mlx5_ib_process_mad
;
2420 dev
->ib_dev
.alloc_mr
= mlx5_ib_alloc_mr
;
2421 dev
->ib_dev
.map_mr_sg
= mlx5_ib_map_mr_sg
;
2422 dev
->ib_dev
.check_mr_status
= mlx5_ib_check_mr_status
;
2423 dev
->ib_dev
.get_port_immutable
= mlx5_port_immutable
;
2424 if (mlx5_core_is_pf(mdev
)) {
2425 dev
->ib_dev
.get_vf_config
= mlx5_ib_get_vf_config
;
2426 dev
->ib_dev
.set_vf_link_state
= mlx5_ib_set_vf_link_state
;
2427 dev
->ib_dev
.get_vf_stats
= mlx5_ib_get_vf_stats
;
2428 dev
->ib_dev
.set_vf_guid
= mlx5_ib_set_vf_guid
;
2431 mlx5_ib_internal_fill_odp_caps(dev
);
2433 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
2434 dev
->ib_dev
.alloc_mw
= mlx5_ib_alloc_mw
;
2435 dev
->ib_dev
.dealloc_mw
= mlx5_ib_dealloc_mw
;
2436 dev
->ib_dev
.uverbs_cmd_mask
|=
2437 (1ull << IB_USER_VERBS_CMD_ALLOC_MW
) |
2438 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW
);
2441 if (MLX5_CAP_GEN(mdev
, xrc
)) {
2442 dev
->ib_dev
.alloc_xrcd
= mlx5_ib_alloc_xrcd
;
2443 dev
->ib_dev
.dealloc_xrcd
= mlx5_ib_dealloc_xrcd
;
2444 dev
->ib_dev
.uverbs_cmd_mask
|=
2445 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD
) |
2446 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD
);
2449 if (mlx5_ib_port_link_layer(&dev
->ib_dev
, 1) ==
2450 IB_LINK_LAYER_ETHERNET
) {
2451 dev
->ib_dev
.create_flow
= mlx5_ib_create_flow
;
2452 dev
->ib_dev
.destroy_flow
= mlx5_ib_destroy_flow
;
2453 dev
->ib_dev
.uverbs_ex_cmd_mask
|=
2454 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW
) |
2455 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW
);
2457 err
= init_node_data(dev
);
2461 mutex_init(&dev
->flow_db
.lock
);
2462 mutex_init(&dev
->cap_mask_mutex
);
2464 if (ll
== IB_LINK_LAYER_ETHERNET
) {
2465 err
= mlx5_enable_roce(dev
);
2470 err
= create_dev_resources(&dev
->devr
);
2472 goto err_disable_roce
;
2474 err
= mlx5_ib_odp_init_one(dev
);
2478 err
= ib_register_device(&dev
->ib_dev
, NULL
);
2482 err
= create_umr_res(dev
);
2486 for (i
= 0; i
< ARRAY_SIZE(mlx5_class_attributes
); i
++) {
2487 err
= device_create_file(&dev
->ib_dev
.dev
,
2488 mlx5_class_attributes
[i
]);
2493 dev
->ib_active
= true;
2498 destroy_umrc_res(dev
);
2501 ib_unregister_device(&dev
->ib_dev
);
2504 mlx5_ib_odp_remove_one(dev
);
2507 destroy_dev_resources(&dev
->devr
);
2510 if (ll
== IB_LINK_LAYER_ETHERNET
)
2511 mlx5_disable_roce(dev
);
2514 ib_dealloc_device((struct ib_device
*)dev
);
2519 static void mlx5_ib_remove(struct mlx5_core_dev
*mdev
, void *context
)
2521 struct mlx5_ib_dev
*dev
= context
;
2522 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&dev
->ib_dev
, 1);
2524 ib_unregister_device(&dev
->ib_dev
);
2525 destroy_umrc_res(dev
);
2526 mlx5_ib_odp_remove_one(dev
);
2527 destroy_dev_resources(&dev
->devr
);
2528 if (ll
== IB_LINK_LAYER_ETHERNET
)
2529 mlx5_disable_roce(dev
);
2530 ib_dealloc_device(&dev
->ib_dev
);
2533 static struct mlx5_interface mlx5_ib_interface
= {
2535 .remove
= mlx5_ib_remove
,
2536 .event
= mlx5_ib_event
,
2537 .protocol
= MLX5_INTERFACE_PROTOCOL_IB
,
2540 static int __init
mlx5_ib_init(void)
2544 if (deprecated_prof_sel
!= 2)
2545 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2547 err
= mlx5_ib_odp_init();
2551 err
= mlx5_register_interface(&mlx5_ib_interface
);
2558 mlx5_ib_odp_cleanup();
2562 static void __exit
mlx5_ib_cleanup(void)
2564 mlx5_unregister_interface(&mlx5_ib_interface
);
2565 mlx5_ib_odp_cleanup();
2568 module_init(mlx5_ib_init
);
2569 module_exit(mlx5_ib_cleanup
);