Merge tag 'drm-intel-fixes-2015-12-11' of git://anongit.freedesktop.org/drm-intel...
[deliverable/linux.git] / drivers / infiniband / hw / mlx5 / user.h
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_IB_USER_H
34 #define MLX5_IB_USER_H
35
36 #include <linux/types.h>
37
38 enum {
39 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
40 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
41 };
42
43 enum {
44 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
45 };
46
47
48 /* Increment this value if any changes that break userspace ABI
49 * compatibility are made.
50 */
51 #define MLX5_IB_UVERBS_ABI_VERSION 1
52
53 /* Make sure that all structs defined in this file remain laid out so
54 * that they pack the same way on 32-bit and 64-bit architectures (to
55 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
56 * In particular do not use pointer types -- pass pointers in __u64
57 * instead.
58 */
59
60 struct mlx5_ib_alloc_ucontext_req {
61 __u32 total_num_uuars;
62 __u32 num_low_latency_uuars;
63 };
64
65 struct mlx5_ib_alloc_ucontext_req_v2 {
66 __u32 total_num_uuars;
67 __u32 num_low_latency_uuars;
68 __u32 flags;
69 __u32 reserved;
70 };
71
72 struct mlx5_ib_alloc_ucontext_resp {
73 __u32 qp_tab_size;
74 __u32 bf_reg_size;
75 __u32 tot_uuars;
76 __u32 cache_line_size;
77 __u16 max_sq_desc_sz;
78 __u16 max_rq_desc_sz;
79 __u32 max_send_wqebb;
80 __u32 max_recv_wr;
81 __u32 max_srq_recv_wr;
82 __u16 num_ports;
83 __u16 reserved;
84 };
85
86 struct mlx5_ib_alloc_pd_resp {
87 __u32 pdn;
88 };
89
90 struct mlx5_ib_create_cq {
91 __u64 buf_addr;
92 __u64 db_addr;
93 __u32 cqe_size;
94 __u32 reserved; /* explicit padding (optional on i386) */
95 };
96
97 struct mlx5_ib_create_cq_resp {
98 __u32 cqn;
99 __u32 reserved;
100 };
101
102 struct mlx5_ib_resize_cq {
103 __u64 buf_addr;
104 __u16 cqe_size;
105 __u16 reserved0;
106 __u32 reserved1;
107 };
108
109 struct mlx5_ib_create_srq {
110 __u64 buf_addr;
111 __u64 db_addr;
112 __u32 flags;
113 __u32 reserved; /* explicit padding (optional on i386) */
114 };
115
116 struct mlx5_ib_create_srq_resp {
117 __u32 srqn;
118 __u32 reserved;
119 };
120
121 struct mlx5_ib_create_qp {
122 __u64 buf_addr;
123 __u64 db_addr;
124 __u32 sq_wqe_count;
125 __u32 rq_wqe_count;
126 __u32 rq_wqe_shift;
127 __u32 flags;
128 };
129
130 struct mlx5_ib_create_qp_resp {
131 __u32 uuar_index;
132 };
133 #endif /* MLX5_IB_USER_H */
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