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[deliverable/linux.git] / drivers / infiniband / hw / mthca / mthca_cq.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005 Cisco Systems, Inc. All rights reserved.
5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 *
36 * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
37 */
38
39 #include <linux/init.h>
40 #include <linux/hardirq.h>
41
42 #include <rdma/ib_pack.h>
43
44 #include "mthca_dev.h"
45 #include "mthca_cmd.h"
46 #include "mthca_memfree.h"
47
48 enum {
49 MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
50 };
51
52 enum {
53 MTHCA_CQ_ENTRY_SIZE = 0x20
54 };
55
56 /*
57 * Must be packed because start is 64 bits but only aligned to 32 bits.
58 */
59 struct mthca_cq_context {
60 __be32 flags;
61 __be64 start;
62 __be32 logsize_usrpage;
63 __be32 error_eqn; /* Tavor only */
64 __be32 comp_eqn;
65 __be32 pd;
66 __be32 lkey;
67 __be32 last_notified_index;
68 __be32 solicit_producer_index;
69 __be32 consumer_index;
70 __be32 producer_index;
71 __be32 cqn;
72 __be32 ci_db; /* Arbel only */
73 __be32 state_db; /* Arbel only */
74 u32 reserved;
75 } __attribute__((packed));
76
77 #define MTHCA_CQ_STATUS_OK ( 0 << 28)
78 #define MTHCA_CQ_STATUS_OVERFLOW ( 9 << 28)
79 #define MTHCA_CQ_STATUS_WRITE_FAIL (10 << 28)
80 #define MTHCA_CQ_FLAG_TR ( 1 << 18)
81 #define MTHCA_CQ_FLAG_OI ( 1 << 17)
82 #define MTHCA_CQ_STATE_DISARMED ( 0 << 8)
83 #define MTHCA_CQ_STATE_ARMED ( 1 << 8)
84 #define MTHCA_CQ_STATE_ARMED_SOL ( 4 << 8)
85 #define MTHCA_EQ_STATE_FIRED (10 << 8)
86
87 enum {
88 MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
89 };
90
91 enum {
92 SYNDROME_LOCAL_LENGTH_ERR = 0x01,
93 SYNDROME_LOCAL_QP_OP_ERR = 0x02,
94 SYNDROME_LOCAL_EEC_OP_ERR = 0x03,
95 SYNDROME_LOCAL_PROT_ERR = 0x04,
96 SYNDROME_WR_FLUSH_ERR = 0x05,
97 SYNDROME_MW_BIND_ERR = 0x06,
98 SYNDROME_BAD_RESP_ERR = 0x10,
99 SYNDROME_LOCAL_ACCESS_ERR = 0x11,
100 SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
101 SYNDROME_REMOTE_ACCESS_ERR = 0x13,
102 SYNDROME_REMOTE_OP_ERR = 0x14,
103 SYNDROME_RETRY_EXC_ERR = 0x15,
104 SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
105 SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20,
106 SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
107 SYNDROME_REMOTE_ABORTED_ERR = 0x22,
108 SYNDROME_INVAL_EECN_ERR = 0x23,
109 SYNDROME_INVAL_EEC_STATE_ERR = 0x24
110 };
111
112 struct mthca_cqe {
113 __be32 my_qpn;
114 __be32 my_ee;
115 __be32 rqpn;
116 __be16 sl_g_mlpath;
117 __be16 rlid;
118 __be32 imm_etype_pkey_eec;
119 __be32 byte_cnt;
120 __be32 wqe;
121 u8 opcode;
122 u8 is_send;
123 u8 reserved;
124 u8 owner;
125 };
126
127 struct mthca_err_cqe {
128 __be32 my_qpn;
129 u32 reserved1[3];
130 u8 syndrome;
131 u8 reserved2;
132 __be16 db_cnt;
133 u32 reserved3;
134 __be32 wqe;
135 u8 opcode;
136 u8 reserved4[2];
137 u8 owner;
138 };
139
140 #define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7)
141 #define MTHCA_CQ_ENTRY_OWNER_HW (1 << 7)
142
143 #define MTHCA_TAVOR_CQ_DB_INC_CI (1 << 24)
144 #define MTHCA_TAVOR_CQ_DB_REQ_NOT (2 << 24)
145 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24)
146 #define MTHCA_TAVOR_CQ_DB_SET_CI (4 << 24)
147 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
148
149 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24)
150 #define MTHCA_ARBEL_CQ_DB_REQ_NOT (2 << 24)
151 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
152
153 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
154 {
155 if (cq->is_direct)
156 return cq->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE);
157 else
158 return cq->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf
159 + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE;
160 }
161
162 static inline struct mthca_cqe *cqe_sw(struct mthca_cq *cq, int i)
163 {
164 struct mthca_cqe *cqe = get_cqe(cq, i);
165 return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
166 }
167
168 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
169 {
170 return cqe_sw(cq, cq->cons_index & cq->ibcq.cqe);
171 }
172
173 static inline void set_cqe_hw(struct mthca_cqe *cqe)
174 {
175 cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
176 }
177
178 static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
179 {
180 __be32 *cqe = cqe_ptr;
181
182 (void) cqe; /* avoid warning if mthca_dbg compiled away... */
183 mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
184 be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]),
185 be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]),
186 be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7]));
187 }
188
189 /*
190 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
191 * should be correct before calling update_cons_index().
192 */
193 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
194 int incr)
195 {
196 __be32 doorbell[2];
197
198 if (mthca_is_memfree(dev)) {
199 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
200 wmb();
201 } else {
202 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
203 doorbell[1] = cpu_to_be32(incr - 1);
204
205 mthca_write64(doorbell,
206 dev->kar + MTHCA_CQ_DOORBELL,
207 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
208 }
209 }
210
211 void mthca_cq_event(struct mthca_dev *dev, u32 cqn)
212 {
213 struct mthca_cq *cq;
214
215 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
216
217 if (!cq) {
218 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
219 return;
220 }
221
222 ++cq->arm_sn;
223
224 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
225 }
226
227 void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn,
228 struct mthca_srq *srq)
229 {
230 struct mthca_cq *cq;
231 struct mthca_cqe *cqe;
232 int prod_index;
233 int nfreed = 0;
234
235 spin_lock_irq(&dev->cq_table.lock);
236 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
237 if (cq)
238 atomic_inc(&cq->refcount);
239 spin_unlock_irq(&dev->cq_table.lock);
240
241 if (!cq)
242 return;
243
244 spin_lock_irq(&cq->lock);
245
246 /*
247 * First we need to find the current producer index, so we
248 * know where to start cleaning from. It doesn't matter if HW
249 * adds new entries after this loop -- the QP we're worried
250 * about is already in RESET, so the new entries won't come
251 * from our QP and therefore don't need to be checked.
252 */
253 for (prod_index = cq->cons_index;
254 cqe_sw(cq, prod_index & cq->ibcq.cqe);
255 ++prod_index)
256 if (prod_index == cq->cons_index + cq->ibcq.cqe)
257 break;
258
259 if (0)
260 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
261 qpn, cqn, cq->cons_index, prod_index);
262
263 /*
264 * Now sweep backwards through the CQ, removing CQ entries
265 * that match our QP by copying older entries on top of them.
266 */
267 while (prod_index > cq->cons_index) {
268 cqe = get_cqe(cq, (prod_index - 1) & cq->ibcq.cqe);
269 if (cqe->my_qpn == cpu_to_be32(qpn)) {
270 if (srq)
271 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe));
272 ++nfreed;
273 }
274 else if (nfreed)
275 memcpy(get_cqe(cq, (prod_index - 1 + nfreed) &
276 cq->ibcq.cqe),
277 cqe,
278 MTHCA_CQ_ENTRY_SIZE);
279 --prod_index;
280 }
281
282 if (nfreed) {
283 wmb();
284 cq->cons_index += nfreed;
285 update_cons_index(dev, cq, nfreed);
286 }
287
288 spin_unlock_irq(&cq->lock);
289 if (atomic_dec_and_test(&cq->refcount))
290 wake_up(&cq->wait);
291 }
292
293 static int handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
294 struct mthca_qp *qp, int wqe_index, int is_send,
295 struct mthca_err_cqe *cqe,
296 struct ib_wc *entry, int *free_cqe)
297 {
298 int err;
299 int dbd;
300 __be32 new_wqe;
301
302 if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
303 mthca_dbg(dev, "local QP operation err "
304 "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
305 be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe),
306 cq->cqn, cq->cons_index);
307 dump_cqe(dev, cqe);
308 }
309
310 /*
311 * For completions in error, only work request ID, status (and
312 * freed resource count for RD) have to be set.
313 */
314 switch (cqe->syndrome) {
315 case SYNDROME_LOCAL_LENGTH_ERR:
316 entry->status = IB_WC_LOC_LEN_ERR;
317 break;
318 case SYNDROME_LOCAL_QP_OP_ERR:
319 entry->status = IB_WC_LOC_QP_OP_ERR;
320 break;
321 case SYNDROME_LOCAL_EEC_OP_ERR:
322 entry->status = IB_WC_LOC_EEC_OP_ERR;
323 break;
324 case SYNDROME_LOCAL_PROT_ERR:
325 entry->status = IB_WC_LOC_PROT_ERR;
326 break;
327 case SYNDROME_WR_FLUSH_ERR:
328 entry->status = IB_WC_WR_FLUSH_ERR;
329 break;
330 case SYNDROME_MW_BIND_ERR:
331 entry->status = IB_WC_MW_BIND_ERR;
332 break;
333 case SYNDROME_BAD_RESP_ERR:
334 entry->status = IB_WC_BAD_RESP_ERR;
335 break;
336 case SYNDROME_LOCAL_ACCESS_ERR:
337 entry->status = IB_WC_LOC_ACCESS_ERR;
338 break;
339 case SYNDROME_REMOTE_INVAL_REQ_ERR:
340 entry->status = IB_WC_REM_INV_REQ_ERR;
341 break;
342 case SYNDROME_REMOTE_ACCESS_ERR:
343 entry->status = IB_WC_REM_ACCESS_ERR;
344 break;
345 case SYNDROME_REMOTE_OP_ERR:
346 entry->status = IB_WC_REM_OP_ERR;
347 break;
348 case SYNDROME_RETRY_EXC_ERR:
349 entry->status = IB_WC_RETRY_EXC_ERR;
350 break;
351 case SYNDROME_RNR_RETRY_EXC_ERR:
352 entry->status = IB_WC_RNR_RETRY_EXC_ERR;
353 break;
354 case SYNDROME_LOCAL_RDD_VIOL_ERR:
355 entry->status = IB_WC_LOC_RDD_VIOL_ERR;
356 break;
357 case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
358 entry->status = IB_WC_REM_INV_RD_REQ_ERR;
359 break;
360 case SYNDROME_REMOTE_ABORTED_ERR:
361 entry->status = IB_WC_REM_ABORT_ERR;
362 break;
363 case SYNDROME_INVAL_EECN_ERR:
364 entry->status = IB_WC_INV_EECN_ERR;
365 break;
366 case SYNDROME_INVAL_EEC_STATE_ERR:
367 entry->status = IB_WC_INV_EEC_STATE_ERR;
368 break;
369 default:
370 entry->status = IB_WC_GENERAL_ERR;
371 break;
372 }
373
374 /*
375 * Mem-free HCAs always generate one CQE per WQE, even in the
376 * error case, so we don't have to check the doorbell count, etc.
377 */
378 if (mthca_is_memfree(dev))
379 return 0;
380
381 err = mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
382 if (err)
383 return err;
384
385 /*
386 * If we're at the end of the WQE chain, or we've used up our
387 * doorbell count, free the CQE. Otherwise just update it for
388 * the next poll operation.
389 */
390 if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
391 return 0;
392
393 cqe->db_cnt = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
394 cqe->wqe = new_wqe;
395 cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
396
397 *free_cqe = 0;
398
399 return 0;
400 }
401
402 static inline int mthca_poll_one(struct mthca_dev *dev,
403 struct mthca_cq *cq,
404 struct mthca_qp **cur_qp,
405 int *freed,
406 struct ib_wc *entry)
407 {
408 struct mthca_wq *wq;
409 struct mthca_cqe *cqe;
410 int wqe_index;
411 int is_error;
412 int is_send;
413 int free_cqe = 1;
414 int err = 0;
415
416 cqe = next_cqe_sw(cq);
417 if (!cqe)
418 return -EAGAIN;
419
420 /*
421 * Make sure we read CQ entry contents after we've checked the
422 * ownership bit.
423 */
424 rmb();
425
426 if (0) {
427 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
428 cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
429 be32_to_cpu(cqe->wqe));
430 dump_cqe(dev, cqe);
431 }
432
433 is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
434 MTHCA_ERROR_CQE_OPCODE_MASK;
435 is_send = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
436
437 if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) {
438 /*
439 * We do not have to take the QP table lock here,
440 * because CQs will be locked while QPs are removed
441 * from the table.
442 */
443 *cur_qp = mthca_array_get(&dev->qp_table.qp,
444 be32_to_cpu(cqe->my_qpn) &
445 (dev->limits.num_qps - 1));
446 if (!*cur_qp) {
447 mthca_warn(dev, "CQ entry for unknown QP %06x\n",
448 be32_to_cpu(cqe->my_qpn) & 0xffffff);
449 err = -EINVAL;
450 goto out;
451 }
452 }
453
454 entry->qp_num = (*cur_qp)->qpn;
455
456 if (is_send) {
457 wq = &(*cur_qp)->sq;
458 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset)
459 >> wq->wqe_shift);
460 entry->wr_id = (*cur_qp)->wrid[wqe_index +
461 (*cur_qp)->rq.max];
462 } else if ((*cur_qp)->ibqp.srq) {
463 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq);
464 u32 wqe = be32_to_cpu(cqe->wqe);
465 wq = NULL;
466 wqe_index = wqe >> srq->wqe_shift;
467 entry->wr_id = srq->wrid[wqe_index];
468 mthca_free_srq_wqe(srq, wqe);
469 } else {
470 wq = &(*cur_qp)->rq;
471 wqe_index = be32_to_cpu(cqe->wqe) >> wq->wqe_shift;
472 entry->wr_id = (*cur_qp)->wrid[wqe_index];
473 }
474
475 if (wq) {
476 if (wq->last_comp < wqe_index)
477 wq->tail += wqe_index - wq->last_comp;
478 else
479 wq->tail += wqe_index + wq->max - wq->last_comp;
480
481 wq->last_comp = wqe_index;
482 }
483
484 if (is_error) {
485 err = handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
486 (struct mthca_err_cqe *) cqe,
487 entry, &free_cqe);
488 goto out;
489 }
490
491 if (is_send) {
492 entry->wc_flags = 0;
493 switch (cqe->opcode) {
494 case MTHCA_OPCODE_RDMA_WRITE:
495 entry->opcode = IB_WC_RDMA_WRITE;
496 break;
497 case MTHCA_OPCODE_RDMA_WRITE_IMM:
498 entry->opcode = IB_WC_RDMA_WRITE;
499 entry->wc_flags |= IB_WC_WITH_IMM;
500 break;
501 case MTHCA_OPCODE_SEND:
502 entry->opcode = IB_WC_SEND;
503 break;
504 case MTHCA_OPCODE_SEND_IMM:
505 entry->opcode = IB_WC_SEND;
506 entry->wc_flags |= IB_WC_WITH_IMM;
507 break;
508 case MTHCA_OPCODE_RDMA_READ:
509 entry->opcode = IB_WC_RDMA_READ;
510 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
511 break;
512 case MTHCA_OPCODE_ATOMIC_CS:
513 entry->opcode = IB_WC_COMP_SWAP;
514 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
515 break;
516 case MTHCA_OPCODE_ATOMIC_FA:
517 entry->opcode = IB_WC_FETCH_ADD;
518 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
519 break;
520 case MTHCA_OPCODE_BIND_MW:
521 entry->opcode = IB_WC_BIND_MW;
522 break;
523 default:
524 entry->opcode = MTHCA_OPCODE_INVALID;
525 break;
526 }
527 } else {
528 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
529 switch (cqe->opcode & 0x1f) {
530 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
531 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
532 entry->wc_flags = IB_WC_WITH_IMM;
533 entry->imm_data = cqe->imm_etype_pkey_eec;
534 entry->opcode = IB_WC_RECV;
535 break;
536 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
537 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
538 entry->wc_flags = IB_WC_WITH_IMM;
539 entry->imm_data = cqe->imm_etype_pkey_eec;
540 entry->opcode = IB_WC_RECV_RDMA_WITH_IMM;
541 break;
542 default:
543 entry->wc_flags = 0;
544 entry->opcode = IB_WC_RECV;
545 break;
546 }
547 entry->slid = be16_to_cpu(cqe->rlid);
548 entry->sl = be16_to_cpu(cqe->sl_g_mlpath) >> 12;
549 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff;
550 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f;
551 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
552 entry->wc_flags |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ?
553 IB_WC_GRH : 0;
554 }
555
556 entry->status = IB_WC_SUCCESS;
557
558 out:
559 if (likely(free_cqe)) {
560 set_cqe_hw(cqe);
561 ++(*freed);
562 ++cq->cons_index;
563 }
564
565 return err;
566 }
567
568 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
569 struct ib_wc *entry)
570 {
571 struct mthca_dev *dev = to_mdev(ibcq->device);
572 struct mthca_cq *cq = to_mcq(ibcq);
573 struct mthca_qp *qp = NULL;
574 unsigned long flags;
575 int err = 0;
576 int freed = 0;
577 int npolled;
578
579 spin_lock_irqsave(&cq->lock, flags);
580
581 for (npolled = 0; npolled < num_entries; ++npolled) {
582 err = mthca_poll_one(dev, cq, &qp,
583 &freed, entry + npolled);
584 if (err)
585 break;
586 }
587
588 if (freed) {
589 wmb();
590 update_cons_index(dev, cq, freed);
591 }
592
593 spin_unlock_irqrestore(&cq->lock, flags);
594
595 return err == 0 || err == -EAGAIN ? npolled : err;
596 }
597
598 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
599 {
600 __be32 doorbell[2];
601
602 doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ?
603 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
604 MTHCA_TAVOR_CQ_DB_REQ_NOT) |
605 to_mcq(cq)->cqn);
606 doorbell[1] = (__force __be32) 0xffffffff;
607
608 mthca_write64(doorbell,
609 to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
610 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
611
612 return 0;
613 }
614
615 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
616 {
617 struct mthca_cq *cq = to_mcq(ibcq);
618 __be32 doorbell[2];
619 u32 sn;
620 __be32 ci;
621
622 sn = cq->arm_sn & 3;
623 ci = cpu_to_be32(cq->cons_index);
624
625 doorbell[0] = ci;
626 doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
627 (notify == IB_CQ_SOLICITED ? 1 : 2));
628
629 mthca_write_db_rec(doorbell, cq->arm_db);
630
631 /*
632 * Make sure that the doorbell record in host memory is
633 * written before ringing the doorbell via PCI MMIO.
634 */
635 wmb();
636
637 doorbell[0] = cpu_to_be32((sn << 28) |
638 (notify == IB_CQ_SOLICITED ?
639 MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
640 MTHCA_ARBEL_CQ_DB_REQ_NOT) |
641 cq->cqn);
642 doorbell[1] = ci;
643
644 mthca_write64(doorbell,
645 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
646 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
647
648 return 0;
649 }
650
651 static void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq *cq)
652 {
653 mthca_buf_free(dev, (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE,
654 &cq->queue, cq->is_direct, &cq->mr);
655 }
656
657 int mthca_init_cq(struct mthca_dev *dev, int nent,
658 struct mthca_ucontext *ctx, u32 pdn,
659 struct mthca_cq *cq)
660 {
661 int size = nent * MTHCA_CQ_ENTRY_SIZE;
662 struct mthca_mailbox *mailbox;
663 struct mthca_cq_context *cq_context;
664 int err = -ENOMEM;
665 u8 status;
666 int i;
667
668 might_sleep();
669
670 cq->ibcq.cqe = nent - 1;
671 cq->is_kernel = !ctx;
672
673 cq->cqn = mthca_alloc(&dev->cq_table.alloc);
674 if (cq->cqn == -1)
675 return -ENOMEM;
676
677 if (mthca_is_memfree(dev)) {
678 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
679 if (err)
680 goto err_out;
681
682 if (cq->is_kernel) {
683 cq->arm_sn = 1;
684
685 err = -ENOMEM;
686
687 cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
688 cq->cqn, &cq->set_ci_db);
689 if (cq->set_ci_db_index < 0)
690 goto err_out_icm;
691
692 cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
693 cq->cqn, &cq->arm_db);
694 if (cq->arm_db_index < 0)
695 goto err_out_ci;
696 }
697 }
698
699 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
700 if (IS_ERR(mailbox))
701 goto err_out_arm;
702
703 cq_context = mailbox->buf;
704
705 if (cq->is_kernel) {
706 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_CQ_SIZE,
707 &cq->queue, &cq->is_direct,
708 &dev->driver_pd, 1, &cq->mr);
709 if (err)
710 goto err_out_mailbox;
711
712 for (i = 0; i < nent; ++i)
713 set_cqe_hw(get_cqe(cq, i));
714 }
715
716 spin_lock_init(&cq->lock);
717 atomic_set(&cq->refcount, 1);
718 init_waitqueue_head(&cq->wait);
719
720 memset(cq_context, 0, sizeof *cq_context);
721 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK |
722 MTHCA_CQ_STATE_DISARMED |
723 MTHCA_CQ_FLAG_TR);
724 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
725 if (ctx)
726 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index);
727 else
728 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
729 cq_context->error_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
730 cq_context->comp_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
731 cq_context->pd = cpu_to_be32(pdn);
732 cq_context->lkey = cpu_to_be32(cq->mr.ibmr.lkey);
733 cq_context->cqn = cpu_to_be32(cq->cqn);
734
735 if (mthca_is_memfree(dev)) {
736 cq_context->ci_db = cpu_to_be32(cq->set_ci_db_index);
737 cq_context->state_db = cpu_to_be32(cq->arm_db_index);
738 }
739
740 err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
741 if (err) {
742 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err);
743 goto err_out_free_mr;
744 }
745
746 if (status) {
747 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n",
748 status);
749 err = -EINVAL;
750 goto err_out_free_mr;
751 }
752
753 spin_lock_irq(&dev->cq_table.lock);
754 if (mthca_array_set(&dev->cq_table.cq,
755 cq->cqn & (dev->limits.num_cqs - 1),
756 cq)) {
757 spin_unlock_irq(&dev->cq_table.lock);
758 goto err_out_free_mr;
759 }
760 spin_unlock_irq(&dev->cq_table.lock);
761
762 cq->cons_index = 0;
763
764 mthca_free_mailbox(dev, mailbox);
765
766 return 0;
767
768 err_out_free_mr:
769 if (cq->is_kernel)
770 mthca_free_cq_buf(dev, cq);
771
772 err_out_mailbox:
773 mthca_free_mailbox(dev, mailbox);
774
775 err_out_arm:
776 if (cq->is_kernel && mthca_is_memfree(dev))
777 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
778
779 err_out_ci:
780 if (cq->is_kernel && mthca_is_memfree(dev))
781 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
782
783 err_out_icm:
784 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
785
786 err_out:
787 mthca_free(&dev->cq_table.alloc, cq->cqn);
788
789 return err;
790 }
791
792 void mthca_free_cq(struct mthca_dev *dev,
793 struct mthca_cq *cq)
794 {
795 struct mthca_mailbox *mailbox;
796 int err;
797 u8 status;
798
799 might_sleep();
800
801 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
802 if (IS_ERR(mailbox)) {
803 mthca_warn(dev, "No memory for mailbox to free CQ.\n");
804 return;
805 }
806
807 err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
808 if (err)
809 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err);
810 else if (status)
811 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
812
813 if (0) {
814 __be32 *ctx = mailbox->buf;
815 int j;
816
817 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
818 cq->cqn, cq->cons_index,
819 cq->is_kernel ? !!next_cqe_sw(cq) : 0);
820 for (j = 0; j < 16; ++j)
821 printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j]));
822 }
823
824 spin_lock_irq(&dev->cq_table.lock);
825 mthca_array_clear(&dev->cq_table.cq,
826 cq->cqn & (dev->limits.num_cqs - 1));
827 spin_unlock_irq(&dev->cq_table.lock);
828
829 if (dev->mthca_flags & MTHCA_FLAG_MSI_X)
830 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector);
831 else
832 synchronize_irq(dev->pdev->irq);
833
834 atomic_dec(&cq->refcount);
835 wait_event(cq->wait, !atomic_read(&cq->refcount));
836
837 if (cq->is_kernel) {
838 mthca_free_cq_buf(dev, cq);
839 if (mthca_is_memfree(dev)) {
840 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
841 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
842 }
843 }
844
845 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
846 mthca_free(&dev->cq_table.alloc, cq->cqn);
847 mthca_free_mailbox(dev, mailbox);
848 }
849
850 int __devinit mthca_init_cq_table(struct mthca_dev *dev)
851 {
852 int err;
853
854 spin_lock_init(&dev->cq_table.lock);
855
856 err = mthca_alloc_init(&dev->cq_table.alloc,
857 dev->limits.num_cqs,
858 (1 << 24) - 1,
859 dev->limits.reserved_cqs);
860 if (err)
861 return err;
862
863 err = mthca_array_init(&dev->cq_table.cq,
864 dev->limits.num_cqs);
865 if (err)
866 mthca_alloc_cleanup(&dev->cq_table.alloc);
867
868 return err;
869 }
870
871 void __devexit mthca_cleanup_cq_table(struct mthca_dev *dev)
872 {
873 mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
874 mthca_alloc_cleanup(&dev->cq_table.alloc);
875 }
Linux kernel - Deliverables
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