2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
38 #include <linux/init.h>
39 #include <linux/string.h>
40 #include <linux/slab.h>
42 #include <rdma/ib_verbs.h>
43 #include <rdma/ib_cache.h>
44 #include <rdma/ib_pack.h>
46 #include "mthca_dev.h"
47 #include "mthca_cmd.h"
48 #include "mthca_memfree.h"
49 #include "mthca_wqe.h"
52 MTHCA_MAX_DIRECT_QP_SIZE
= 4 * PAGE_SIZE
,
53 MTHCA_ACK_REQ_FREQ
= 10,
54 MTHCA_FLIGHT_LIMIT
= 9,
55 MTHCA_UD_HEADER_SIZE
= 72, /* largest UD header possible */
56 MTHCA_INLINE_HEADER_SIZE
= 4, /* data segment overhead for inline */
57 MTHCA_INLINE_CHUNK_SIZE
= 16 /* inline data segment chunk */
61 MTHCA_QP_STATE_RST
= 0,
62 MTHCA_QP_STATE_INIT
= 1,
63 MTHCA_QP_STATE_RTR
= 2,
64 MTHCA_QP_STATE_RTS
= 3,
65 MTHCA_QP_STATE_SQE
= 4,
66 MTHCA_QP_STATE_SQD
= 5,
67 MTHCA_QP_STATE_ERR
= 6,
68 MTHCA_QP_STATE_DRAINING
= 7
80 MTHCA_QP_PM_MIGRATED
= 0x3,
81 MTHCA_QP_PM_ARMED
= 0x0,
82 MTHCA_QP_PM_REARM
= 0x1
86 /* qp_context flags */
87 MTHCA_QP_BIT_DE
= 1 << 8,
89 MTHCA_QP_BIT_SRE
= 1 << 15,
90 MTHCA_QP_BIT_SWE
= 1 << 14,
91 MTHCA_QP_BIT_SAE
= 1 << 13,
92 MTHCA_QP_BIT_SIC
= 1 << 4,
93 MTHCA_QP_BIT_SSC
= 1 << 3,
95 MTHCA_QP_BIT_RRE
= 1 << 15,
96 MTHCA_QP_BIT_RWE
= 1 << 14,
97 MTHCA_QP_BIT_RAE
= 1 << 13,
98 MTHCA_QP_BIT_RIC
= 1 << 4,
99 MTHCA_QP_BIT_RSC
= 1 << 3
102 struct mthca_qp_path
{
111 __be32 sl_tclass_flowlabel
;
113 } __attribute__((packed
));
115 struct mthca_qp_context
{
117 __be32 tavor_sched_queue
; /* Reserved on Arbel */
119 u8 rq_size_stride
; /* Reserved on Tavor */
120 u8 sq_size_stride
; /* Reserved on Tavor */
121 u8 rlkey_arbel_sched_queue
; /* Reserved on Tavor */
126 struct mthca_qp_path pri_path
;
127 struct mthca_qp_path alt_path
;
134 __be32 next_send_psn
;
136 __be32 snd_wqe_base_l
; /* Next send WQE on Tavor */
137 __be32 snd_db_index
; /* (debugging only entries) */
138 __be32 last_acked_psn
;
141 __be32 rnr_nextrecvpsn
;
144 __be32 rcv_wqe_base_l
; /* Next recv WQE on Tavor */
145 __be32 rcv_db_index
; /* (debugging only entries) */
149 __be16 rq_wqe_counter
; /* reserved on Tavor */
150 __be16 sq_wqe_counter
; /* reserved on Tavor */
152 } __attribute__((packed
));
154 struct mthca_qp_param
{
155 __be32 opt_param_mask
;
157 struct mthca_qp_context context
;
159 } __attribute__((packed
));
162 MTHCA_QP_OPTPAR_ALT_ADDR_PATH
= 1 << 0,
163 MTHCA_QP_OPTPAR_RRE
= 1 << 1,
164 MTHCA_QP_OPTPAR_RAE
= 1 << 2,
165 MTHCA_QP_OPTPAR_RWE
= 1 << 3,
166 MTHCA_QP_OPTPAR_PKEY_INDEX
= 1 << 4,
167 MTHCA_QP_OPTPAR_Q_KEY
= 1 << 5,
168 MTHCA_QP_OPTPAR_RNR_TIMEOUT
= 1 << 6,
169 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH
= 1 << 7,
170 MTHCA_QP_OPTPAR_SRA_MAX
= 1 << 8,
171 MTHCA_QP_OPTPAR_RRA_MAX
= 1 << 9,
172 MTHCA_QP_OPTPAR_PM_STATE
= 1 << 10,
173 MTHCA_QP_OPTPAR_PORT_NUM
= 1 << 11,
174 MTHCA_QP_OPTPAR_RETRY_COUNT
= 1 << 12,
175 MTHCA_QP_OPTPAR_ALT_RNR_RETRY
= 1 << 13,
176 MTHCA_QP_OPTPAR_ACK_TIMEOUT
= 1 << 14,
177 MTHCA_QP_OPTPAR_RNR_RETRY
= 1 << 15,
178 MTHCA_QP_OPTPAR_SCHED_QUEUE
= 1 << 16
181 static const u8 mthca_opcode
[] = {
182 [IB_WR_SEND
] = MTHCA_OPCODE_SEND
,
183 [IB_WR_SEND_WITH_IMM
] = MTHCA_OPCODE_SEND_IMM
,
184 [IB_WR_RDMA_WRITE
] = MTHCA_OPCODE_RDMA_WRITE
,
185 [IB_WR_RDMA_WRITE_WITH_IMM
] = MTHCA_OPCODE_RDMA_WRITE_IMM
,
186 [IB_WR_RDMA_READ
] = MTHCA_OPCODE_RDMA_READ
,
187 [IB_WR_ATOMIC_CMP_AND_SWP
] = MTHCA_OPCODE_ATOMIC_CS
,
188 [IB_WR_ATOMIC_FETCH_AND_ADD
] = MTHCA_OPCODE_ATOMIC_FA
,
191 static int is_sqp(struct mthca_dev
*dev
, struct mthca_qp
*qp
)
193 return qp
->qpn
>= dev
->qp_table
.sqp_start
&&
194 qp
->qpn
<= dev
->qp_table
.sqp_start
+ 3;
197 static int is_qp0(struct mthca_dev
*dev
, struct mthca_qp
*qp
)
199 return qp
->qpn
>= dev
->qp_table
.sqp_start
&&
200 qp
->qpn
<= dev
->qp_table
.sqp_start
+ 1;
203 static void *get_recv_wqe(struct mthca_qp
*qp
, int n
)
206 return qp
->queue
.direct
.buf
+ (n
<< qp
->rq
.wqe_shift
);
208 return qp
->queue
.page_list
[(n
<< qp
->rq
.wqe_shift
) >> PAGE_SHIFT
].buf
+
209 ((n
<< qp
->rq
.wqe_shift
) & (PAGE_SIZE
- 1));
212 static void *get_send_wqe(struct mthca_qp
*qp
, int n
)
215 return qp
->queue
.direct
.buf
+ qp
->send_wqe_offset
+
216 (n
<< qp
->sq
.wqe_shift
);
218 return qp
->queue
.page_list
[(qp
->send_wqe_offset
+
219 (n
<< qp
->sq
.wqe_shift
)) >>
221 ((qp
->send_wqe_offset
+ (n
<< qp
->sq
.wqe_shift
)) &
225 static void mthca_wq_init(struct mthca_wq
*wq
)
227 spin_lock_init(&wq
->lock
);
229 wq
->last_comp
= wq
->max
- 1;
234 void mthca_qp_event(struct mthca_dev
*dev
, u32 qpn
,
235 enum ib_event_type event_type
)
238 struct ib_event event
;
240 spin_lock(&dev
->qp_table
.lock
);
241 qp
= mthca_array_get(&dev
->qp_table
.qp
, qpn
& (dev
->limits
.num_qps
- 1));
243 atomic_inc(&qp
->refcount
);
244 spin_unlock(&dev
->qp_table
.lock
);
247 mthca_warn(dev
, "Async event for bogus QP %08x\n", qpn
);
251 event
.device
= &dev
->ib_dev
;
252 event
.event
= event_type
;
253 event
.element
.qp
= &qp
->ibqp
;
254 if (qp
->ibqp
.event_handler
)
255 qp
->ibqp
.event_handler(&event
, qp
->ibqp
.qp_context
);
257 if (atomic_dec_and_test(&qp
->refcount
))
261 static int to_mthca_state(enum ib_qp_state ib_state
)
264 case IB_QPS_RESET
: return MTHCA_QP_STATE_RST
;
265 case IB_QPS_INIT
: return MTHCA_QP_STATE_INIT
;
266 case IB_QPS_RTR
: return MTHCA_QP_STATE_RTR
;
267 case IB_QPS_RTS
: return MTHCA_QP_STATE_RTS
;
268 case IB_QPS_SQD
: return MTHCA_QP_STATE_SQD
;
269 case IB_QPS_SQE
: return MTHCA_QP_STATE_SQE
;
270 case IB_QPS_ERR
: return MTHCA_QP_STATE_ERR
;
275 enum { RC
, UC
, UD
, RD
, RDEE
, MLX
, NUM_TRANS
};
277 static int to_mthca_st(int transport
)
280 case RC
: return MTHCA_QP_ST_RC
;
281 case UC
: return MTHCA_QP_ST_UC
;
282 case UD
: return MTHCA_QP_ST_UD
;
283 case RD
: return MTHCA_QP_ST_RD
;
284 case MLX
: return MTHCA_QP_ST_MLX
;
289 static const struct {
291 u32 req_param
[NUM_TRANS
];
292 u32 opt_param
[NUM_TRANS
];
293 } state_table
[IB_QPS_ERR
+ 1][IB_QPS_ERR
+ 1] = {
295 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
296 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
298 .trans
= MTHCA_TRANS_RST2INIT
,
300 [UD
] = (IB_QP_PKEY_INDEX
|
303 [UC
] = (IB_QP_PKEY_INDEX
|
306 [RC
] = (IB_QP_PKEY_INDEX
|
309 [MLX
] = (IB_QP_PKEY_INDEX
|
312 /* bug-for-bug compatibility with VAPI: */
319 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
320 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
322 .trans
= MTHCA_TRANS_INIT2INIT
,
324 [UD
] = (IB_QP_PKEY_INDEX
|
327 [UC
] = (IB_QP_PKEY_INDEX
|
330 [RC
] = (IB_QP_PKEY_INDEX
|
333 [MLX
] = (IB_QP_PKEY_INDEX
|
338 .trans
= MTHCA_TRANS_INIT2RTR
,
348 IB_QP_MAX_DEST_RD_ATOMIC
|
349 IB_QP_MIN_RNR_TIMER
),
352 [UD
] = (IB_QP_PKEY_INDEX
|
354 [UC
] = (IB_QP_ALT_PATH
|
357 [RC
] = (IB_QP_ALT_PATH
|
360 [MLX
] = (IB_QP_PKEY_INDEX
|
366 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
367 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
369 .trans
= MTHCA_TRANS_RTR2RTS
,
373 [RC
] = (IB_QP_TIMEOUT
|
377 IB_QP_MAX_QP_RD_ATOMIC
),
378 [MLX
] = IB_QP_SQ_PSN
,
381 [UD
] = (IB_QP_CUR_STATE
|
383 [UC
] = (IB_QP_CUR_STATE
|
387 IB_QP_PATH_MIG_STATE
),
388 [RC
] = (IB_QP_CUR_STATE
|
392 IB_QP_MIN_RNR_TIMER
|
393 IB_QP_PATH_MIG_STATE
),
394 [MLX
] = (IB_QP_CUR_STATE
|
400 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
401 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
403 .trans
= MTHCA_TRANS_RTS2RTS
,
405 [UD
] = (IB_QP_CUR_STATE
|
407 [UC
] = (IB_QP_ACCESS_FLAGS
|
409 IB_QP_PATH_MIG_STATE
),
410 [RC
] = (IB_QP_ACCESS_FLAGS
|
412 IB_QP_PATH_MIG_STATE
|
413 IB_QP_MIN_RNR_TIMER
),
414 [MLX
] = (IB_QP_CUR_STATE
|
419 .trans
= MTHCA_TRANS_RTS2SQD
,
423 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
424 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
426 .trans
= MTHCA_TRANS_SQD2RTS
,
428 [UD
] = (IB_QP_CUR_STATE
|
430 [UC
] = (IB_QP_CUR_STATE
|
433 IB_QP_PATH_MIG_STATE
),
434 [RC
] = (IB_QP_CUR_STATE
|
437 IB_QP_MIN_RNR_TIMER
|
438 IB_QP_PATH_MIG_STATE
),
439 [MLX
] = (IB_QP_CUR_STATE
|
444 .trans
= MTHCA_TRANS_SQD2SQD
,
446 [UD
] = (IB_QP_PKEY_INDEX
|
453 IB_QP_PATH_MIG_STATE
),
458 IB_QP_MAX_QP_RD_ATOMIC
|
459 IB_QP_MAX_DEST_RD_ATOMIC
|
464 IB_QP_MIN_RNR_TIMER
|
465 IB_QP_PATH_MIG_STATE
),
466 [MLX
] = (IB_QP_PKEY_INDEX
|
472 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
473 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
475 .trans
= MTHCA_TRANS_SQERR2RTS
,
477 [UD
] = (IB_QP_CUR_STATE
|
479 [UC
] = IB_QP_CUR_STATE
,
480 [RC
] = (IB_QP_CUR_STATE
|
481 IB_QP_MIN_RNR_TIMER
),
482 [MLX
] = (IB_QP_CUR_STATE
|
488 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
489 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
}
493 static void store_attrs(struct mthca_sqp
*sqp
, struct ib_qp_attr
*attr
,
496 if (attr_mask
& IB_QP_PKEY_INDEX
)
497 sqp
->pkey_index
= attr
->pkey_index
;
498 if (attr_mask
& IB_QP_QKEY
)
499 sqp
->qkey
= attr
->qkey
;
500 if (attr_mask
& IB_QP_SQ_PSN
)
501 sqp
->send_psn
= attr
->sq_psn
;
504 static void init_port(struct mthca_dev
*dev
, int port
)
508 struct mthca_init_ib_param param
;
510 memset(¶m
, 0, sizeof param
);
512 param
.port_width
= dev
->limits
.port_width_cap
;
513 param
.vl_cap
= dev
->limits
.vl_cap
;
514 param
.mtu_cap
= dev
->limits
.mtu_cap
;
515 param
.gid_cap
= dev
->limits
.gid_table_len
;
516 param
.pkey_cap
= dev
->limits
.pkey_table_len
;
518 err
= mthca_INIT_IB(dev
, ¶m
, port
, &status
);
520 mthca_warn(dev
, "INIT_IB failed, return code %d.\n", err
);
522 mthca_warn(dev
, "INIT_IB returned status %02x.\n", status
);
525 static __be32
get_hw_access_flags(struct mthca_qp
*qp
, struct ib_qp_attr
*attr
,
530 u32 hw_access_flags
= 0;
532 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
533 dest_rd_atomic
= attr
->max_dest_rd_atomic
;
535 dest_rd_atomic
= qp
->resp_depth
;
537 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
538 access_flags
= attr
->qp_access_flags
;
540 access_flags
= qp
->atomic_rd_en
;
543 access_flags
&= IB_ACCESS_REMOTE_WRITE
;
545 if (access_flags
& IB_ACCESS_REMOTE_READ
)
546 hw_access_flags
|= MTHCA_QP_BIT_RRE
;
547 if (access_flags
& IB_ACCESS_REMOTE_ATOMIC
)
548 hw_access_flags
|= MTHCA_QP_BIT_RAE
;
549 if (access_flags
& IB_ACCESS_REMOTE_WRITE
)
550 hw_access_flags
|= MTHCA_QP_BIT_RWE
;
552 return cpu_to_be32(hw_access_flags
);
555 int mthca_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
, int attr_mask
)
557 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
558 struct mthca_qp
*qp
= to_mqp(ibqp
);
559 enum ib_qp_state cur_state
, new_state
;
560 struct mthca_mailbox
*mailbox
;
561 struct mthca_qp_param
*qp_param
;
562 struct mthca_qp_context
*qp_context
;
563 u32 req_param
, opt_param
;
567 if (attr_mask
& IB_QP_CUR_STATE
) {
568 if (attr
->cur_qp_state
!= IB_QPS_RTR
&&
569 attr
->cur_qp_state
!= IB_QPS_RTS
&&
570 attr
->cur_qp_state
!= IB_QPS_SQD
&&
571 attr
->cur_qp_state
!= IB_QPS_SQE
)
574 cur_state
= attr
->cur_qp_state
;
576 spin_lock_irq(&qp
->sq
.lock
);
577 spin_lock(&qp
->rq
.lock
);
578 cur_state
= qp
->state
;
579 spin_unlock(&qp
->rq
.lock
);
580 spin_unlock_irq(&qp
->sq
.lock
);
583 if (attr_mask
& IB_QP_STATE
) {
584 if (attr
->qp_state
< 0 || attr
->qp_state
> IB_QPS_ERR
)
586 new_state
= attr
->qp_state
;
588 new_state
= cur_state
;
590 if (state_table
[cur_state
][new_state
].trans
== MTHCA_TRANS_INVALID
) {
591 mthca_dbg(dev
, "Illegal QP transition "
592 "%d->%d\n", cur_state
, new_state
);
596 req_param
= state_table
[cur_state
][new_state
].req_param
[qp
->transport
];
597 opt_param
= state_table
[cur_state
][new_state
].opt_param
[qp
->transport
];
599 if ((req_param
& attr_mask
) != req_param
) {
600 mthca_dbg(dev
, "QP transition "
601 "%d->%d missing req attr 0x%08x\n",
602 cur_state
, new_state
,
603 req_param
& ~attr_mask
);
607 if (attr_mask
& ~(req_param
| opt_param
| IB_QP_STATE
)) {
608 mthca_dbg(dev
, "QP transition (transport %d) "
609 "%d->%d has extra attr 0x%08x\n",
611 cur_state
, new_state
,
612 attr_mask
& ~(req_param
| opt_param
|
617 if ((attr_mask
& IB_QP_PKEY_INDEX
) &&
618 attr
->pkey_index
>= dev
->limits
.pkey_table_len
) {
619 mthca_dbg(dev
, "PKey index (%u) too large. max is %d\n",
620 attr
->pkey_index
,dev
->limits
.pkey_table_len
-1);
624 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
&&
625 attr
->max_rd_atomic
> dev
->limits
.max_qp_init_rdma
) {
626 mthca_dbg(dev
, "Max rdma_atomic as initiator %u too large (max is %d)\n",
627 attr
->max_rd_atomic
, dev
->limits
.max_qp_init_rdma
);
631 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
&&
632 attr
->max_dest_rd_atomic
> 1 << dev
->qp_table
.rdb_shift
) {
633 mthca_dbg(dev
, "Max rdma_atomic as responder %u too large (max %d)\n",
634 attr
->max_dest_rd_atomic
, 1 << dev
->qp_table
.rdb_shift
);
638 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
640 return PTR_ERR(mailbox
);
641 qp_param
= mailbox
->buf
;
642 qp_context
= &qp_param
->context
;
643 memset(qp_param
, 0, sizeof *qp_param
);
645 qp_context
->flags
= cpu_to_be32((to_mthca_state(new_state
) << 28) |
646 (to_mthca_st(qp
->transport
) << 16));
647 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_BIT_DE
);
648 if (!(attr_mask
& IB_QP_PATH_MIG_STATE
))
649 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_MIGRATED
<< 11);
651 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE
);
652 switch (attr
->path_mig_state
) {
653 case IB_MIG_MIGRATED
:
654 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_MIGRATED
<< 11);
657 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_REARM
<< 11);
660 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_ARMED
<< 11);
665 /* leave tavor_sched_queue as 0 */
667 if (qp
->transport
== MLX
|| qp
->transport
== UD
)
668 qp_context
->mtu_msgmax
= (IB_MTU_2048
<< 5) | 11;
669 else if (attr_mask
& IB_QP_PATH_MTU
)
670 qp_context
->mtu_msgmax
= (attr
->path_mtu
<< 5) | 31;
672 if (mthca_is_memfree(dev
)) {
674 qp_context
->rq_size_stride
= long_log2(qp
->rq
.max
) << 3;
675 qp_context
->rq_size_stride
|= qp
->rq
.wqe_shift
- 4;
678 qp_context
->sq_size_stride
= long_log2(qp
->sq
.max
) << 3;
679 qp_context
->sq_size_stride
|= qp
->sq
.wqe_shift
- 4;
682 /* leave arbel_sched_queue as 0 */
684 if (qp
->ibqp
.uobject
)
685 qp_context
->usr_page
=
686 cpu_to_be32(to_mucontext(qp
->ibqp
.uobject
->context
)->uar
.index
);
688 qp_context
->usr_page
= cpu_to_be32(dev
->driver_uar
.index
);
689 qp_context
->local_qpn
= cpu_to_be32(qp
->qpn
);
690 if (attr_mask
& IB_QP_DEST_QPN
) {
691 qp_context
->remote_qpn
= cpu_to_be32(attr
->dest_qp_num
);
694 if (qp
->transport
== MLX
)
695 qp_context
->pri_path
.port_pkey
|=
696 cpu_to_be32(to_msqp(qp
)->port
<< 24);
698 if (attr_mask
& IB_QP_PORT
) {
699 qp_context
->pri_path
.port_pkey
|=
700 cpu_to_be32(attr
->port_num
<< 24);
701 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM
);
705 if (attr_mask
& IB_QP_PKEY_INDEX
) {
706 qp_context
->pri_path
.port_pkey
|=
707 cpu_to_be32(attr
->pkey_index
);
708 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX
);
711 if (attr_mask
& IB_QP_RNR_RETRY
) {
712 qp_context
->pri_path
.rnr_retry
= attr
->rnr_retry
<< 5;
713 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY
);
716 if (attr_mask
& IB_QP_AV
) {
717 qp_context
->pri_path
.g_mylmc
= attr
->ah_attr
.src_path_bits
& 0x7f;
718 qp_context
->pri_path
.rlid
= cpu_to_be16(attr
->ah_attr
.dlid
);
719 qp_context
->pri_path
.static_rate
= !!attr
->ah_attr
.static_rate
;
720 if (attr
->ah_attr
.ah_flags
& IB_AH_GRH
) {
721 qp_context
->pri_path
.g_mylmc
|= 1 << 7;
722 qp_context
->pri_path
.mgid_index
= attr
->ah_attr
.grh
.sgid_index
;
723 qp_context
->pri_path
.hop_limit
= attr
->ah_attr
.grh
.hop_limit
;
724 qp_context
->pri_path
.sl_tclass_flowlabel
=
725 cpu_to_be32((attr
->ah_attr
.sl
<< 28) |
726 (attr
->ah_attr
.grh
.traffic_class
<< 20) |
727 (attr
->ah_attr
.grh
.flow_label
));
728 memcpy(qp_context
->pri_path
.rgid
,
729 attr
->ah_attr
.grh
.dgid
.raw
, 16);
731 qp_context
->pri_path
.sl_tclass_flowlabel
=
732 cpu_to_be32(attr
->ah_attr
.sl
<< 28);
734 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH
);
737 if (attr_mask
& IB_QP_TIMEOUT
) {
738 qp_context
->pri_path
.ackto
= attr
->timeout
<< 3;
739 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT
);
745 qp_context
->pd
= cpu_to_be32(to_mpd(ibqp
->pd
)->pd_num
);
746 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
747 qp_context
->wqe_lkey
= cpu_to_be32(qp
->mr
.ibmr
.lkey
);
748 qp_context
->params1
= cpu_to_be32((MTHCA_ACK_REQ_FREQ
<< 28) |
749 (MTHCA_FLIGHT_LIMIT
<< 24) |
753 if (qp
->sq_policy
== IB_SIGNAL_ALL_WR
)
754 qp_context
->params1
|= cpu_to_be32(MTHCA_QP_BIT_SSC
);
755 if (attr_mask
& IB_QP_RETRY_CNT
) {
756 qp_context
->params1
|= cpu_to_be32(attr
->retry_cnt
<< 16);
757 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT
);
760 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
) {
761 if (attr
->max_rd_atomic
)
762 qp_context
->params1
|=
763 cpu_to_be32(fls(attr
->max_rd_atomic
- 1) << 21);
764 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX
);
767 if (attr_mask
& IB_QP_SQ_PSN
)
768 qp_context
->next_send_psn
= cpu_to_be32(attr
->sq_psn
);
769 qp_context
->cqn_snd
= cpu_to_be32(to_mcq(ibqp
->send_cq
)->cqn
);
771 if (mthca_is_memfree(dev
)) {
772 qp_context
->snd_wqe_base_l
= cpu_to_be32(qp
->send_wqe_offset
);
773 qp_context
->snd_db_index
= cpu_to_be32(qp
->sq
.db_index
);
776 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
) {
777 if (attr
->max_dest_rd_atomic
)
778 qp_context
->params2
|=
779 cpu_to_be32(fls(attr
->max_dest_rd_atomic
- 1) << 21);
781 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX
);
784 if (attr_mask
& (IB_QP_ACCESS_FLAGS
| IB_QP_MAX_DEST_RD_ATOMIC
)) {
785 qp_context
->params2
|= get_hw_access_flags(qp
, attr
, attr_mask
);
786 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RWE
|
787 MTHCA_QP_OPTPAR_RRE
|
788 MTHCA_QP_OPTPAR_RAE
);
791 qp_context
->params2
|= cpu_to_be32(MTHCA_QP_BIT_RSC
);
794 qp_context
->params2
|= cpu_to_be32(MTHCA_QP_BIT_RIC
);
796 if (attr_mask
& IB_QP_MIN_RNR_TIMER
) {
797 qp_context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->min_rnr_timer
<< 24);
798 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT
);
800 if (attr_mask
& IB_QP_RQ_PSN
)
801 qp_context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->rq_psn
);
803 qp_context
->ra_buff_indx
=
804 cpu_to_be32(dev
->qp_table
.rdb_base
+
805 ((qp
->qpn
& (dev
->limits
.num_qps
- 1)) * MTHCA_RDB_ENTRY_SIZE
<<
806 dev
->qp_table
.rdb_shift
));
808 qp_context
->cqn_rcv
= cpu_to_be32(to_mcq(ibqp
->recv_cq
)->cqn
);
810 if (mthca_is_memfree(dev
))
811 qp_context
->rcv_db_index
= cpu_to_be32(qp
->rq
.db_index
);
813 if (attr_mask
& IB_QP_QKEY
) {
814 qp_context
->qkey
= cpu_to_be32(attr
->qkey
);
815 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY
);
819 qp_context
->srqn
= cpu_to_be32(1 << 24 |
820 to_msrq(ibqp
->srq
)->srqn
);
822 err
= mthca_MODIFY_QP(dev
, state_table
[cur_state
][new_state
].trans
,
823 qp
->qpn
, 0, mailbox
, 0, &status
);
825 mthca_warn(dev
, "modify QP %d returned status %02x.\n",
826 state_table
[cur_state
][new_state
].trans
, status
);
831 qp
->state
= new_state
;
832 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
833 qp
->atomic_rd_en
= attr
->qp_access_flags
;
834 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
835 qp
->resp_depth
= attr
->max_dest_rd_atomic
;
838 mthca_free_mailbox(dev
, mailbox
);
841 store_attrs(to_msqp(qp
), attr
, attr_mask
);
844 * If we moved QP0 to RTR, bring the IB link up; if we moved
845 * QP0 to RESET or ERROR, bring the link back down.
847 if (is_qp0(dev
, qp
)) {
848 if (cur_state
!= IB_QPS_RTR
&&
849 new_state
== IB_QPS_RTR
)
850 init_port(dev
, to_msqp(qp
)->port
);
852 if (cur_state
!= IB_QPS_RESET
&&
853 cur_state
!= IB_QPS_ERR
&&
854 (new_state
== IB_QPS_RESET
||
855 new_state
== IB_QPS_ERR
))
856 mthca_CLOSE_IB(dev
, to_msqp(qp
)->port
, &status
);
860 * If we moved a kernel QP to RESET, clean up all old CQ
861 * entries and reinitialize the QP.
863 if (!err
&& new_state
== IB_QPS_RESET
&& !qp
->ibqp
.uobject
) {
864 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.send_cq
)->cqn
, qp
->qpn
,
865 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
866 if (qp
->ibqp
.send_cq
!= qp
->ibqp
.recv_cq
)
867 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.recv_cq
)->cqn
, qp
->qpn
,
868 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
870 mthca_wq_init(&qp
->sq
);
871 qp
->sq
.last
= get_send_wqe(qp
, qp
->sq
.max
- 1);
873 mthca_wq_init(&qp
->rq
);
874 qp
->rq
.last
= get_recv_wqe(qp
, qp
->rq
.max
- 1);
876 if (mthca_is_memfree(dev
)) {
885 static void mthca_adjust_qp_caps(struct mthca_dev
*dev
,
892 * Calculate the maximum size of WQE s/g segments, excluding
893 * the next segment and other non-data segments.
895 max_data_size
= min(dev
->limits
.max_desc_sz
, 1 << qp
->sq
.wqe_shift
) -
896 sizeof (struct mthca_next_seg
);
898 switch (qp
->transport
) {
900 max_data_size
-= 2 * sizeof (struct mthca_data_seg
);
904 if (mthca_is_memfree(dev
))
905 max_data_size
-= sizeof (struct mthca_arbel_ud_seg
);
907 max_data_size
-= sizeof (struct mthca_tavor_ud_seg
);
911 max_data_size
-= sizeof (struct mthca_raddr_seg
);
915 /* We don't support inline data for kernel QPs (yet). */
916 if (!pd
->ibpd
.uobject
)
917 qp
->max_inline_data
= 0;
919 qp
->max_inline_data
= max_data_size
- MTHCA_INLINE_HEADER_SIZE
;
921 qp
->sq
.max_gs
= min_t(int, dev
->limits
.max_sg
,
922 max_data_size
/ sizeof (struct mthca_data_seg
));
923 qp
->rq
.max_gs
= min_t(int, dev
->limits
.max_sg
,
924 (min(dev
->limits
.max_desc_sz
, 1 << qp
->rq
.wqe_shift
) -
925 sizeof (struct mthca_next_seg
)) /
926 sizeof (struct mthca_data_seg
));
930 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
931 * rq.max_gs and sq.max_gs must all be assigned.
932 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
933 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
936 static int mthca_alloc_wqe_buf(struct mthca_dev
*dev
,
943 size
= sizeof (struct mthca_next_seg
) +
944 qp
->rq
.max_gs
* sizeof (struct mthca_data_seg
);
946 if (size
> dev
->limits
.max_desc_sz
)
949 for (qp
->rq
.wqe_shift
= 6; 1 << qp
->rq
.wqe_shift
< size
;
953 size
= qp
->sq
.max_gs
* sizeof (struct mthca_data_seg
);
954 switch (qp
->transport
) {
956 size
+= 2 * sizeof (struct mthca_data_seg
);
960 size
+= mthca_is_memfree(dev
) ?
961 sizeof (struct mthca_arbel_ud_seg
) :
962 sizeof (struct mthca_tavor_ud_seg
);
966 size
+= sizeof (struct mthca_raddr_seg
);
970 size
+= sizeof (struct mthca_raddr_seg
);
972 * An atomic op will require an atomic segment, a
973 * remote address segment and one scatter entry.
975 size
= max_t(int, size
,
976 sizeof (struct mthca_atomic_seg
) +
977 sizeof (struct mthca_raddr_seg
) +
978 sizeof (struct mthca_data_seg
));
985 /* Make sure that we have enough space for a bind request */
986 size
= max_t(int, size
, sizeof (struct mthca_bind_seg
));
988 size
+= sizeof (struct mthca_next_seg
);
990 if (size
> dev
->limits
.max_desc_sz
)
993 for (qp
->sq
.wqe_shift
= 6; 1 << qp
->sq
.wqe_shift
< size
;
997 qp
->send_wqe_offset
= ALIGN(qp
->rq
.max
<< qp
->rq
.wqe_shift
,
998 1 << qp
->sq
.wqe_shift
);
1001 * If this is a userspace QP, we don't actually have to
1002 * allocate anything. All we need is to calculate the WQE
1003 * sizes and the send_wqe_offset, so we're done now.
1005 if (pd
->ibpd
.uobject
)
1008 size
= PAGE_ALIGN(qp
->send_wqe_offset
+
1009 (qp
->sq
.max
<< qp
->sq
.wqe_shift
));
1011 qp
->wrid
= kmalloc((qp
->rq
.max
+ qp
->sq
.max
) * sizeof (u64
),
1016 err
= mthca_buf_alloc(dev
, size
, MTHCA_MAX_DIRECT_QP_SIZE
,
1017 &qp
->queue
, &qp
->is_direct
, pd
, 0, &qp
->mr
);
1028 static void mthca_free_wqe_buf(struct mthca_dev
*dev
,
1029 struct mthca_qp
*qp
)
1031 mthca_buf_free(dev
, PAGE_ALIGN(qp
->send_wqe_offset
+
1032 (qp
->sq
.max
<< qp
->sq
.wqe_shift
)),
1033 &qp
->queue
, qp
->is_direct
, &qp
->mr
);
1037 static int mthca_map_memfree(struct mthca_dev
*dev
,
1038 struct mthca_qp
*qp
)
1042 if (mthca_is_memfree(dev
)) {
1043 ret
= mthca_table_get(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1047 ret
= mthca_table_get(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1051 ret
= mthca_table_get(dev
, dev
->qp_table
.rdb_table
,
1052 qp
->qpn
<< dev
->qp_table
.rdb_shift
);
1061 mthca_table_put(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1064 mthca_table_put(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1069 static void mthca_unmap_memfree(struct mthca_dev
*dev
,
1070 struct mthca_qp
*qp
)
1072 mthca_table_put(dev
, dev
->qp_table
.rdb_table
,
1073 qp
->qpn
<< dev
->qp_table
.rdb_shift
);
1074 mthca_table_put(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1075 mthca_table_put(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1078 static int mthca_alloc_memfree(struct mthca_dev
*dev
,
1079 struct mthca_qp
*qp
)
1083 if (mthca_is_memfree(dev
)) {
1084 qp
->rq
.db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_RQ
,
1085 qp
->qpn
, &qp
->rq
.db
);
1086 if (qp
->rq
.db_index
< 0)
1089 qp
->sq
.db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_SQ
,
1090 qp
->qpn
, &qp
->sq
.db
);
1091 if (qp
->sq
.db_index
< 0)
1092 mthca_free_db(dev
, MTHCA_DB_TYPE_RQ
, qp
->rq
.db_index
);
1098 static void mthca_free_memfree(struct mthca_dev
*dev
,
1099 struct mthca_qp
*qp
)
1101 if (mthca_is_memfree(dev
)) {
1102 mthca_free_db(dev
, MTHCA_DB_TYPE_SQ
, qp
->sq
.db_index
);
1103 mthca_free_db(dev
, MTHCA_DB_TYPE_RQ
, qp
->rq
.db_index
);
1107 static int mthca_alloc_qp_common(struct mthca_dev
*dev
,
1108 struct mthca_pd
*pd
,
1109 struct mthca_cq
*send_cq
,
1110 struct mthca_cq
*recv_cq
,
1111 enum ib_sig_type send_policy
,
1112 struct mthca_qp
*qp
)
1117 atomic_set(&qp
->refcount
, 1);
1118 init_waitqueue_head(&qp
->wait
);
1119 qp
->state
= IB_QPS_RESET
;
1120 qp
->atomic_rd_en
= 0;
1122 qp
->sq_policy
= send_policy
;
1123 mthca_wq_init(&qp
->sq
);
1124 mthca_wq_init(&qp
->rq
);
1126 ret
= mthca_map_memfree(dev
, qp
);
1130 ret
= mthca_alloc_wqe_buf(dev
, pd
, qp
);
1132 mthca_unmap_memfree(dev
, qp
);
1136 mthca_adjust_qp_caps(dev
, pd
, qp
);
1139 * If this is a userspace QP, we're done now. The doorbells
1140 * will be allocated and buffers will be initialized in
1143 if (pd
->ibpd
.uobject
)
1146 ret
= mthca_alloc_memfree(dev
, qp
);
1148 mthca_free_wqe_buf(dev
, qp
);
1149 mthca_unmap_memfree(dev
, qp
);
1153 if (mthca_is_memfree(dev
)) {
1154 struct mthca_next_seg
*next
;
1155 struct mthca_data_seg
*scatter
;
1156 int size
= (sizeof (struct mthca_next_seg
) +
1157 qp
->rq
.max_gs
* sizeof (struct mthca_data_seg
)) / 16;
1159 for (i
= 0; i
< qp
->rq
.max
; ++i
) {
1160 next
= get_recv_wqe(qp
, i
);
1161 next
->nda_op
= cpu_to_be32(((i
+ 1) & (qp
->rq
.max
- 1)) <<
1163 next
->ee_nds
= cpu_to_be32(size
);
1165 for (scatter
= (void *) (next
+ 1);
1166 (void *) scatter
< (void *) next
+ (1 << qp
->rq
.wqe_shift
);
1168 scatter
->lkey
= cpu_to_be32(MTHCA_INVAL_LKEY
);
1171 for (i
= 0; i
< qp
->sq
.max
; ++i
) {
1172 next
= get_send_wqe(qp
, i
);
1173 next
->nda_op
= cpu_to_be32((((i
+ 1) & (qp
->sq
.max
- 1)) <<
1175 qp
->send_wqe_offset
);
1179 qp
->sq
.last
= get_send_wqe(qp
, qp
->sq
.max
- 1);
1180 qp
->rq
.last
= get_recv_wqe(qp
, qp
->rq
.max
- 1);
1185 static int mthca_set_qp_size(struct mthca_dev
*dev
, struct ib_qp_cap
*cap
,
1186 struct mthca_qp
*qp
)
1188 /* Sanity check QP size before proceeding */
1189 if (cap
->max_send_wr
> dev
->limits
.max_wqes
||
1190 cap
->max_recv_wr
> dev
->limits
.max_wqes
||
1191 cap
->max_send_sge
> dev
->limits
.max_sg
||
1192 cap
->max_recv_sge
> dev
->limits
.max_sg
)
1195 if (mthca_is_memfree(dev
)) {
1196 qp
->rq
.max
= cap
->max_recv_wr
?
1197 roundup_pow_of_two(cap
->max_recv_wr
) : 0;
1198 qp
->sq
.max
= cap
->max_send_wr
?
1199 roundup_pow_of_two(cap
->max_send_wr
) : 0;
1201 qp
->rq
.max
= cap
->max_recv_wr
;
1202 qp
->sq
.max
= cap
->max_send_wr
;
1205 qp
->rq
.max_gs
= cap
->max_recv_sge
;
1206 qp
->sq
.max_gs
= max_t(int, cap
->max_send_sge
,
1207 ALIGN(cap
->max_inline_data
+ MTHCA_INLINE_HEADER_SIZE
,
1208 MTHCA_INLINE_CHUNK_SIZE
) /
1209 sizeof (struct mthca_data_seg
));
1212 * For MLX transport we need 2 extra S/G entries:
1213 * one for the header and one for the checksum at the end
1215 if ((qp
->transport
== MLX
&& qp
->sq
.max_gs
+ 2 > dev
->limits
.max_sg
) ||
1216 qp
->sq
.max_gs
> dev
->limits
.max_sg
|| qp
->rq
.max_gs
> dev
->limits
.max_sg
)
1222 int mthca_alloc_qp(struct mthca_dev
*dev
,
1223 struct mthca_pd
*pd
,
1224 struct mthca_cq
*send_cq
,
1225 struct mthca_cq
*recv_cq
,
1226 enum ib_qp_type type
,
1227 enum ib_sig_type send_policy
,
1228 struct ib_qp_cap
*cap
,
1229 struct mthca_qp
*qp
)
1233 err
= mthca_set_qp_size(dev
, cap
, qp
);
1238 case IB_QPT_RC
: qp
->transport
= RC
; break;
1239 case IB_QPT_UC
: qp
->transport
= UC
; break;
1240 case IB_QPT_UD
: qp
->transport
= UD
; break;
1241 default: return -EINVAL
;
1244 qp
->qpn
= mthca_alloc(&dev
->qp_table
.alloc
);
1248 err
= mthca_alloc_qp_common(dev
, pd
, send_cq
, recv_cq
,
1251 mthca_free(&dev
->qp_table
.alloc
, qp
->qpn
);
1255 spin_lock_irq(&dev
->qp_table
.lock
);
1256 mthca_array_set(&dev
->qp_table
.qp
,
1257 qp
->qpn
& (dev
->limits
.num_qps
- 1), qp
);
1258 spin_unlock_irq(&dev
->qp_table
.lock
);
1263 int mthca_alloc_sqp(struct mthca_dev
*dev
,
1264 struct mthca_pd
*pd
,
1265 struct mthca_cq
*send_cq
,
1266 struct mthca_cq
*recv_cq
,
1267 enum ib_sig_type send_policy
,
1268 struct ib_qp_cap
*cap
,
1271 struct mthca_sqp
*sqp
)
1273 u32 mqpn
= qpn
* 2 + dev
->qp_table
.sqp_start
+ port
- 1;
1276 err
= mthca_set_qp_size(dev
, cap
, &sqp
->qp
);
1280 sqp
->header_buf_size
= sqp
->qp
.sq
.max
* MTHCA_UD_HEADER_SIZE
;
1281 sqp
->header_buf
= dma_alloc_coherent(&dev
->pdev
->dev
, sqp
->header_buf_size
,
1282 &sqp
->header_dma
, GFP_KERNEL
);
1283 if (!sqp
->header_buf
)
1286 spin_lock_irq(&dev
->qp_table
.lock
);
1287 if (mthca_array_get(&dev
->qp_table
.qp
, mqpn
))
1290 mthca_array_set(&dev
->qp_table
.qp
, mqpn
, sqp
);
1291 spin_unlock_irq(&dev
->qp_table
.lock
);
1298 sqp
->qp
.transport
= MLX
;
1300 err
= mthca_alloc_qp_common(dev
, pd
, send_cq
, recv_cq
,
1301 send_policy
, &sqp
->qp
);
1305 atomic_inc(&pd
->sqp_count
);
1311 * Lock CQs here, so that CQ polling code can do QP lookup
1312 * without taking a lock.
1314 spin_lock_irq(&send_cq
->lock
);
1315 if (send_cq
!= recv_cq
)
1316 spin_lock(&recv_cq
->lock
);
1318 spin_lock(&dev
->qp_table
.lock
);
1319 mthca_array_clear(&dev
->qp_table
.qp
, mqpn
);
1320 spin_unlock(&dev
->qp_table
.lock
);
1322 if (send_cq
!= recv_cq
)
1323 spin_unlock(&recv_cq
->lock
);
1324 spin_unlock_irq(&send_cq
->lock
);
1327 dma_free_coherent(&dev
->pdev
->dev
, sqp
->header_buf_size
,
1328 sqp
->header_buf
, sqp
->header_dma
);
1333 void mthca_free_qp(struct mthca_dev
*dev
,
1334 struct mthca_qp
*qp
)
1337 struct mthca_cq
*send_cq
;
1338 struct mthca_cq
*recv_cq
;
1340 send_cq
= to_mcq(qp
->ibqp
.send_cq
);
1341 recv_cq
= to_mcq(qp
->ibqp
.recv_cq
);
1344 * Lock CQs here, so that CQ polling code can do QP lookup
1345 * without taking a lock.
1347 spin_lock_irq(&send_cq
->lock
);
1348 if (send_cq
!= recv_cq
)
1349 spin_lock(&recv_cq
->lock
);
1351 spin_lock(&dev
->qp_table
.lock
);
1352 mthca_array_clear(&dev
->qp_table
.qp
,
1353 qp
->qpn
& (dev
->limits
.num_qps
- 1));
1354 spin_unlock(&dev
->qp_table
.lock
);
1356 if (send_cq
!= recv_cq
)
1357 spin_unlock(&recv_cq
->lock
);
1358 spin_unlock_irq(&send_cq
->lock
);
1360 atomic_dec(&qp
->refcount
);
1361 wait_event(qp
->wait
, !atomic_read(&qp
->refcount
));
1363 if (qp
->state
!= IB_QPS_RESET
)
1364 mthca_MODIFY_QP(dev
, MTHCA_TRANS_ANY2RST
, qp
->qpn
, 0, NULL
, 0, &status
);
1367 * If this is a userspace QP, the buffers, MR, CQs and so on
1368 * will be cleaned up in userspace, so all we have to do is
1369 * unref the mem-free tables and free the QPN in our table.
1371 if (!qp
->ibqp
.uobject
) {
1372 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.send_cq
)->cqn
, qp
->qpn
,
1373 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
1374 if (qp
->ibqp
.send_cq
!= qp
->ibqp
.recv_cq
)
1375 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.recv_cq
)->cqn
, qp
->qpn
,
1376 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
1378 mthca_free_memfree(dev
, qp
);
1379 mthca_free_wqe_buf(dev
, qp
);
1382 mthca_unmap_memfree(dev
, qp
);
1384 if (is_sqp(dev
, qp
)) {
1385 atomic_dec(&(to_mpd(qp
->ibqp
.pd
)->sqp_count
));
1386 dma_free_coherent(&dev
->pdev
->dev
,
1387 to_msqp(qp
)->header_buf_size
,
1388 to_msqp(qp
)->header_buf
,
1389 to_msqp(qp
)->header_dma
);
1391 mthca_free(&dev
->qp_table
.alloc
, qp
->qpn
);
1394 /* Create UD header for an MLX send and build a data segment for it */
1395 static int build_mlx_header(struct mthca_dev
*dev
, struct mthca_sqp
*sqp
,
1396 int ind
, struct ib_send_wr
*wr
,
1397 struct mthca_mlx_seg
*mlx
,
1398 struct mthca_data_seg
*data
)
1404 ib_ud_header_init(256, /* assume a MAD */
1405 sqp
->ud_header
.grh_present
,
1408 err
= mthca_read_ah(dev
, to_mah(wr
->wr
.ud
.ah
), &sqp
->ud_header
);
1411 mlx
->flags
&= ~cpu_to_be32(MTHCA_NEXT_SOLICIT
| 1);
1412 mlx
->flags
|= cpu_to_be32((!sqp
->qp
.ibqp
.qp_num
? MTHCA_MLX_VL15
: 0) |
1413 (sqp
->ud_header
.lrh
.destination_lid
==
1414 IB_LID_PERMISSIVE
? MTHCA_MLX_SLR
: 0) |
1415 (sqp
->ud_header
.lrh
.service_level
<< 8));
1416 mlx
->rlid
= sqp
->ud_header
.lrh
.destination_lid
;
1419 switch (wr
->opcode
) {
1421 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY
;
1422 sqp
->ud_header
.immediate_present
= 0;
1424 case IB_WR_SEND_WITH_IMM
:
1425 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE
;
1426 sqp
->ud_header
.immediate_present
= 1;
1427 sqp
->ud_header
.immediate_data
= wr
->imm_data
;
1433 sqp
->ud_header
.lrh
.virtual_lane
= !sqp
->qp
.ibqp
.qp_num
? 15 : 0;
1434 if (sqp
->ud_header
.lrh
.destination_lid
== IB_LID_PERMISSIVE
)
1435 sqp
->ud_header
.lrh
.source_lid
= IB_LID_PERMISSIVE
;
1436 sqp
->ud_header
.bth
.solicited_event
= !!(wr
->send_flags
& IB_SEND_SOLICITED
);
1437 if (!sqp
->qp
.ibqp
.qp_num
)
1438 ib_get_cached_pkey(&dev
->ib_dev
, sqp
->port
,
1439 sqp
->pkey_index
, &pkey
);
1441 ib_get_cached_pkey(&dev
->ib_dev
, sqp
->port
,
1442 wr
->wr
.ud
.pkey_index
, &pkey
);
1443 sqp
->ud_header
.bth
.pkey
= cpu_to_be16(pkey
);
1444 sqp
->ud_header
.bth
.destination_qpn
= cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1445 sqp
->ud_header
.bth
.psn
= cpu_to_be32((sqp
->send_psn
++) & ((1 << 24) - 1));
1446 sqp
->ud_header
.deth
.qkey
= cpu_to_be32(wr
->wr
.ud
.remote_qkey
& 0x80000000 ?
1447 sqp
->qkey
: wr
->wr
.ud
.remote_qkey
);
1448 sqp
->ud_header
.deth
.source_qpn
= cpu_to_be32(sqp
->qp
.ibqp
.qp_num
);
1450 header_size
= ib_ud_header_pack(&sqp
->ud_header
,
1452 ind
* MTHCA_UD_HEADER_SIZE
);
1454 data
->byte_count
= cpu_to_be32(header_size
);
1455 data
->lkey
= cpu_to_be32(to_mpd(sqp
->qp
.ibqp
.pd
)->ntmr
.ibmr
.lkey
);
1456 data
->addr
= cpu_to_be64(sqp
->header_dma
+
1457 ind
* MTHCA_UD_HEADER_SIZE
);
1462 static inline int mthca_wq_overflow(struct mthca_wq
*wq
, int nreq
,
1463 struct ib_cq
*ib_cq
)
1466 struct mthca_cq
*cq
;
1468 cur
= wq
->head
- wq
->tail
;
1469 if (likely(cur
+ nreq
< wq
->max
))
1473 spin_lock(&cq
->lock
);
1474 cur
= wq
->head
- wq
->tail
;
1475 spin_unlock(&cq
->lock
);
1477 return cur
+ nreq
>= wq
->max
;
1480 int mthca_tavor_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1481 struct ib_send_wr
**bad_wr
)
1483 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1484 struct mthca_qp
*qp
= to_mqp(ibqp
);
1487 unsigned long flags
;
1497 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1499 /* XXX check that state is OK to post send */
1501 ind
= qp
->sq
.next_ind
;
1503 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1504 if (mthca_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1505 mthca_err(dev
, "SQ %06x full (%u head, %u tail,"
1506 " %d max, %d nreq)\n", qp
->qpn
,
1507 qp
->sq
.head
, qp
->sq
.tail
,
1514 wqe
= get_send_wqe(qp
, ind
);
1515 prev_wqe
= qp
->sq
.last
;
1518 ((struct mthca_next_seg
*) wqe
)->nda_op
= 0;
1519 ((struct mthca_next_seg
*) wqe
)->ee_nds
= 0;
1520 ((struct mthca_next_seg
*) wqe
)->flags
=
1521 ((wr
->send_flags
& IB_SEND_SIGNALED
) ?
1522 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE
) : 0) |
1523 ((wr
->send_flags
& IB_SEND_SOLICITED
) ?
1524 cpu_to_be32(MTHCA_NEXT_SOLICIT
) : 0) |
1526 if (wr
->opcode
== IB_WR_SEND_WITH_IMM
||
1527 wr
->opcode
== IB_WR_RDMA_WRITE_WITH_IMM
)
1528 ((struct mthca_next_seg
*) wqe
)->imm
= wr
->imm_data
;
1530 wqe
+= sizeof (struct mthca_next_seg
);
1531 size
= sizeof (struct mthca_next_seg
) / 16;
1533 switch (qp
->transport
) {
1535 switch (wr
->opcode
) {
1536 case IB_WR_ATOMIC_CMP_AND_SWP
:
1537 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1538 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1539 cpu_to_be64(wr
->wr
.atomic
.remote_addr
);
1540 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1541 cpu_to_be32(wr
->wr
.atomic
.rkey
);
1542 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1544 wqe
+= sizeof (struct mthca_raddr_seg
);
1546 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1547 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1548 cpu_to_be64(wr
->wr
.atomic
.swap
);
1549 ((struct mthca_atomic_seg
*) wqe
)->compare
=
1550 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1552 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1553 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1554 ((struct mthca_atomic_seg
*) wqe
)->compare
= 0;
1557 wqe
+= sizeof (struct mthca_atomic_seg
);
1558 size
+= (sizeof (struct mthca_raddr_seg
) +
1559 sizeof (struct mthca_atomic_seg
)) / 16;
1562 case IB_WR_RDMA_WRITE
:
1563 case IB_WR_RDMA_WRITE_WITH_IMM
:
1564 case IB_WR_RDMA_READ
:
1565 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1566 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1567 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1568 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1569 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1570 wqe
+= sizeof (struct mthca_raddr_seg
);
1571 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1575 /* No extra segments required for sends */
1582 switch (wr
->opcode
) {
1583 case IB_WR_RDMA_WRITE
:
1584 case IB_WR_RDMA_WRITE_WITH_IMM
:
1585 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1586 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1587 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1588 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1589 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1590 wqe
+= sizeof (struct mthca_raddr_seg
);
1591 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1595 /* No extra segments required for sends */
1602 ((struct mthca_tavor_ud_seg
*) wqe
)->lkey
=
1603 cpu_to_be32(to_mah(wr
->wr
.ud
.ah
)->key
);
1604 ((struct mthca_tavor_ud_seg
*) wqe
)->av_addr
=
1605 cpu_to_be64(to_mah(wr
->wr
.ud
.ah
)->avdma
);
1606 ((struct mthca_tavor_ud_seg
*) wqe
)->dqpn
=
1607 cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1608 ((struct mthca_tavor_ud_seg
*) wqe
)->qkey
=
1609 cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1611 wqe
+= sizeof (struct mthca_tavor_ud_seg
);
1612 size
+= sizeof (struct mthca_tavor_ud_seg
) / 16;
1616 err
= build_mlx_header(dev
, to_msqp(qp
), ind
, wr
,
1617 wqe
- sizeof (struct mthca_next_seg
),
1623 wqe
+= sizeof (struct mthca_data_seg
);
1624 size
+= sizeof (struct mthca_data_seg
) / 16;
1628 if (wr
->num_sge
> qp
->sq
.max_gs
) {
1629 mthca_err(dev
, "too many gathers\n");
1635 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1636 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1637 cpu_to_be32(wr
->sg_list
[i
].length
);
1638 ((struct mthca_data_seg
*) wqe
)->lkey
=
1639 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1640 ((struct mthca_data_seg
*) wqe
)->addr
=
1641 cpu_to_be64(wr
->sg_list
[i
].addr
);
1642 wqe
+= sizeof (struct mthca_data_seg
);
1643 size
+= sizeof (struct mthca_data_seg
) / 16;
1646 /* Add one more inline data segment for ICRC */
1647 if (qp
->transport
== MLX
) {
1648 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1649 cpu_to_be32((1 << 31) | 4);
1650 ((u32
*) wqe
)[1] = 0;
1651 wqe
+= sizeof (struct mthca_data_seg
);
1652 size
+= sizeof (struct mthca_data_seg
) / 16;
1655 qp
->wrid
[ind
+ qp
->rq
.max
] = wr
->wr_id
;
1657 if (wr
->opcode
>= ARRAY_SIZE(mthca_opcode
)) {
1658 mthca_err(dev
, "opcode invalid\n");
1664 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1665 cpu_to_be32(((ind
<< qp
->sq
.wqe_shift
) +
1666 qp
->send_wqe_offset
) |
1667 mthca_opcode
[wr
->opcode
]);
1669 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1670 cpu_to_be32((size0
? 0 : MTHCA_NEXT_DBD
) | size
);
1674 op0
= mthca_opcode
[wr
->opcode
];
1678 if (unlikely(ind
>= qp
->sq
.max
))
1686 doorbell
[0] = cpu_to_be32(((qp
->sq
.next_ind
<< qp
->sq
.wqe_shift
) +
1687 qp
->send_wqe_offset
) | f0
| op0
);
1688 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
1692 mthca_write64(doorbell
,
1693 dev
->kar
+ MTHCA_SEND_DOORBELL
,
1694 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1697 qp
->sq
.next_ind
= ind
;
1698 qp
->sq
.head
+= nreq
;
1700 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
1704 int mthca_tavor_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
1705 struct ib_recv_wr
**bad_wr
)
1707 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1708 struct mthca_qp
*qp
= to_mqp(ibqp
);
1710 unsigned long flags
;
1720 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
1722 /* XXX check that state is OK to post receive */
1724 ind
= qp
->rq
.next_ind
;
1726 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1727 if (unlikely(nreq
== MTHCA_TAVOR_MAX_WQES_PER_RECV_DB
)) {
1730 doorbell
[0] = cpu_to_be32((qp
->rq
.next_ind
<< qp
->rq
.wqe_shift
) | size0
);
1731 doorbell
[1] = cpu_to_be32(qp
->qpn
<< 8);
1735 mthca_write64(doorbell
,
1736 dev
->kar
+ MTHCA_RECEIVE_DOORBELL
,
1737 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1739 qp
->rq
.head
+= MTHCA_TAVOR_MAX_WQES_PER_RECV_DB
;
1743 if (mthca_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
1744 mthca_err(dev
, "RQ %06x full (%u head, %u tail,"
1745 " %d max, %d nreq)\n", qp
->qpn
,
1746 qp
->rq
.head
, qp
->rq
.tail
,
1753 wqe
= get_recv_wqe(qp
, ind
);
1754 prev_wqe
= qp
->rq
.last
;
1757 ((struct mthca_next_seg
*) wqe
)->nda_op
= 0;
1758 ((struct mthca_next_seg
*) wqe
)->ee_nds
=
1759 cpu_to_be32(MTHCA_NEXT_DBD
);
1760 ((struct mthca_next_seg
*) wqe
)->flags
= 0;
1762 wqe
+= sizeof (struct mthca_next_seg
);
1763 size
= sizeof (struct mthca_next_seg
) / 16;
1765 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
1771 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1772 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1773 cpu_to_be32(wr
->sg_list
[i
].length
);
1774 ((struct mthca_data_seg
*) wqe
)->lkey
=
1775 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1776 ((struct mthca_data_seg
*) wqe
)->addr
=
1777 cpu_to_be64(wr
->sg_list
[i
].addr
);
1778 wqe
+= sizeof (struct mthca_data_seg
);
1779 size
+= sizeof (struct mthca_data_seg
) / 16;
1782 qp
->wrid
[ind
] = wr
->wr_id
;
1784 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1785 cpu_to_be32((ind
<< qp
->rq
.wqe_shift
) | 1);
1787 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1788 cpu_to_be32(MTHCA_NEXT_DBD
| size
);
1794 if (unlikely(ind
>= qp
->rq
.max
))
1800 doorbell
[0] = cpu_to_be32((qp
->rq
.next_ind
<< qp
->rq
.wqe_shift
) | size0
);
1801 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | nreq
);
1805 mthca_write64(doorbell
,
1806 dev
->kar
+ MTHCA_RECEIVE_DOORBELL
,
1807 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1810 qp
->rq
.next_ind
= ind
;
1811 qp
->rq
.head
+= nreq
;
1813 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
1817 int mthca_arbel_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1818 struct ib_send_wr
**bad_wr
)
1820 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1821 struct mthca_qp
*qp
= to_mqp(ibqp
);
1825 unsigned long flags
;
1835 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1837 /* XXX check that state is OK to post send */
1839 ind
= qp
->sq
.head
& (qp
->sq
.max
- 1);
1841 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1842 if (unlikely(nreq
== MTHCA_ARBEL_MAX_WQES_PER_SEND_DB
)) {
1845 doorbell
[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB
<< 24) |
1846 ((qp
->sq
.head
& 0xffff) << 8) |
1848 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
1850 qp
->sq
.head
+= MTHCA_ARBEL_MAX_WQES_PER_SEND_DB
;
1854 * Make sure that descriptors are written before
1858 *qp
->sq
.db
= cpu_to_be32(qp
->sq
.head
& 0xffff);
1861 * Make sure doorbell record is written before we
1862 * write MMIO send doorbell.
1865 mthca_write64(doorbell
,
1866 dev
->kar
+ MTHCA_SEND_DOORBELL
,
1867 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1870 if (mthca_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1871 mthca_err(dev
, "SQ %06x full (%u head, %u tail,"
1872 " %d max, %d nreq)\n", qp
->qpn
,
1873 qp
->sq
.head
, qp
->sq
.tail
,
1880 wqe
= get_send_wqe(qp
, ind
);
1881 prev_wqe
= qp
->sq
.last
;
1884 ((struct mthca_next_seg
*) wqe
)->flags
=
1885 ((wr
->send_flags
& IB_SEND_SIGNALED
) ?
1886 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE
) : 0) |
1887 ((wr
->send_flags
& IB_SEND_SOLICITED
) ?
1888 cpu_to_be32(MTHCA_NEXT_SOLICIT
) : 0) |
1890 if (wr
->opcode
== IB_WR_SEND_WITH_IMM
||
1891 wr
->opcode
== IB_WR_RDMA_WRITE_WITH_IMM
)
1892 ((struct mthca_next_seg
*) wqe
)->imm
= wr
->imm_data
;
1894 wqe
+= sizeof (struct mthca_next_seg
);
1895 size
= sizeof (struct mthca_next_seg
) / 16;
1897 switch (qp
->transport
) {
1899 switch (wr
->opcode
) {
1900 case IB_WR_ATOMIC_CMP_AND_SWP
:
1901 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1902 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1903 cpu_to_be64(wr
->wr
.atomic
.remote_addr
);
1904 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1905 cpu_to_be32(wr
->wr
.atomic
.rkey
);
1906 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1908 wqe
+= sizeof (struct mthca_raddr_seg
);
1910 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1911 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1912 cpu_to_be64(wr
->wr
.atomic
.swap
);
1913 ((struct mthca_atomic_seg
*) wqe
)->compare
=
1914 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1916 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1917 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1918 ((struct mthca_atomic_seg
*) wqe
)->compare
= 0;
1921 wqe
+= sizeof (struct mthca_atomic_seg
);
1922 size
+= (sizeof (struct mthca_raddr_seg
) +
1923 sizeof (struct mthca_atomic_seg
)) / 16;
1926 case IB_WR_RDMA_READ
:
1927 case IB_WR_RDMA_WRITE
:
1928 case IB_WR_RDMA_WRITE_WITH_IMM
:
1929 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1930 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1931 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1932 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1933 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1934 wqe
+= sizeof (struct mthca_raddr_seg
);
1935 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1939 /* No extra segments required for sends */
1946 switch (wr
->opcode
) {
1947 case IB_WR_RDMA_WRITE
:
1948 case IB_WR_RDMA_WRITE_WITH_IMM
:
1949 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1950 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1951 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1952 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1953 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1954 wqe
+= sizeof (struct mthca_raddr_seg
);
1955 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1959 /* No extra segments required for sends */
1966 memcpy(((struct mthca_arbel_ud_seg
*) wqe
)->av
,
1967 to_mah(wr
->wr
.ud
.ah
)->av
, MTHCA_AV_SIZE
);
1968 ((struct mthca_arbel_ud_seg
*) wqe
)->dqpn
=
1969 cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1970 ((struct mthca_arbel_ud_seg
*) wqe
)->qkey
=
1971 cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1973 wqe
+= sizeof (struct mthca_arbel_ud_seg
);
1974 size
+= sizeof (struct mthca_arbel_ud_seg
) / 16;
1978 err
= build_mlx_header(dev
, to_msqp(qp
), ind
, wr
,
1979 wqe
- sizeof (struct mthca_next_seg
),
1985 wqe
+= sizeof (struct mthca_data_seg
);
1986 size
+= sizeof (struct mthca_data_seg
) / 16;
1990 if (wr
->num_sge
> qp
->sq
.max_gs
) {
1991 mthca_err(dev
, "too many gathers\n");
1997 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1998 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1999 cpu_to_be32(wr
->sg_list
[i
].length
);
2000 ((struct mthca_data_seg
*) wqe
)->lkey
=
2001 cpu_to_be32(wr
->sg_list
[i
].lkey
);
2002 ((struct mthca_data_seg
*) wqe
)->addr
=
2003 cpu_to_be64(wr
->sg_list
[i
].addr
);
2004 wqe
+= sizeof (struct mthca_data_seg
);
2005 size
+= sizeof (struct mthca_data_seg
) / 16;
2008 /* Add one more inline data segment for ICRC */
2009 if (qp
->transport
== MLX
) {
2010 ((struct mthca_data_seg
*) wqe
)->byte_count
=
2011 cpu_to_be32((1 << 31) | 4);
2012 ((u32
*) wqe
)[1] = 0;
2013 wqe
+= sizeof (struct mthca_data_seg
);
2014 size
+= sizeof (struct mthca_data_seg
) / 16;
2017 qp
->wrid
[ind
+ qp
->rq
.max
] = wr
->wr_id
;
2019 if (wr
->opcode
>= ARRAY_SIZE(mthca_opcode
)) {
2020 mthca_err(dev
, "opcode invalid\n");
2026 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
2027 cpu_to_be32(((ind
<< qp
->sq
.wqe_shift
) +
2028 qp
->send_wqe_offset
) |
2029 mthca_opcode
[wr
->opcode
]);
2031 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
2032 cpu_to_be32(MTHCA_NEXT_DBD
| size
);
2036 op0
= mthca_opcode
[wr
->opcode
];
2040 if (unlikely(ind
>= qp
->sq
.max
))
2046 doorbell
[0] = cpu_to_be32((nreq
<< 24) |
2047 ((qp
->sq
.head
& 0xffff) << 8) |
2049 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
2051 qp
->sq
.head
+= nreq
;
2054 * Make sure that descriptors are written before
2058 *qp
->sq
.db
= cpu_to_be32(qp
->sq
.head
& 0xffff);
2061 * Make sure doorbell record is written before we
2062 * write MMIO send doorbell.
2065 mthca_write64(doorbell
,
2066 dev
->kar
+ MTHCA_SEND_DOORBELL
,
2067 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
2070 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
2074 int mthca_arbel_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
2075 struct ib_recv_wr
**bad_wr
)
2077 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
2078 struct mthca_qp
*qp
= to_mqp(ibqp
);
2079 unsigned long flags
;
2086 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
2088 /* XXX check that state is OK to post receive */
2090 ind
= qp
->rq
.head
& (qp
->rq
.max
- 1);
2092 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
2093 if (mthca_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
2094 mthca_err(dev
, "RQ %06x full (%u head, %u tail,"
2095 " %d max, %d nreq)\n", qp
->qpn
,
2096 qp
->rq
.head
, qp
->rq
.tail
,
2103 wqe
= get_recv_wqe(qp
, ind
);
2105 ((struct mthca_next_seg
*) wqe
)->flags
= 0;
2107 wqe
+= sizeof (struct mthca_next_seg
);
2109 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
2115 for (i
= 0; i
< wr
->num_sge
; ++i
) {
2116 ((struct mthca_data_seg
*) wqe
)->byte_count
=
2117 cpu_to_be32(wr
->sg_list
[i
].length
);
2118 ((struct mthca_data_seg
*) wqe
)->lkey
=
2119 cpu_to_be32(wr
->sg_list
[i
].lkey
);
2120 ((struct mthca_data_seg
*) wqe
)->addr
=
2121 cpu_to_be64(wr
->sg_list
[i
].addr
);
2122 wqe
+= sizeof (struct mthca_data_seg
);
2125 if (i
< qp
->rq
.max_gs
) {
2126 ((struct mthca_data_seg
*) wqe
)->byte_count
= 0;
2127 ((struct mthca_data_seg
*) wqe
)->lkey
= cpu_to_be32(MTHCA_INVAL_LKEY
);
2128 ((struct mthca_data_seg
*) wqe
)->addr
= 0;
2131 qp
->wrid
[ind
] = wr
->wr_id
;
2134 if (unlikely(ind
>= qp
->rq
.max
))
2139 qp
->rq
.head
+= nreq
;
2142 * Make sure that descriptors are written before
2146 *qp
->rq
.db
= cpu_to_be32(qp
->rq
.head
& 0xffff);
2149 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
2153 int mthca_free_err_wqe(struct mthca_dev
*dev
, struct mthca_qp
*qp
, int is_send
,
2154 int index
, int *dbd
, __be32
*new_wqe
)
2156 struct mthca_next_seg
*next
;
2159 * For SRQs, all WQEs generate a CQE, so we're always at the
2160 * end of the doorbell chain.
2168 next
= get_send_wqe(qp
, index
);
2170 next
= get_recv_wqe(qp
, index
);
2172 *dbd
= !!(next
->ee_nds
& cpu_to_be32(MTHCA_NEXT_DBD
));
2173 if (next
->ee_nds
& cpu_to_be32(0x3f))
2174 *new_wqe
= (next
->nda_op
& cpu_to_be32(~0x3f)) |
2175 (next
->ee_nds
& cpu_to_be32(0x3f));
2182 int __devinit
mthca_init_qp_table(struct mthca_dev
*dev
)
2188 spin_lock_init(&dev
->qp_table
.lock
);
2191 * We reserve 2 extra QPs per port for the special QPs. The
2192 * special QP for port 1 has to be even, so round up.
2194 dev
->qp_table
.sqp_start
= (dev
->limits
.reserved_qps
+ 1) & ~1UL;
2195 err
= mthca_alloc_init(&dev
->qp_table
.alloc
,
2196 dev
->limits
.num_qps
,
2198 dev
->qp_table
.sqp_start
+
2199 MTHCA_MAX_PORTS
* 2);
2203 err
= mthca_array_init(&dev
->qp_table
.qp
,
2204 dev
->limits
.num_qps
);
2206 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);
2210 for (i
= 0; i
< 2; ++i
) {
2211 err
= mthca_CONF_SPECIAL_QP(dev
, i
? IB_QPT_GSI
: IB_QPT_SMI
,
2212 dev
->qp_table
.sqp_start
+ i
* 2,
2217 mthca_warn(dev
, "CONF_SPECIAL_QP returned "
2218 "status %02x, aborting.\n",
2227 for (i
= 0; i
< 2; ++i
)
2228 mthca_CONF_SPECIAL_QP(dev
, i
, 0, &status
);
2230 mthca_array_cleanup(&dev
->qp_table
.qp
, dev
->limits
.num_qps
);
2231 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);
2236 void __devexit
mthca_cleanup_qp_table(struct mthca_dev
*dev
)
2241 for (i
= 0; i
< 2; ++i
)
2242 mthca_CONF_SPECIAL_QP(dev
, i
, 0, &status
);
2244 mthca_array_cleanup(&dev
->qp_table
.qp
, dev
->limits
.num_qps
);
2245 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);