2 * Copyright (c) 2006 - 2009 Intel-NE, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
39 #include <linux/tcp.h>
40 #include <linux/if_vlan.h>
41 #include <linux/inet_lro.h>
45 static unsigned int nes_lro_max_aggr
= NES_LRO_MAX_AGGR
;
46 module_param(nes_lro_max_aggr
, uint
, 0444);
47 MODULE_PARM_DESC(nes_lro_max_aggr
, "NIC LRO max packet aggregation");
49 static u32 crit_err_count
;
50 u32 int_mod_timer_init
;
51 u32 int_mod_cq_depth_256
;
52 u32 int_mod_cq_depth_128
;
53 u32 int_mod_cq_depth_32
;
54 u32 int_mod_cq_depth_24
;
55 u32 int_mod_cq_depth_16
;
56 u32 int_mod_cq_depth_4
;
57 u32 int_mod_cq_depth_1
;
58 static const u8 nes_max_critical_error_count
= 100;
61 static void nes_cqp_ce_handler(struct nes_device
*nesdev
, struct nes_hw_cq
*cq
);
62 static void nes_init_csr_ne020(struct nes_device
*nesdev
, u8 hw_rev
, u8 port_count
);
63 static int nes_init_serdes(struct nes_device
*nesdev
, u8 hw_rev
, u8 port_count
,
64 struct nes_adapter
*nesadapter
, u8 OneG_Mode
);
65 static void nes_nic_napi_ce_handler(struct nes_device
*nesdev
, struct nes_hw_nic_cq
*cq
);
66 static void nes_process_aeq(struct nes_device
*nesdev
, struct nes_hw_aeq
*aeq
);
67 static void nes_process_ceq(struct nes_device
*nesdev
, struct nes_hw_ceq
*ceq
);
68 static void nes_process_iwarp_aeqe(struct nes_device
*nesdev
,
69 struct nes_hw_aeqe
*aeqe
);
70 static void process_critical_error(struct nes_device
*nesdev
);
71 static void nes_process_mac_intr(struct nes_device
*nesdev
, u32 mac_number
);
72 static unsigned int nes_reset_adapter_ne020(struct nes_device
*nesdev
, u8
*OneG_Mode
);
74 #ifdef CONFIG_INFINIBAND_NES_DEBUG
75 static unsigned char *nes_iwarp_state_str
[] = {
86 static unsigned char *nes_tcp_state_str
[] = {
108 * nes_nic_init_timer_defaults
110 void nes_nic_init_timer_defaults(struct nes_device
*nesdev
, u8 jumbomode
)
113 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
114 struct nes_hw_tune_timer
*shared_timer
= &nesadapter
->tune_timer
;
116 spin_lock_irqsave(&nesadapter
->periodic_timer_lock
, flags
);
118 shared_timer
->timer_in_use_min
= NES_NIC_FAST_TIMER_LOW
;
119 shared_timer
->timer_in_use_max
= NES_NIC_FAST_TIMER_HIGH
;
121 shared_timer
->threshold_low
= DEFAULT_JUMBO_NES_QL_LOW
;
122 shared_timer
->threshold_target
= DEFAULT_JUMBO_NES_QL_TARGET
;
123 shared_timer
->threshold_high
= DEFAULT_JUMBO_NES_QL_HIGH
;
125 shared_timer
->threshold_low
= DEFAULT_NES_QL_LOW
;
126 shared_timer
->threshold_target
= DEFAULT_NES_QL_TARGET
;
127 shared_timer
->threshold_high
= DEFAULT_NES_QL_HIGH
;
130 /* todo use netdev->mtu to set thresholds */
131 spin_unlock_irqrestore(&nesadapter
->periodic_timer_lock
, flags
);
138 static void nes_nic_init_timer(struct nes_device
*nesdev
)
141 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
142 struct nes_hw_tune_timer
*shared_timer
= &nesadapter
->tune_timer
;
144 spin_lock_irqsave(&nesadapter
->periodic_timer_lock
, flags
);
146 if (shared_timer
->timer_in_use_old
== 0) {
147 nesdev
->deepcq_count
= 0;
148 shared_timer
->timer_direction_upward
= 0;
149 shared_timer
->timer_direction_downward
= 0;
150 shared_timer
->timer_in_use
= NES_NIC_FAST_TIMER
;
151 shared_timer
->timer_in_use_old
= 0;
154 if (shared_timer
->timer_in_use
!= shared_timer
->timer_in_use_old
) {
155 shared_timer
->timer_in_use_old
= shared_timer
->timer_in_use
;
156 nes_write32(nesdev
->regs
+NES_PERIODIC_CONTROL
,
157 0x80000000 | ((u32
)(shared_timer
->timer_in_use
*8)));
159 /* todo use netdev->mtu to set thresholds */
160 spin_unlock_irqrestore(&nesadapter
->periodic_timer_lock
, flags
);
167 static void nes_nic_tune_timer(struct nes_device
*nesdev
)
170 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
171 struct nes_hw_tune_timer
*shared_timer
= &nesadapter
->tune_timer
;
172 u16 cq_count
= nesdev
->currcq_count
;
174 spin_lock_irqsave(&nesadapter
->periodic_timer_lock
, flags
);
176 if (shared_timer
->cq_count_old
<= cq_count
)
177 shared_timer
->cq_direction_downward
= 0;
179 shared_timer
->cq_direction_downward
++;
180 shared_timer
->cq_count_old
= cq_count
;
181 if (shared_timer
->cq_direction_downward
> NES_NIC_CQ_DOWNWARD_TREND
) {
182 if (cq_count
<= shared_timer
->threshold_low
&&
183 shared_timer
->threshold_low
> 4) {
184 shared_timer
->threshold_low
= shared_timer
->threshold_low
/2;
185 shared_timer
->cq_direction_downward
=0;
186 nesdev
->currcq_count
= 0;
187 spin_unlock_irqrestore(&nesadapter
->periodic_timer_lock
, flags
);
193 nesdev
->deepcq_count
+= cq_count
;
194 if (cq_count
<= shared_timer
->threshold_low
) { /* increase timer gently */
195 shared_timer
->timer_direction_upward
++;
196 shared_timer
->timer_direction_downward
= 0;
197 } else if (cq_count
<= shared_timer
->threshold_target
) { /* balanced */
198 shared_timer
->timer_direction_upward
= 0;
199 shared_timer
->timer_direction_downward
= 0;
200 } else if (cq_count
<= shared_timer
->threshold_high
) { /* decrease timer gently */
201 shared_timer
->timer_direction_downward
++;
202 shared_timer
->timer_direction_upward
= 0;
203 } else if (cq_count
<= (shared_timer
->threshold_high
) * 2) {
204 shared_timer
->timer_in_use
-= 2;
205 shared_timer
->timer_direction_upward
= 0;
206 shared_timer
->timer_direction_downward
++;
208 shared_timer
->timer_in_use
-= 4;
209 shared_timer
->timer_direction_upward
= 0;
210 shared_timer
->timer_direction_downward
++;
213 if (shared_timer
->timer_direction_upward
> 3 ) { /* using history */
214 shared_timer
->timer_in_use
+= 3;
215 shared_timer
->timer_direction_upward
= 0;
216 shared_timer
->timer_direction_downward
= 0;
218 if (shared_timer
->timer_direction_downward
> 5) { /* using history */
219 shared_timer
->timer_in_use
-= 4 ;
220 shared_timer
->timer_direction_downward
= 0;
221 shared_timer
->timer_direction_upward
= 0;
225 /* boundary checking */
226 if (shared_timer
->timer_in_use
> shared_timer
->threshold_high
)
227 shared_timer
->timer_in_use
= shared_timer
->threshold_high
;
228 else if (shared_timer
->timer_in_use
< shared_timer
->threshold_low
)
229 shared_timer
->timer_in_use
= shared_timer
->threshold_low
;
231 nesdev
->currcq_count
= 0;
233 spin_unlock_irqrestore(&nesadapter
->periodic_timer_lock
, flags
);
238 * nes_init_adapter - initialize adapter
240 struct nes_adapter
*nes_init_adapter(struct nes_device
*nesdev
, u8 hw_rev
) {
241 struct nes_adapter
*nesadapter
= NULL
;
242 unsigned long num_pds
;
261 /* search the list of existing adapters */
262 list_for_each_entry(nesadapter
, &nes_adapter_list
, list
) {
263 nes_debug(NES_DBG_INIT
, "Searching Adapter list for PCI devfn = 0x%X,"
264 " adapter PCI slot/bus = %u/%u, pci devices PCI slot/bus = %u/%u, .\n",
265 nesdev
->pcidev
->devfn
,
266 PCI_SLOT(nesadapter
->devfn
),
267 nesadapter
->bus_number
,
268 PCI_SLOT(nesdev
->pcidev
->devfn
),
269 nesdev
->pcidev
->bus
->number
);
270 if ((PCI_SLOT(nesadapter
->devfn
) == PCI_SLOT(nesdev
->pcidev
->devfn
)) &&
271 (nesadapter
->bus_number
== nesdev
->pcidev
->bus
->number
)) {
272 nesadapter
->ref_count
++;
277 /* no adapter found */
278 num_pds
= pci_resource_len(nesdev
->pcidev
, BAR_1
) >> PAGE_SHIFT
;
279 if ((hw_rev
!= NE020_REV
) && (hw_rev
!= NE020_REV1
)) {
280 nes_debug(NES_DBG_INIT
, "NE020 driver detected unknown hardware revision 0x%x\n",
285 nes_debug(NES_DBG_INIT
, "Determine Soft Reset, QP_control=0x%x, CPU0=0x%x, CPU1=0x%x, CPU2=0x%x\n",
286 nes_read_indexed(nesdev
, NES_IDX_QP_CONTROL
+ PCI_FUNC(nesdev
->pcidev
->devfn
) * 8),
287 nes_read_indexed(nesdev
, NES_IDX_INT_CPU_STATUS
),
288 nes_read_indexed(nesdev
, NES_IDX_INT_CPU_STATUS
+ 4),
289 nes_read_indexed(nesdev
, NES_IDX_INT_CPU_STATUS
+ 8));
291 nes_debug(NES_DBG_INIT
, "Reset and init NE020\n");
294 if ((port_count
= nes_reset_adapter_ne020(nesdev
, &OneG_Mode
)) == 0)
297 max_qp
= nes_read_indexed(nesdev
, NES_IDX_QP_CTX_SIZE
);
298 nes_debug(NES_DBG_INIT
, "QP_CTX_SIZE=%u\n", max_qp
);
300 u32temp
= nes_read_indexed(nesdev
, NES_IDX_QUAD_HASH_TABLE_SIZE
);
301 if (max_qp
> ((u32
)1 << (u32temp
& 0x001f))) {
302 nes_debug(NES_DBG_INIT
, "Reducing Max QPs to %u due to hash table size = 0x%08X\n",
304 max_qp
= (u32
)1 << (u32temp
& 0x001f);
307 hte_index_mask
= ((u32
)1 << ((u32temp
& 0x001f)+1))-1;
308 nes_debug(NES_DBG_INIT
, "Max QP = %u, hte_index_mask = 0x%08X.\n",
309 max_qp
, hte_index_mask
);
311 u32temp
= nes_read_indexed(nesdev
, NES_IDX_IRRQ_COUNT
);
313 max_irrq
= 1 << (u32temp
& 0x001f);
315 if (max_qp
> max_irrq
) {
317 nes_debug(NES_DBG_INIT
, "Reducing Max QPs to %u due to Available Q1s.\n",
321 /* there should be no reason to allocate more pds than qps */
322 if (num_pds
> max_qp
)
325 u32temp
= nes_read_indexed(nesdev
, NES_IDX_MRT_SIZE
);
326 max_mr
= (u32
)8192 << (u32temp
& 0x7);
328 u32temp
= nes_read_indexed(nesdev
, NES_IDX_PBL_REGION_SIZE
);
329 max_256pbl
= (u32
)1 << (u32temp
& 0x0000001f);
330 max_4kpbl
= (u32
)1 << ((u32temp
>> 16) & 0x0000001f);
331 max_cq
= nes_read_indexed(nesdev
, NES_IDX_CQ_CTX_SIZE
);
333 u32temp
= nes_read_indexed(nesdev
, NES_IDX_ARP_CACHE_SIZE
);
334 arp_table_size
= 1 << u32temp
;
336 adapter_size
= (sizeof(struct nes_adapter
) +
337 (sizeof(unsigned long)-1)) & (~(sizeof(unsigned long)-1));
338 adapter_size
+= sizeof(unsigned long) * BITS_TO_LONGS(max_qp
);
339 adapter_size
+= sizeof(unsigned long) * BITS_TO_LONGS(max_mr
);
340 adapter_size
+= sizeof(unsigned long) * BITS_TO_LONGS(max_cq
);
341 adapter_size
+= sizeof(unsigned long) * BITS_TO_LONGS(num_pds
);
342 adapter_size
+= sizeof(unsigned long) * BITS_TO_LONGS(arp_table_size
);
343 adapter_size
+= sizeof(struct nes_qp
**) * max_qp
;
345 /* allocate a new adapter struct */
346 nesadapter
= kzalloc(adapter_size
, GFP_KERNEL
);
347 if (nesadapter
== NULL
) {
351 nes_debug(NES_DBG_INIT
, "Allocating new nesadapter @ %p, size = %u (actual size = %u).\n",
352 nesadapter
, (u32
)sizeof(struct nes_adapter
), adapter_size
);
354 if (nes_read_eeprom_values(nesdev
, nesadapter
)) {
355 printk(KERN_ERR PFX
"Unable to read EEPROM data.\n");
360 nesadapter
->vendor_id
= (((u32
) nesadapter
->mac_addr_high
) << 8) |
361 (nesadapter
->mac_addr_low
>> 24);
363 pci_bus_read_config_word(nesdev
->pcidev
->bus
, nesdev
->pcidev
->devfn
,
364 PCI_DEVICE_ID
, &device_id
);
365 nesadapter
->vendor_part_id
= device_id
;
367 if (nes_init_serdes(nesdev
, hw_rev
, port_count
, nesadapter
,
372 nes_init_csr_ne020(nesdev
, hw_rev
, port_count
);
374 memset(nesadapter
->pft_mcast_map
, 255,
375 sizeof nesadapter
->pft_mcast_map
);
377 /* populate the new nesadapter */
378 nesadapter
->devfn
= nesdev
->pcidev
->devfn
;
379 nesadapter
->bus_number
= nesdev
->pcidev
->bus
->number
;
380 nesadapter
->ref_count
= 1;
381 nesadapter
->timer_int_req
= 0xffff0000;
382 nesadapter
->OneG_Mode
= OneG_Mode
;
383 nesadapter
->doorbell_start
= nesdev
->doorbell_region
;
385 /* nesadapter->tick_delta = clk_divisor; */
386 nesadapter
->hw_rev
= hw_rev
;
387 nesadapter
->port_count
= port_count
;
389 nesadapter
->max_qp
= max_qp
;
390 nesadapter
->hte_index_mask
= hte_index_mask
;
391 nesadapter
->max_irrq
= max_irrq
;
392 nesadapter
->max_mr
= max_mr
;
393 nesadapter
->max_256pbl
= max_256pbl
- 1;
394 nesadapter
->max_4kpbl
= max_4kpbl
- 1;
395 nesadapter
->max_cq
= max_cq
;
396 nesadapter
->free_256pbl
= max_256pbl
- 1;
397 nesadapter
->free_4kpbl
= max_4kpbl
- 1;
398 nesadapter
->max_pd
= num_pds
;
399 nesadapter
->arp_table_size
= arp_table_size
;
401 nesadapter
->et_pkt_rate_low
= NES_TIMER_ENABLE_LIMIT
;
402 if (nes_drv_opt
& NES_DRV_OPT_DISABLE_INT_MOD
) {
403 nesadapter
->et_use_adaptive_rx_coalesce
= 0;
404 nesadapter
->timer_int_limit
= NES_TIMER_INT_LIMIT
;
405 nesadapter
->et_rx_coalesce_usecs_irq
= interrupt_mod_interval
;
407 nesadapter
->et_use_adaptive_rx_coalesce
= 1;
408 nesadapter
->timer_int_limit
= NES_TIMER_INT_LIMIT_DYNAMIC
;
409 nesadapter
->et_rx_coalesce_usecs_irq
= 0;
410 printk(PFX
"%s: Using Adaptive Interrupt Moderation\n", __func__
);
412 /* Setup and enable the periodic timer */
413 if (nesadapter
->et_rx_coalesce_usecs_irq
)
414 nes_write32(nesdev
->regs
+NES_PERIODIC_CONTROL
, 0x80000000 |
415 ((u32
)(nesadapter
->et_rx_coalesce_usecs_irq
* 8)));
417 nes_write32(nesdev
->regs
+NES_PERIODIC_CONTROL
, 0x00000000);
419 nesadapter
->base_pd
= 1;
421 nesadapter
->device_cap_flags
=
422 IB_DEVICE_LOCAL_DMA_LKEY
| IB_DEVICE_MEM_WINDOW
;
424 nesadapter
->allocated_qps
= (unsigned long *)&(((unsigned char *)nesadapter
)
425 [(sizeof(struct nes_adapter
)+(sizeof(unsigned long)-1))&(~(sizeof(unsigned long)-1))]);
426 nesadapter
->allocated_cqs
= &nesadapter
->allocated_qps
[BITS_TO_LONGS(max_qp
)];
427 nesadapter
->allocated_mrs
= &nesadapter
->allocated_cqs
[BITS_TO_LONGS(max_cq
)];
428 nesadapter
->allocated_pds
= &nesadapter
->allocated_mrs
[BITS_TO_LONGS(max_mr
)];
429 nesadapter
->allocated_arps
= &nesadapter
->allocated_pds
[BITS_TO_LONGS(num_pds
)];
430 nesadapter
->qp_table
= (struct nes_qp
**)(&nesadapter
->allocated_arps
[BITS_TO_LONGS(arp_table_size
)]);
433 /* mark the usual suspect QPs and CQs as in use */
434 for (u32temp
= 0; u32temp
< NES_FIRST_QPN
; u32temp
++) {
435 set_bit(u32temp
, nesadapter
->allocated_qps
);
436 set_bit(u32temp
, nesadapter
->allocated_cqs
);
439 for (u32temp
= 0; u32temp
< 20; u32temp
++)
440 set_bit(u32temp
, nesadapter
->allocated_pds
);
441 u32temp
= nes_read_indexed(nesdev
, NES_IDX_QP_MAX_CFG_SIZES
);
443 max_rq_wrs
= ((u32temp
>> 8) & 3);
444 switch (max_rq_wrs
) {
459 max_sq_wrs
= (u32temp
& 3);
460 switch (max_sq_wrs
) {
474 nesadapter
->max_qp_wr
= min(max_rq_wrs
, max_sq_wrs
);
475 nesadapter
->max_irrq_wr
= (u32temp
>> 16) & 3;
477 nesadapter
->max_sge
= 4;
478 nesadapter
->max_cqe
= 32767;
480 if (nes_read_eeprom_values(nesdev
, nesadapter
)) {
481 printk(KERN_ERR PFX
"Unable to read EEPROM data.\n");
486 u32temp
= nes_read_indexed(nesdev
, NES_IDX_TCP_TIMER_CONFIG
);
487 nes_write_indexed(nesdev
, NES_IDX_TCP_TIMER_CONFIG
,
488 (u32temp
& 0xff000000) | (nesadapter
->tcp_timer_core_clk_divisor
& 0x00ffffff));
490 /* setup port configuration */
491 if (nesadapter
->port_count
== 1) {
492 nesadapter
->log_port
= 0x00000000;
493 if (nes_drv_opt
& NES_DRV_OPT_DUAL_LOGICAL_PORT
)
494 nes_write_indexed(nesdev
, NES_IDX_TX_POOL_SIZE
, 0x00000002);
496 nes_write_indexed(nesdev
, NES_IDX_TX_POOL_SIZE
, 0x00000003);
498 if (nesadapter
->phy_type
[0] == NES_PHY_TYPE_PUMA_1G
) {
499 nesadapter
->log_port
= 0x000000D8;
501 if (nesadapter
->port_count
== 2)
502 nesadapter
->log_port
= 0x00000044;
504 nesadapter
->log_port
= 0x000000e4;
506 nes_write_indexed(nesdev
, NES_IDX_TX_POOL_SIZE
, 0x00000003);
509 nes_write_indexed(nesdev
, NES_IDX_NIC_LOGPORT_TO_PHYPORT
,
510 nesadapter
->log_port
);
511 nes_debug(NES_DBG_INIT
, "Probe time, LOG2PHY=%u\n",
512 nes_read_indexed(nesdev
, NES_IDX_NIC_LOGPORT_TO_PHYPORT
));
514 spin_lock_init(&nesadapter
->resource_lock
);
515 spin_lock_init(&nesadapter
->phy_lock
);
516 spin_lock_init(&nesadapter
->pbl_lock
);
517 spin_lock_init(&nesadapter
->periodic_timer_lock
);
519 INIT_LIST_HEAD(&nesadapter
->nesvnic_list
[0]);
520 INIT_LIST_HEAD(&nesadapter
->nesvnic_list
[1]);
521 INIT_LIST_HEAD(&nesadapter
->nesvnic_list
[2]);
522 INIT_LIST_HEAD(&nesadapter
->nesvnic_list
[3]);
524 if ((!nesadapter
->OneG_Mode
) && (nesadapter
->port_count
== 2)) {
525 u32 pcs_control_status0
, pcs_control_status1
;
533 pcs_control_status0
= nes_read_indexed(nesdev
,
534 NES_IDX_PHY_PCS_CONTROL_STATUS0
);
535 pcs_control_status1
= nes_read_indexed(nesdev
,
536 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ 0x200);
538 for (i
= 0; i
< NES_MAX_LINK_CHECK
; i
++) {
539 pcs_control_status0
= nes_read_indexed(nesdev
,
540 NES_IDX_PHY_PCS_CONTROL_STATUS0
);
541 pcs_control_status1
= nes_read_indexed(nesdev
,
542 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ 0x200);
543 if ((0x0F000100 == (pcs_control_status0
& 0x0F000100))
544 || (0x0F000100 == (pcs_control_status1
& 0x0F000100)))
549 spin_lock_irqsave(&nesadapter
->phy_lock
, flags
);
550 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, 0x0000F088);
552 reset_value
= nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
);
553 reset_value
|= 0x0000003d;
554 nes_write32(nesdev
->regs
+NES_SOFTWARE_RESET
, reset_value
);
556 while (((nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
)
557 & 0x00000040) != 0x00000040) && (j
++ < 5000));
558 spin_unlock_irqrestore(&nesadapter
->phy_lock
, flags
);
560 pcs_control_status0
= nes_read_indexed(nesdev
,
561 NES_IDX_PHY_PCS_CONTROL_STATUS0
);
562 pcs_control_status1
= nes_read_indexed(nesdev
,
563 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ 0x200);
565 for (i
= 0; i
< NES_MAX_LINK_CHECK
; i
++) {
566 pcs_control_status0
= nes_read_indexed(nesdev
,
567 NES_IDX_PHY_PCS_CONTROL_STATUS0
);
568 pcs_control_status1
= nes_read_indexed(nesdev
,
569 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ 0x200);
570 if ((0x0F000100 == (pcs_control_status0
& 0x0F000100))
571 || (0x0F000100 == (pcs_control_status1
& 0x0F000100))) {
572 if (++ext_cnt
> int_cnt
) {
573 spin_lock_irqsave(&nesadapter
->phy_lock
, flags
);
574 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
,
577 reset_value
= nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
);
578 reset_value
|= 0x0000003d;
579 nes_write32(nesdev
->regs
+NES_SOFTWARE_RESET
, reset_value
);
581 while (((nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
)
582 & 0x00000040) != 0x00000040) && (j
++ < 5000));
583 spin_unlock_irqrestore(&nesadapter
->phy_lock
, flags
);
592 if (nesadapter
->hw_rev
== NE020_REV
) {
593 init_timer(&nesadapter
->mh_timer
);
594 nesadapter
->mh_timer
.function
= nes_mh_fix
;
595 nesadapter
->mh_timer
.expires
= jiffies
+ (HZ
/5); /* 1 second */
596 nesadapter
->mh_timer
.data
= (unsigned long)nesdev
;
597 add_timer(&nesadapter
->mh_timer
);
599 nes_write32(nesdev
->regs
+NES_INTF_INT_STAT
, 0x0f000000);
602 init_timer(&nesadapter
->lc_timer
);
603 nesadapter
->lc_timer
.function
= nes_clc
;
604 nesadapter
->lc_timer
.expires
= jiffies
+ 3600 * HZ
; /* 1 hour */
605 nesadapter
->lc_timer
.data
= (unsigned long)nesdev
;
606 add_timer(&nesadapter
->lc_timer
);
608 list_add_tail(&nesadapter
->list
, &nes_adapter_list
);
610 for (func_index
= 0; func_index
< 8; func_index
++) {
611 pci_bus_read_config_word(nesdev
->pcidev
->bus
,
612 PCI_DEVFN(PCI_SLOT(nesdev
->pcidev
->devfn
),
613 func_index
), 0, &vendor_id
);
614 if (vendor_id
== 0xffff)
617 nes_debug(NES_DBG_INIT
, "%s %d functions found for %s.\n", __func__
,
618 func_index
, pci_name(nesdev
->pcidev
));
619 nesadapter
->adapter_fcn_count
= func_index
;
626 * nes_reset_adapter_ne020
628 static unsigned int nes_reset_adapter_ne020(struct nes_device
*nesdev
, u8
*OneG_Mode
)
634 u32temp
= nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
);
635 port_count
= ((u32temp
& 0x00000300) >> 8) + 1;
636 /* TODO: assuming that both SERDES are set the same for now */
637 *OneG_Mode
= (u32temp
& 0x00003c00) ? 0 : 1;
638 nes_debug(NES_DBG_INIT
, "Initial Software Reset = 0x%08X, port_count=%u\n",
639 u32temp
, port_count
);
641 nes_debug(NES_DBG_INIT
, "Running in 1G mode.\n");
642 u32temp
&= 0xff00ffc0;
643 switch (port_count
) {
645 u32temp
|= 0x00ee0000;
648 u32temp
|= 0x00cc0000;
651 u32temp
|= 0x00000000;
658 /* check and do full reset if needed */
659 if (nes_read_indexed(nesdev
, NES_IDX_QP_CONTROL
+(PCI_FUNC(nesdev
->pcidev
->devfn
)*8))) {
660 nes_debug(NES_DBG_INIT
, "Issuing Full Soft reset = 0x%08X\n", u32temp
| 0xd);
661 nes_write32(nesdev
->regs
+NES_SOFTWARE_RESET
, u32temp
| 0xd);
664 while (((nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
) & 0x00000040) == 0) && i
++ < 10000)
667 nes_debug(NES_DBG_INIT
, "Did not see full soft reset done.\n");
672 while ((nes_read_indexed(nesdev
, NES_IDX_INT_CPU_STATUS
) != 0x80) && i
++ < 10000)
675 printk(KERN_ERR PFX
"Internal CPU not ready, status = %02X\n",
676 nes_read_indexed(nesdev
, NES_IDX_INT_CPU_STATUS
));
682 switch (port_count
) {
684 u32temp
|= 0x00ee0010;
687 u32temp
|= 0x00cc0030;
690 u32temp
|= 0x00000030;
694 nes_debug(NES_DBG_INIT
, "Issuing Port Soft reset = 0x%08X\n", u32temp
| 0xd);
695 nes_write32(nesdev
->regs
+NES_SOFTWARE_RESET
, u32temp
| 0xd);
698 while (((nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
) & 0x00000040) == 0) && i
++ < 10000)
701 nes_debug(NES_DBG_INIT
, "Did not see port soft reset done.\n");
707 while (((u32temp
= (nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_STATUS0
)
708 & 0x0000000f)) != 0x0000000f) && i
++ < 5000)
711 nes_debug(NES_DBG_INIT
, "Serdes 0 not ready, status=%x\n", u32temp
);
716 if (port_count
> 1) {
718 while (((u32temp
= (nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_STATUS1
)
719 & 0x0000000f)) != 0x0000000f) && i
++ < 5000)
722 nes_debug(NES_DBG_INIT
, "Serdes 1 not ready, status=%x\n", u32temp
);
734 static int nes_init_serdes(struct nes_device
*nesdev
, u8 hw_rev
, u8 port_count
,
735 struct nes_adapter
*nesadapter
, u8 OneG_Mode
)
739 u32 serdes_common_control
;
741 if (hw_rev
!= NE020_REV
) {
744 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_CDR_CONTROL0
, 0x000000FF);
745 if (nesadapter
->phy_type
[0] == NES_PHY_TYPE_PUMA_1G
) {
746 serdes_common_control
= nes_read_indexed(nesdev
,
747 NES_IDX_ETH_SERDES_COMMON_CONTROL0
);
748 serdes_common_control
|= 0x000000100;
749 nes_write_indexed(nesdev
,
750 NES_IDX_ETH_SERDES_COMMON_CONTROL0
,
751 serdes_common_control
);
752 } else if (!OneG_Mode
) {
753 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0
, 0x11110000);
755 if (((port_count
> 1) &&
756 (nesadapter
->phy_type
[0] != NES_PHY_TYPE_PUMA_1G
)) ||
758 (nesadapter
->phy_type
[0] == NES_PHY_TYPE_PUMA_1G
))) {
760 if (nesadapter
->phy_type
[0] == NES_PHY_TYPE_ARGUS
) {
761 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_EMP0
, 0x00000000);
762 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_EMP1
, 0x00000000);
764 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_CDR_CONTROL1
, 0x000000FF);
765 if (nesadapter
->phy_type
[0] == NES_PHY_TYPE_PUMA_1G
) {
766 serdes_common_control
= nes_read_indexed(nesdev
,
767 NES_IDX_ETH_SERDES_COMMON_CONTROL1
);
768 serdes_common_control
|= 0x000000100;
769 nes_write_indexed(nesdev
,
770 NES_IDX_ETH_SERDES_COMMON_CONTROL1
,
771 serdes_common_control
);
772 } else if (!OneG_Mode
) {
773 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1
, 0x11110000);
778 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL0
, 0x00000008);
780 while (((u32temp
= (nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_STATUS0
)
781 & 0x0000000f)) != 0x0000000f) && i
++ < 5000)
784 nes_debug(NES_DBG_PHY
, "Init: serdes 0 not ready, status=%x\n", u32temp
);
787 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_EMP0
, 0x000bdef7);
788 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_DRIVE0
, 0x9ce73000);
789 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_MODE0
, 0x0ff00000);
790 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_SIGDET0
, 0x00000000);
791 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_BYPASS0
, 0x00000000);
792 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0
, 0x00000000);
794 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0
, 0xf0182222);
796 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0
, 0xf0042222);
798 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_CDR_CONTROL0
, 0x000000ff);
799 if (port_count
> 1) {
801 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, 0x00000048);
803 while (((u32temp
= (nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_STATUS1
)
804 & 0x0000000f)) != 0x0000000f) && (i
++ < 5000))
807 printk("%s: Init: serdes 1 not ready, status=%x\n", __func__
, u32temp
);
810 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_EMP1
, 0x000bdef7);
811 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_DRIVE1
, 0x9ce73000);
812 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_MODE1
, 0x0ff00000);
813 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_SIGDET1
, 0x00000000);
814 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_BYPASS1
, 0x00000000);
815 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1
, 0x00000000);
816 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_EQ_CONTROL1
, 0xf0002222);
817 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_CDR_CONTROL1
, 0x000000ff);
826 * Initialize registers for ne020 hardware
828 static void nes_init_csr_ne020(struct nes_device
*nesdev
, u8 hw_rev
, u8 port_count
)
832 nes_debug(NES_DBG_INIT
, "port_count=%d\n", port_count
);
834 nes_write_indexed(nesdev
, 0x000001E4, 0x00000007);
835 /* nes_write_indexed(nesdev, 0x000001E8, 0x000208C4); */
836 nes_write_indexed(nesdev
, 0x000001E8, 0x00020874);
837 nes_write_indexed(nesdev
, 0x000001D8, 0x00048002);
838 /* nes_write_indexed(nesdev, 0x000001D8, 0x0004B002); */
839 nes_write_indexed(nesdev
, 0x000001FC, 0x00050005);
840 nes_write_indexed(nesdev
, 0x00000600, 0x55555555);
841 nes_write_indexed(nesdev
, 0x00000604, 0x55555555);
843 /* TODO: move these MAC register settings to NIC bringup */
844 nes_write_indexed(nesdev
, 0x00002000, 0x00000001);
845 nes_write_indexed(nesdev
, 0x00002004, 0x00000001);
846 nes_write_indexed(nesdev
, 0x00002008, 0x0000FFFF);
847 nes_write_indexed(nesdev
, 0x0000200C, 0x00000001);
848 nes_write_indexed(nesdev
, 0x00002010, 0x000003c1);
849 nes_write_indexed(nesdev
, 0x0000201C, 0x75345678);
850 if (port_count
> 1) {
851 nes_write_indexed(nesdev
, 0x00002200, 0x00000001);
852 nes_write_indexed(nesdev
, 0x00002204, 0x00000001);
853 nes_write_indexed(nesdev
, 0x00002208, 0x0000FFFF);
854 nes_write_indexed(nesdev
, 0x0000220C, 0x00000001);
855 nes_write_indexed(nesdev
, 0x00002210, 0x000003c1);
856 nes_write_indexed(nesdev
, 0x0000221C, 0x75345678);
857 nes_write_indexed(nesdev
, 0x00000908, 0x20000001);
859 if (port_count
> 2) {
860 nes_write_indexed(nesdev
, 0x00002400, 0x00000001);
861 nes_write_indexed(nesdev
, 0x00002404, 0x00000001);
862 nes_write_indexed(nesdev
, 0x00002408, 0x0000FFFF);
863 nes_write_indexed(nesdev
, 0x0000240C, 0x00000001);
864 nes_write_indexed(nesdev
, 0x00002410, 0x000003c1);
865 nes_write_indexed(nesdev
, 0x0000241C, 0x75345678);
866 nes_write_indexed(nesdev
, 0x00000910, 0x20000001);
868 nes_write_indexed(nesdev
, 0x00002600, 0x00000001);
869 nes_write_indexed(nesdev
, 0x00002604, 0x00000001);
870 nes_write_indexed(nesdev
, 0x00002608, 0x0000FFFF);
871 nes_write_indexed(nesdev
, 0x0000260C, 0x00000001);
872 nes_write_indexed(nesdev
, 0x00002610, 0x000003c1);
873 nes_write_indexed(nesdev
, 0x0000261C, 0x75345678);
874 nes_write_indexed(nesdev
, 0x00000918, 0x20000001);
877 nes_write_indexed(nesdev
, 0x00005000, 0x00018000);
878 /* nes_write_indexed(nesdev, 0x00005000, 0x00010000); */
879 nes_write_indexed(nesdev
, NES_IDX_WQM_CONFIG1
, (wqm_quanta
<< 1) |
881 nes_write_indexed(nesdev
, 0x00005008, 0x1F1F1F1F);
882 nes_write_indexed(nesdev
, 0x00005010, 0x1F1F1F1F);
883 nes_write_indexed(nesdev
, 0x00005018, 0x1F1F1F1F);
884 nes_write_indexed(nesdev
, 0x00005020, 0x1F1F1F1F);
885 nes_write_indexed(nesdev
, 0x00006090, 0xFFFFFFFF);
887 /* TODO: move this to code, get from EEPROM */
888 nes_write_indexed(nesdev
, 0x00000900, 0x20000001);
889 nes_write_indexed(nesdev
, 0x000060C0, 0x0000028e);
890 nes_write_indexed(nesdev
, 0x000060C8, 0x00000020);
892 nes_write_indexed(nesdev
, 0x000001EC, 0x7b2625a0);
893 /* nes_write_indexed(nesdev, 0x000001EC, 0x5f2625a0); */
895 if (hw_rev
!= NE020_REV
) {
896 u32temp
= nes_read_indexed(nesdev
, 0x000008e8);
897 u32temp
|= 0x80000000;
898 nes_write_indexed(nesdev
, 0x000008e8, u32temp
);
899 u32temp
= nes_read_indexed(nesdev
, 0x000021f8);
900 u32temp
&= 0x7fffffff;
901 u32temp
|= 0x7fff0010;
902 nes_write_indexed(nesdev
, 0x000021f8, u32temp
);
908 * nes_destroy_adapter - destroy the adapter structure
910 void nes_destroy_adapter(struct nes_adapter
*nesadapter
)
912 struct nes_adapter
*tmp_adapter
;
914 list_for_each_entry(tmp_adapter
, &nes_adapter_list
, list
) {
915 nes_debug(NES_DBG_SHUTDOWN
, "Nes Adapter list entry = 0x%p.\n",
919 nesadapter
->ref_count
--;
920 if (!nesadapter
->ref_count
) {
921 if (nesadapter
->hw_rev
== NE020_REV
) {
922 del_timer(&nesadapter
->mh_timer
);
924 del_timer(&nesadapter
->lc_timer
);
926 list_del(&nesadapter
->list
);
935 int nes_init_cqp(struct nes_device
*nesdev
)
937 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
938 struct nes_hw_cqp_qp_context
*cqp_qp_context
;
939 struct nes_hw_cqp_wqe
*cqp_wqe
;
940 struct nes_hw_ceq
*ceq
;
941 struct nes_hw_ceq
*nic_ceq
;
942 struct nes_hw_aeq
*aeq
;
950 /* allocate CQP memory */
951 /* Need to add max_cq to the aeq size once cq overflow checking is added back */
952 /* SQ is 512 byte aligned, others are 256 byte aligned */
953 nesdev
->cqp_mem_size
= 512 +
954 (sizeof(struct nes_hw_cqp_wqe
) * NES_CQP_SQ_SIZE
) +
955 (sizeof(struct nes_hw_cqe
) * NES_CCQ_SIZE
) +
956 max(((u32
)sizeof(struct nes_hw_ceqe
) * NES_CCEQ_SIZE
), (u32
)256) +
957 max(((u32
)sizeof(struct nes_hw_ceqe
) * NES_NIC_CEQ_SIZE
), (u32
)256) +
958 (sizeof(struct nes_hw_aeqe
) * nesadapter
->max_qp
) +
959 sizeof(struct nes_hw_cqp_qp_context
);
961 nesdev
->cqp_vbase
= pci_alloc_consistent(nesdev
->pcidev
, nesdev
->cqp_mem_size
,
963 if (!nesdev
->cqp_vbase
) {
964 nes_debug(NES_DBG_INIT
, "Unable to allocate memory for host descriptor rings\n");
967 memset(nesdev
->cqp_vbase
, 0, nesdev
->cqp_mem_size
);
969 /* Allocate a twice the number of CQP requests as the SQ size */
970 nesdev
->nes_cqp_requests
= kzalloc(sizeof(struct nes_cqp_request
) *
971 2 * NES_CQP_SQ_SIZE
, GFP_KERNEL
);
972 if (nesdev
->nes_cqp_requests
== NULL
) {
973 nes_debug(NES_DBG_INIT
, "Unable to allocate memory CQP request entries.\n");
974 pci_free_consistent(nesdev
->pcidev
, nesdev
->cqp_mem_size
, nesdev
->cqp
.sq_vbase
,
975 nesdev
->cqp
.sq_pbase
);
979 nes_debug(NES_DBG_INIT
, "Allocated CQP structures at %p (phys = %016lX), size = %u.\n",
980 nesdev
->cqp_vbase
, (unsigned long)nesdev
->cqp_pbase
, nesdev
->cqp_mem_size
);
982 spin_lock_init(&nesdev
->cqp
.lock
);
983 init_waitqueue_head(&nesdev
->cqp
.waitq
);
985 /* Setup Various Structures */
986 vmem
= (void *)(((unsigned long)nesdev
->cqp_vbase
+ (512 - 1)) &
987 ~(unsigned long)(512 - 1));
988 pmem
= (dma_addr_t
)(((unsigned long long)nesdev
->cqp_pbase
+ (512 - 1)) &
989 ~(unsigned long long)(512 - 1));
991 nesdev
->cqp
.sq_vbase
= vmem
;
992 nesdev
->cqp
.sq_pbase
= pmem
;
993 nesdev
->cqp
.sq_size
= NES_CQP_SQ_SIZE
;
994 nesdev
->cqp
.sq_head
= 0;
995 nesdev
->cqp
.sq_tail
= 0;
996 nesdev
->cqp
.qp_id
= PCI_FUNC(nesdev
->pcidev
->devfn
);
998 vmem
+= (sizeof(struct nes_hw_cqp_wqe
) * nesdev
->cqp
.sq_size
);
999 pmem
+= (sizeof(struct nes_hw_cqp_wqe
) * nesdev
->cqp
.sq_size
);
1001 nesdev
->ccq
.cq_vbase
= vmem
;
1002 nesdev
->ccq
.cq_pbase
= pmem
;
1003 nesdev
->ccq
.cq_size
= NES_CCQ_SIZE
;
1004 nesdev
->ccq
.cq_head
= 0;
1005 nesdev
->ccq
.ce_handler
= nes_cqp_ce_handler
;
1006 nesdev
->ccq
.cq_number
= PCI_FUNC(nesdev
->pcidev
->devfn
);
1008 vmem
+= (sizeof(struct nes_hw_cqe
) * nesdev
->ccq
.cq_size
);
1009 pmem
+= (sizeof(struct nes_hw_cqe
) * nesdev
->ccq
.cq_size
);
1011 nesdev
->ceq_index
= PCI_FUNC(nesdev
->pcidev
->devfn
);
1012 ceq
= &nesadapter
->ceq
[nesdev
->ceq_index
];
1013 ceq
->ceq_vbase
= vmem
;
1014 ceq
->ceq_pbase
= pmem
;
1015 ceq
->ceq_size
= NES_CCEQ_SIZE
;
1018 vmem
+= max(((u32
)sizeof(struct nes_hw_ceqe
) * ceq
->ceq_size
), (u32
)256);
1019 pmem
+= max(((u32
)sizeof(struct nes_hw_ceqe
) * ceq
->ceq_size
), (u32
)256);
1021 nesdev
->nic_ceq_index
= PCI_FUNC(nesdev
->pcidev
->devfn
) + 8;
1022 nic_ceq
= &nesadapter
->ceq
[nesdev
->nic_ceq_index
];
1023 nic_ceq
->ceq_vbase
= vmem
;
1024 nic_ceq
->ceq_pbase
= pmem
;
1025 nic_ceq
->ceq_size
= NES_NIC_CEQ_SIZE
;
1026 nic_ceq
->ceq_head
= 0;
1028 vmem
+= max(((u32
)sizeof(struct nes_hw_ceqe
) * nic_ceq
->ceq_size
), (u32
)256);
1029 pmem
+= max(((u32
)sizeof(struct nes_hw_ceqe
) * nic_ceq
->ceq_size
), (u32
)256);
1031 aeq
= &nesadapter
->aeq
[PCI_FUNC(nesdev
->pcidev
->devfn
)];
1032 aeq
->aeq_vbase
= vmem
;
1033 aeq
->aeq_pbase
= pmem
;
1034 aeq
->aeq_size
= nesadapter
->max_qp
;
1037 /* Setup QP Context */
1038 vmem
+= (sizeof(struct nes_hw_aeqe
) * aeq
->aeq_size
);
1039 pmem
+= (sizeof(struct nes_hw_aeqe
) * aeq
->aeq_size
);
1041 cqp_qp_context
= vmem
;
1042 cqp_qp_context
->context_words
[0] =
1043 cpu_to_le32((PCI_FUNC(nesdev
->pcidev
->devfn
) << 12) + (2 << 10));
1044 cqp_qp_context
->context_words
[1] = 0;
1045 cqp_qp_context
->context_words
[2] = cpu_to_le32((u32
)nesdev
->cqp
.sq_pbase
);
1046 cqp_qp_context
->context_words
[3] = cpu_to_le32(((u64
)nesdev
->cqp
.sq_pbase
) >> 32);
1049 /* Write the address to Create CQP */
1050 if ((sizeof(dma_addr_t
) > 4)) {
1051 nes_write_indexed(nesdev
,
1052 NES_IDX_CREATE_CQP_HIGH
+ (PCI_FUNC(nesdev
->pcidev
->devfn
) * 8),
1055 nes_write_indexed(nesdev
,
1056 NES_IDX_CREATE_CQP_HIGH
+ (PCI_FUNC(nesdev
->pcidev
->devfn
) * 8), 0);
1058 nes_write_indexed(nesdev
,
1059 NES_IDX_CREATE_CQP_LOW
+ (PCI_FUNC(nesdev
->pcidev
->devfn
) * 8),
1062 INIT_LIST_HEAD(&nesdev
->cqp_avail_reqs
);
1063 INIT_LIST_HEAD(&nesdev
->cqp_pending_reqs
);
1065 for (count
= 0; count
< 2*NES_CQP_SQ_SIZE
; count
++) {
1066 init_waitqueue_head(&nesdev
->nes_cqp_requests
[count
].waitq
);
1067 list_add_tail(&nesdev
->nes_cqp_requests
[count
].list
, &nesdev
->cqp_avail_reqs
);
1070 /* Write Create CCQ WQE */
1071 cqp_head
= nesdev
->cqp
.sq_head
++;
1072 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1073 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1074 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
,
1075 (NES_CQP_CREATE_CQ
| NES_CQP_CQ_CEQ_VALID
|
1076 NES_CQP_CQ_CHK_OVERFLOW
| ((u32
)nesdev
->ccq
.cq_size
<< 16)));
1077 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_ID_IDX
,
1078 (nesdev
->ccq
.cq_number
|
1079 ((u32
)nesdev
->ceq_index
<< 16)));
1080 u64temp
= (u64
)nesdev
->ccq
.cq_pbase
;
1081 set_wqe_64bit_value(cqp_wqe
->wqe_words
, NES_CQP_CQ_WQE_PBL_LOW_IDX
, u64temp
);
1082 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX
] = 0;
1083 u64temp
= (unsigned long)&nesdev
->ccq
;
1084 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX
] =
1085 cpu_to_le32((u32
)(u64temp
>> 1));
1086 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX
] =
1087 cpu_to_le32(((u32
)((u64temp
) >> 33)) & 0x7FFFFFFF);
1088 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX
] = 0;
1090 /* Write Create CEQ WQE */
1091 cqp_head
= nesdev
->cqp
.sq_head
++;
1092 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1093 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1094 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
,
1095 (NES_CQP_CREATE_CEQ
+ ((u32
)nesdev
->ceq_index
<< 8)));
1096 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX
, ceq
->ceq_size
);
1097 u64temp
= (u64
)ceq
->ceq_pbase
;
1098 set_wqe_64bit_value(cqp_wqe
->wqe_words
, NES_CQP_CQ_WQE_PBL_LOW_IDX
, u64temp
);
1100 /* Write Create AEQ WQE */
1101 cqp_head
= nesdev
->cqp
.sq_head
++;
1102 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1103 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1104 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
,
1105 (NES_CQP_CREATE_AEQ
+ ((u32
)PCI_FUNC(nesdev
->pcidev
->devfn
) << 8)));
1106 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX
, aeq
->aeq_size
);
1107 u64temp
= (u64
)aeq
->aeq_pbase
;
1108 set_wqe_64bit_value(cqp_wqe
->wqe_words
, NES_CQP_CQ_WQE_PBL_LOW_IDX
, u64temp
);
1110 /* Write Create NIC CEQ WQE */
1111 cqp_head
= nesdev
->cqp
.sq_head
++;
1112 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1113 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1114 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
,
1115 (NES_CQP_CREATE_CEQ
+ ((u32
)nesdev
->nic_ceq_index
<< 8)));
1116 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX
, nic_ceq
->ceq_size
);
1117 u64temp
= (u64
)nic_ceq
->ceq_pbase
;
1118 set_wqe_64bit_value(cqp_wqe
->wqe_words
, NES_CQP_CQ_WQE_PBL_LOW_IDX
, u64temp
);
1120 /* Poll until CCQP done */
1123 if (count
++ > 1000) {
1124 printk(KERN_ERR PFX
"Error creating CQP\n");
1125 pci_free_consistent(nesdev
->pcidev
, nesdev
->cqp_mem_size
,
1126 nesdev
->cqp_vbase
, nesdev
->cqp_pbase
);
1130 } while (!(nes_read_indexed(nesdev
,
1131 NES_IDX_QP_CONTROL
+ (PCI_FUNC(nesdev
->pcidev
->devfn
) * 8)) & (1 << 8)));
1133 nes_debug(NES_DBG_INIT
, "CQP Status = 0x%08X\n", nes_read_indexed(nesdev
,
1134 NES_IDX_QP_CONTROL
+(PCI_FUNC(nesdev
->pcidev
->devfn
)*8)));
1136 u32temp
= 0x04800000;
1137 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, u32temp
| nesdev
->cqp
.qp_id
);
1139 /* wait for the CCQ, CEQ, and AEQ to get created */
1142 if (count
++ > 1000) {
1143 printk(KERN_ERR PFX
"Error creating CCQ, CEQ, and AEQ\n");
1144 pci_free_consistent(nesdev
->pcidev
, nesdev
->cqp_mem_size
,
1145 nesdev
->cqp_vbase
, nesdev
->cqp_pbase
);
1149 } while (((nes_read_indexed(nesdev
,
1150 NES_IDX_QP_CONTROL
+(PCI_FUNC(nesdev
->pcidev
->devfn
)*8)) & (15<<8)) != (15<<8)));
1152 /* dump the QP status value */
1153 nes_debug(NES_DBG_INIT
, "QP Status = 0x%08X\n", nes_read_indexed(nesdev
,
1154 NES_IDX_QP_CONTROL
+(PCI_FUNC(nesdev
->pcidev
->devfn
)*8)));
1156 nesdev
->cqp
.sq_tail
++;
1165 int nes_destroy_cqp(struct nes_device
*nesdev
)
1167 struct nes_hw_cqp_wqe
*cqp_wqe
;
1170 unsigned long flags
;
1176 } while (!(nesdev
->cqp
.sq_head
== nesdev
->cqp
.sq_tail
));
1179 nes_write32(nesdev
->regs
+NES_CQE_ALLOC
, NES_CQE_ALLOC_RESET
|
1180 nesdev
->ccq
.cq_number
);
1182 /* Disable device interrupts */
1183 nes_write32(nesdev
->regs
+NES_INT_MASK
, 0x7fffffff);
1185 spin_lock_irqsave(&nesdev
->cqp
.lock
, flags
);
1187 /* Destroy the AEQ */
1188 cqp_head
= nesdev
->cqp
.sq_head
++;
1189 nesdev
->cqp
.sq_head
&= nesdev
->cqp
.sq_size
-1;
1190 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1191 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(NES_CQP_DESTROY_AEQ
|
1192 ((u32
)PCI_FUNC(nesdev
->pcidev
->devfn
) << 8));
1193 cqp_wqe
->wqe_words
[NES_CQP_WQE_COMP_CTX_HIGH_IDX
] = 0;
1195 /* Destroy the NIC CEQ */
1196 cqp_head
= nesdev
->cqp
.sq_head
++;
1197 nesdev
->cqp
.sq_head
&= nesdev
->cqp
.sq_size
-1;
1198 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1199 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(NES_CQP_DESTROY_CEQ
|
1200 ((u32
)nesdev
->nic_ceq_index
<< 8));
1202 /* Destroy the CEQ */
1203 cqp_head
= nesdev
->cqp
.sq_head
++;
1204 nesdev
->cqp
.sq_head
&= nesdev
->cqp
.sq_size
-1;
1205 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1206 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(NES_CQP_DESTROY_CEQ
|
1207 (nesdev
->ceq_index
<< 8));
1209 /* Destroy the CCQ */
1210 cqp_head
= nesdev
->cqp
.sq_head
++;
1211 nesdev
->cqp
.sq_head
&= nesdev
->cqp
.sq_size
-1;
1212 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1213 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(NES_CQP_DESTROY_CQ
);
1214 cqp_wqe
->wqe_words
[NES_CQP_WQE_ID_IDX
] = cpu_to_le32(nesdev
->ccq
.cq_number
|
1215 ((u32
)nesdev
->ceq_index
<< 16));
1218 cqp_head
= nesdev
->cqp
.sq_head
++;
1219 nesdev
->cqp
.sq_head
&= nesdev
->cqp
.sq_size
-1;
1220 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1221 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(NES_CQP_DESTROY_QP
|
1222 NES_CQP_QP_TYPE_CQP
);
1223 cqp_wqe
->wqe_words
[NES_CQP_WQE_ID_IDX
] = cpu_to_le32(nesdev
->cqp
.qp_id
);
1226 /* Ring doorbell (5 WQEs) */
1227 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, 0x05800000 | nesdev
->cqp
.qp_id
);
1229 spin_unlock_irqrestore(&nesdev
->cqp
.lock
, flags
);
1231 /* wait for the CCQ, CEQ, and AEQ to get destroyed */
1234 if (count
++ > 1000) {
1235 printk(KERN_ERR PFX
"Function%d: Error destroying CCQ, CEQ, and AEQ\n",
1236 PCI_FUNC(nesdev
->pcidev
->devfn
));
1240 } while (((nes_read_indexed(nesdev
,
1241 NES_IDX_QP_CONTROL
+ (PCI_FUNC(nesdev
->pcidev
->devfn
)*8)) & (15 << 8)) != 0));
1243 /* dump the QP status value */
1244 nes_debug(NES_DBG_SHUTDOWN
, "Function%d: QP Status = 0x%08X\n",
1245 PCI_FUNC(nesdev
->pcidev
->devfn
),
1246 nes_read_indexed(nesdev
,
1247 NES_IDX_QP_CONTROL
+(PCI_FUNC(nesdev
->pcidev
->devfn
)*8)));
1249 kfree(nesdev
->nes_cqp_requests
);
1251 /* Free the control structures */
1252 pci_free_consistent(nesdev
->pcidev
, nesdev
->cqp_mem_size
, nesdev
->cqp
.sq_vbase
,
1253 nesdev
->cqp
.sq_pbase
);
1262 int nes_init_phy(struct nes_device
*nesdev
)
1264 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
1267 u32 mac_index
= nesdev
->mac_index
;
1270 u32 temp_phy_data
= 0;
1271 u32 temp_phy_data2
= 0;
1272 u8 phy_type
= nesadapter
->phy_type
[mac_index
];
1273 u8 phy_index
= nesadapter
->phy_index
[mac_index
];
1275 if ((nesadapter
->OneG_Mode
) &&
1276 (phy_type
!= NES_PHY_TYPE_PUMA_1G
)) {
1277 nes_debug(NES_DBG_PHY
, "1G PHY, mac_index = %d.\n", mac_index
);
1278 if (phy_type
== NES_PHY_TYPE_1G
) {
1279 tx_config
= nes_read_indexed(nesdev
, NES_IDX_MAC_TX_CONFIG
);
1280 tx_config
&= 0xFFFFFFE3;
1282 nes_write_indexed(nesdev
, NES_IDX_MAC_TX_CONFIG
, tx_config
);
1285 nes_read_1G_phy_reg(nesdev
, 1, phy_index
, &phy_data
);
1286 nes_write_1G_phy_reg(nesdev
, 23, phy_index
, 0xb000);
1289 nes_write_1G_phy_reg(nesdev
, 0, phy_index
, 0x8000);
1293 nes_read_1G_phy_reg(nesdev
, 0, phy_index
, &phy_data
);
1294 if (counter
++ > 100)
1296 } while (phy_data
& 0x8000);
1298 /* Setting no phy loopback */
1301 nes_write_1G_phy_reg(nesdev
, 0, phy_index
, phy_data
);
1302 nes_read_1G_phy_reg(nesdev
, 0, phy_index
, &phy_data
);
1303 nes_read_1G_phy_reg(nesdev
, 0x17, phy_index
, &phy_data
);
1304 nes_read_1G_phy_reg(nesdev
, 0x1e, phy_index
, &phy_data
);
1306 /* Setting the interrupt mask */
1307 nes_read_1G_phy_reg(nesdev
, 0x19, phy_index
, &phy_data
);
1308 nes_write_1G_phy_reg(nesdev
, 0x19, phy_index
, 0xffee);
1309 nes_read_1G_phy_reg(nesdev
, 0x19, phy_index
, &phy_data
);
1311 /* turning on flow control */
1312 nes_read_1G_phy_reg(nesdev
, 4, phy_index
, &phy_data
);
1313 nes_write_1G_phy_reg(nesdev
, 4, phy_index
, (phy_data
& ~(0x03E0)) | 0xc00);
1314 nes_read_1G_phy_reg(nesdev
, 4, phy_index
, &phy_data
);
1316 /* Clear Half duplex */
1317 nes_read_1G_phy_reg(nesdev
, 9, phy_index
, &phy_data
);
1318 nes_write_1G_phy_reg(nesdev
, 9, phy_index
, phy_data
& ~(0x0100));
1319 nes_read_1G_phy_reg(nesdev
, 9, phy_index
, &phy_data
);
1321 nes_read_1G_phy_reg(nesdev
, 0, phy_index
, &phy_data
);
1322 nes_write_1G_phy_reg(nesdev
, 0, phy_index
, phy_data
| 0x0300);
1327 if ((phy_type
== NES_PHY_TYPE_IRIS
) ||
1328 (phy_type
== NES_PHY_TYPE_ARGUS
)) {
1329 /* setup 10G MDIO operation */
1330 tx_config
= nes_read_indexed(nesdev
, NES_IDX_MAC_TX_CONFIG
);
1331 tx_config
&= 0xFFFFFFE3;
1333 nes_write_indexed(nesdev
, NES_IDX_MAC_TX_CONFIG
, tx_config
);
1335 if ((phy_type
== NES_PHY_TYPE_ARGUS
)) {
1336 /* Check firmware heartbeat */
1337 nes_read_10G_phy_reg(nesdev
, phy_index
, 0x3, 0xd7ee);
1338 temp_phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
1340 nes_read_10G_phy_reg(nesdev
, phy_index
, 0x3, 0xd7ee);
1341 temp_phy_data2
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
1343 if (temp_phy_data
!= temp_phy_data2
)
1346 /* no heartbeat, configure the PHY */
1347 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0x0000, 0x8000);
1348 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc300, 0x0000);
1349 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc302, 0x000C);
1350 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc316, 0x000A);
1351 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc318, 0x0052);
1352 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc319, 0x0008);
1353 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc31a, 0x0098);
1354 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0x0026, 0x0E00);
1355 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0x0027, 0x0001);
1358 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd006, 0x0007);
1359 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd007, 0x000A);
1360 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd008, 0x0009);
1362 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0x0028, 0xA528);
1364 /* Bring PHY out of reset */
1365 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc300, 0x0002);
1367 /* Check for heartbeat */
1370 nes_read_10G_phy_reg(nesdev
, phy_index
, 0x3, 0xd7ee);
1371 temp_phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
1373 if (counter
++ > 150) {
1374 nes_debug(NES_DBG_PHY
, "No PHY heartbeat\n");
1378 nes_read_10G_phy_reg(nesdev
, phy_index
, 0x3, 0xd7ee);
1379 temp_phy_data2
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
1380 } while ((temp_phy_data2
== temp_phy_data
));
1382 /* wait for tracking */
1385 nes_read_10G_phy_reg(nesdev
, phy_index
, 0x3, 0xd7fd);
1386 temp_phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
1387 if (counter
++ > 300) {
1388 nes_debug(NES_DBG_PHY
, "PHY did not track\n");
1392 } while (((temp_phy_data
& 0xff) != 0x50) && ((temp_phy_data
& 0xff) != 0x70));
1394 /* setup signal integrity */
1395 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd003, 0x0000);
1396 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xF00D, 0x00FE);
1397 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xF00E, 0x0032);
1398 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xF00F, 0x0002);
1399 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc314, 0x0063);
1402 sds
= nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL0
+
1405 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL0
+
1406 mac_index
* 0x200, sds
);
1408 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL0
+
1409 mac_index
* 0x200, sds
);
1412 while (((nes_read32(nesdev
->regs
+ NES_SOFTWARE_RESET
) & 0x00000040) != 0x00000040)
1413 && (counter
++ < 5000))
1421 * nes_replenish_nic_rq
1423 static void nes_replenish_nic_rq(struct nes_vnic
*nesvnic
)
1425 unsigned long flags
;
1426 dma_addr_t bus_address
;
1427 struct sk_buff
*skb
;
1428 struct nes_hw_nic_rq_wqe
*nic_rqe
;
1429 struct nes_hw_nic
*nesnic
;
1430 struct nes_device
*nesdev
;
1431 u32 rx_wqes_posted
= 0;
1433 nesnic
= &nesvnic
->nic
;
1434 nesdev
= nesvnic
->nesdev
;
1435 spin_lock_irqsave(&nesnic
->rq_lock
, flags
);
1436 if (nesnic
->replenishing_rq
!=0) {
1437 if (((nesnic
->rq_size
-1) == atomic_read(&nesvnic
->rx_skbs_needed
)) &&
1438 (atomic_read(&nesvnic
->rx_skb_timer_running
) == 0)) {
1439 atomic_set(&nesvnic
->rx_skb_timer_running
, 1);
1440 spin_unlock_irqrestore(&nesnic
->rq_lock
, flags
);
1441 nesvnic
->rq_wqes_timer
.expires
= jiffies
+ (HZ
/2); /* 1/2 second */
1442 add_timer(&nesvnic
->rq_wqes_timer
);
1444 spin_unlock_irqrestore(&nesnic
->rq_lock
, flags
);
1447 nesnic
->replenishing_rq
= 1;
1448 spin_unlock_irqrestore(&nesnic
->rq_lock
, flags
);
1450 skb
= dev_alloc_skb(nesvnic
->max_frame_size
);
1452 skb
->dev
= nesvnic
->netdev
;
1454 bus_address
= pci_map_single(nesdev
->pcidev
,
1455 skb
->data
, nesvnic
->max_frame_size
, PCI_DMA_FROMDEVICE
);
1457 nic_rqe
= &nesnic
->rq_vbase
[nesvnic
->nic
.rq_head
];
1458 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_LENGTH_1_0_IDX
] =
1459 cpu_to_le32(nesvnic
->max_frame_size
);
1460 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_LENGTH_3_2_IDX
] = 0;
1461 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_LOW_IDX
] =
1462 cpu_to_le32((u32
)bus_address
);
1463 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX
] =
1464 cpu_to_le32((u32
)((u64
)bus_address
>> 32));
1465 nesnic
->rx_skb
[nesnic
->rq_head
] = skb
;
1467 nesnic
->rq_head
&= nesnic
->rq_size
- 1;
1468 atomic_dec(&nesvnic
->rx_skbs_needed
);
1470 if (++rx_wqes_posted
== 255) {
1471 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, (rx_wqes_posted
<< 24) | nesnic
->qp_id
);
1475 spin_lock_irqsave(&nesnic
->rq_lock
, flags
);
1476 if (((nesnic
->rq_size
-1) == atomic_read(&nesvnic
->rx_skbs_needed
)) &&
1477 (atomic_read(&nesvnic
->rx_skb_timer_running
) == 0)) {
1478 atomic_set(&nesvnic
->rx_skb_timer_running
, 1);
1479 spin_unlock_irqrestore(&nesnic
->rq_lock
, flags
);
1480 nesvnic
->rq_wqes_timer
.expires
= jiffies
+ (HZ
/2); /* 1/2 second */
1481 add_timer(&nesvnic
->rq_wqes_timer
);
1483 spin_unlock_irqrestore(&nesnic
->rq_lock
, flags
);
1486 } while (atomic_read(&nesvnic
->rx_skbs_needed
));
1489 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, (rx_wqes_posted
<< 24) | nesnic
->qp_id
);
1490 nesnic
->replenishing_rq
= 0;
1495 * nes_rq_wqes_timeout
1497 static void nes_rq_wqes_timeout(unsigned long parm
)
1499 struct nes_vnic
*nesvnic
= (struct nes_vnic
*)parm
;
1500 printk("%s: Timer fired.\n", __func__
);
1501 atomic_set(&nesvnic
->rx_skb_timer_running
, 0);
1502 if (atomic_read(&nesvnic
->rx_skbs_needed
))
1503 nes_replenish_nic_rq(nesvnic
);
1507 static int nes_lro_get_skb_hdr(struct sk_buff
*skb
, void **iphdr
,
1508 void **tcph
, u64
*hdr_flags
, void *priv
)
1510 unsigned int ip_len
;
1512 skb_reset_network_header(skb
);
1514 if (iph
->protocol
!= IPPROTO_TCP
)
1516 ip_len
= ip_hdrlen(skb
);
1517 skb_set_transport_header(skb
, ip_len
);
1518 *tcph
= tcp_hdr(skb
);
1520 *hdr_flags
= LRO_IPV4
| LRO_TCP
;
1529 int nes_init_nic_qp(struct nes_device
*nesdev
, struct net_device
*netdev
)
1531 struct nes_hw_cqp_wqe
*cqp_wqe
;
1532 struct nes_hw_nic_sq_wqe
*nic_sqe
;
1533 struct nes_hw_nic_qp_context
*nic_context
;
1534 struct sk_buff
*skb
;
1535 struct nes_hw_nic_rq_wqe
*nic_rqe
;
1536 struct nes_vnic
*nesvnic
= netdev_priv(netdev
);
1537 unsigned long flags
;
1547 /* Allocate fragment, SQ, RQ, and CQ; Reuse CEQ based on the PCI function */
1548 nesvnic
->nic_mem_size
= 256 +
1549 (NES_NIC_WQ_SIZE
* sizeof(struct nes_first_frag
)) +
1550 (NES_NIC_WQ_SIZE
* sizeof(struct nes_hw_nic_sq_wqe
)) +
1551 (NES_NIC_WQ_SIZE
* sizeof(struct nes_hw_nic_rq_wqe
)) +
1552 (NES_NIC_WQ_SIZE
* 2 * sizeof(struct nes_hw_nic_cqe
)) +
1553 sizeof(struct nes_hw_nic_qp_context
);
1555 nesvnic
->nic_vbase
= pci_alloc_consistent(nesdev
->pcidev
, nesvnic
->nic_mem_size
,
1556 &nesvnic
->nic_pbase
);
1557 if (!nesvnic
->nic_vbase
) {
1558 nes_debug(NES_DBG_INIT
, "Unable to allocate memory for NIC host descriptor rings\n");
1561 memset(nesvnic
->nic_vbase
, 0, nesvnic
->nic_mem_size
);
1562 nes_debug(NES_DBG_INIT
, "Allocated NIC QP structures at %p (phys = %016lX), size = %u.\n",
1563 nesvnic
->nic_vbase
, (unsigned long)nesvnic
->nic_pbase
, nesvnic
->nic_mem_size
);
1565 vmem
= (void *)(((unsigned long)nesvnic
->nic_vbase
+ (256 - 1)) &
1566 ~(unsigned long)(256 - 1));
1567 pmem
= (dma_addr_t
)(((unsigned long long)nesvnic
->nic_pbase
+ (256 - 1)) &
1568 ~(unsigned long long)(256 - 1));
1570 /* Setup the first Fragment buffers */
1571 nesvnic
->nic
.first_frag_vbase
= vmem
;
1573 for (counter
= 0; counter
< NES_NIC_WQ_SIZE
; counter
++) {
1574 nesvnic
->nic
.frag_paddr
[counter
] = pmem
;
1575 pmem
+= sizeof(struct nes_first_frag
);
1579 vmem
+= (NES_NIC_WQ_SIZE
* sizeof(struct nes_first_frag
));
1581 nesvnic
->nic
.sq_vbase
= (void *)vmem
;
1582 nesvnic
->nic
.sq_pbase
= pmem
;
1583 nesvnic
->nic
.sq_head
= 0;
1584 nesvnic
->nic
.sq_tail
= 0;
1585 nesvnic
->nic
.sq_size
= NES_NIC_WQ_SIZE
;
1586 for (counter
= 0; counter
< NES_NIC_WQ_SIZE
; counter
++) {
1587 nic_sqe
= &nesvnic
->nic
.sq_vbase
[counter
];
1588 nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_MISC_IDX
] =
1589 cpu_to_le32(NES_NIC_SQ_WQE_DISABLE_CHKSUM
|
1590 NES_NIC_SQ_WQE_COMPLETION
);
1591 nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX
] =
1592 cpu_to_le32((u32
)NES_FIRST_FRAG_SIZE
<< 16);
1593 nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_LOW_IDX
] =
1594 cpu_to_le32((u32
)nesvnic
->nic
.frag_paddr
[counter
]);
1595 nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
] =
1596 cpu_to_le32((u32
)((u64
)nesvnic
->nic
.frag_paddr
[counter
] >> 32));
1599 nesvnic
->get_cqp_request
= nes_get_cqp_request
;
1600 nesvnic
->post_cqp_request
= nes_post_cqp_request
;
1601 nesvnic
->mcrq_mcast_filter
= NULL
;
1603 spin_lock_init(&nesvnic
->nic
.rq_lock
);
1606 vmem
+= (NES_NIC_WQ_SIZE
* sizeof(struct nes_hw_nic_sq_wqe
));
1607 pmem
+= (NES_NIC_WQ_SIZE
* sizeof(struct nes_hw_nic_sq_wqe
));
1610 nesvnic
->nic
.rq_vbase
= vmem
;
1611 nesvnic
->nic
.rq_pbase
= pmem
;
1612 nesvnic
->nic
.rq_head
= 0;
1613 nesvnic
->nic
.rq_tail
= 0;
1614 nesvnic
->nic
.rq_size
= NES_NIC_WQ_SIZE
;
1617 vmem
+= (NES_NIC_WQ_SIZE
* sizeof(struct nes_hw_nic_rq_wqe
));
1618 pmem
+= (NES_NIC_WQ_SIZE
* sizeof(struct nes_hw_nic_rq_wqe
));
1620 if (nesdev
->nesadapter
->netdev_count
> 2)
1621 nesvnic
->mcrq_qp_id
= nesvnic
->nic_index
+ 32;
1623 nesvnic
->mcrq_qp_id
= nesvnic
->nic
.qp_id
+ 4;
1625 nesvnic
->nic_cq
.cq_vbase
= vmem
;
1626 nesvnic
->nic_cq
.cq_pbase
= pmem
;
1627 nesvnic
->nic_cq
.cq_head
= 0;
1628 nesvnic
->nic_cq
.cq_size
= NES_NIC_WQ_SIZE
* 2;
1630 nesvnic
->nic_cq
.ce_handler
= nes_nic_napi_ce_handler
;
1632 /* Send CreateCQ request to CQP */
1633 spin_lock_irqsave(&nesdev
->cqp
.lock
, flags
);
1634 cqp_head
= nesdev
->cqp
.sq_head
;
1636 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1637 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1639 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(
1640 NES_CQP_CREATE_CQ
| NES_CQP_CQ_CEQ_VALID
|
1641 ((u32
)nesvnic
->nic_cq
.cq_size
<< 16));
1642 cqp_wqe
->wqe_words
[NES_CQP_WQE_ID_IDX
] = cpu_to_le32(
1643 nesvnic
->nic_cq
.cq_number
| ((u32
)nesdev
->nic_ceq_index
<< 16));
1644 u64temp
= (u64
)nesvnic
->nic_cq
.cq_pbase
;
1645 set_wqe_64bit_value(cqp_wqe
->wqe_words
, NES_CQP_CQ_WQE_PBL_LOW_IDX
, u64temp
);
1646 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX
] = 0;
1647 u64temp
= (unsigned long)&nesvnic
->nic_cq
;
1648 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX
] = cpu_to_le32((u32
)(u64temp
>> 1));
1649 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX
] =
1650 cpu_to_le32(((u32
)((u64temp
) >> 33)) & 0x7FFFFFFF);
1651 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX
] = 0;
1652 if (++cqp_head
>= nesdev
->cqp
.sq_size
)
1654 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1655 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1657 /* Send CreateQP request to CQP */
1658 nic_context
= (void *)(&nesvnic
->nic_cq
.cq_vbase
[nesvnic
->nic_cq
.cq_size
]);
1659 nic_context
->context_words
[NES_NIC_CTX_MISC_IDX
] =
1660 cpu_to_le32((u32
)NES_NIC_CTX_SIZE
|
1661 ((u32
)PCI_FUNC(nesdev
->pcidev
->devfn
) << 12));
1662 nes_debug(NES_DBG_INIT
, "RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x%08X, RX_WINDOW_BUFFER_SIZE = 0x%08X\n",
1663 nes_read_indexed(nesdev
, NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE
),
1664 nes_read_indexed(nesdev
, NES_IDX_RX_WINDOW_BUFFER_SIZE
));
1665 if (nes_read_indexed(nesdev
, NES_IDX_RX_WINDOW_BUFFER_SIZE
) != 0) {
1666 nic_context
->context_words
[NES_NIC_CTX_MISC_IDX
] |= cpu_to_le32(NES_NIC_BACK_STORE
);
1669 u64temp
= (u64
)nesvnic
->nic
.sq_pbase
;
1670 nic_context
->context_words
[NES_NIC_CTX_SQ_LOW_IDX
] = cpu_to_le32((u32
)u64temp
);
1671 nic_context
->context_words
[NES_NIC_CTX_SQ_HIGH_IDX
] = cpu_to_le32((u32
)(u64temp
>> 32));
1672 u64temp
= (u64
)nesvnic
->nic
.rq_pbase
;
1673 nic_context
->context_words
[NES_NIC_CTX_RQ_LOW_IDX
] = cpu_to_le32((u32
)u64temp
);
1674 nic_context
->context_words
[NES_NIC_CTX_RQ_HIGH_IDX
] = cpu_to_le32((u32
)(u64temp
>> 32));
1676 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(NES_CQP_CREATE_QP
|
1677 NES_CQP_QP_TYPE_NIC
);
1678 cqp_wqe
->wqe_words
[NES_CQP_WQE_ID_IDX
] = cpu_to_le32(nesvnic
->nic
.qp_id
);
1679 u64temp
= (u64
)nesvnic
->nic_cq
.cq_pbase
+
1680 (nesvnic
->nic_cq
.cq_size
* sizeof(struct nes_hw_nic_cqe
));
1681 set_wqe_64bit_value(cqp_wqe
->wqe_words
, NES_CQP_QP_WQE_CONTEXT_LOW_IDX
, u64temp
);
1683 if (++cqp_head
>= nesdev
->cqp
.sq_size
)
1685 nesdev
->cqp
.sq_head
= cqp_head
;
1689 /* Ring doorbell (2 WQEs) */
1690 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, 0x02800000 | nesdev
->cqp
.qp_id
);
1692 spin_unlock_irqrestore(&nesdev
->cqp
.lock
, flags
);
1693 nes_debug(NES_DBG_INIT
, "Waiting for create NIC QP%u to complete.\n",
1694 nesvnic
->nic
.qp_id
);
1696 ret
= wait_event_timeout(nesdev
->cqp
.waitq
, (nesdev
->cqp
.sq_tail
== cqp_head
),
1698 nes_debug(NES_DBG_INIT
, "Create NIC QP%u completed, wait_event_timeout ret = %u.\n",
1699 nesvnic
->nic
.qp_id
, ret
);
1701 nes_debug(NES_DBG_INIT
, "NIC QP%u create timeout expired\n", nesvnic
->nic
.qp_id
);
1702 pci_free_consistent(nesdev
->pcidev
, nesvnic
->nic_mem_size
, nesvnic
->nic_vbase
,
1703 nesvnic
->nic_pbase
);
1707 /* Populate the RQ */
1708 for (counter
= 0; counter
< (NES_NIC_WQ_SIZE
- 1); counter
++) {
1709 skb
= dev_alloc_skb(nesvnic
->max_frame_size
);
1711 nes_debug(NES_DBG_INIT
, "%s: out of memory for receive skb\n", netdev
->name
);
1713 nes_destroy_nic_qp(nesvnic
);
1719 pmem
= pci_map_single(nesdev
->pcidev
, skb
->data
,
1720 nesvnic
->max_frame_size
, PCI_DMA_FROMDEVICE
);
1722 nic_rqe
= &nesvnic
->nic
.rq_vbase
[counter
];
1723 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_LENGTH_1_0_IDX
] = cpu_to_le32(nesvnic
->max_frame_size
);
1724 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_LENGTH_3_2_IDX
] = 0;
1725 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_LOW_IDX
] = cpu_to_le32((u32
)pmem
);
1726 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX
] = cpu_to_le32((u32
)((u64
)pmem
>> 32));
1727 nesvnic
->nic
.rx_skb
[counter
] = skb
;
1730 wqe_count
= NES_NIC_WQ_SIZE
- 1;
1731 nesvnic
->nic
.rq_head
= wqe_count
;
1734 counter
= min(wqe_count
, ((u32
)255));
1735 wqe_count
-= counter
;
1736 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, (counter
<< 24) | nesvnic
->nic
.qp_id
);
1737 } while (wqe_count
);
1738 init_timer(&nesvnic
->rq_wqes_timer
);
1739 nesvnic
->rq_wqes_timer
.function
= nes_rq_wqes_timeout
;
1740 nesvnic
->rq_wqes_timer
.data
= (unsigned long)nesvnic
;
1741 nes_debug(NES_DBG_INIT
, "NAPI support Enabled\n");
1742 if (nesdev
->nesadapter
->et_use_adaptive_rx_coalesce
)
1744 nes_nic_init_timer(nesdev
);
1745 if (netdev
->mtu
> 1500)
1747 nes_nic_init_timer_defaults(nesdev
, jumbomode
);
1749 nesvnic
->lro_mgr
.max_aggr
= nes_lro_max_aggr
;
1750 nesvnic
->lro_mgr
.max_desc
= NES_MAX_LRO_DESCRIPTORS
;
1751 nesvnic
->lro_mgr
.lro_arr
= nesvnic
->lro_desc
;
1752 nesvnic
->lro_mgr
.get_skb_header
= nes_lro_get_skb_hdr
;
1753 nesvnic
->lro_mgr
.features
= LRO_F_NAPI
| LRO_F_EXTRACT_VLAN_ID
;
1754 nesvnic
->lro_mgr
.dev
= netdev
;
1755 nesvnic
->lro_mgr
.ip_summed
= CHECKSUM_UNNECESSARY
;
1756 nesvnic
->lro_mgr
.ip_summed_aggr
= CHECKSUM_UNNECESSARY
;
1762 * nes_destroy_nic_qp
1764 void nes_destroy_nic_qp(struct nes_vnic
*nesvnic
)
1767 dma_addr_t bus_address
;
1768 struct nes_device
*nesdev
= nesvnic
->nesdev
;
1769 struct nes_hw_cqp_wqe
*cqp_wqe
;
1770 struct nes_hw_nic_sq_wqe
*nic_sqe
;
1771 struct nes_hw_nic_rq_wqe
*nic_rqe
;
1772 __le16
*wqe_fragment_length
;
1773 u16 wqe_fragment_index
;
1776 unsigned long flags
;
1779 /* Free remaining NIC receive buffers */
1780 while (nesvnic
->nic
.rq_head
!= nesvnic
->nic
.rq_tail
) {
1781 nic_rqe
= &nesvnic
->nic
.rq_vbase
[nesvnic
->nic
.rq_tail
];
1782 wqe_frag
= (u64
)le32_to_cpu(
1783 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_LOW_IDX
]);
1784 wqe_frag
|= ((u64
)le32_to_cpu(
1785 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX
]))<<32;
1786 pci_unmap_single(nesdev
->pcidev
, (dma_addr_t
)wqe_frag
,
1787 nesvnic
->max_frame_size
, PCI_DMA_FROMDEVICE
);
1788 dev_kfree_skb(nesvnic
->nic
.rx_skb
[nesvnic
->nic
.rq_tail
++]);
1789 nesvnic
->nic
.rq_tail
&= (nesvnic
->nic
.rq_size
- 1);
1792 /* Free remaining NIC transmit buffers */
1793 while (nesvnic
->nic
.sq_head
!= nesvnic
->nic
.sq_tail
) {
1794 nic_sqe
= &nesvnic
->nic
.sq_vbase
[nesvnic
->nic
.sq_tail
];
1795 wqe_fragment_index
= 1;
1796 wqe_fragment_length
= (__le16
*)
1797 &nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX
];
1798 /* bump past the vlan tag */
1799 wqe_fragment_length
++;
1800 if (le16_to_cpu(wqe_fragment_length
[wqe_fragment_index
]) != 0) {
1801 u64temp
= (u64
)le32_to_cpu(
1802 nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_LOW_IDX
+
1803 wqe_fragment_index
*2]);
1804 u64temp
+= ((u64
)le32_to_cpu(
1805 nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
1806 + wqe_fragment_index
*2]))<<32;
1807 bus_address
= (dma_addr_t
)u64temp
;
1808 if (test_and_clear_bit(nesvnic
->nic
.sq_tail
,
1809 nesvnic
->nic
.first_frag_overflow
)) {
1810 pci_unmap_single(nesdev
->pcidev
,
1812 le16_to_cpu(wqe_fragment_length
[
1813 wqe_fragment_index
++]),
1816 for (; wqe_fragment_index
< 5; wqe_fragment_index
++) {
1817 if (wqe_fragment_length
[wqe_fragment_index
]) {
1818 u64temp
= le32_to_cpu(
1820 NES_NIC_SQ_WQE_FRAG0_LOW_IDX
+
1821 wqe_fragment_index
*2]);
1822 u64temp
+= ((u64
)le32_to_cpu(
1824 NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
+
1825 wqe_fragment_index
*2]))<<32;
1826 bus_address
= (dma_addr_t
)u64temp
;
1827 pci_unmap_page(nesdev
->pcidev
,
1830 wqe_fragment_length
[
1831 wqe_fragment_index
]),
1837 if (nesvnic
->nic
.tx_skb
[nesvnic
->nic
.sq_tail
])
1839 nesvnic
->nic
.tx_skb
[nesvnic
->nic
.sq_tail
]);
1841 nesvnic
->nic
.sq_tail
= (++nesvnic
->nic
.sq_tail
)
1842 & (nesvnic
->nic
.sq_size
- 1);
1845 spin_lock_irqsave(&nesdev
->cqp
.lock
, flags
);
1847 /* Destroy NIC QP */
1848 cqp_head
= nesdev
->cqp
.sq_head
;
1849 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1850 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1852 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
,
1853 (NES_CQP_DESTROY_QP
| NES_CQP_QP_TYPE_NIC
));
1854 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_ID_IDX
,
1855 nesvnic
->nic
.qp_id
);
1857 if (++cqp_head
>= nesdev
->cqp
.sq_size
)
1860 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1862 /* Destroy NIC CQ */
1863 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1864 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
,
1865 (NES_CQP_DESTROY_CQ
| ((u32
)nesvnic
->nic_cq
.cq_size
<< 16)));
1866 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_ID_IDX
,
1867 (nesvnic
->nic_cq
.cq_number
| ((u32
)nesdev
->nic_ceq_index
<< 16)));
1869 if (++cqp_head
>= nesdev
->cqp
.sq_size
)
1872 nesdev
->cqp
.sq_head
= cqp_head
;
1875 /* Ring doorbell (2 WQEs) */
1876 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, 0x02800000 | nesdev
->cqp
.qp_id
);
1878 spin_unlock_irqrestore(&nesdev
->cqp
.lock
, flags
);
1879 nes_debug(NES_DBG_SHUTDOWN
, "Waiting for CQP, cqp_head=%u, cqp.sq_head=%u,"
1880 " cqp.sq_tail=%u, cqp.sq_size=%u\n",
1881 cqp_head
, nesdev
->cqp
.sq_head
,
1882 nesdev
->cqp
.sq_tail
, nesdev
->cqp
.sq_size
);
1884 ret
= wait_event_timeout(nesdev
->cqp
.waitq
, (nesdev
->cqp
.sq_tail
== cqp_head
),
1887 nes_debug(NES_DBG_SHUTDOWN
, "Destroy NIC QP returned, wait_event_timeout ret = %u, cqp_head=%u,"
1888 " cqp.sq_head=%u, cqp.sq_tail=%u\n",
1889 ret
, cqp_head
, nesdev
->cqp
.sq_head
, nesdev
->cqp
.sq_tail
);
1891 nes_debug(NES_DBG_SHUTDOWN
, "NIC QP%u destroy timeout expired\n",
1892 nesvnic
->nic
.qp_id
);
1895 pci_free_consistent(nesdev
->pcidev
, nesvnic
->nic_mem_size
, nesvnic
->nic_vbase
,
1896 nesvnic
->nic_pbase
);
1902 int nes_napi_isr(struct nes_device
*nesdev
)
1904 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
1907 if (nesdev
->napi_isr_ran
) {
1908 /* interrupt status has already been read in ISR */
1909 int_stat
= nesdev
->int_stat
;
1911 int_stat
= nes_read32(nesdev
->regs
+ NES_INT_STAT
);
1912 nesdev
->int_stat
= int_stat
;
1913 nesdev
->napi_isr_ran
= 1;
1916 int_stat
&= nesdev
->int_req
;
1917 /* iff NIC, process here, else wait for DPC */
1918 if ((int_stat
) && ((int_stat
& 0x0000ff00) == int_stat
)) {
1919 nesdev
->napi_isr_ran
= 0;
1920 nes_write32(nesdev
->regs
+ NES_INT_STAT
,
1922 ~(NES_INT_INTF
| NES_INT_TIMER
| NES_INT_MAC0
| NES_INT_MAC1
| NES_INT_MAC2
| NES_INT_MAC3
)));
1924 /* Process the CEQs */
1925 nes_process_ceq(nesdev
, &nesdev
->nesadapter
->ceq
[nesdev
->nic_ceq_index
]);
1927 if (unlikely((((nesadapter
->et_rx_coalesce_usecs_irq
) &&
1928 (!nesadapter
->et_use_adaptive_rx_coalesce
)) ||
1929 ((nesadapter
->et_use_adaptive_rx_coalesce
) &&
1930 (nesdev
->deepcq_count
> nesadapter
->et_pkt_rate_low
))))) {
1931 if ((nesdev
->int_req
& NES_INT_TIMER
) == 0) {
1932 /* Enable Periodic timer interrupts */
1933 nesdev
->int_req
|= NES_INT_TIMER
;
1934 /* ack any pending periodic timer interrupts so we don't get an immediate interrupt */
1935 /* TODO: need to also ack other unused periodic timer values, get from nesadapter */
1936 nes_write32(nesdev
->regs
+NES_TIMER_STAT
,
1937 nesdev
->timer_int_req
| ~(nesdev
->nesadapter
->timer_int_req
));
1938 nes_write32(nesdev
->regs
+NES_INTF_INT_MASK
,
1939 ~(nesdev
->intf_int_req
| NES_INTF_PERIODIC_TIMER
));
1942 if (unlikely(nesadapter
->et_use_adaptive_rx_coalesce
))
1944 nes_nic_init_timer(nesdev
);
1946 /* Enable interrupts, except CEQs */
1947 nes_write32(nesdev
->regs
+NES_INT_MASK
, 0x0000ffff | (~nesdev
->int_req
));
1949 /* Enable interrupts, make sure timer is off */
1950 nesdev
->int_req
&= ~NES_INT_TIMER
;
1951 nes_write32(nesdev
->regs
+NES_INTF_INT_MASK
, ~(nesdev
->intf_int_req
));
1952 nes_write32(nesdev
->regs
+NES_INT_MASK
, ~nesdev
->int_req
);
1954 nesdev
->deepcq_count
= 0;
1961 static void process_critical_error(struct nes_device
*nesdev
)
1964 u32 nes_idx_debug_error_masks0
= 0;
1965 u16 error_module
= 0;
1967 debug_error
= nes_read_indexed(nesdev
, NES_IDX_DEBUG_ERROR_CONTROL_STATUS
);
1968 printk(KERN_ERR PFX
"Critical Error reported by device!!! 0x%02X\n",
1970 nes_write_indexed(nesdev
, NES_IDX_DEBUG_ERROR_CONTROL_STATUS
,
1971 0x01010000 | (debug_error
& 0x0000ffff));
1972 if (crit_err_count
++ > 10)
1973 nes_write_indexed(nesdev
, NES_IDX_DEBUG_ERROR_MASKS1
, 1 << 0x17);
1974 error_module
= (u16
) (debug_error
& 0x1F00) >> 8;
1975 if (++nesdev
->nesadapter
->crit_error_count
[error_module
-1] >=
1976 nes_max_critical_error_count
) {
1977 printk(KERN_ERR PFX
"Masking off critical error for module "
1978 "0x%02X\n", (u16
)error_module
);
1979 nes_idx_debug_error_masks0
= nes_read_indexed(nesdev
,
1980 NES_IDX_DEBUG_ERROR_MASKS0
);
1981 nes_write_indexed(nesdev
, NES_IDX_DEBUG_ERROR_MASKS0
,
1982 nes_idx_debug_error_masks0
| (1 << error_module
));
1988 void nes_dpc(unsigned long param
)
1990 struct nes_device
*nesdev
= (struct nes_device
*)param
;
1991 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
1993 u32 loop_counter
= 0;
1999 u32 processed_intf_int
= 0;
2000 u16 processed_timer_int
= 0;
2001 u16 completion_ints
= 0;
2004 /* nes_debug(NES_DBG_ISR, "\n"); */
2008 if (nesdev
->napi_isr_ran
) {
2009 nesdev
->napi_isr_ran
= 0;
2010 int_stat
= nesdev
->int_stat
;
2012 int_stat
= nes_read32(nesdev
->regs
+NES_INT_STAT
);
2013 if (processed_intf_int
!= 0)
2014 int_stat
&= nesdev
->int_req
& ~NES_INT_INTF
;
2016 int_stat
&= nesdev
->int_req
;
2017 if (processed_timer_int
== 0) {
2018 processed_timer_int
= 1;
2019 if (int_stat
& NES_INT_TIMER
) {
2020 timer_stat
= nes_read32(nesdev
->regs
+ NES_TIMER_STAT
);
2021 if ((timer_stat
& nesdev
->timer_int_req
) == 0) {
2022 int_stat
&= ~NES_INT_TIMER
;
2026 int_stat
&= ~NES_INT_TIMER
;
2030 if (int_stat
& ~(NES_INT_INTF
| NES_INT_TIMER
| NES_INT_MAC0
|
2031 NES_INT_MAC1
|NES_INT_MAC2
| NES_INT_MAC3
)) {
2032 /* Ack the interrupts */
2033 nes_write32(nesdev
->regs
+NES_INT_STAT
,
2034 (int_stat
& ~(NES_INT_INTF
| NES_INT_TIMER
| NES_INT_MAC0
|
2035 NES_INT_MAC1
| NES_INT_MAC2
| NES_INT_MAC3
)));
2038 temp_int_stat
= int_stat
;
2039 for (counter
= 0, int_status_bit
= 1; counter
< 16; counter
++) {
2040 if (int_stat
& int_status_bit
) {
2041 nes_process_ceq(nesdev
, &nesadapter
->ceq
[counter
]);
2042 temp_int_stat
&= ~int_status_bit
;
2043 completion_ints
= 1;
2045 if (!(temp_int_stat
& 0x0000ffff))
2047 int_status_bit
<<= 1;
2050 /* Process the AEQ for this pci function */
2051 int_status_bit
= 1 << (16 + PCI_FUNC(nesdev
->pcidev
->devfn
));
2052 if (int_stat
& int_status_bit
) {
2053 nes_process_aeq(nesdev
, &nesadapter
->aeq
[PCI_FUNC(nesdev
->pcidev
->devfn
)]);
2056 /* Process the MAC interrupt for this pci function */
2057 int_status_bit
= 1 << (24 + nesdev
->mac_index
);
2058 if (int_stat
& int_status_bit
) {
2059 nes_process_mac_intr(nesdev
, nesdev
->mac_index
);
2062 if (int_stat
& NES_INT_TIMER
) {
2063 if (timer_stat
& nesdev
->timer_int_req
) {
2064 nes_write32(nesdev
->regs
+ NES_TIMER_STAT
,
2065 (timer_stat
& nesdev
->timer_int_req
) |
2066 ~(nesdev
->nesadapter
->timer_int_req
));
2071 if (int_stat
& NES_INT_INTF
) {
2072 processed_intf_int
= 1;
2073 intf_int_stat
= nes_read32(nesdev
->regs
+NES_INTF_INT_STAT
);
2074 intf_int_stat
&= nesdev
->intf_int_req
;
2075 if (NES_INTF_INT_CRITERR
& intf_int_stat
) {
2076 process_critical_error(nesdev
);
2078 if (NES_INTF_INT_PCIERR
& intf_int_stat
) {
2079 printk(KERN_ERR PFX
"PCI Error reported by device!!!\n");
2082 if (NES_INTF_INT_AEQ_OFLOW
& intf_int_stat
) {
2083 printk(KERN_ERR PFX
"AEQ Overflow reported by device!!!\n");
2086 nes_write32(nesdev
->regs
+NES_INTF_INT_STAT
, intf_int_stat
);
2089 if (int_stat
& NES_INT_TSW
) {
2092 /* Don't use the interface interrupt bit stay in loop */
2093 int_stat
&= ~NES_INT_INTF
| NES_INT_TIMER
| NES_INT_MAC0
|
2094 NES_INT_MAC1
| NES_INT_MAC2
| NES_INT_MAC3
;
2095 } while ((int_stat
!= 0) && (loop_counter
++ < MAX_DPC_ITERATIONS
));
2097 if (timer_ints
== 1) {
2098 if ((nesadapter
->et_rx_coalesce_usecs_irq
) || (nesadapter
->et_use_adaptive_rx_coalesce
)) {
2099 if (completion_ints
== 0) {
2100 nesdev
->timer_only_int_count
++;
2101 if (nesdev
->timer_only_int_count
>=nesadapter
->timer_int_limit
) {
2102 nesdev
->timer_only_int_count
= 0;
2103 nesdev
->int_req
&= ~NES_INT_TIMER
;
2104 nes_write32(nesdev
->regs
+ NES_INTF_INT_MASK
, ~(nesdev
->intf_int_req
));
2105 nes_write32(nesdev
->regs
+ NES_INT_MASK
, ~nesdev
->int_req
);
2107 nes_write32(nesdev
->regs
+NES_INT_MASK
, 0x0000ffff | (~nesdev
->int_req
));
2110 if (unlikely(nesadapter
->et_use_adaptive_rx_coalesce
))
2112 nes_nic_init_timer(nesdev
);
2114 nesdev
->timer_only_int_count
= 0;
2115 nes_write32(nesdev
->regs
+NES_INT_MASK
, 0x0000ffff | (~nesdev
->int_req
));
2118 nesdev
->timer_only_int_count
= 0;
2119 nesdev
->int_req
&= ~NES_INT_TIMER
;
2120 nes_write32(nesdev
->regs
+NES_INTF_INT_MASK
, ~(nesdev
->intf_int_req
));
2121 nes_write32(nesdev
->regs
+NES_TIMER_STAT
,
2122 nesdev
->timer_int_req
| ~(nesdev
->nesadapter
->timer_int_req
));
2123 nes_write32(nesdev
->regs
+NES_INT_MASK
, ~nesdev
->int_req
);
2126 if ( (completion_ints
== 1) &&
2127 (((nesadapter
->et_rx_coalesce_usecs_irq
) &&
2128 (!nesadapter
->et_use_adaptive_rx_coalesce
)) ||
2129 ((nesdev
->deepcq_count
> nesadapter
->et_pkt_rate_low
) &&
2130 (nesadapter
->et_use_adaptive_rx_coalesce
) )) ) {
2131 /* nes_debug(NES_DBG_ISR, "Enabling periodic timer interrupt.\n" ); */
2132 nesdev
->timer_only_int_count
= 0;
2133 nesdev
->int_req
|= NES_INT_TIMER
;
2134 nes_write32(nesdev
->regs
+NES_TIMER_STAT
,
2135 nesdev
->timer_int_req
| ~(nesdev
->nesadapter
->timer_int_req
));
2136 nes_write32(nesdev
->regs
+NES_INTF_INT_MASK
,
2137 ~(nesdev
->intf_int_req
| NES_INTF_PERIODIC_TIMER
));
2138 nes_write32(nesdev
->regs
+NES_INT_MASK
, 0x0000ffff | (~nesdev
->int_req
));
2140 nes_write32(nesdev
->regs
+NES_INT_MASK
, ~nesdev
->int_req
);
2143 nesdev
->deepcq_count
= 0;
2150 static void nes_process_ceq(struct nes_device
*nesdev
, struct nes_hw_ceq
*ceq
)
2153 struct nes_hw_cq
*cq
;
2157 /* nes_debug(NES_DBG_CQ, "\n"); */
2158 head
= ceq
->ceq_head
;
2159 ceq_size
= ceq
->ceq_size
;
2162 if (le32_to_cpu(ceq
->ceq_vbase
[head
].ceqe_words
[NES_CEQE_CQ_CTX_HIGH_IDX
]) &
2164 u64temp
= (((u64
)(le32_to_cpu(ceq
->ceq_vbase
[head
].ceqe_words
[NES_CEQE_CQ_CTX_HIGH_IDX
]))) << 32) |
2165 ((u64
)(le32_to_cpu(ceq
->ceq_vbase
[head
].ceqe_words
[NES_CEQE_CQ_CTX_LOW_IDX
])));
2167 cq
= *((struct nes_hw_cq
**)&u64temp
);
2168 /* nes_debug(NES_DBG_CQ, "pCQ = %p\n", cq); */
2170 ceq
->ceq_vbase
[head
].ceqe_words
[NES_CEQE_CQ_CTX_HIGH_IDX
] = 0;
2172 /* call the event handler */
2173 cq
->ce_handler(nesdev
, cq
);
2175 if (++head
>= ceq_size
)
2183 ceq
->ceq_head
= head
;
2190 static void nes_process_aeq(struct nes_device
*nesdev
, struct nes_hw_aeq
*aeq
)
2197 struct nes_hw_aeqe
volatile *aeqe
;
2199 head
= aeq
->aeq_head
;
2200 aeq_size
= aeq
->aeq_size
;
2203 aeqe
= &aeq
->aeq_vbase
[head
];
2204 if ((le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_MISC_IDX
]) & NES_AEQE_VALID
) == 0)
2206 aeqe_misc
= le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_MISC_IDX
]);
2207 aeqe_cq_id
= le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]);
2208 if (aeqe_misc
& (NES_AEQE_QP
|NES_AEQE_CQ
)) {
2209 if (aeqe_cq_id
>= NES_FIRST_QPN
) {
2210 /* dealing with an accelerated QP related AE */
2212 * u64temp = (((u64)(le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_HIGH_IDX]))) << 32) |
2213 * ((u64)(le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_LOW_IDX])));
2215 nes_process_iwarp_aeqe(nesdev
, (struct nes_hw_aeqe
*)aeqe
);
2217 /* TODO: dealing with a CQP related AE */
2218 nes_debug(NES_DBG_AEQ
, "Processing CQP related AE, misc = 0x%04X\n",
2219 (u16
)(aeqe_misc
>> 16));
2223 aeqe
->aeqe_words
[NES_AEQE_MISC_IDX
] = 0;
2225 if (++head
>= aeq_size
)
2228 nes_write32(nesdev
->regs
+ NES_AEQ_ALLOC
, 1 << 16);
2231 aeq
->aeq_head
= head
;
2234 static void nes_reset_link(struct nes_device
*nesdev
, u32 mac_index
)
2236 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
2241 if (nesadapter
->hw_rev
== NE020_REV
) {
2246 reset_value
= nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
);
2248 if ((mac_index
== 0) || ((mac_index
== 1) && (nesadapter
->OneG_Mode
)))
2249 reset_value
|= 0x0000001d;
2251 reset_value
|= 0x0000002d;
2253 if (4 <= (nesadapter
->link_interrupt_count
[mac_index
] / ((u16
)NES_MAX_LINK_INTERRUPTS
))) {
2254 if ((!nesadapter
->OneG_Mode
) && (nesadapter
->port_count
== 2)) {
2255 nesadapter
->link_interrupt_count
[0] = 0;
2256 nesadapter
->link_interrupt_count
[1] = 0;
2257 u32temp
= nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
);
2258 if (0x00000040 & u32temp
)
2259 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, 0x0000F088);
2261 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, 0x0000F0C8);
2263 reset_value
|= 0x0000003d;
2265 nesadapter
->link_interrupt_count
[mac_index
] = 0;
2268 nes_write32(nesdev
->regs
+NES_SOFTWARE_RESET
, reset_value
);
2270 while (((nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
)
2271 & 0x00000040) != 0x00000040) && (i
++ < 5000));
2273 if (0x0000003d == (reset_value
& 0x0000003d)) {
2274 u32 pcs_control_status0
, pcs_control_status1
;
2276 for (i
= 0; i
< 10; i
++) {
2277 pcs_control_status0
= nes_read_indexed(nesdev
, NES_IDX_PHY_PCS_CONTROL_STATUS0
);
2278 pcs_control_status1
= nes_read_indexed(nesdev
, NES_IDX_PHY_PCS_CONTROL_STATUS0
+ 0x200);
2279 if (((0x0F000000 == (pcs_control_status0
& 0x0F000000))
2280 && (pcs_control_status0
& 0x00100000))
2281 || ((0x0F000000 == (pcs_control_status1
& 0x0F000000))
2282 && (pcs_control_status1
& 0x00100000)))
2288 u32temp
= nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
);
2289 if (0x00000040 & u32temp
)
2290 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, 0x0000F088);
2292 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, 0x0000F0C8);
2294 nes_write32(nesdev
->regs
+NES_SOFTWARE_RESET
, reset_value
);
2296 while (((nes_read32(nesdev
->regs
+ NES_SOFTWARE_RESET
)
2297 & 0x00000040) != 0x00000040) && (i
++ < 5000));
2303 * nes_process_mac_intr
2305 static void nes_process_mac_intr(struct nes_device
*nesdev
, u32 mac_number
)
2307 unsigned long flags
;
2308 u32 pcs_control_status
;
2309 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
2310 struct nes_vnic
*nesvnic
;
2312 u32 mac_index
= nesdev
->mac_index
;
2316 u32 pcs_val
= 0x0f0f0000;
2317 u32 pcs_mask
= 0x0f1f0000;
2319 spin_lock_irqsave(&nesadapter
->phy_lock
, flags
);
2320 if (nesadapter
->mac_sw_state
[mac_number
] != NES_MAC_SW_IDLE
) {
2321 spin_unlock_irqrestore(&nesadapter
->phy_lock
, flags
);
2324 nesadapter
->mac_sw_state
[mac_number
] = NES_MAC_SW_INTERRUPT
;
2325 spin_unlock_irqrestore(&nesadapter
->phy_lock
, flags
);
2327 /* ack the MAC interrupt */
2328 mac_status
= nes_read_indexed(nesdev
, NES_IDX_MAC_INT_STATUS
+ (mac_index
* 0x200));
2329 /* Clear the interrupt */
2330 nes_write_indexed(nesdev
, NES_IDX_MAC_INT_STATUS
+ (mac_index
* 0x200), mac_status
);
2332 nes_debug(NES_DBG_PHY
, "MAC%u interrupt status = 0x%X.\n", mac_number
, mac_status
);
2334 if (mac_status
& (NES_MAC_INT_LINK_STAT_CHG
| NES_MAC_INT_XGMII_EXT
)) {
2335 nesdev
->link_status_interrupts
++;
2336 if (0 == (++nesadapter
->link_interrupt_count
[mac_index
] % ((u16
)NES_MAX_LINK_INTERRUPTS
))) {
2337 spin_lock_irqsave(&nesadapter
->phy_lock
, flags
);
2338 nes_reset_link(nesdev
, mac_index
);
2339 spin_unlock_irqrestore(&nesadapter
->phy_lock
, flags
);
2341 /* read the PHY interrupt status register */
2342 if ((nesadapter
->OneG_Mode
) &&
2343 (nesadapter
->phy_type
[mac_index
] != NES_PHY_TYPE_PUMA_1G
)) {
2345 nes_read_1G_phy_reg(nesdev
, 0x1a,
2346 nesadapter
->phy_index
[mac_index
], &phy_data
);
2347 nes_debug(NES_DBG_PHY
, "Phy%d data from register 0x1a = 0x%X.\n",
2348 nesadapter
->phy_index
[mac_index
], phy_data
);
2349 } while (phy_data
&0x8000);
2353 nes_read_1G_phy_reg(nesdev
, 0x11,
2354 nesadapter
->phy_index
[mac_index
], &phy_data
);
2355 nes_debug(NES_DBG_PHY
, "Phy%d data from register 0x11 = 0x%X.\n",
2356 nesadapter
->phy_index
[mac_index
], phy_data
);
2357 if (temp_phy_data
== phy_data
)
2359 temp_phy_data
= phy_data
;
2362 nes_read_1G_phy_reg(nesdev
, 0x1e,
2363 nesadapter
->phy_index
[mac_index
], &phy_data
);
2364 nes_debug(NES_DBG_PHY
, "Phy%d data from register 0x1e = 0x%X.\n",
2365 nesadapter
->phy_index
[mac_index
], phy_data
);
2367 nes_read_1G_phy_reg(nesdev
, 1,
2368 nesadapter
->phy_index
[mac_index
], &phy_data
);
2369 nes_debug(NES_DBG_PHY
, "1G phy%u data from register 1 = 0x%X\n",
2370 nesadapter
->phy_index
[mac_index
], phy_data
);
2372 if (temp_phy_data
& 0x1000) {
2373 nes_debug(NES_DBG_PHY
, "The Link is up according to the PHY\n");
2376 nes_debug(NES_DBG_PHY
, "The Link is down according to the PHY\n");
2379 nes_debug(NES_DBG_PHY
, "Eth SERDES Common Status: 0=0x%08X, 1=0x%08X\n",
2380 nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_STATUS0
),
2381 nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_STATUS0
+0x200));
2383 if (nesadapter
->phy_type
[mac_index
] == NES_PHY_TYPE_PUMA_1G
) {
2384 switch (mac_index
) {
2387 pcs_control_status
= nes_read_indexed(nesdev
,
2388 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ 0x200);
2391 pcs_control_status
= nes_read_indexed(nesdev
,
2392 NES_IDX_PHY_PCS_CONTROL_STATUS0
);
2396 pcs_control_status
= nes_read_indexed(nesdev
,
2397 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ ((mac_index
& 1) * 0x200));
2398 pcs_control_status
= nes_read_indexed(nesdev
,
2399 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ ((mac_index
& 1) * 0x200));
2402 nes_debug(NES_DBG_PHY
, "PCS PHY Control/Status%u: 0x%08X\n",
2403 mac_index
, pcs_control_status
);
2404 if ((nesadapter
->OneG_Mode
) &&
2405 (nesadapter
->phy_type
[mac_index
] != NES_PHY_TYPE_PUMA_1G
)) {
2406 u32temp
= 0x01010000;
2407 if (nesadapter
->port_count
> 2) {
2408 u32temp
|= 0x02020000;
2410 if ((pcs_control_status
& u32temp
)!= u32temp
) {
2412 nes_debug(NES_DBG_PHY
, "PCS says the link is down\n");
2415 switch (nesadapter
->phy_type
[mac_index
]) {
2416 case NES_PHY_TYPE_IRIS
:
2417 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 1, 1);
2418 temp_phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
2421 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 1, 1);
2422 phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
2423 if ((phy_data
== temp_phy_data
) || (!(--u32temp
)))
2425 temp_phy_data
= phy_data
;
2427 nes_debug(NES_DBG_PHY
, "%s: Phy data = 0x%04X, link was %s.\n",
2428 __func__
, phy_data
, nesadapter
->mac_link_down
[mac_index
] ? "DOWN" : "UP");
2431 case NES_PHY_TYPE_ARGUS
:
2432 /* clear the alarms */
2433 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 4, 0x0008);
2434 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 4, 0xc001);
2435 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 4, 0xc002);
2436 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 4, 0xc005);
2437 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 4, 0xc006);
2438 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 1, 0x9003);
2439 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 1, 0x9004);
2440 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 1, 0x9005);
2441 /* check link status */
2442 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 1, 0x9003);
2443 temp_phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
2445 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 3, 0x0021);
2446 nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
2447 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 3, 0x0021);
2448 phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
2450 phy_data
= (!temp_phy_data
&& (phy_data
== 0x8000)) ? 0x4 : 0x0;
2452 nes_debug(NES_DBG_PHY
, "%s: Phy data = 0x%04X, link was %s.\n",
2453 __func__
, phy_data
, nesadapter
->mac_link_down
[mac_index
] ? "DOWN" : "UP");
2456 case NES_PHY_TYPE_PUMA_1G
:
2458 pcs_val
= pcs_mask
= 0x01010000;
2460 pcs_val
= pcs_mask
= 0x02020000;
2463 phy_data
= (pcs_val
== (pcs_control_status
& pcs_mask
)) ? 0x4 : 0x0;
2468 if (phy_data
& 0x0004) {
2469 nesadapter
->mac_link_down
[mac_index
] = 0;
2470 list_for_each_entry(nesvnic
, &nesadapter
->nesvnic_list
[mac_index
], list
) {
2471 nes_debug(NES_DBG_PHY
, "The Link is UP!!. linkup was %d\n",
2473 if (nesvnic
->linkup
== 0) {
2474 printk(PFX
"The Link is now up for port %s, netdev %p.\n",
2475 nesvnic
->netdev
->name
, nesvnic
->netdev
);
2476 if (netif_queue_stopped(nesvnic
->netdev
))
2477 netif_start_queue(nesvnic
->netdev
);
2478 nesvnic
->linkup
= 1;
2479 netif_carrier_on(nesvnic
->netdev
);
2483 nesadapter
->mac_link_down
[mac_index
] = 1;
2484 list_for_each_entry(nesvnic
, &nesadapter
->nesvnic_list
[mac_index
], list
) {
2485 nes_debug(NES_DBG_PHY
, "The Link is Down!!. linkup was %d\n",
2487 if (nesvnic
->linkup
== 1) {
2488 printk(PFX
"The Link is now down for port %s, netdev %p.\n",
2489 nesvnic
->netdev
->name
, nesvnic
->netdev
);
2490 if (!(netif_queue_stopped(nesvnic
->netdev
)))
2491 netif_stop_queue(nesvnic
->netdev
);
2492 nesvnic
->linkup
= 0;
2493 netif_carrier_off(nesvnic
->netdev
);
2499 nesadapter
->mac_sw_state
[mac_number
] = NES_MAC_SW_IDLE
;
2504 static void nes_nic_napi_ce_handler(struct nes_device
*nesdev
, struct nes_hw_nic_cq
*cq
)
2506 struct nes_vnic
*nesvnic
= container_of(cq
, struct nes_vnic
, nic_cq
);
2508 napi_schedule(&nesvnic
->napi
);
2512 /* The MAX_RQES_TO_PROCESS defines how many max read requests to complete before
2513 * getting out of nic_ce_handler
2515 #define MAX_RQES_TO_PROCESS 384
2518 * nes_nic_ce_handler
2520 void nes_nic_ce_handler(struct nes_device
*nesdev
, struct nes_hw_nic_cq
*cq
)
2523 dma_addr_t bus_address
;
2524 struct nes_hw_nic
*nesnic
;
2525 struct nes_vnic
*nesvnic
= container_of(cq
, struct nes_vnic
, nic_cq
);
2526 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
2527 struct nes_hw_nic_rq_wqe
*nic_rqe
;
2528 struct nes_hw_nic_sq_wqe
*nic_sqe
;
2529 struct sk_buff
*skb
;
2530 struct sk_buff
*rx_skb
;
2531 __le16
*wqe_fragment_length
;
2538 u16 wqe_fragment_index
= 1; /* first fragment (0) is used by copy buffer */
2541 u16 rqes_processed
= 0;
2546 cq_size
= cq
->cq_size
;
2547 cq
->cqes_pending
= 1;
2548 if (nesvnic
->netdev
->features
& NETIF_F_LRO
)
2551 if (le32_to_cpu(cq
->cq_vbase
[head
].cqe_words
[NES_NIC_CQE_MISC_IDX
]) &
2552 NES_NIC_CQE_VALID
) {
2553 nesnic
= &nesvnic
->nic
;
2554 cqe_misc
= le32_to_cpu(cq
->cq_vbase
[head
].cqe_words
[NES_NIC_CQE_MISC_IDX
]);
2555 if (cqe_misc
& NES_NIC_CQE_SQ
) {
2557 wqe_fragment_index
= 1;
2558 nic_sqe
= &nesnic
->sq_vbase
[nesnic
->sq_tail
];
2559 skb
= nesnic
->tx_skb
[nesnic
->sq_tail
];
2560 wqe_fragment_length
= (__le16
*)&nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX
];
2561 /* bump past the vlan tag */
2562 wqe_fragment_length
++;
2563 if (le16_to_cpu(wqe_fragment_length
[wqe_fragment_index
]) != 0) {
2564 u64temp
= (u64
) le32_to_cpu(nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_LOW_IDX
+
2565 wqe_fragment_index
* 2]);
2566 u64temp
+= ((u64
)le32_to_cpu(nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
+
2567 wqe_fragment_index
* 2])) << 32;
2568 bus_address
= (dma_addr_t
)u64temp
;
2569 if (test_and_clear_bit(nesnic
->sq_tail
, nesnic
->first_frag_overflow
)) {
2570 pci_unmap_single(nesdev
->pcidev
,
2572 le16_to_cpu(wqe_fragment_length
[wqe_fragment_index
++]),
2575 for (; wqe_fragment_index
< 5; wqe_fragment_index
++) {
2576 if (wqe_fragment_length
[wqe_fragment_index
]) {
2577 u64temp
= le32_to_cpu(nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_LOW_IDX
+
2578 wqe_fragment_index
* 2]);
2579 u64temp
+= ((u64
)le32_to_cpu(nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
2580 + wqe_fragment_index
* 2])) <<32;
2581 bus_address
= (dma_addr_t
)u64temp
;
2582 pci_unmap_page(nesdev
->pcidev
,
2584 le16_to_cpu(wqe_fragment_length
[wqe_fragment_index
]),
2591 dev_kfree_skb_any(skb
);
2593 nesnic
->sq_tail
&= nesnic
->sq_size
-1;
2594 if (sq_cqes
> 128) {
2596 /* restart the queue if it had been stopped */
2597 if (netif_queue_stopped(nesvnic
->netdev
))
2598 netif_wake_queue(nesvnic
->netdev
);
2604 cq
->rx_cqes_completed
++;
2605 cq
->rx_pkts_indicated
++;
2606 rx_pkt_size
= cqe_misc
& 0x0000ffff;
2607 nic_rqe
= &nesnic
->rq_vbase
[nesnic
->rq_tail
];
2609 rx_skb
= nesnic
->rx_skb
[nesnic
->rq_tail
];
2610 nic_rqe
= &nesnic
->rq_vbase
[nesvnic
->nic
.rq_tail
];
2611 bus_address
= (dma_addr_t
)le32_to_cpu(nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_LOW_IDX
]);
2612 bus_address
+= ((u64
)le32_to_cpu(nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX
])) << 32;
2613 pci_unmap_single(nesdev
->pcidev
, bus_address
,
2614 nesvnic
->max_frame_size
, PCI_DMA_FROMDEVICE
);
2615 /* rx_skb->tail = rx_skb->data + rx_pkt_size; */
2616 /* rx_skb->len = rx_pkt_size; */
2617 rx_skb
->len
= 0; /* TODO: see if this is necessary */
2618 skb_put(rx_skb
, rx_pkt_size
);
2619 rx_skb
->protocol
= eth_type_trans(rx_skb
, nesvnic
->netdev
);
2621 nesnic
->rq_tail
&= nesnic
->rq_size
- 1;
2623 atomic_inc(&nesvnic
->rx_skbs_needed
);
2624 if (atomic_read(&nesvnic
->rx_skbs_needed
) > (nesvnic
->nic
.rq_size
>>1)) {
2625 nes_write32(nesdev
->regs
+NES_CQE_ALLOC
,
2626 cq
->cq_number
| (cqe_count
<< 16));
2627 /* nesadapter->tune_timer.cq_count += cqe_count; */
2628 nesdev
->currcq_count
+= cqe_count
;
2630 nes_replenish_nic_rq(nesvnic
);
2632 pkt_type
= (u16
)(le32_to_cpu(cq
->cq_vbase
[head
].cqe_words
[NES_NIC_CQE_TAG_PKT_TYPE_IDX
]));
2633 cqe_errv
= (cqe_misc
& NES_NIC_CQE_ERRV_MASK
) >> NES_NIC_CQE_ERRV_SHIFT
;
2634 rx_skb
->ip_summed
= CHECKSUM_NONE
;
2636 if ((NES_PKT_TYPE_TCPV4_BITS
== (pkt_type
& NES_PKT_TYPE_TCPV4_MASK
)) ||
2637 (NES_PKT_TYPE_UDPV4_BITS
== (pkt_type
& NES_PKT_TYPE_UDPV4_MASK
))) {
2639 (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR
| NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR
|
2640 NES_NIC_ERRV_BITS_IPH_ERR
| NES_NIC_ERRV_BITS_WQE_OVERRUN
)) == 0) {
2641 if (nesvnic
->rx_checksum_disabled
== 0) {
2642 rx_skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2645 nes_debug(NES_DBG_CQ
, "%s: unsuccessfully checksummed TCP or UDP packet."
2646 " errv = 0x%X, pkt_type = 0x%X.\n",
2647 nesvnic
->netdev
->name
, cqe_errv
, pkt_type
);
2649 } else if ((pkt_type
& NES_PKT_TYPE_IPV4_MASK
) == NES_PKT_TYPE_IPV4_BITS
) {
2651 (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR
| NES_NIC_ERRV_BITS_IPH_ERR
|
2652 NES_NIC_ERRV_BITS_WQE_OVERRUN
)) == 0) {
2653 if (nesvnic
->rx_checksum_disabled
== 0) {
2654 rx_skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2655 /* nes_debug(NES_DBG_CQ, "%s: Reporting successfully checksummed IPv4 packet.\n",
2656 nesvnic->netdev->name); */
2659 nes_debug(NES_DBG_CQ
, "%s: unsuccessfully checksummed TCP or UDP packet."
2660 " errv = 0x%X, pkt_type = 0x%X.\n",
2661 nesvnic
->netdev
->name
, cqe_errv
, pkt_type
);
2663 /* nes_debug(NES_DBG_CQ, "pkt_type=%x, APBVT_MASK=%x\n",
2664 pkt_type, (pkt_type & NES_PKT_TYPE_APBVT_MASK)); */
2666 if ((pkt_type
& NES_PKT_TYPE_APBVT_MASK
) == NES_PKT_TYPE_APBVT_BITS
) {
2667 if (nes_cm_recv(rx_skb
, nesvnic
->netdev
))
2671 goto skip_rx_indicate0
;
2674 if ((cqe_misc
& NES_NIC_CQE_TAG_VALID
) &&
2675 (nesvnic
->vlan_grp
!= NULL
)) {
2676 vlan_tag
= (u16
)(le32_to_cpu(
2677 cq
->cq_vbase
[head
].cqe_words
[NES_NIC_CQE_TAG_PKT_TYPE_IDX
])
2679 nes_debug(NES_DBG_CQ
, "%s: Reporting stripped VLAN packet. Tag = 0x%04X\n",
2680 nesvnic
->netdev
->name
, vlan_tag
);
2682 lro_vlan_hwaccel_receive_skb(&nesvnic
->lro_mgr
, rx_skb
,
2683 nesvnic
->vlan_grp
, vlan_tag
, NULL
);
2685 nes_vlan_rx(rx_skb
, nesvnic
->vlan_grp
, vlan_tag
);
2688 lro_receive_skb(&nesvnic
->lro_mgr
, rx_skb
, NULL
);
2690 nes_netif_rx(rx_skb
);
2694 nesvnic
->netdev
->last_rx
= jiffies
;
2695 /* nesvnic->netstats.rx_packets++; */
2696 /* nesvnic->netstats.rx_bytes += rx_pkt_size; */
2699 cq
->cq_vbase
[head
].cqe_words
[NES_NIC_CQE_MISC_IDX
] = 0;
2702 if (++head
>= cq_size
)
2704 if (cqe_count
== 255) {
2705 /* Replenish Nic CQ */
2706 nes_write32(nesdev
->regs
+NES_CQE_ALLOC
,
2707 cq
->cq_number
| (cqe_count
<< 16));
2708 /* nesdev->nesadapter->tune_timer.cq_count += cqe_count; */
2709 nesdev
->currcq_count
+= cqe_count
;
2713 if (cq
->rx_cqes_completed
>= nesvnic
->budget
)
2716 cq
->cqes_pending
= 0;
2723 lro_flush_all(&nesvnic
->lro_mgr
);
2726 /* restart the queue if it had been stopped */
2727 if (netif_queue_stopped(nesvnic
->netdev
))
2728 netif_wake_queue(nesvnic
->netdev
);
2731 /* nes_debug(NES_DBG_CQ, "CQ%u Processed = %u cqes, new head = %u.\n",
2732 cq->cq_number, cqe_count, cq->cq_head); */
2733 cq
->cqe_allocs_pending
= cqe_count
;
2734 if (unlikely(nesadapter
->et_use_adaptive_rx_coalesce
))
2736 /* nesdev->nesadapter->tune_timer.cq_count += cqe_count; */
2737 nesdev
->currcq_count
+= cqe_count
;
2738 nes_nic_tune_timer(nesdev
);
2740 if (atomic_read(&nesvnic
->rx_skbs_needed
))
2741 nes_replenish_nic_rq(nesvnic
);
2746 * nes_cqp_ce_handler
2748 static void nes_cqp_ce_handler(struct nes_device
*nesdev
, struct nes_hw_cq
*cq
)
2751 unsigned long flags
;
2752 struct nes_hw_cqp
*cqp
= NULL
;
2753 struct nes_cqp_request
*cqp_request
;
2754 struct nes_hw_cqp_wqe
*cqp_wqe
;
2762 cq_size
= cq
->cq_size
;
2765 /* process the CQE */
2766 /* nes_debug(NES_DBG_CQP, "head=%u cqe_words=%08X\n", head,
2767 le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX])); */
2769 if (le32_to_cpu(cq
->cq_vbase
[head
].cqe_words
[NES_CQE_OPCODE_IDX
]) & NES_CQE_VALID
) {
2770 u64temp
= (((u64
)(le32_to_cpu(cq
->cq_vbase
[head
].
2771 cqe_words
[NES_CQE_COMP_COMP_CTX_HIGH_IDX
]))) << 32) |
2772 ((u64
)(le32_to_cpu(cq
->cq_vbase
[head
].
2773 cqe_words
[NES_CQE_COMP_COMP_CTX_LOW_IDX
])));
2774 cqp
= *((struct nes_hw_cqp
**)&u64temp
);
2776 error_code
= le32_to_cpu(cq
->cq_vbase
[head
].cqe_words
[NES_CQE_ERROR_CODE_IDX
]);
2778 nes_debug(NES_DBG_CQP
, "Bad Completion code for opcode 0x%02X from CQP,"
2779 " Major/Minor codes = 0x%04X:%04X.\n",
2780 le32_to_cpu(cq
->cq_vbase
[head
].cqe_words
[NES_CQE_OPCODE_IDX
])&0x3f,
2781 (u16
)(error_code
>> 16),
2783 nes_debug(NES_DBG_CQP
, "cqp: qp_id=%u, sq_head=%u, sq_tail=%u\n",
2784 cqp
->qp_id
, cqp
->sq_head
, cqp
->sq_tail
);
2787 u64temp
= (((u64
)(le32_to_cpu(nesdev
->cqp
.sq_vbase
[cqp
->sq_tail
].
2788 wqe_words
[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX
]))) << 32) |
2789 ((u64
)(le32_to_cpu(nesdev
->cqp
.sq_vbase
[cqp
->sq_tail
].
2790 wqe_words
[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX
])));
2791 cqp_request
= *((struct nes_cqp_request
**)&u64temp
);
2793 if (cqp_request
->waiting
) {
2794 /* nes_debug(NES_DBG_CQP, "%s: Waking up requestor\n"); */
2795 cqp_request
->major_code
= (u16
)(error_code
>> 16);
2796 cqp_request
->minor_code
= (u16
)error_code
;
2798 cqp_request
->request_done
= 1;
2799 wake_up(&cqp_request
->waitq
);
2800 nes_put_cqp_request(nesdev
, cqp_request
);
2802 if (cqp_request
->callback
)
2803 cqp_request
->cqp_callback(nesdev
, cqp_request
);
2804 nes_free_cqp_request(nesdev
, cqp_request
);
2807 wake_up(&nesdev
->cqp
.waitq
);
2810 cq
->cq_vbase
[head
].cqe_words
[NES_CQE_OPCODE_IDX
] = 0;
2811 nes_write32(nesdev
->regs
+ NES_CQE_ALLOC
, cq
->cq_number
| (1 << 16));
2812 if (++cqp
->sq_tail
>= cqp
->sq_size
)
2817 if (++head
>= cq_size
)
2825 spin_lock_irqsave(&nesdev
->cqp
.lock
, flags
);
2826 while ((!list_empty(&nesdev
->cqp_pending_reqs
)) &&
2827 ((((nesdev
->cqp
.sq_tail
+nesdev
->cqp
.sq_size
)-nesdev
->cqp
.sq_head
) &
2828 (nesdev
->cqp
.sq_size
- 1)) != 1)) {
2829 cqp_request
= list_entry(nesdev
->cqp_pending_reqs
.next
,
2830 struct nes_cqp_request
, list
);
2831 list_del_init(&cqp_request
->list
);
2832 head
= nesdev
->cqp
.sq_head
++;
2833 nesdev
->cqp
.sq_head
&= nesdev
->cqp
.sq_size
-1;
2834 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[head
];
2835 memcpy(cqp_wqe
, &cqp_request
->cqp_wqe
, sizeof(*cqp_wqe
));
2837 cqp_wqe
->wqe_words
[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX
] =
2838 cpu_to_le32((u32
)((unsigned long)cqp_request
));
2839 cqp_wqe
->wqe_words
[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX
] =
2840 cpu_to_le32((u32
)(upper_32_bits((unsigned long)cqp_request
)));
2841 nes_debug(NES_DBG_CQP
, "CQP request %p (opcode 0x%02X) put on CQPs SQ wqe%u.\n",
2842 cqp_request
, le32_to_cpu(cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
])&0x3f, head
);
2843 /* Ring doorbell (1 WQEs) */
2845 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, 0x01800000 | nesdev
->cqp
.qp_id
);
2847 spin_unlock_irqrestore(&nesdev
->cqp
.lock
, flags
);
2850 nes_write32(nesdev
->regs
+NES_CQE_ALLOC
, NES_CQE_ALLOC_NOTIFY_NEXT
|
2852 nes_read32(nesdev
->regs
+NES_CQE_ALLOC
);
2857 * nes_process_iwarp_aeqe
2859 static void nes_process_iwarp_aeqe(struct nes_device
*nesdev
,
2860 struct nes_hw_aeqe
*aeqe
)
2863 u64 aeqe_context
= 0;
2864 unsigned long flags
;
2865 struct nes_qp
*nesqp
;
2866 int resource_allocated
;
2867 /* struct iw_cm_id *cm_id; */
2868 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
2869 struct ib_event ibevent
;
2870 /* struct iw_cm_event cm_event; */
2872 u32 next_iwarp_state
= 0;
2877 nes_debug(NES_DBG_AEQ
, "\n");
2878 aeq_info
= le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_MISC_IDX
]);
2879 if ((NES_AEQE_INBOUND_RDMA
&aeq_info
) || (!(NES_AEQE_QP
&aeq_info
))) {
2880 context
= le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_CTXT_LOW_IDX
]);
2881 context
+= ((u64
)le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_CTXT_HIGH_IDX
])) << 32;
2883 aeqe_context
= le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_CTXT_LOW_IDX
]);
2884 aeqe_context
+= ((u64
)le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_CTXT_HIGH_IDX
])) << 32;
2885 context
= (unsigned long)nesadapter
->qp_table
[le32_to_cpu(
2886 aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]) - NES_FIRST_QPN
];
2890 async_event_id
= (u16
)aeq_info
;
2891 tcp_state
= (aeq_info
& NES_AEQE_TCP_STATE_MASK
) >> NES_AEQE_TCP_STATE_SHIFT
;
2892 iwarp_state
= (aeq_info
& NES_AEQE_IWARP_STATE_MASK
) >> NES_AEQE_IWARP_STATE_SHIFT
;
2893 nes_debug(NES_DBG_AEQ
, "aeid = 0x%04X, qp-cq id = %d, aeqe = %p,"
2894 " Tcp state = %s, iWARP state = %s\n",
2896 le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]), aeqe
,
2897 nes_tcp_state_str
[tcp_state
], nes_iwarp_state_str
[iwarp_state
]);
2899 switch (async_event_id
) {
2900 case NES_AEQE_AEID_LLP_FIN_RECEIVED
:
2901 nesqp
= *((struct nes_qp
**)&context
);
2902 if (atomic_inc_return(&nesqp
->close_timer_started
) == 1) {
2903 nesqp
->cm_id
->add_ref(nesqp
->cm_id
);
2904 schedule_nes_timer(nesqp
->cm_node
, (struct sk_buff
*)nesqp
,
2905 NES_TIMER_TYPE_CLOSE
, 1, 0);
2906 nes_debug(NES_DBG_AEQ
, "QP%u Not decrementing QP refcount (%d),"
2907 " need ae to finish up, original_last_aeq = 0x%04X."
2908 " last_aeq = 0x%04X, scheduling timer. TCP state = %d\n",
2909 nesqp
->hwqp
.qp_id
, atomic_read(&nesqp
->refcount
),
2910 async_event_id
, nesqp
->last_aeq
, tcp_state
);
2912 if ((tcp_state
!= NES_AEQE_TCP_STATE_CLOSE_WAIT
) ||
2913 (nesqp
->ibqp_state
!= IB_QPS_RTS
)) {
2914 /* FIN Received but tcp state or IB state moved on,
2915 should expect a close complete */
2918 case NES_AEQE_AEID_LLP_CLOSE_COMPLETE
:
2919 case NES_AEQE_AEID_LLP_CONNECTION_RESET
:
2920 case NES_AEQE_AEID_TERMINATE_SENT
:
2921 case NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE
:
2922 case NES_AEQE_AEID_RESET_SENT
:
2923 nesqp
= *((struct nes_qp
**)&context
);
2924 if (async_event_id
== NES_AEQE_AEID_RESET_SENT
) {
2925 tcp_state
= NES_AEQE_TCP_STATE_CLOSED
;
2927 spin_lock_irqsave(&nesqp
->lock
, flags
);
2928 nesqp
->hw_iwarp_state
= iwarp_state
;
2929 nesqp
->hw_tcp_state
= tcp_state
;
2930 nesqp
->last_aeq
= async_event_id
;
2932 if ((tcp_state
== NES_AEQE_TCP_STATE_CLOSED
) ||
2933 (tcp_state
== NES_AEQE_TCP_STATE_TIME_WAIT
)) {
2934 nesqp
->hte_added
= 0;
2935 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
2936 nes_debug(NES_DBG_AEQ
, "issuing hw modifyqp for QP%u to remove hte\n",
2938 nes_hw_modify_qp(nesdev
, nesqp
,
2939 NES_CQP_QP_IWARP_STATE_ERROR
| NES_CQP_QP_DEL_HTE
, 0);
2940 spin_lock_irqsave(&nesqp
->lock
, flags
);
2943 if ((nesqp
->ibqp_state
== IB_QPS_RTS
) &&
2944 ((tcp_state
== NES_AEQE_TCP_STATE_CLOSE_WAIT
) ||
2945 (async_event_id
== NES_AEQE_AEID_LLP_CONNECTION_RESET
))) {
2946 switch (nesqp
->hw_iwarp_state
) {
2947 case NES_AEQE_IWARP_STATE_RTS
:
2948 next_iwarp_state
= NES_CQP_QP_IWARP_STATE_CLOSING
;
2949 nesqp
->hw_iwarp_state
= NES_AEQE_IWARP_STATE_CLOSING
;
2951 case NES_AEQE_IWARP_STATE_TERMINATE
:
2952 next_iwarp_state
= NES_CQP_QP_IWARP_STATE_TERMINATE
;
2953 nesqp
->hw_iwarp_state
= NES_AEQE_IWARP_STATE_TERMINATE
;
2954 if (async_event_id
== NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE
) {
2955 next_iwarp_state
|= 0x02000000;
2956 nesqp
->hw_tcp_state
= NES_AEQE_TCP_STATE_CLOSED
;
2960 next_iwarp_state
= 0;
2962 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
2963 if (next_iwarp_state
) {
2964 nes_debug(NES_DBG_AEQ
, "issuing hw modifyqp for QP%u. next state = 0x%08X,"
2965 " also added another reference\n",
2966 nesqp
->hwqp
.qp_id
, next_iwarp_state
);
2967 nes_hw_modify_qp(nesdev
, nesqp
, next_iwarp_state
, 0);
2969 nes_cm_disconn(nesqp
);
2971 if (async_event_id
== NES_AEQE_AEID_LLP_FIN_RECEIVED
) {
2972 /* FIN Received but ib state not RTS,
2973 close complete will be on its way */
2974 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
2977 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
2978 if (async_event_id
== NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE
) {
2979 next_iwarp_state
= NES_CQP_QP_IWARP_STATE_TERMINATE
| 0x02000000;
2980 nesqp
->hw_tcp_state
= NES_AEQE_TCP_STATE_CLOSED
;
2981 nes_debug(NES_DBG_AEQ
, "issuing hw modifyqp for QP%u. next state = 0x%08X,"
2982 " also added another reference\n",
2983 nesqp
->hwqp
.qp_id
, next_iwarp_state
);
2984 nes_hw_modify_qp(nesdev
, nesqp
, next_iwarp_state
, 0);
2986 nes_cm_disconn(nesqp
);
2989 case NES_AEQE_AEID_LLP_TERMINATE_RECEIVED
:
2990 nesqp
= *((struct nes_qp
**)&context
);
2991 spin_lock_irqsave(&nesqp
->lock
, flags
);
2992 nesqp
->hw_iwarp_state
= iwarp_state
;
2993 nesqp
->hw_tcp_state
= tcp_state
;
2994 nesqp
->last_aeq
= async_event_id
;
2995 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
2996 nes_debug(NES_DBG_AEQ
, "Processing an NES_AEQE_AEID_LLP_TERMINATE_RECEIVED"
2997 " event on QP%u \n Q2 Data:\n",
2999 if (nesqp
->ibqp
.event_handler
) {
3000 ibevent
.device
= nesqp
->ibqp
.device
;
3001 ibevent
.element
.qp
= &nesqp
->ibqp
;
3002 ibevent
.event
= IB_EVENT_QP_FATAL
;
3003 nesqp
->ibqp
.event_handler(&ibevent
, nesqp
->ibqp
.qp_context
);
3005 if ((tcp_state
== NES_AEQE_TCP_STATE_CLOSE_WAIT
) ||
3006 ((nesqp
->ibqp_state
== IB_QPS_RTS
)&&
3007 (async_event_id
== NES_AEQE_AEID_LLP_CONNECTION_RESET
))) {
3008 nes_cm_disconn(nesqp
);
3010 nesqp
->in_disconnect
= 0;
3011 wake_up(&nesqp
->kick_waitq
);
3014 case NES_AEQE_AEID_LLP_TOO_MANY_RETRIES
:
3015 nesqp
= *((struct nes_qp
**)&context
);
3016 spin_lock_irqsave(&nesqp
->lock
, flags
);
3017 nesqp
->hw_iwarp_state
= NES_AEQE_IWARP_STATE_ERROR
;
3018 nesqp
->hw_tcp_state
= NES_AEQE_TCP_STATE_CLOSED
;
3019 nesqp
->last_aeq
= async_event_id
;
3021 nes_debug(NES_DBG_AEQ
, "Processing an NES_AEQE_AEID_LLP_TOO_MANY_RETRIES"
3022 " event on QP%u, remote IP = 0x%08X \n",
3024 ntohl(nesqp
->cm_id
->remote_addr
.sin_addr
.s_addr
));
3026 nes_debug(NES_DBG_AEQ
, "Processing an NES_AEQE_AEID_LLP_TOO_MANY_RETRIES"
3027 " event on QP%u \n",
3030 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3031 next_iwarp_state
= NES_CQP_QP_IWARP_STATE_ERROR
| NES_CQP_QP_RESET
;
3032 nes_hw_modify_qp(nesdev
, nesqp
, next_iwarp_state
, 0);
3033 if (nesqp
->ibqp
.event_handler
) {
3034 ibevent
.device
= nesqp
->ibqp
.device
;
3035 ibevent
.element
.qp
= &nesqp
->ibqp
;
3036 ibevent
.event
= IB_EVENT_QP_FATAL
;
3037 nesqp
->ibqp
.event_handler(&ibevent
, nesqp
->ibqp
.qp_context
);
3040 case NES_AEQE_AEID_AMP_BAD_STAG_INDEX
:
3041 if (NES_AEQE_INBOUND_RDMA
&aeq_info
) {
3042 nesqp
= nesadapter
->qp_table
[le32_to_cpu(
3043 aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
])-NES_FIRST_QPN
];
3045 /* TODO: get the actual WQE and mask off wqe index */
3046 context
&= ~((u64
)511);
3047 nesqp
= *((struct nes_qp
**)&context
);
3049 spin_lock_irqsave(&nesqp
->lock
, flags
);
3050 nesqp
->hw_iwarp_state
= iwarp_state
;
3051 nesqp
->hw_tcp_state
= tcp_state
;
3052 nesqp
->last_aeq
= async_event_id
;
3053 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3054 nes_debug(NES_DBG_AEQ
, "Processing an NES_AEQE_AEID_AMP_BAD_STAG_INDEX event on QP%u\n",
3056 if (nesqp
->ibqp
.event_handler
) {
3057 ibevent
.device
= nesqp
->ibqp
.device
;
3058 ibevent
.element
.qp
= &nesqp
->ibqp
;
3059 ibevent
.event
= IB_EVENT_QP_ACCESS_ERR
;
3060 nesqp
->ibqp
.event_handler(&ibevent
, nesqp
->ibqp
.qp_context
);
3063 case NES_AEQE_AEID_AMP_UNALLOCATED_STAG
:
3064 nesqp
= *((struct nes_qp
**)&context
);
3065 spin_lock_irqsave(&nesqp
->lock
, flags
);
3066 nesqp
->hw_iwarp_state
= iwarp_state
;
3067 nesqp
->hw_tcp_state
= tcp_state
;
3068 nesqp
->last_aeq
= async_event_id
;
3069 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3070 nes_debug(NES_DBG_AEQ
, "Processing an NES_AEQE_AEID_AMP_UNALLOCATED_STAG event on QP%u\n",
3072 if (nesqp
->ibqp
.event_handler
) {
3073 ibevent
.device
= nesqp
->ibqp
.device
;
3074 ibevent
.element
.qp
= &nesqp
->ibqp
;
3075 ibevent
.event
= IB_EVENT_QP_ACCESS_ERR
;
3076 nesqp
->ibqp
.event_handler(&ibevent
, nesqp
->ibqp
.qp_context
);
3079 case NES_AEQE_AEID_PRIV_OPERATION_DENIED
:
3080 nesqp
= nesadapter
->qp_table
[le32_to_cpu(aeqe
->aeqe_words
3081 [NES_AEQE_COMP_QP_CQ_ID_IDX
])-NES_FIRST_QPN
];
3082 spin_lock_irqsave(&nesqp
->lock
, flags
);
3083 nesqp
->hw_iwarp_state
= iwarp_state
;
3084 nesqp
->hw_tcp_state
= tcp_state
;
3085 nesqp
->last_aeq
= async_event_id
;
3086 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3087 nes_debug(NES_DBG_AEQ
, "Processing an NES_AEQE_AEID_PRIV_OPERATION_DENIED event on QP%u,"
3088 " nesqp = %p, AE reported %p\n",
3089 nesqp
->hwqp
.qp_id
, nesqp
, *((struct nes_qp
**)&context
));
3090 if (nesqp
->ibqp
.event_handler
) {
3091 ibevent
.device
= nesqp
->ibqp
.device
;
3092 ibevent
.element
.qp
= &nesqp
->ibqp
;
3093 ibevent
.event
= IB_EVENT_QP_ACCESS_ERR
;
3094 nesqp
->ibqp
.event_handler(&ibevent
, nesqp
->ibqp
.qp_context
);
3097 case NES_AEQE_AEID_CQ_OPERATION_ERROR
:
3099 nes_debug(NES_DBG_AEQ
, "Processing an NES_AEQE_AEID_CQ_OPERATION_ERROR event on CQ%u, %p\n",
3100 le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]), (void *)(unsigned long)context
);
3101 resource_allocated
= nes_is_resource_allocated(nesadapter
, nesadapter
->allocated_cqs
,
3102 le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]));
3103 if (resource_allocated
) {
3104 printk(KERN_ERR PFX
"%s: Processing an NES_AEQE_AEID_CQ_OPERATION_ERROR event on CQ%u\n",
3105 __func__
, le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]));
3108 case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER
:
3109 nesqp
= nesadapter
->qp_table
[le32_to_cpu(
3110 aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
])-NES_FIRST_QPN
];
3111 spin_lock_irqsave(&nesqp
->lock
, flags
);
3112 nesqp
->hw_iwarp_state
= iwarp_state
;
3113 nesqp
->hw_tcp_state
= tcp_state
;
3114 nesqp
->last_aeq
= async_event_id
;
3115 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3116 nes_debug(NES_DBG_AEQ
, "Processing an NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG"
3117 "_FOR_AVAILABLE_BUFFER event on QP%u\n",
3119 if (nesqp
->ibqp
.event_handler
) {
3120 ibevent
.device
= nesqp
->ibqp
.device
;
3121 ibevent
.element
.qp
= &nesqp
->ibqp
;
3122 ibevent
.event
= IB_EVENT_QP_ACCESS_ERR
;
3123 nesqp
->ibqp
.event_handler(&ibevent
, nesqp
->ibqp
.qp_context
);
3125 /* tell cm to disconnect, cm will queue work to thread */
3126 nes_cm_disconn(nesqp
);
3128 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE
:
3129 nesqp
= *((struct nes_qp
**)&context
);
3130 spin_lock_irqsave(&nesqp
->lock
, flags
);
3131 nesqp
->hw_iwarp_state
= iwarp_state
;
3132 nesqp
->hw_tcp_state
= tcp_state
;
3133 nesqp
->last_aeq
= async_event_id
;
3134 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3135 nes_debug(NES_DBG_AEQ
, "Processing an NES_AEQE_AEID_DDP_UBE_INVALID_MSN"
3136 "_NO_BUFFER_AVAILABLE event on QP%u\n",
3138 if (nesqp
->ibqp
.event_handler
) {
3139 ibevent
.device
= nesqp
->ibqp
.device
;
3140 ibevent
.element
.qp
= &nesqp
->ibqp
;
3141 ibevent
.event
= IB_EVENT_QP_FATAL
;
3142 nesqp
->ibqp
.event_handler(&ibevent
, nesqp
->ibqp
.qp_context
);
3144 /* tell cm to disconnect, cm will queue work to thread */
3145 nes_cm_disconn(nesqp
);
3147 case NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR
:
3148 nesqp
= *((struct nes_qp
**)&context
);
3149 spin_lock_irqsave(&nesqp
->lock
, flags
);
3150 nesqp
->hw_iwarp_state
= iwarp_state
;
3151 nesqp
->hw_tcp_state
= tcp_state
;
3152 nesqp
->last_aeq
= async_event_id
;
3153 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3154 nes_debug(NES_DBG_AEQ
, "Processing an NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR"
3155 " event on QP%u \n Q2 Data:\n",
3157 if (nesqp
->ibqp
.event_handler
) {
3158 ibevent
.device
= nesqp
->ibqp
.device
;
3159 ibevent
.element
.qp
= &nesqp
->ibqp
;
3160 ibevent
.event
= IB_EVENT_QP_FATAL
;
3161 nesqp
->ibqp
.event_handler(&ibevent
, nesqp
->ibqp
.qp_context
);
3163 /* tell cm to disconnect, cm will queue work to thread */
3164 nes_cm_disconn(nesqp
);
3166 /* TODO: additional AEs need to be here */
3167 case NES_AEQE_AEID_AMP_BOUNDS_VIOLATION
:
3168 nesqp
= *((struct nes_qp
**)&context
);
3169 spin_lock_irqsave(&nesqp
->lock
, flags
);
3170 nesqp
->hw_iwarp_state
= iwarp_state
;
3171 nesqp
->hw_tcp_state
= tcp_state
;
3172 nesqp
->last_aeq
= async_event_id
;
3173 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3174 if (nesqp
->ibqp
.event_handler
) {
3175 ibevent
.device
= nesqp
->ibqp
.device
;
3176 ibevent
.element
.qp
= &nesqp
->ibqp
;
3177 ibevent
.event
= IB_EVENT_QP_ACCESS_ERR
;
3178 nesqp
->ibqp
.event_handler(&ibevent
,
3179 nesqp
->ibqp
.qp_context
);
3181 nes_cm_disconn(nesqp
);
3184 nes_debug(NES_DBG_AEQ
, "Processing an iWARP related AE for QP, misc = 0x%04X\n",
3193 * nes_iwarp_ce_handler
3195 void nes_iwarp_ce_handler(struct nes_device
*nesdev
, struct nes_hw_cq
*hw_cq
)
3197 struct nes_cq
*nescq
= container_of(hw_cq
, struct nes_cq
, hw_cq
);
3199 /* nes_debug(NES_DBG_CQ, "Processing completion event for iWARP CQ%u.\n",
3200 nescq->hw_cq.cq_number); */
3201 nes_write32(nesdev
->regs
+NES_CQ_ACK
, nescq
->hw_cq
.cq_number
);
3203 if (nescq
->ibcq
.comp_handler
)
3204 nescq
->ibcq
.comp_handler(&nescq
->ibcq
, nescq
->ibcq
.cq_context
);
3211 * nes_manage_apbvt()
3213 int nes_manage_apbvt(struct nes_vnic
*nesvnic
, u32 accel_local_port
,
3214 u32 nic_index
, u32 add_port
)
3216 struct nes_device
*nesdev
= nesvnic
->nesdev
;
3217 struct nes_hw_cqp_wqe
*cqp_wqe
;
3218 struct nes_cqp_request
*cqp_request
;
3222 /* Send manage APBVT request to CQP */
3223 cqp_request
= nes_get_cqp_request(nesdev
);
3224 if (cqp_request
== NULL
) {
3225 nes_debug(NES_DBG_QP
, "Failed to get a cqp_request.\n");
3228 cqp_request
->waiting
= 1;
3229 cqp_wqe
= &cqp_request
->cqp_wqe
;
3231 nes_debug(NES_DBG_QP
, "%s APBV for local port=%u(0x%04x), nic_index=%u\n",
3232 (add_port
== NES_MANAGE_APBVT_ADD
) ? "ADD" : "DEL",
3233 accel_local_port
, accel_local_port
, nic_index
);
3235 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
3236 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
, (NES_CQP_MANAGE_APBVT
|
3237 ((add_port
== NES_MANAGE_APBVT_ADD
) ? NES_CQP_APBVT_ADD
: 0)));
3238 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_ID_IDX
,
3239 ((nic_index
<< NES_CQP_APBVT_NIC_SHIFT
) | accel_local_port
));
3241 nes_debug(NES_DBG_QP
, "Waiting for CQP completion for APBVT.\n");
3243 atomic_set(&cqp_request
->refcount
, 2);
3244 nes_post_cqp_request(nesdev
, cqp_request
);
3246 if (add_port
== NES_MANAGE_APBVT_ADD
)
3247 ret
= wait_event_timeout(cqp_request
->waitq
, (cqp_request
->request_done
!= 0),
3249 nes_debug(NES_DBG_QP
, "Completed, ret=%u, CQP Major:Minor codes = 0x%04X:0x%04X\n",
3250 ret
, cqp_request
->major_code
, cqp_request
->minor_code
);
3251 major_code
= cqp_request
->major_code
;
3253 nes_put_cqp_request(nesdev
, cqp_request
);
3257 else if (major_code
)
3265 * nes_manage_arp_cache
3267 void nes_manage_arp_cache(struct net_device
*netdev
, unsigned char *mac_addr
,
3268 u32 ip_addr
, u32 action
)
3270 struct nes_hw_cqp_wqe
*cqp_wqe
;
3271 struct nes_vnic
*nesvnic
= netdev_priv(netdev
);
3272 struct nes_device
*nesdev
;
3273 struct nes_cqp_request
*cqp_request
;
3276 nesdev
= nesvnic
->nesdev
;
3277 arp_index
= nes_arp_table(nesdev
, ip_addr
, mac_addr
, action
);
3278 if (arp_index
== -1) {
3282 /* update the ARP entry */
3283 cqp_request
= nes_get_cqp_request(nesdev
);
3284 if (cqp_request
== NULL
) {
3285 nes_debug(NES_DBG_NETDEV
, "Failed to get a cqp_request.\n");
3288 cqp_request
->waiting
= 0;
3289 cqp_wqe
= &cqp_request
->cqp_wqe
;
3290 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
3292 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(
3293 NES_CQP_MANAGE_ARP_CACHE
| NES_CQP_ARP_PERM
);
3294 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] |= cpu_to_le32(
3295 (u32
)PCI_FUNC(nesdev
->pcidev
->devfn
) << NES_CQP_ARP_AEQ_INDEX_SHIFT
);
3296 cqp_wqe
->wqe_words
[NES_CQP_WQE_ID_IDX
] = cpu_to_le32(arp_index
);
3298 if (action
== NES_ARP_ADD
) {
3299 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] |= cpu_to_le32(NES_CQP_ARP_VALID
);
3300 cqp_wqe
->wqe_words
[NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX
] = cpu_to_le32(
3301 (((u32
)mac_addr
[2]) << 24) | (((u32
)mac_addr
[3]) << 16) |
3302 (((u32
)mac_addr
[4]) << 8) | (u32
)mac_addr
[5]);
3303 cqp_wqe
->wqe_words
[NES_CQP_ARP_WQE_MAC_HIGH_IDX
] = cpu_to_le32(
3304 (((u32
)mac_addr
[0]) << 16) | (u32
)mac_addr
[1]);
3306 cqp_wqe
->wqe_words
[NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX
] = 0;
3307 cqp_wqe
->wqe_words
[NES_CQP_ARP_WQE_MAC_HIGH_IDX
] = 0;
3310 nes_debug(NES_DBG_NETDEV
, "Not waiting for CQP, cqp.sq_head=%u, cqp.sq_tail=%u\n",
3311 nesdev
->cqp
.sq_head
, nesdev
->cqp
.sq_tail
);
3313 atomic_set(&cqp_request
->refcount
, 1);
3314 nes_post_cqp_request(nesdev
, cqp_request
);
3321 void flush_wqes(struct nes_device
*nesdev
, struct nes_qp
*nesqp
,
3322 u32 which_wq
, u32 wait_completion
)
3324 struct nes_cqp_request
*cqp_request
;
3325 struct nes_hw_cqp_wqe
*cqp_wqe
;
3328 cqp_request
= nes_get_cqp_request(nesdev
);
3329 if (cqp_request
== NULL
) {
3330 nes_debug(NES_DBG_QP
, "Failed to get a cqp_request.\n");
3333 if (wait_completion
) {
3334 cqp_request
->waiting
= 1;
3335 atomic_set(&cqp_request
->refcount
, 2);
3337 cqp_request
->waiting
= 0;
3339 cqp_wqe
= &cqp_request
->cqp_wqe
;
3340 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
3342 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] =
3343 cpu_to_le32(NES_CQP_FLUSH_WQES
| which_wq
);
3344 cqp_wqe
->wqe_words
[NES_CQP_WQE_ID_IDX
] = cpu_to_le32(nesqp
->hwqp
.qp_id
);
3346 nes_post_cqp_request(nesdev
, cqp_request
);
3348 if (wait_completion
) {
3350 ret
= wait_event_timeout(cqp_request
->waitq
, (cqp_request
->request_done
!= 0),
3352 nes_debug(NES_DBG_QP
, "Flush SQ QP WQEs completed, ret=%u,"
3353 " CQP Major:Minor codes = 0x%04X:0x%04X\n",
3354 ret
, cqp_request
->major_code
, cqp_request
->minor_code
);
3355 nes_put_cqp_request(nesdev
, cqp_request
);