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mlx4: Implement devlink interface
[deliverable/linux.git] / drivers / infiniband / hw / ocrdma / ocrdma_hw.c
1 /* This file is part of the Emulex RoCE Device Driver for
2 * RoCE (RDMA over Converged Ethernet) adapters.
3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
4 * EMULEX and SLI are trademarks of Emulex.
5 * www.emulex.com
6 *
7 * This software is available to you under a choice of one of two licenses.
8 * You may choose to be licensed under the terms of the GNU General Public
9 * License (GPL) Version 2, available from the file COPYING in the main
10 * directory of this source tree, or the BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * - Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * Contact Information:
36 * linux-drivers@emulex.com
37 *
38 * Emulex
39 * 3333 Susan Street
40 * Costa Mesa, CA 92626
41 */
42
43 #include <linux/sched.h>
44 #include <linux/interrupt.h>
45 #include <linux/log2.h>
46 #include <linux/dma-mapping.h>
47
48 #include <rdma/ib_verbs.h>
49 #include <rdma/ib_user_verbs.h>
50 #include <rdma/ib_cache.h>
51
52 #include "ocrdma.h"
53 #include "ocrdma_hw.h"
54 #include "ocrdma_verbs.h"
55 #include "ocrdma_ah.h"
56
57 enum mbx_status {
58 OCRDMA_MBX_STATUS_FAILED = 1,
59 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
60 OCRDMA_MBX_STATUS_OOR = 100,
61 OCRDMA_MBX_STATUS_INVALID_PD = 101,
62 OCRDMA_MBX_STATUS_PD_INUSE = 102,
63 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
64 OCRDMA_MBX_STATUS_INVALID_QP = 104,
65 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
66 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
67 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
68 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
69 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
70 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
71 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
72 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
73 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
74 OCRDMA_MBX_STATUS_MW_BOUND = 114,
75 OCRDMA_MBX_STATUS_INVALID_VA = 115,
76 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
77 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
78 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
79 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
80 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
81 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
82 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
83 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
84 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
85 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
86 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
87 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
88 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
89 OCRDMA_MBX_STATUS_QP_BOUND = 130,
90 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
91 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
92 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
93 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
94 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
95 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
96 };
97
98 enum additional_status {
99 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
100 };
101
102 enum cqe_status {
103 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
104 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
105 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
106 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
107 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
108 };
109
110 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
111 {
112 return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
113 }
114
115 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
116 {
117 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
118 }
119
120 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
121 {
122 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
123 (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
124
125 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
126 return NULL;
127 return cqe;
128 }
129
130 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
131 {
132 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
133 }
134
135 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
136 {
137 return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
138 }
139
140 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
141 {
142 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
143 }
144
145 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
146 {
147 return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
148 }
149
150 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
151 {
152 switch (qps) {
153 case OCRDMA_QPS_RST:
154 return IB_QPS_RESET;
155 case OCRDMA_QPS_INIT:
156 return IB_QPS_INIT;
157 case OCRDMA_QPS_RTR:
158 return IB_QPS_RTR;
159 case OCRDMA_QPS_RTS:
160 return IB_QPS_RTS;
161 case OCRDMA_QPS_SQD:
162 case OCRDMA_QPS_SQ_DRAINING:
163 return IB_QPS_SQD;
164 case OCRDMA_QPS_SQE:
165 return IB_QPS_SQE;
166 case OCRDMA_QPS_ERR:
167 return IB_QPS_ERR;
168 }
169 return IB_QPS_ERR;
170 }
171
172 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
173 {
174 switch (qps) {
175 case IB_QPS_RESET:
176 return OCRDMA_QPS_RST;
177 case IB_QPS_INIT:
178 return OCRDMA_QPS_INIT;
179 case IB_QPS_RTR:
180 return OCRDMA_QPS_RTR;
181 case IB_QPS_RTS:
182 return OCRDMA_QPS_RTS;
183 case IB_QPS_SQD:
184 return OCRDMA_QPS_SQD;
185 case IB_QPS_SQE:
186 return OCRDMA_QPS_SQE;
187 case IB_QPS_ERR:
188 return OCRDMA_QPS_ERR;
189 }
190 return OCRDMA_QPS_ERR;
191 }
192
193 static int ocrdma_get_mbx_errno(u32 status)
194 {
195 int err_num;
196 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
197 OCRDMA_MBX_RSP_STATUS_SHIFT;
198 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
199 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
200
201 switch (mbox_status) {
202 case OCRDMA_MBX_STATUS_OOR:
203 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
204 err_num = -EAGAIN;
205 break;
206
207 case OCRDMA_MBX_STATUS_INVALID_PD:
208 case OCRDMA_MBX_STATUS_INVALID_CQ:
209 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
210 case OCRDMA_MBX_STATUS_INVALID_QP:
211 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
212 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
213 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
214 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
215 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
216 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
217 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
218 case OCRDMA_MBX_STATUS_INVALID_LKEY:
219 case OCRDMA_MBX_STATUS_INVALID_VA:
220 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
221 case OCRDMA_MBX_STATUS_INVALID_FBO:
222 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
223 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
224 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
225 case OCRDMA_MBX_STATUS_SRQ_ERROR:
226 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
227 err_num = -EINVAL;
228 break;
229
230 case OCRDMA_MBX_STATUS_PD_INUSE:
231 case OCRDMA_MBX_STATUS_QP_BOUND:
232 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
233 case OCRDMA_MBX_STATUS_MW_BOUND:
234 err_num = -EBUSY;
235 break;
236
237 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
238 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
239 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
240 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
241 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
242 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
243 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
244 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
245 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
246 err_num = -ENOBUFS;
247 break;
248
249 case OCRDMA_MBX_STATUS_FAILED:
250 switch (add_status) {
251 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
252 err_num = -EAGAIN;
253 break;
254 }
255 default:
256 err_num = -EFAULT;
257 }
258 return err_num;
259 }
260
261 char *port_speed_string(struct ocrdma_dev *dev)
262 {
263 char *str = "";
264 u16 speeds_supported;
265
266 speeds_supported = dev->phy.fixed_speeds_supported |
267 dev->phy.auto_speeds_supported;
268 if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
269 str = "40Gbps ";
270 else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
271 str = "10Gbps ";
272 else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
273 str = "1Gbps ";
274
275 return str;
276 }
277
278 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
279 {
280 int err_num = -EINVAL;
281
282 switch (cqe_status) {
283 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
284 err_num = -EPERM;
285 break;
286 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
287 err_num = -EINVAL;
288 break;
289 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
290 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
291 err_num = -EINVAL;
292 break;
293 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
294 default:
295 err_num = -EINVAL;
296 break;
297 }
298 return err_num;
299 }
300
301 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
302 bool solicited, u16 cqe_popped)
303 {
304 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
305
306 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
307 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
308
309 if (armed)
310 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
311 if (solicited)
312 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
313 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
314 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
315 }
316
317 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
318 {
319 u32 val = 0;
320
321 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
322 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
323 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
324 }
325
326 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
327 bool arm, bool clear_int, u16 num_eqe)
328 {
329 u32 val = 0;
330
331 val |= eq_id & OCRDMA_EQ_ID_MASK;
332 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
333 if (arm)
334 val |= (1 << OCRDMA_REARM_SHIFT);
335 if (clear_int)
336 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
337 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
338 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
339 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
340 }
341
342 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
343 u8 opcode, u8 subsys, u32 cmd_len)
344 {
345 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
346 cmd_hdr->timeout = 20; /* seconds */
347 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
348 }
349
350 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
351 {
352 struct ocrdma_mqe *mqe;
353
354 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
355 if (!mqe)
356 return NULL;
357 mqe->hdr.spcl_sge_cnt_emb |=
358 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
359 OCRDMA_MQE_HDR_EMB_MASK;
360 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
361
362 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
363 mqe->hdr.pyld_len);
364 return mqe;
365 }
366
367 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
368 {
369 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
370 }
371
372 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
373 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
374 {
375 memset(q, 0, sizeof(*q));
376 q->len = len;
377 q->entry_size = entry_size;
378 q->size = len * entry_size;
379 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
380 &q->dma, GFP_KERNEL);
381 if (!q->va)
382 return -ENOMEM;
383 memset(q->va, 0, q->size);
384 return 0;
385 }
386
387 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
388 dma_addr_t host_pa, int hw_page_size)
389 {
390 int i;
391
392 for (i = 0; i < cnt; i++) {
393 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
394 q_pa[i].hi = (u32) upper_32_bits(host_pa);
395 host_pa += hw_page_size;
396 }
397 }
398
399 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
400 struct ocrdma_queue_info *q, int queue_type)
401 {
402 u8 opcode = 0;
403 int status;
404 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
405
406 switch (queue_type) {
407 case QTYPE_MCCQ:
408 opcode = OCRDMA_CMD_DELETE_MQ;
409 break;
410 case QTYPE_CQ:
411 opcode = OCRDMA_CMD_DELETE_CQ;
412 break;
413 case QTYPE_EQ:
414 opcode = OCRDMA_CMD_DELETE_EQ;
415 break;
416 default:
417 BUG();
418 }
419 memset(cmd, 0, sizeof(*cmd));
420 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
421 cmd->id = q->id;
422
423 status = be_roce_mcc_cmd(dev->nic_info.netdev,
424 cmd, sizeof(*cmd), NULL, NULL);
425 if (!status)
426 q->created = false;
427 return status;
428 }
429
430 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
431 {
432 int status;
433 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
434 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
435
436 memset(cmd, 0, sizeof(*cmd));
437 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
438 sizeof(*cmd));
439
440 cmd->req.rsvd_version = 2;
441 cmd->num_pages = 4;
442 cmd->valid = OCRDMA_CREATE_EQ_VALID;
443 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
444
445 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
446 PAGE_SIZE_4K);
447 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
448 NULL);
449 if (!status) {
450 eq->q.id = rsp->vector_eqid & 0xffff;
451 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
452 eq->q.created = true;
453 }
454 return status;
455 }
456
457 static int ocrdma_create_eq(struct ocrdma_dev *dev,
458 struct ocrdma_eq *eq, u16 q_len)
459 {
460 int status;
461
462 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
463 sizeof(struct ocrdma_eqe));
464 if (status)
465 return status;
466
467 status = ocrdma_mbx_create_eq(dev, eq);
468 if (status)
469 goto mbx_err;
470 eq->dev = dev;
471 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
472
473 return 0;
474 mbx_err:
475 ocrdma_free_q(dev, &eq->q);
476 return status;
477 }
478
479 int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
480 {
481 int irq;
482
483 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
484 irq = dev->nic_info.pdev->irq;
485 else
486 irq = dev->nic_info.msix.vector_list[eq->vector];
487 return irq;
488 }
489
490 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
491 {
492 if (eq->q.created) {
493 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
494 ocrdma_free_q(dev, &eq->q);
495 }
496 }
497
498 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
499 {
500 int irq;
501
502 /* disarm EQ so that interrupts are not generated
503 * during freeing and EQ delete is in progress.
504 */
505 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
506
507 irq = ocrdma_get_irq(dev, eq);
508 free_irq(irq, eq);
509 _ocrdma_destroy_eq(dev, eq);
510 }
511
512 static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
513 {
514 int i;
515
516 for (i = 0; i < dev->eq_cnt; i++)
517 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
518 }
519
520 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
521 struct ocrdma_queue_info *cq,
522 struct ocrdma_queue_info *eq)
523 {
524 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
525 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
526 int status;
527
528 memset(cmd, 0, sizeof(*cmd));
529 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
530 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
531
532 cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
533 cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
534 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
535 cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
536
537 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
538 cmd->eqn = eq->id;
539 cmd->pdid_cqecnt = cq->size / sizeof(struct ocrdma_mcqe);
540
541 ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
542 cq->dma, PAGE_SIZE_4K);
543 status = be_roce_mcc_cmd(dev->nic_info.netdev,
544 cmd, sizeof(*cmd), NULL, NULL);
545 if (!status) {
546 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
547 cq->created = true;
548 }
549 return status;
550 }
551
552 static u32 ocrdma_encoded_q_len(int q_len)
553 {
554 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
555
556 if (len_encoded == 16)
557 len_encoded = 0;
558 return len_encoded;
559 }
560
561 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
562 struct ocrdma_queue_info *mq,
563 struct ocrdma_queue_info *cq)
564 {
565 int num_pages, status;
566 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
567 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
568 struct ocrdma_pa *pa;
569
570 memset(cmd, 0, sizeof(*cmd));
571 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
572
573 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
574 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
575 cmd->req.rsvd_version = 1;
576 cmd->cqid_pages = num_pages;
577 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
578 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
579
580 cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE);
581 cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE);
582 /* Request link events on this MQ. */
583 cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_LINK_EVE_CODE);
584
585 cmd->async_cqid_ringsize = cq->id;
586 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
587 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
588 cmd->valid = OCRDMA_CREATE_MQ_VALID;
589 pa = &cmd->pa[0];
590
591 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
592 status = be_roce_mcc_cmd(dev->nic_info.netdev,
593 cmd, sizeof(*cmd), NULL, NULL);
594 if (!status) {
595 mq->id = rsp->id;
596 mq->created = true;
597 }
598 return status;
599 }
600
601 static int ocrdma_create_mq(struct ocrdma_dev *dev)
602 {
603 int status;
604
605 /* Alloc completion queue for Mailbox queue */
606 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
607 sizeof(struct ocrdma_mcqe));
608 if (status)
609 goto alloc_err;
610
611 dev->eq_tbl[0].cq_cnt++;
612 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
613 if (status)
614 goto mbx_cq_free;
615
616 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
617 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
618 mutex_init(&dev->mqe_ctx.lock);
619
620 /* Alloc Mailbox queue */
621 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
622 sizeof(struct ocrdma_mqe));
623 if (status)
624 goto mbx_cq_destroy;
625 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
626 if (status)
627 goto mbx_q_free;
628 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
629 return 0;
630
631 mbx_q_free:
632 ocrdma_free_q(dev, &dev->mq.sq);
633 mbx_cq_destroy:
634 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
635 mbx_cq_free:
636 ocrdma_free_q(dev, &dev->mq.cq);
637 alloc_err:
638 return status;
639 }
640
641 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
642 {
643 struct ocrdma_queue_info *mbxq, *cq;
644
645 /* mqe_ctx lock synchronizes with any other pending cmds. */
646 mutex_lock(&dev->mqe_ctx.lock);
647 mbxq = &dev->mq.sq;
648 if (mbxq->created) {
649 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
650 ocrdma_free_q(dev, mbxq);
651 }
652 mutex_unlock(&dev->mqe_ctx.lock);
653
654 cq = &dev->mq.cq;
655 if (cq->created) {
656 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
657 ocrdma_free_q(dev, cq);
658 }
659 }
660
661 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
662 struct ocrdma_qp *qp)
663 {
664 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
665 enum ib_qp_state old_ib_qps;
666
667 if (qp == NULL)
668 BUG();
669 ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
670 }
671
672 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
673 struct ocrdma_ae_mcqe *cqe)
674 {
675 struct ocrdma_qp *qp = NULL;
676 struct ocrdma_cq *cq = NULL;
677 struct ib_event ib_evt;
678 int cq_event = 0;
679 int qp_event = 1;
680 int srq_event = 0;
681 int dev_event = 0;
682 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
683 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
684 u16 qpid = cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK;
685 u16 cqid = cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK;
686
687 /*
688 * Some FW version returns wrong qp or cq ids in CQEs.
689 * Checking whether the IDs are valid
690 */
691
692 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID) {
693 if (qpid < dev->attr.max_qp)
694 qp = dev->qp_tbl[qpid];
695 if (qp == NULL) {
696 pr_err("ocrdma%d:Async event - qpid %u is not valid\n",
697 dev->id, qpid);
698 return;
699 }
700 }
701
702 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID) {
703 if (cqid < dev->attr.max_cq)
704 cq = dev->cq_tbl[cqid];
705 if (cq == NULL) {
706 pr_err("ocrdma%d:Async event - cqid %u is not valid\n",
707 dev->id, cqid);
708 return;
709 }
710 }
711
712 memset(&ib_evt, 0, sizeof(ib_evt));
713
714 ib_evt.device = &dev->ibdev;
715
716 switch (type) {
717 case OCRDMA_CQ_ERROR:
718 ib_evt.element.cq = &cq->ibcq;
719 ib_evt.event = IB_EVENT_CQ_ERR;
720 cq_event = 1;
721 qp_event = 0;
722 break;
723 case OCRDMA_CQ_OVERRUN_ERROR:
724 ib_evt.element.cq = &cq->ibcq;
725 ib_evt.event = IB_EVENT_CQ_ERR;
726 cq_event = 1;
727 qp_event = 0;
728 break;
729 case OCRDMA_CQ_QPCAT_ERROR:
730 ib_evt.element.qp = &qp->ibqp;
731 ib_evt.event = IB_EVENT_QP_FATAL;
732 ocrdma_process_qpcat_error(dev, qp);
733 break;
734 case OCRDMA_QP_ACCESS_ERROR:
735 ib_evt.element.qp = &qp->ibqp;
736 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
737 break;
738 case OCRDMA_QP_COMM_EST_EVENT:
739 ib_evt.element.qp = &qp->ibqp;
740 ib_evt.event = IB_EVENT_COMM_EST;
741 break;
742 case OCRDMA_SQ_DRAINED_EVENT:
743 ib_evt.element.qp = &qp->ibqp;
744 ib_evt.event = IB_EVENT_SQ_DRAINED;
745 break;
746 case OCRDMA_DEVICE_FATAL_EVENT:
747 ib_evt.element.port_num = 1;
748 ib_evt.event = IB_EVENT_DEVICE_FATAL;
749 qp_event = 0;
750 dev_event = 1;
751 break;
752 case OCRDMA_SRQCAT_ERROR:
753 ib_evt.element.srq = &qp->srq->ibsrq;
754 ib_evt.event = IB_EVENT_SRQ_ERR;
755 srq_event = 1;
756 qp_event = 0;
757 break;
758 case OCRDMA_SRQ_LIMIT_EVENT:
759 ib_evt.element.srq = &qp->srq->ibsrq;
760 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
761 srq_event = 1;
762 qp_event = 0;
763 break;
764 case OCRDMA_QP_LAST_WQE_EVENT:
765 ib_evt.element.qp = &qp->ibqp;
766 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
767 break;
768 default:
769 cq_event = 0;
770 qp_event = 0;
771 srq_event = 0;
772 dev_event = 0;
773 pr_err("%s() unknown type=0x%x\n", __func__, type);
774 break;
775 }
776
777 if (type < OCRDMA_MAX_ASYNC_ERRORS)
778 atomic_inc(&dev->async_err_stats[type]);
779
780 if (qp_event) {
781 if (qp->ibqp.event_handler)
782 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
783 } else if (cq_event) {
784 if (cq->ibcq.event_handler)
785 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
786 } else if (srq_event) {
787 if (qp->srq->ibsrq.event_handler)
788 qp->srq->ibsrq.event_handler(&ib_evt,
789 qp->srq->ibsrq.
790 srq_context);
791 } else if (dev_event) {
792 pr_err("%s: Fatal event received\n", dev->ibdev.name);
793 ib_dispatch_event(&ib_evt);
794 }
795
796 }
797
798 static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
799 struct ocrdma_ae_mcqe *cqe)
800 {
801 struct ocrdma_ae_pvid_mcqe *evt;
802 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
803 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
804
805 switch (type) {
806 case OCRDMA_ASYNC_EVENT_PVID_STATE:
807 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
808 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
809 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
810 dev->pvid = ((evt->tag_enabled &
811 OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
812 OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
813 break;
814
815 case OCRDMA_ASYNC_EVENT_COS_VALUE:
816 atomic_set(&dev->update_sl, 1);
817 break;
818 default:
819 /* Not interested evts. */
820 break;
821 }
822 }
823
824 static void ocrdma_process_link_state(struct ocrdma_dev *dev,
825 struct ocrdma_ae_mcqe *cqe)
826 {
827 struct ocrdma_ae_lnkst_mcqe *evt;
828 u8 lstate;
829
830 evt = (struct ocrdma_ae_lnkst_mcqe *)cqe;
831 lstate = ocrdma_get_ae_link_state(evt->speed_state_ptn);
832
833 if (!(lstate & OCRDMA_AE_LSC_LLINK_MASK))
834 return;
835
836 if (dev->flags & OCRDMA_FLAGS_LINK_STATUS_INIT)
837 ocrdma_update_link_state(dev, (lstate & OCRDMA_LINK_ST_MASK));
838 }
839
840 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
841 {
842 /* async CQE processing */
843 struct ocrdma_ae_mcqe *cqe = ae_cqe;
844 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
845 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
846 switch (evt_code) {
847 case OCRDMA_ASYNC_LINK_EVE_CODE:
848 ocrdma_process_link_state(dev, cqe);
849 break;
850 case OCRDMA_ASYNC_RDMA_EVE_CODE:
851 ocrdma_dispatch_ibevent(dev, cqe);
852 break;
853 case OCRDMA_ASYNC_GRP5_EVE_CODE:
854 ocrdma_process_grp5_aync(dev, cqe);
855 break;
856 default:
857 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
858 dev->id, evt_code);
859 }
860 }
861
862 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
863 {
864 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
865 dev->mqe_ctx.cqe_status = (cqe->status &
866 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
867 dev->mqe_ctx.ext_status =
868 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
869 >> OCRDMA_MCQE_ESTATUS_SHIFT;
870 dev->mqe_ctx.cmd_done = true;
871 wake_up(&dev->mqe_ctx.cmd_wait);
872 } else
873 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
874 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
875 }
876
877 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
878 {
879 u16 cqe_popped = 0;
880 struct ocrdma_mcqe *cqe;
881
882 while (1) {
883 cqe = ocrdma_get_mcqe(dev);
884 if (cqe == NULL)
885 break;
886 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
887 cqe_popped += 1;
888 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
889 ocrdma_process_acqe(dev, cqe);
890 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
891 ocrdma_process_mcqe(dev, cqe);
892 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
893 ocrdma_mcq_inc_tail(dev);
894 }
895 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
896 return 0;
897 }
898
899 static struct ocrdma_cq *_ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
900 struct ocrdma_cq *cq, bool sq)
901 {
902 struct ocrdma_qp *qp;
903 struct list_head *cur;
904 struct ocrdma_cq *bcq = NULL;
905 struct list_head *head = sq?(&cq->sq_head):(&cq->rq_head);
906
907 list_for_each(cur, head) {
908 if (sq)
909 qp = list_entry(cur, struct ocrdma_qp, sq_entry);
910 else
911 qp = list_entry(cur, struct ocrdma_qp, rq_entry);
912
913 if (qp->srq)
914 continue;
915 /* if wq and rq share the same cq, than comp_handler
916 * is already invoked.
917 */
918 if (qp->sq_cq == qp->rq_cq)
919 continue;
920 /* if completion came on sq, rq's cq is buddy cq.
921 * if completion came on rq, sq's cq is buddy cq.
922 */
923 if (qp->sq_cq == cq)
924 bcq = qp->rq_cq;
925 else
926 bcq = qp->sq_cq;
927 return bcq;
928 }
929 return NULL;
930 }
931
932 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
933 struct ocrdma_cq *cq)
934 {
935 unsigned long flags;
936 struct ocrdma_cq *bcq = NULL;
937
938 /* Go through list of QPs in error state which are using this CQ
939 * and invoke its callback handler to trigger CQE processing for
940 * error/flushed CQE. It is rare to find more than few entries in
941 * this list as most consumers stops after getting error CQE.
942 * List is traversed only once when a matching buddy cq found for a QP.
943 */
944 spin_lock_irqsave(&dev->flush_q_lock, flags);
945 /* Check if buddy CQ is present.
946 * true - Check for SQ CQ
947 * false - Check for RQ CQ
948 */
949 bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, true);
950 if (bcq == NULL)
951 bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, false);
952 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
953
954 /* if there is valid buddy cq, look for its completion handler */
955 if (bcq && bcq->ibcq.comp_handler) {
956 spin_lock_irqsave(&bcq->comp_handler_lock, flags);
957 (*bcq->ibcq.comp_handler) (&bcq->ibcq, bcq->ibcq.cq_context);
958 spin_unlock_irqrestore(&bcq->comp_handler_lock, flags);
959 }
960 }
961
962 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
963 {
964 unsigned long flags;
965 struct ocrdma_cq *cq;
966
967 if (cq_idx >= OCRDMA_MAX_CQ)
968 BUG();
969
970 cq = dev->cq_tbl[cq_idx];
971 if (cq == NULL)
972 return;
973
974 if (cq->ibcq.comp_handler) {
975 spin_lock_irqsave(&cq->comp_handler_lock, flags);
976 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
977 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
978 }
979 ocrdma_qp_buddy_cq_handler(dev, cq);
980 }
981
982 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
983 {
984 /* process the MQ-CQE. */
985 if (cq_id == dev->mq.cq.id)
986 ocrdma_mq_cq_handler(dev, cq_id);
987 else
988 ocrdma_qp_cq_handler(dev, cq_id);
989 }
990
991 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
992 {
993 struct ocrdma_eq *eq = handle;
994 struct ocrdma_dev *dev = eq->dev;
995 struct ocrdma_eqe eqe;
996 struct ocrdma_eqe *ptr;
997 u16 cq_id;
998 u8 mcode;
999 int budget = eq->cq_cnt;
1000
1001 do {
1002 ptr = ocrdma_get_eqe(eq);
1003 eqe = *ptr;
1004 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
1005 mcode = (eqe.id_valid & OCRDMA_EQE_MAJOR_CODE_MASK)
1006 >> OCRDMA_EQE_MAJOR_CODE_SHIFT;
1007 if (mcode == OCRDMA_MAJOR_CODE_SENTINAL)
1008 pr_err("EQ full on eqid = 0x%x, eqe = 0x%x\n",
1009 eq->q.id, eqe.id_valid);
1010 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
1011 break;
1012
1013 ptr->id_valid = 0;
1014 /* ring eq doorbell as soon as its consumed. */
1015 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
1016 /* check whether its CQE or not. */
1017 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
1018 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
1019 ocrdma_cq_handler(dev, cq_id);
1020 }
1021 ocrdma_eq_inc_tail(eq);
1022
1023 /* There can be a stale EQE after the last bound CQ is
1024 * destroyed. EQE valid and budget == 0 implies this.
1025 */
1026 if (budget)
1027 budget--;
1028
1029 } while (budget);
1030
1031 eq->aic_obj.eq_intr_cnt++;
1032 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
1033 return IRQ_HANDLED;
1034 }
1035
1036 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
1037 {
1038 struct ocrdma_mqe *mqe;
1039
1040 dev->mqe_ctx.tag = dev->mq.sq.head;
1041 dev->mqe_ctx.cmd_done = false;
1042 mqe = ocrdma_get_mqe(dev);
1043 cmd->hdr.tag_lo = dev->mq.sq.head;
1044 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
1045 /* make sure descriptor is written before ringing doorbell */
1046 wmb();
1047 ocrdma_mq_inc_head(dev);
1048 ocrdma_ring_mq_db(dev);
1049 }
1050
1051 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
1052 {
1053 long status;
1054 /* 30 sec timeout */
1055 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
1056 (dev->mqe_ctx.cmd_done != false),
1057 msecs_to_jiffies(30000));
1058 if (status)
1059 return 0;
1060 else {
1061 dev->mqe_ctx.fw_error_state = true;
1062 pr_err("%s(%d) mailbox timeout: fw not responding\n",
1063 __func__, dev->id);
1064 return -1;
1065 }
1066 }
1067
1068 /* issue a mailbox command on the MQ */
1069 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
1070 {
1071 int status = 0;
1072 u16 cqe_status, ext_status;
1073 struct ocrdma_mqe *rsp_mqe;
1074 struct ocrdma_mbx_rsp *rsp = NULL;
1075
1076 mutex_lock(&dev->mqe_ctx.lock);
1077 if (dev->mqe_ctx.fw_error_state)
1078 goto mbx_err;
1079 ocrdma_post_mqe(dev, mqe);
1080 status = ocrdma_wait_mqe_cmpl(dev);
1081 if (status)
1082 goto mbx_err;
1083 cqe_status = dev->mqe_ctx.cqe_status;
1084 ext_status = dev->mqe_ctx.ext_status;
1085 rsp_mqe = ocrdma_get_mqe_rsp(dev);
1086 ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
1087 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1088 OCRDMA_MQE_HDR_EMB_SHIFT)
1089 rsp = &mqe->u.rsp;
1090
1091 if (cqe_status || ext_status) {
1092 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
1093 __func__, cqe_status, ext_status);
1094 if (rsp) {
1095 /* This is for embedded cmds. */
1096 pr_err("opcode=0x%x, subsystem=0x%x\n",
1097 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1098 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1099 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1100 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1101 }
1102 status = ocrdma_get_mbx_cqe_errno(cqe_status);
1103 goto mbx_err;
1104 }
1105 /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1106 if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
1107 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1108 mbx_err:
1109 mutex_unlock(&dev->mqe_ctx.lock);
1110 return status;
1111 }
1112
1113 static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1114 void *payload_va)
1115 {
1116 int status = 0;
1117 struct ocrdma_mbx_rsp *rsp = payload_va;
1118
1119 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1120 OCRDMA_MQE_HDR_EMB_SHIFT)
1121 BUG();
1122
1123 status = ocrdma_mbx_cmd(dev, mqe);
1124 if (!status)
1125 /* For non embedded, only CQE failures are handled in
1126 * ocrdma_mbx_cmd. We need to check for RSP errors.
1127 */
1128 if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1129 status = ocrdma_get_mbx_errno(rsp->status);
1130
1131 if (status)
1132 pr_err("opcode=0x%x, subsystem=0x%x\n",
1133 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1134 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1135 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1136 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1137 return status;
1138 }
1139
1140 static void ocrdma_get_attr(struct ocrdma_dev *dev,
1141 struct ocrdma_dev_attr *attr,
1142 struct ocrdma_mbx_query_config *rsp)
1143 {
1144 attr->max_pd =
1145 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1146 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
1147 attr->max_dpp_pds =
1148 (rsp->max_dpp_pds_credits & OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK) >>
1149 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET;
1150 attr->max_qp =
1151 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1152 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
1153 attr->max_srq =
1154 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1155 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
1156 attr->max_send_sge = ((rsp->max_write_send_sge &
1157 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1158 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1159 attr->max_recv_sge = (rsp->max_write_send_sge &
1160 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1161 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
1162 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1163 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1164 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
1165 attr->max_rdma_sge = (rsp->max_write_send_sge &
1166 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
1167 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
1168 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1169 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1170 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1171 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1172 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1173 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1174 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1175 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1176 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1177 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1178 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1179 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1180 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1181 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1182 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1183 attr->max_mw = rsp->max_mw;
1184 attr->max_mr = rsp->max_mr;
1185 attr->max_mr_size = ((u64)rsp->max_mr_size_hi << 32) |
1186 rsp->max_mr_size_lo;
1187 attr->max_fmr = 0;
1188 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1189 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1190 attr->max_cqe = rsp->max_cq_cqes_per_cq &
1191 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1192 attr->max_cq = (rsp->max_cq_cqes_per_cq &
1193 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1194 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
1195 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1196 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1197 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1198 OCRDMA_WQE_STRIDE;
1199 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1200 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1201 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1202 OCRDMA_WQE_STRIDE;
1203 attr->max_inline_data =
1204 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1205 sizeof(struct ocrdma_sge));
1206 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1207 attr->ird = 1;
1208 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1209 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1210 }
1211 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1212 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1213 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1214 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1215 }
1216
1217 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1218 struct ocrdma_fw_conf_rsp *conf)
1219 {
1220 u32 fn_mode;
1221
1222 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1223 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1224 return -EINVAL;
1225 dev->base_eqid = conf->base_eqid;
1226 dev->max_eq = conf->max_eq;
1227 return 0;
1228 }
1229
1230 /* can be issued only during init time. */
1231 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1232 {
1233 int status = -ENOMEM;
1234 struct ocrdma_mqe *cmd;
1235 struct ocrdma_fw_ver_rsp *rsp;
1236
1237 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1238 if (!cmd)
1239 return -ENOMEM;
1240 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1241 OCRDMA_CMD_GET_FW_VER,
1242 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1243
1244 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1245 if (status)
1246 goto mbx_err;
1247 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1248 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1249 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1250 sizeof(rsp->running_ver));
1251 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1252 mbx_err:
1253 kfree(cmd);
1254 return status;
1255 }
1256
1257 /* can be issued only during init time. */
1258 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1259 {
1260 int status = -ENOMEM;
1261 struct ocrdma_mqe *cmd;
1262 struct ocrdma_fw_conf_rsp *rsp;
1263
1264 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1265 if (!cmd)
1266 return -ENOMEM;
1267 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1268 OCRDMA_CMD_GET_FW_CONFIG,
1269 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1270 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1271 if (status)
1272 goto mbx_err;
1273 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1274 status = ocrdma_check_fw_config(dev, rsp);
1275 mbx_err:
1276 kfree(cmd);
1277 return status;
1278 }
1279
1280 int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1281 {
1282 struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1283 struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
1284 struct ocrdma_rdma_stats_resp *old_stats;
1285 int status;
1286
1287 old_stats = kmalloc(sizeof(*old_stats), GFP_KERNEL);
1288 if (old_stats == NULL)
1289 return -ENOMEM;
1290
1291 memset(mqe, 0, sizeof(*mqe));
1292 mqe->hdr.pyld_len = dev->stats_mem.size;
1293 mqe->hdr.spcl_sge_cnt_emb |=
1294 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1295 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1296 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1297 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1298 mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1299
1300 /* Cache the old stats */
1301 memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1302 memset(req, 0, dev->stats_mem.size);
1303
1304 ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1305 OCRDMA_CMD_GET_RDMA_STATS,
1306 OCRDMA_SUBSYS_ROCE,
1307 dev->stats_mem.size);
1308 if (reset)
1309 req->reset_stats = reset;
1310
1311 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1312 if (status)
1313 /* Copy from cache, if mbox fails */
1314 memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1315 else
1316 ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1317
1318 kfree(old_stats);
1319 return status;
1320 }
1321
1322 static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1323 {
1324 int status = -ENOMEM;
1325 struct ocrdma_dma_mem dma;
1326 struct ocrdma_mqe *mqe;
1327 struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1328 struct mgmt_hba_attribs *hba_attribs;
1329
1330 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
1331 if (!mqe)
1332 return status;
1333
1334 dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1335 dma.va = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1336 dma.size, &dma.pa, GFP_KERNEL);
1337 if (!dma.va)
1338 goto free_mqe;
1339
1340 mqe->hdr.pyld_len = dma.size;
1341 mqe->hdr.spcl_sge_cnt_emb |=
1342 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1343 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1344 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1345 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1346 mqe->u.nonemb_req.sge[0].len = dma.size;
1347
1348 memset(dma.va, 0, dma.size);
1349 ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1350 OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1351 OCRDMA_SUBSYS_COMMON,
1352 dma.size);
1353
1354 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1355 if (!status) {
1356 ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1357 hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1358
1359 dev->hba_port_num = (hba_attribs->ptpnum_maxdoms_hbast_cv &
1360 OCRDMA_HBA_ATTRB_PTNUM_MASK)
1361 >> OCRDMA_HBA_ATTRB_PTNUM_SHIFT;
1362 strncpy(dev->model_number,
1363 hba_attribs->controller_model_number, 31);
1364 }
1365 dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1366 free_mqe:
1367 kfree(mqe);
1368 return status;
1369 }
1370
1371 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1372 {
1373 int status = -ENOMEM;
1374 struct ocrdma_mbx_query_config *rsp;
1375 struct ocrdma_mqe *cmd;
1376
1377 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1378 if (!cmd)
1379 return status;
1380 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1381 if (status)
1382 goto mbx_err;
1383 rsp = (struct ocrdma_mbx_query_config *)cmd;
1384 ocrdma_get_attr(dev, &dev->attr, rsp);
1385 mbx_err:
1386 kfree(cmd);
1387 return status;
1388 }
1389
1390 int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed,
1391 u8 *lnk_state)
1392 {
1393 int status = -ENOMEM;
1394 struct ocrdma_get_link_speed_rsp *rsp;
1395 struct ocrdma_mqe *cmd;
1396
1397 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1398 sizeof(*cmd));
1399 if (!cmd)
1400 return status;
1401 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1402 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1403 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1404
1405 ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1406
1407 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1408 if (status)
1409 goto mbx_err;
1410
1411 rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1412 if (lnk_speed)
1413 *lnk_speed = (rsp->pflt_pps_ld_pnum & OCRDMA_PHY_PS_MASK)
1414 >> OCRDMA_PHY_PS_SHIFT;
1415 if (lnk_state)
1416 *lnk_state = (rsp->res_lnk_st & OCRDMA_LINK_ST_MASK);
1417
1418 mbx_err:
1419 kfree(cmd);
1420 return status;
1421 }
1422
1423 static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1424 {
1425 int status = -ENOMEM;
1426 struct ocrdma_mqe *cmd;
1427 struct ocrdma_get_phy_info_rsp *rsp;
1428
1429 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1430 if (!cmd)
1431 return status;
1432
1433 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1434 OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1435 sizeof(*cmd));
1436
1437 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1438 if (status)
1439 goto mbx_err;
1440
1441 rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
1442 dev->phy.phy_type =
1443 (rsp->ityp_ptyp & OCRDMA_PHY_TYPE_MASK);
1444 dev->phy.interface_type =
1445 (rsp->ityp_ptyp & OCRDMA_IF_TYPE_MASK)
1446 >> OCRDMA_IF_TYPE_SHIFT;
1447 dev->phy.auto_speeds_supported =
1448 (rsp->fspeed_aspeed & OCRDMA_ASPEED_SUPP_MASK);
1449 dev->phy.fixed_speeds_supported =
1450 (rsp->fspeed_aspeed & OCRDMA_FSPEED_SUPP_MASK)
1451 >> OCRDMA_FSPEED_SUPP_SHIFT;
1452 mbx_err:
1453 kfree(cmd);
1454 return status;
1455 }
1456
1457 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1458 {
1459 int status = -ENOMEM;
1460 struct ocrdma_alloc_pd *cmd;
1461 struct ocrdma_alloc_pd_rsp *rsp;
1462
1463 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1464 if (!cmd)
1465 return status;
1466 if (pd->dpp_enabled)
1467 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1468 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1469 if (status)
1470 goto mbx_err;
1471 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1472 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1473 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1474 pd->dpp_enabled = true;
1475 pd->dpp_page = rsp->dpp_page_pdid >>
1476 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1477 } else {
1478 pd->dpp_enabled = false;
1479 pd->num_dpp_qp = 0;
1480 }
1481 mbx_err:
1482 kfree(cmd);
1483 return status;
1484 }
1485
1486 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1487 {
1488 int status = -ENOMEM;
1489 struct ocrdma_dealloc_pd *cmd;
1490
1491 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1492 if (!cmd)
1493 return status;
1494 cmd->id = pd->id;
1495 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1496 kfree(cmd);
1497 return status;
1498 }
1499
1500
1501 static int ocrdma_mbx_alloc_pd_range(struct ocrdma_dev *dev)
1502 {
1503 int status = -ENOMEM;
1504 size_t pd_bitmap_size;
1505 struct ocrdma_alloc_pd_range *cmd;
1506 struct ocrdma_alloc_pd_range_rsp *rsp;
1507
1508 /* Pre allocate the DPP PDs */
1509 if (dev->attr.max_dpp_pds) {
1510 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE,
1511 sizeof(*cmd));
1512 if (!cmd)
1513 return -ENOMEM;
1514 cmd->pd_count = dev->attr.max_dpp_pds;
1515 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1516 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1517 rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1518
1519 if (!status && (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) &&
1520 rsp->pd_count) {
1521 dev->pd_mgr->dpp_page_index = rsp->dpp_page_pdid >>
1522 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1523 dev->pd_mgr->pd_dpp_start = rsp->dpp_page_pdid &
1524 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1525 dev->pd_mgr->max_dpp_pd = rsp->pd_count;
1526 pd_bitmap_size =
1527 BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1528 dev->pd_mgr->pd_dpp_bitmap = kzalloc(pd_bitmap_size,
1529 GFP_KERNEL);
1530 }
1531 kfree(cmd);
1532 }
1533
1534 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd));
1535 if (!cmd)
1536 return -ENOMEM;
1537
1538 cmd->pd_count = dev->attr.max_pd - dev->attr.max_dpp_pds;
1539 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1540 rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1541 if (!status && rsp->pd_count) {
1542 dev->pd_mgr->pd_norm_start = rsp->dpp_page_pdid &
1543 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1544 dev->pd_mgr->max_normal_pd = rsp->pd_count;
1545 pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1546 dev->pd_mgr->pd_norm_bitmap = kzalloc(pd_bitmap_size,
1547 GFP_KERNEL);
1548 }
1549 kfree(cmd);
1550
1551 if (dev->pd_mgr->pd_norm_bitmap || dev->pd_mgr->pd_dpp_bitmap) {
1552 /* Enable PD resource manager */
1553 dev->pd_mgr->pd_prealloc_valid = true;
1554 return 0;
1555 }
1556 return status;
1557 }
1558
1559 static void ocrdma_mbx_dealloc_pd_range(struct ocrdma_dev *dev)
1560 {
1561 struct ocrdma_dealloc_pd_range *cmd;
1562
1563 /* return normal PDs to firmware */
1564 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE, sizeof(*cmd));
1565 if (!cmd)
1566 goto mbx_err;
1567
1568 if (dev->pd_mgr->max_normal_pd) {
1569 cmd->start_pd_id = dev->pd_mgr->pd_norm_start;
1570 cmd->pd_count = dev->pd_mgr->max_normal_pd;
1571 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1572 }
1573
1574 if (dev->pd_mgr->max_dpp_pd) {
1575 kfree(cmd);
1576 /* return DPP PDs to firmware */
1577 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE,
1578 sizeof(*cmd));
1579 if (!cmd)
1580 goto mbx_err;
1581
1582 cmd->start_pd_id = dev->pd_mgr->pd_dpp_start;
1583 cmd->pd_count = dev->pd_mgr->max_dpp_pd;
1584 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1585 }
1586 mbx_err:
1587 kfree(cmd);
1588 }
1589
1590 void ocrdma_alloc_pd_pool(struct ocrdma_dev *dev)
1591 {
1592 int status;
1593
1594 dev->pd_mgr = kzalloc(sizeof(struct ocrdma_pd_resource_mgr),
1595 GFP_KERNEL);
1596 if (!dev->pd_mgr) {
1597 pr_err("%s(%d)Memory allocation failure.\n", __func__, dev->id);
1598 return;
1599 }
1600 status = ocrdma_mbx_alloc_pd_range(dev);
1601 if (status) {
1602 pr_err("%s(%d) Unable to initialize PD pool, using default.\n",
1603 __func__, dev->id);
1604 }
1605 }
1606
1607 static void ocrdma_free_pd_pool(struct ocrdma_dev *dev)
1608 {
1609 ocrdma_mbx_dealloc_pd_range(dev);
1610 kfree(dev->pd_mgr->pd_norm_bitmap);
1611 kfree(dev->pd_mgr->pd_dpp_bitmap);
1612 kfree(dev->pd_mgr);
1613 }
1614
1615 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1616 int *num_pages, int *page_size)
1617 {
1618 int i;
1619 int mem_size;
1620
1621 *num_entries = roundup_pow_of_two(*num_entries);
1622 mem_size = *num_entries * entry_size;
1623 /* find the possible lowest possible multiplier */
1624 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1625 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1626 break;
1627 }
1628 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1629 return -EINVAL;
1630 mem_size = roundup(mem_size,
1631 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1632 *num_pages =
1633 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1634 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1635 *num_entries = mem_size / entry_size;
1636 return 0;
1637 }
1638
1639 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1640 {
1641 int i;
1642 int status = 0;
1643 int max_ah;
1644 struct ocrdma_create_ah_tbl *cmd;
1645 struct ocrdma_create_ah_tbl_rsp *rsp;
1646 struct pci_dev *pdev = dev->nic_info.pdev;
1647 dma_addr_t pa;
1648 struct ocrdma_pbe *pbes;
1649
1650 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1651 if (!cmd)
1652 return status;
1653
1654 max_ah = OCRDMA_MAX_AH;
1655 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1656
1657 /* number of PBEs in PBL */
1658 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1659 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1660 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1661
1662 /* page size */
1663 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1664 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1665 break;
1666 }
1667 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1668 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1669
1670 /* ah_entry size */
1671 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1672 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1673 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1674
1675 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1676 &dev->av_tbl.pbl.pa,
1677 GFP_KERNEL);
1678 if (dev->av_tbl.pbl.va == NULL)
1679 goto mem_err;
1680
1681 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1682 &pa, GFP_KERNEL);
1683 if (dev->av_tbl.va == NULL)
1684 goto mem_err_ah;
1685 dev->av_tbl.pa = pa;
1686 dev->av_tbl.num_ah = max_ah;
1687 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1688
1689 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1690 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1691 pbes[i].pa_lo = (u32)cpu_to_le32(pa & 0xffffffff);
1692 pbes[i].pa_hi = (u32)cpu_to_le32(upper_32_bits(pa));
1693 pa += PAGE_SIZE;
1694 }
1695 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1696 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1697 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1698 if (status)
1699 goto mbx_err;
1700 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1701 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1702 kfree(cmd);
1703 return 0;
1704
1705 mbx_err:
1706 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1707 dev->av_tbl.pa);
1708 dev->av_tbl.va = NULL;
1709 mem_err_ah:
1710 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1711 dev->av_tbl.pbl.pa);
1712 dev->av_tbl.pbl.va = NULL;
1713 dev->av_tbl.size = 0;
1714 mem_err:
1715 kfree(cmd);
1716 return status;
1717 }
1718
1719 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1720 {
1721 struct ocrdma_delete_ah_tbl *cmd;
1722 struct pci_dev *pdev = dev->nic_info.pdev;
1723
1724 if (dev->av_tbl.va == NULL)
1725 return;
1726
1727 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1728 if (!cmd)
1729 return;
1730 cmd->ahid = dev->av_tbl.ahid;
1731
1732 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1733 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1734 dev->av_tbl.pa);
1735 dev->av_tbl.va = NULL;
1736 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1737 dev->av_tbl.pbl.pa);
1738 kfree(cmd);
1739 }
1740
1741 /* Multiple CQs uses the EQ. This routine returns least used
1742 * EQ to associate with CQ. This will distributes the interrupt
1743 * processing and CPU load to associated EQ, vector and so to that CPU.
1744 */
1745 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1746 {
1747 int i, selected_eq = 0, cq_cnt = 0;
1748 u16 eq_id;
1749
1750 mutex_lock(&dev->dev_lock);
1751 cq_cnt = dev->eq_tbl[0].cq_cnt;
1752 eq_id = dev->eq_tbl[0].q.id;
1753 /* find the EQ which is has the least number of
1754 * CQs associated with it.
1755 */
1756 for (i = 0; i < dev->eq_cnt; i++) {
1757 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1758 cq_cnt = dev->eq_tbl[i].cq_cnt;
1759 eq_id = dev->eq_tbl[i].q.id;
1760 selected_eq = i;
1761 }
1762 }
1763 dev->eq_tbl[selected_eq].cq_cnt += 1;
1764 mutex_unlock(&dev->dev_lock);
1765 return eq_id;
1766 }
1767
1768 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1769 {
1770 int i;
1771
1772 mutex_lock(&dev->dev_lock);
1773 i = ocrdma_get_eq_table_index(dev, eq_id);
1774 if (i == -EINVAL)
1775 BUG();
1776 dev->eq_tbl[i].cq_cnt -= 1;
1777 mutex_unlock(&dev->dev_lock);
1778 }
1779
1780 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1781 int entries, int dpp_cq, u16 pd_id)
1782 {
1783 int status = -ENOMEM; int max_hw_cqe;
1784 struct pci_dev *pdev = dev->nic_info.pdev;
1785 struct ocrdma_create_cq *cmd;
1786 struct ocrdma_create_cq_rsp *rsp;
1787 u32 hw_pages, cqe_size, page_size, cqe_count;
1788
1789 if (entries > dev->attr.max_cqe) {
1790 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1791 __func__, dev->id, dev->attr.max_cqe, entries);
1792 return -EINVAL;
1793 }
1794 if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
1795 return -EINVAL;
1796
1797 if (dpp_cq) {
1798 cq->max_hw_cqe = 1;
1799 max_hw_cqe = 1;
1800 cqe_size = OCRDMA_DPP_CQE_SIZE;
1801 hw_pages = 1;
1802 } else {
1803 cq->max_hw_cqe = dev->attr.max_cqe;
1804 max_hw_cqe = dev->attr.max_cqe;
1805 cqe_size = sizeof(struct ocrdma_cqe);
1806 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1807 }
1808
1809 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1810
1811 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1812 if (!cmd)
1813 return -ENOMEM;
1814 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1815 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1816 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1817 if (!cq->va) {
1818 status = -ENOMEM;
1819 goto mem_err;
1820 }
1821 memset(cq->va, 0, cq->len);
1822 page_size = cq->len / hw_pages;
1823 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1824 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1825 cmd->cmd.pgsz_pgcnt |= hw_pages;
1826 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1827
1828 cq->eqn = ocrdma_bind_eq(dev);
1829 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
1830 cqe_count = cq->len / cqe_size;
1831 cq->cqe_cnt = cqe_count;
1832 if (cqe_count > 1024) {
1833 /* Set cnt to 3 to indicate more than 1024 cq entries */
1834 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1835 } else {
1836 u8 count = 0;
1837 switch (cqe_count) {
1838 case 256:
1839 count = 0;
1840 break;
1841 case 512:
1842 count = 1;
1843 break;
1844 case 1024:
1845 count = 2;
1846 break;
1847 default:
1848 goto mbx_err;
1849 }
1850 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1851 }
1852 /* shared eq between all the consumer cqs. */
1853 cmd->cmd.eqn = cq->eqn;
1854 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1855 if (dpp_cq)
1856 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1857 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1858 cq->phase_change = false;
1859 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size);
1860 } else {
1861 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size) - 1;
1862 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1863 cq->phase_change = true;
1864 }
1865
1866 /* pd_id valid only for v3 */
1867 cmd->cmd.pdid_cqecnt |= (pd_id <<
1868 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT);
1869 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1870 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1871 if (status)
1872 goto mbx_err;
1873
1874 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1875 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1876 kfree(cmd);
1877 return 0;
1878 mbx_err:
1879 ocrdma_unbind_eq(dev, cq->eqn);
1880 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1881 mem_err:
1882 kfree(cmd);
1883 return status;
1884 }
1885
1886 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1887 {
1888 int status = -ENOMEM;
1889 struct ocrdma_destroy_cq *cmd;
1890
1891 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1892 if (!cmd)
1893 return status;
1894 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1895 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1896
1897 cmd->bypass_flush_qid |=
1898 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1899 OCRDMA_DESTROY_CQ_QID_MASK;
1900
1901 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1902 ocrdma_unbind_eq(dev, cq->eqn);
1903 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1904 kfree(cmd);
1905 return status;
1906 }
1907
1908 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1909 u32 pdid, int addr_check)
1910 {
1911 int status = -ENOMEM;
1912 struct ocrdma_alloc_lkey *cmd;
1913 struct ocrdma_alloc_lkey_rsp *rsp;
1914
1915 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1916 if (!cmd)
1917 return status;
1918 cmd->pdid = pdid;
1919 cmd->pbl_sz_flags |= addr_check;
1920 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1921 cmd->pbl_sz_flags |=
1922 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1923 cmd->pbl_sz_flags |=
1924 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1925 cmd->pbl_sz_flags |=
1926 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1927 cmd->pbl_sz_flags |=
1928 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1929 cmd->pbl_sz_flags |=
1930 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1931
1932 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1933 if (status)
1934 goto mbx_err;
1935 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1936 hwmr->lkey = rsp->lrkey;
1937 mbx_err:
1938 kfree(cmd);
1939 return status;
1940 }
1941
1942 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1943 {
1944 int status = -ENOMEM;
1945 struct ocrdma_dealloc_lkey *cmd;
1946
1947 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1948 if (!cmd)
1949 return -ENOMEM;
1950 cmd->lkey = lkey;
1951 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1952 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1953 if (status)
1954 goto mbx_err;
1955 mbx_err:
1956 kfree(cmd);
1957 return status;
1958 }
1959
1960 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1961 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1962 {
1963 int status = -ENOMEM;
1964 int i;
1965 struct ocrdma_reg_nsmr *cmd;
1966 struct ocrdma_reg_nsmr_rsp *rsp;
1967
1968 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1969 if (!cmd)
1970 return -ENOMEM;
1971 cmd->num_pbl_pdid =
1972 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1973 cmd->fr_mr = hwmr->fr_mr;
1974
1975 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1976 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1977 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1978 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1979 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1980 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1981 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1982 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1983 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1984 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1985 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1986
1987 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1988 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1989 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1990 cmd->totlen_low = hwmr->len;
1991 cmd->totlen_high = upper_32_bits(hwmr->len);
1992 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1993 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1994 cmd->va_loaddr = (u32) hwmr->va;
1995 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1996
1997 for (i = 0; i < pbl_cnt; i++) {
1998 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1999 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
2000 }
2001 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2002 if (status)
2003 goto mbx_err;
2004 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
2005 hwmr->lkey = rsp->lrkey;
2006 mbx_err:
2007 kfree(cmd);
2008 return status;
2009 }
2010
2011 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
2012 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
2013 u32 pbl_offset, u32 last)
2014 {
2015 int status = -ENOMEM;
2016 int i;
2017 struct ocrdma_reg_nsmr_cont *cmd;
2018
2019 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
2020 if (!cmd)
2021 return -ENOMEM;
2022 cmd->lrkey = hwmr->lkey;
2023 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
2024 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
2025 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
2026
2027 for (i = 0; i < pbl_cnt; i++) {
2028 cmd->pbl[i].lo =
2029 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
2030 cmd->pbl[i].hi =
2031 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
2032 }
2033 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2034 if (status)
2035 goto mbx_err;
2036 mbx_err:
2037 kfree(cmd);
2038 return status;
2039 }
2040
2041 int ocrdma_reg_mr(struct ocrdma_dev *dev,
2042 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
2043 {
2044 int status;
2045 u32 last = 0;
2046 u32 cur_pbl_cnt, pbl_offset;
2047 u32 pending_pbl_cnt = hwmr->num_pbls;
2048
2049 pbl_offset = 0;
2050 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
2051 if (cur_pbl_cnt == pending_pbl_cnt)
2052 last = 1;
2053
2054 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
2055 cur_pbl_cnt, hwmr->pbe_size, last);
2056 if (status) {
2057 pr_err("%s() status=%d\n", __func__, status);
2058 return status;
2059 }
2060 /* if there is no more pbls to register then exit. */
2061 if (last)
2062 return 0;
2063
2064 while (!last) {
2065 pbl_offset += cur_pbl_cnt;
2066 pending_pbl_cnt -= cur_pbl_cnt;
2067 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
2068 /* if we reach the end of the pbls, then need to set the last
2069 * bit, indicating no more pbls to register for this memory key.
2070 */
2071 if (cur_pbl_cnt == pending_pbl_cnt)
2072 last = 1;
2073
2074 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
2075 pbl_offset, last);
2076 if (status)
2077 break;
2078 }
2079 if (status)
2080 pr_err("%s() err. status=%d\n", __func__, status);
2081
2082 return status;
2083 }
2084
2085 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2086 {
2087 struct ocrdma_qp *tmp;
2088 bool found = false;
2089 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
2090 if (qp == tmp) {
2091 found = true;
2092 break;
2093 }
2094 }
2095 return found;
2096 }
2097
2098 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2099 {
2100 struct ocrdma_qp *tmp;
2101 bool found = false;
2102 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
2103 if (qp == tmp) {
2104 found = true;
2105 break;
2106 }
2107 }
2108 return found;
2109 }
2110
2111 void ocrdma_flush_qp(struct ocrdma_qp *qp)
2112 {
2113 bool found;
2114 unsigned long flags;
2115 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2116
2117 spin_lock_irqsave(&dev->flush_q_lock, flags);
2118 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
2119 if (!found)
2120 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
2121 if (!qp->srq) {
2122 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
2123 if (!found)
2124 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
2125 }
2126 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
2127 }
2128
2129 static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
2130 {
2131 qp->sq.head = 0;
2132 qp->sq.tail = 0;
2133 qp->rq.head = 0;
2134 qp->rq.tail = 0;
2135 }
2136
2137 int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
2138 enum ib_qp_state *old_ib_state)
2139 {
2140 unsigned long flags;
2141 int status = 0;
2142 enum ocrdma_qp_state new_state;
2143 new_state = get_ocrdma_qp_state(new_ib_state);
2144
2145 /* sync with wqe and rqe posting */
2146 spin_lock_irqsave(&qp->q_lock, flags);
2147
2148 if (old_ib_state)
2149 *old_ib_state = get_ibqp_state(qp->state);
2150 if (new_state == qp->state) {
2151 spin_unlock_irqrestore(&qp->q_lock, flags);
2152 return 1;
2153 }
2154
2155
2156 if (new_state == OCRDMA_QPS_INIT) {
2157 ocrdma_init_hwq_ptr(qp);
2158 ocrdma_del_flush_qp(qp);
2159 } else if (new_state == OCRDMA_QPS_ERR) {
2160 ocrdma_flush_qp(qp);
2161 }
2162
2163 qp->state = new_state;
2164
2165 spin_unlock_irqrestore(&qp->q_lock, flags);
2166 return status;
2167 }
2168
2169 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
2170 {
2171 u32 flags = 0;
2172 if (qp->cap_flags & OCRDMA_QP_INB_RD)
2173 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
2174 if (qp->cap_flags & OCRDMA_QP_INB_WR)
2175 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
2176 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
2177 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
2178 if (qp->cap_flags & OCRDMA_QP_LKEY0)
2179 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
2180 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
2181 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
2182 return flags;
2183 }
2184
2185 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
2186 struct ib_qp_init_attr *attrs,
2187 struct ocrdma_qp *qp)
2188 {
2189 int status;
2190 u32 len, hw_pages, hw_page_size;
2191 dma_addr_t pa;
2192 struct ocrdma_pd *pd = qp->pd;
2193 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2194 struct pci_dev *pdev = dev->nic_info.pdev;
2195 u32 max_wqe_allocated;
2196 u32 max_sges = attrs->cap.max_send_sge;
2197
2198 /* QP1 may exceed 127 */
2199 max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
2200 dev->attr.max_wqe);
2201
2202 status = ocrdma_build_q_conf(&max_wqe_allocated,
2203 dev->attr.wqe_size, &hw_pages, &hw_page_size);
2204 if (status) {
2205 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
2206 max_wqe_allocated);
2207 return -EINVAL;
2208 }
2209 qp->sq.max_cnt = max_wqe_allocated;
2210 len = (hw_pages * hw_page_size);
2211
2212 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2213 if (!qp->sq.va)
2214 return -EINVAL;
2215 memset(qp->sq.va, 0, len);
2216 qp->sq.len = len;
2217 qp->sq.pa = pa;
2218 qp->sq.entry_size = dev->attr.wqe_size;
2219 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
2220
2221 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2222 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
2223 cmd->num_wq_rq_pages |= (hw_pages <<
2224 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
2225 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
2226 cmd->max_sge_send_write |= (max_sges <<
2227 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
2228 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
2229 cmd->max_sge_send_write |= (max_sges <<
2230 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
2231 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
2232 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
2233 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
2234 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
2235 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2236 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2237 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2238 return 0;
2239 }
2240
2241 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2242 struct ib_qp_init_attr *attrs,
2243 struct ocrdma_qp *qp)
2244 {
2245 int status;
2246 u32 len, hw_pages, hw_page_size;
2247 dma_addr_t pa = 0;
2248 struct ocrdma_pd *pd = qp->pd;
2249 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2250 struct pci_dev *pdev = dev->nic_info.pdev;
2251 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2252
2253 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2254 &hw_pages, &hw_page_size);
2255 if (status) {
2256 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2257 attrs->cap.max_recv_wr + 1);
2258 return status;
2259 }
2260 qp->rq.max_cnt = max_rqe_allocated;
2261 len = (hw_pages * hw_page_size);
2262
2263 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2264 if (!qp->rq.va)
2265 return -ENOMEM;
2266 memset(qp->rq.va, 0, len);
2267 qp->rq.pa = pa;
2268 qp->rq.len = len;
2269 qp->rq.entry_size = dev->attr.rqe_size;
2270
2271 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2272 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2273 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2274 cmd->num_wq_rq_pages |=
2275 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2276 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2277 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2278 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2279 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2280 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2281 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2282 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2283 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2284 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2285 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2286 return 0;
2287 }
2288
2289 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2290 struct ocrdma_pd *pd,
2291 struct ocrdma_qp *qp,
2292 u8 enable_dpp_cq, u16 dpp_cq_id)
2293 {
2294 pd->num_dpp_qp--;
2295 qp->dpp_enabled = true;
2296 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2297 if (!enable_dpp_cq)
2298 return;
2299 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2300 cmd->dpp_credits_cqid = dpp_cq_id;
2301 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2302 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2303 }
2304
2305 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2306 struct ocrdma_qp *qp)
2307 {
2308 struct ocrdma_pd *pd = qp->pd;
2309 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2310 struct pci_dev *pdev = dev->nic_info.pdev;
2311 dma_addr_t pa = 0;
2312 int ird_page_size = dev->attr.ird_page_size;
2313 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
2314 struct ocrdma_hdr_wqe *rqe;
2315 int i = 0;
2316
2317 if (dev->attr.ird == 0)
2318 return 0;
2319
2320 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
2321 &pa, GFP_KERNEL);
2322 if (!qp->ird_q_va)
2323 return -ENOMEM;
2324 memset(qp->ird_q_va, 0, ird_q_len);
2325 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2326 pa, ird_page_size);
2327 for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2328 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2329 (i * dev->attr.rqe_size));
2330 rqe->cw = 0;
2331 rqe->cw |= 2;
2332 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2333 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2334 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2335 }
2336 return 0;
2337 }
2338
2339 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2340 struct ocrdma_qp *qp,
2341 struct ib_qp_init_attr *attrs,
2342 u16 *dpp_offset, u16 *dpp_credit_lmt)
2343 {
2344 u32 max_wqe_allocated, max_rqe_allocated;
2345 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2346 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2347 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2348 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2349 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2350 qp->dpp_enabled = false;
2351 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2352 qp->dpp_enabled = true;
2353 *dpp_credit_lmt = (rsp->dpp_response &
2354 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2355 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2356 *dpp_offset = (rsp->dpp_response &
2357 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2358 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2359 }
2360 max_wqe_allocated =
2361 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2362 max_wqe_allocated = 1 << max_wqe_allocated;
2363 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2364
2365 qp->sq.max_cnt = max_wqe_allocated;
2366 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2367
2368 if (!attrs->srq) {
2369 qp->rq.max_cnt = max_rqe_allocated;
2370 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
2371 }
2372 }
2373
2374 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2375 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2376 u16 *dpp_credit_lmt)
2377 {
2378 int status = -ENOMEM;
2379 u32 flags = 0;
2380 struct ocrdma_pd *pd = qp->pd;
2381 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2382 struct pci_dev *pdev = dev->nic_info.pdev;
2383 struct ocrdma_cq *cq;
2384 struct ocrdma_create_qp_req *cmd;
2385 struct ocrdma_create_qp_rsp *rsp;
2386 int qptype;
2387
2388 switch (attrs->qp_type) {
2389 case IB_QPT_GSI:
2390 qptype = OCRDMA_QPT_GSI;
2391 break;
2392 case IB_QPT_RC:
2393 qptype = OCRDMA_QPT_RC;
2394 break;
2395 case IB_QPT_UD:
2396 qptype = OCRDMA_QPT_UD;
2397 break;
2398 default:
2399 return -EINVAL;
2400 }
2401
2402 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2403 if (!cmd)
2404 return status;
2405 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2406 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2407 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2408 if (status)
2409 goto sq_err;
2410
2411 if (attrs->srq) {
2412 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2413 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2414 cmd->rq_addr[0].lo = srq->id;
2415 qp->srq = srq;
2416 } else {
2417 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2418 if (status)
2419 goto rq_err;
2420 }
2421
2422 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2423 if (status)
2424 goto mbx_err;
2425
2426 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2427 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2428
2429 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2430
2431 cmd->max_sge_recv_flags |= flags;
2432 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2433 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2434 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2435 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2436 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2437 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2438 cq = get_ocrdma_cq(attrs->send_cq);
2439 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2440 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2441 qp->sq_cq = cq;
2442 cq = get_ocrdma_cq(attrs->recv_cq);
2443 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2444 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2445 qp->rq_cq = cq;
2446
2447 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2448 (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
2449 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2450 dpp_cq_id);
2451 }
2452
2453 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2454 if (status)
2455 goto mbx_err;
2456 rsp = (struct ocrdma_create_qp_rsp *)cmd;
2457 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2458 qp->state = OCRDMA_QPS_RST;
2459 kfree(cmd);
2460 return 0;
2461 mbx_err:
2462 if (qp->rq.va)
2463 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2464 rq_err:
2465 pr_err("%s(%d) rq_err\n", __func__, dev->id);
2466 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2467 sq_err:
2468 pr_err("%s(%d) sq_err\n", __func__, dev->id);
2469 kfree(cmd);
2470 return status;
2471 }
2472
2473 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2474 struct ocrdma_qp_params *param)
2475 {
2476 int status = -ENOMEM;
2477 struct ocrdma_query_qp *cmd;
2478 struct ocrdma_query_qp_rsp *rsp;
2479
2480 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*rsp));
2481 if (!cmd)
2482 return status;
2483 cmd->qp_id = qp->id;
2484 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2485 if (status)
2486 goto mbx_err;
2487 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2488 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2489 mbx_err:
2490 kfree(cmd);
2491 return status;
2492 }
2493
2494 static int ocrdma_set_av_params(struct ocrdma_qp *qp,
2495 struct ocrdma_modify_qp *cmd,
2496 struct ib_qp_attr *attrs,
2497 int attr_mask)
2498 {
2499 int status;
2500 struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2501 union ib_gid sgid, zgid;
2502 struct ib_gid_attr sgid_attr;
2503 u32 vlan_id = 0xFFFF;
2504 u8 mac_addr[6];
2505 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2506
2507 if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2508 return -EINVAL;
2509 if (atomic_cmpxchg(&dev->update_sl, 1, 0))
2510 ocrdma_init_service_level(dev);
2511 cmd->params.tclass_sq_psn |=
2512 (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2513 cmd->params.rnt_rc_sl_fl |=
2514 (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2515 cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
2516 cmd->params.hop_lmt_rq_psn |=
2517 (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2518 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2519 memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2520 sizeof(cmd->params.dgid));
2521
2522 status = ib_get_cached_gid(&dev->ibdev, 1, ah_attr->grh.sgid_index,
2523 &sgid, &sgid_attr);
2524 if (!status && sgid_attr.ndev) {
2525 vlan_id = rdma_vlan_dev_vlan_id(sgid_attr.ndev);
2526 memcpy(mac_addr, sgid_attr.ndev->dev_addr, ETH_ALEN);
2527 dev_put(sgid_attr.ndev);
2528 }
2529
2530 memset(&zgid, 0, sizeof(zgid));
2531 if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2532 return -EINVAL;
2533
2534 qp->sgid_idx = ah_attr->grh.sgid_index;
2535 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2536 status = ocrdma_resolve_dmac(dev, ah_attr, &mac_addr[0]);
2537 if (status)
2538 return status;
2539 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2540 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2541 /* convert them to LE format. */
2542 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2543 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2544 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2545
2546 if (vlan_id == 0xFFFF)
2547 vlan_id = 0;
2548 if (vlan_id || dev->pfc_state) {
2549 if (!vlan_id) {
2550 pr_err("ocrdma%d:Using VLAN with PFC is recommended\n",
2551 dev->id);
2552 pr_err("ocrdma%d:Using VLAN 0 for this connection\n",
2553 dev->id);
2554 }
2555 cmd->params.vlan_dmac_b4_to_b5 |=
2556 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2557 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2558 cmd->params.rnt_rc_sl_fl |=
2559 (dev->sl & 0x07) << OCRDMA_QP_PARAMS_SL_SHIFT;
2560 }
2561
2562 return 0;
2563 }
2564
2565 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2566 struct ocrdma_modify_qp *cmd,
2567 struct ib_qp_attr *attrs, int attr_mask)
2568 {
2569 int status = 0;
2570 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2571
2572 if (attr_mask & IB_QP_PKEY_INDEX) {
2573 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2574 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2575 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2576 }
2577 if (attr_mask & IB_QP_QKEY) {
2578 qp->qkey = attrs->qkey;
2579 cmd->params.qkey = attrs->qkey;
2580 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2581 }
2582 if (attr_mask & IB_QP_AV) {
2583 status = ocrdma_set_av_params(qp, cmd, attrs, attr_mask);
2584 if (status)
2585 return status;
2586 } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2587 /* set the default mac address for UD, GSI QPs */
2588 cmd->params.dmac_b0_to_b3 = dev->nic_info.mac_addr[0] |
2589 (dev->nic_info.mac_addr[1] << 8) |
2590 (dev->nic_info.mac_addr[2] << 16) |
2591 (dev->nic_info.mac_addr[3] << 24);
2592 cmd->params.vlan_dmac_b4_to_b5 = dev->nic_info.mac_addr[4] |
2593 (dev->nic_info.mac_addr[5] << 8);
2594 }
2595 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2596 attrs->en_sqd_async_notify) {
2597 cmd->params.max_sge_recv_flags |=
2598 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2599 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2600 }
2601 if (attr_mask & IB_QP_DEST_QPN) {
2602 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2603 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2604 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2605 }
2606 if (attr_mask & IB_QP_PATH_MTU) {
2607 if (attrs->path_mtu < IB_MTU_512 ||
2608 attrs->path_mtu > IB_MTU_4096) {
2609 pr_err("ocrdma%d: IB MTU %d is not supported\n",
2610 dev->id, ib_mtu_enum_to_int(attrs->path_mtu));
2611 status = -EINVAL;
2612 goto pmtu_err;
2613 }
2614 cmd->params.path_mtu_pkey_indx |=
2615 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2616 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2617 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2618 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2619 }
2620 if (attr_mask & IB_QP_TIMEOUT) {
2621 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2622 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2623 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2624 }
2625 if (attr_mask & IB_QP_RETRY_CNT) {
2626 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2627 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2628 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2629 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2630 }
2631 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2632 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2633 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2634 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2635 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2636 }
2637 if (attr_mask & IB_QP_RNR_RETRY) {
2638 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2639 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2640 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2641 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2642 }
2643 if (attr_mask & IB_QP_SQ_PSN) {
2644 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2645 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2646 }
2647 if (attr_mask & IB_QP_RQ_PSN) {
2648 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2649 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2650 }
2651 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2652 if (attrs->max_rd_atomic > dev->attr.max_ord_per_qp) {
2653 status = -EINVAL;
2654 goto pmtu_err;
2655 }
2656 qp->max_ord = attrs->max_rd_atomic;
2657 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2658 }
2659 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2660 if (attrs->max_dest_rd_atomic > dev->attr.max_ird_per_qp) {
2661 status = -EINVAL;
2662 goto pmtu_err;
2663 }
2664 qp->max_ird = attrs->max_dest_rd_atomic;
2665 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2666 }
2667 cmd->params.max_ord_ird = (qp->max_ord <<
2668 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2669 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2670 pmtu_err:
2671 return status;
2672 }
2673
2674 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2675 struct ib_qp_attr *attrs, int attr_mask)
2676 {
2677 int status = -ENOMEM;
2678 struct ocrdma_modify_qp *cmd;
2679
2680 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2681 if (!cmd)
2682 return status;
2683
2684 cmd->params.id = qp->id;
2685 cmd->flags = 0;
2686 if (attr_mask & IB_QP_STATE) {
2687 cmd->params.max_sge_recv_flags |=
2688 (get_ocrdma_qp_state(attrs->qp_state) <<
2689 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2690 OCRDMA_QP_PARAMS_STATE_MASK;
2691 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2692 } else {
2693 cmd->params.max_sge_recv_flags |=
2694 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2695 OCRDMA_QP_PARAMS_STATE_MASK;
2696 }
2697
2698 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
2699 if (status)
2700 goto mbx_err;
2701 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2702 if (status)
2703 goto mbx_err;
2704
2705 mbx_err:
2706 kfree(cmd);
2707 return status;
2708 }
2709
2710 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2711 {
2712 int status = -ENOMEM;
2713 struct ocrdma_destroy_qp *cmd;
2714 struct pci_dev *pdev = dev->nic_info.pdev;
2715
2716 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2717 if (!cmd)
2718 return status;
2719 cmd->qp_id = qp->id;
2720 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2721 if (status)
2722 goto mbx_err;
2723
2724 mbx_err:
2725 kfree(cmd);
2726 if (qp->sq.va)
2727 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2728 if (!qp->srq && qp->rq.va)
2729 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2730 if (qp->dpp_enabled)
2731 qp->pd->num_dpp_qp++;
2732 return status;
2733 }
2734
2735 int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
2736 struct ib_srq_init_attr *srq_attr,
2737 struct ocrdma_pd *pd)
2738 {
2739 int status = -ENOMEM;
2740 int hw_pages, hw_page_size;
2741 int len;
2742 struct ocrdma_create_srq_rsp *rsp;
2743 struct ocrdma_create_srq *cmd;
2744 dma_addr_t pa;
2745 struct pci_dev *pdev = dev->nic_info.pdev;
2746 u32 max_rqe_allocated;
2747
2748 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2749 if (!cmd)
2750 return status;
2751
2752 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2753 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2754 status = ocrdma_build_q_conf(&max_rqe_allocated,
2755 dev->attr.rqe_size,
2756 &hw_pages, &hw_page_size);
2757 if (status) {
2758 pr_err("%s() req. max_wr=0x%x\n", __func__,
2759 srq_attr->attr.max_wr);
2760 status = -EINVAL;
2761 goto ret;
2762 }
2763 len = hw_pages * hw_page_size;
2764 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2765 if (!srq->rq.va) {
2766 status = -ENOMEM;
2767 goto ret;
2768 }
2769 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2770
2771 srq->rq.entry_size = dev->attr.rqe_size;
2772 srq->rq.pa = pa;
2773 srq->rq.len = len;
2774 srq->rq.max_cnt = max_rqe_allocated;
2775
2776 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2777 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2778 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2779
2780 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2781 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2782 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2783 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2784 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2785 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2786
2787 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2788 if (status)
2789 goto mbx_err;
2790 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2791 srq->id = rsp->id;
2792 srq->rq.dbid = rsp->id;
2793 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2794 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2795 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2796 max_rqe_allocated = (1 << max_rqe_allocated);
2797 srq->rq.max_cnt = max_rqe_allocated;
2798 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2799 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2800 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2801 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2802 goto ret;
2803 mbx_err:
2804 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2805 ret:
2806 kfree(cmd);
2807 return status;
2808 }
2809
2810 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2811 {
2812 int status = -ENOMEM;
2813 struct ocrdma_modify_srq *cmd;
2814 struct ocrdma_pd *pd = srq->pd;
2815 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2816
2817 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
2818 if (!cmd)
2819 return status;
2820 cmd->id = srq->id;
2821 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2822 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2823 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2824 kfree(cmd);
2825 return status;
2826 }
2827
2828 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2829 {
2830 int status = -ENOMEM;
2831 struct ocrdma_query_srq *cmd;
2832 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2833
2834 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
2835 if (!cmd)
2836 return status;
2837 cmd->id = srq->rq.dbid;
2838 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2839 if (status == 0) {
2840 struct ocrdma_query_srq_rsp *rsp =
2841 (struct ocrdma_query_srq_rsp *)cmd;
2842 srq_attr->max_sge =
2843 rsp->srq_lmt_max_sge &
2844 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2845 srq_attr->max_wr =
2846 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2847 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2848 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2849 }
2850 kfree(cmd);
2851 return status;
2852 }
2853
2854 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2855 {
2856 int status = -ENOMEM;
2857 struct ocrdma_destroy_srq *cmd;
2858 struct pci_dev *pdev = dev->nic_info.pdev;
2859 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2860 if (!cmd)
2861 return status;
2862 cmd->id = srq->id;
2863 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2864 if (srq->rq.va)
2865 dma_free_coherent(&pdev->dev, srq->rq.len,
2866 srq->rq.va, srq->rq.pa);
2867 kfree(cmd);
2868 return status;
2869 }
2870
2871 static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
2872 struct ocrdma_dcbx_cfg *dcbxcfg)
2873 {
2874 int status = 0;
2875 dma_addr_t pa;
2876 struct ocrdma_mqe cmd;
2877
2878 struct ocrdma_get_dcbx_cfg_req *req = NULL;
2879 struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
2880 struct pci_dev *pdev = dev->nic_info.pdev;
2881 struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
2882
2883 memset(&cmd, 0, sizeof(struct ocrdma_mqe));
2884 cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
2885 sizeof(struct ocrdma_get_dcbx_cfg_req));
2886 req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
2887 if (!req) {
2888 status = -ENOMEM;
2889 goto mem_err;
2890 }
2891
2892 cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
2893 OCRDMA_MQE_HDR_SGE_CNT_MASK;
2894 mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
2895 mqe_sge->pa_hi = (u32) upper_32_bits(pa);
2896 mqe_sge->len = cmd.hdr.pyld_len;
2897
2898 memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
2899 ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
2900 OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
2901 req->param_type = ptype;
2902
2903 status = ocrdma_mbx_cmd(dev, &cmd);
2904 if (status)
2905 goto mbx_err;
2906
2907 rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
2908 ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
2909 memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
2910
2911 mbx_err:
2912 dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
2913 mem_err:
2914 return status;
2915 }
2916
2917 #define OCRDMA_MAX_SERVICE_LEVEL_INDEX 0x08
2918 #define OCRDMA_DEFAULT_SERVICE_LEVEL 0x05
2919
2920 static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
2921 struct ocrdma_dcbx_cfg *dcbxcfg,
2922 u8 *srvc_lvl)
2923 {
2924 int status = -EINVAL, indx, slindx;
2925 int ventry_cnt;
2926 struct ocrdma_app_parameter *app_param;
2927 u8 valid, proto_sel;
2928 u8 app_prio, pfc_prio;
2929 u16 proto;
2930
2931 if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
2932 pr_info("%s ocrdma%d DCBX is disabled\n",
2933 dev_name(&dev->nic_info.pdev->dev), dev->id);
2934 goto out;
2935 }
2936
2937 if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
2938 pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2939 dev_name(&dev->nic_info.pdev->dev), dev->id,
2940 (ptype > 0 ? "operational" : "admin"),
2941 (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
2942 "enabled" : "disabled",
2943 (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
2944 "" : ", not sync'ed");
2945 goto out;
2946 } else {
2947 pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2948 dev_name(&dev->nic_info.pdev->dev), dev->id);
2949 }
2950
2951 ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
2952 OCRDMA_DCBX_APP_ENTRY_SHIFT)
2953 & OCRDMA_DCBX_STATE_MASK;
2954
2955 for (indx = 0; indx < ventry_cnt; indx++) {
2956 app_param = &dcbxcfg->app_param[indx];
2957 valid = (app_param->valid_proto_app >>
2958 OCRDMA_APP_PARAM_VALID_SHIFT)
2959 & OCRDMA_APP_PARAM_VALID_MASK;
2960 proto_sel = (app_param->valid_proto_app
2961 >> OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
2962 & OCRDMA_APP_PARAM_PROTO_SEL_MASK;
2963 proto = app_param->valid_proto_app &
2964 OCRDMA_APP_PARAM_APP_PROTO_MASK;
2965
2966 if (
2967 valid && proto == OCRDMA_APP_PROTO_ROCE &&
2968 proto_sel == OCRDMA_PROTO_SELECT_L2) {
2969 for (slindx = 0; slindx <
2970 OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
2971 app_prio = ocrdma_get_app_prio(
2972 (u8 *)app_param->app_prio,
2973 slindx);
2974 pfc_prio = ocrdma_get_pfc_prio(
2975 (u8 *)dcbxcfg->pfc_prio,
2976 slindx);
2977
2978 if (app_prio && pfc_prio) {
2979 *srvc_lvl = slindx;
2980 status = 0;
2981 goto out;
2982 }
2983 }
2984 if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
2985 pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
2986 dev_name(&dev->nic_info.pdev->dev),
2987 dev->id, proto);
2988 }
2989 }
2990 }
2991
2992 out:
2993 return status;
2994 }
2995
2996 void ocrdma_init_service_level(struct ocrdma_dev *dev)
2997 {
2998 int status = 0, indx;
2999 struct ocrdma_dcbx_cfg dcbxcfg;
3000 u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
3001 int ptype = OCRDMA_PARAMETER_TYPE_OPER;
3002
3003 for (indx = 0; indx < 2; indx++) {
3004 status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
3005 if (status) {
3006 pr_err("%s(): status=%d\n", __func__, status);
3007 ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
3008 continue;
3009 }
3010
3011 status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
3012 &dcbxcfg, &srvc_lvl);
3013 if (status) {
3014 ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
3015 continue;
3016 }
3017
3018 break;
3019 }
3020
3021 if (status)
3022 pr_info("%s ocrdma%d service level default\n",
3023 dev_name(&dev->nic_info.pdev->dev), dev->id);
3024 else
3025 pr_info("%s ocrdma%d service level %d\n",
3026 dev_name(&dev->nic_info.pdev->dev), dev->id,
3027 srvc_lvl);
3028
3029 dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
3030 dev->sl = srvc_lvl;
3031 }
3032
3033 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
3034 {
3035 int i;
3036 int status = -EINVAL;
3037 struct ocrdma_av *av;
3038 unsigned long flags;
3039
3040 av = dev->av_tbl.va;
3041 spin_lock_irqsave(&dev->av_tbl.lock, flags);
3042 for (i = 0; i < dev->av_tbl.num_ah; i++) {
3043 if (av->valid == 0) {
3044 av->valid = OCRDMA_AV_VALID;
3045 ah->av = av;
3046 ah->id = i;
3047 status = 0;
3048 break;
3049 }
3050 av++;
3051 }
3052 if (i == dev->av_tbl.num_ah)
3053 status = -EAGAIN;
3054 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
3055 return status;
3056 }
3057
3058 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
3059 {
3060 unsigned long flags;
3061 spin_lock_irqsave(&dev->av_tbl.lock, flags);
3062 ah->av->valid = 0;
3063 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
3064 return 0;
3065 }
3066
3067 static int ocrdma_create_eqs(struct ocrdma_dev *dev)
3068 {
3069 int num_eq, i, status = 0;
3070 int irq;
3071 unsigned long flags = 0;
3072
3073 num_eq = dev->nic_info.msix.num_vectors -
3074 dev->nic_info.msix.start_vector;
3075 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
3076 num_eq = 1;
3077 flags = IRQF_SHARED;
3078 } else {
3079 num_eq = min_t(u32, num_eq, num_online_cpus());
3080 }
3081
3082 if (!num_eq)
3083 return -EINVAL;
3084
3085 dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
3086 if (!dev->eq_tbl)
3087 return -ENOMEM;
3088
3089 for (i = 0; i < num_eq; i++) {
3090 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
3091 OCRDMA_EQ_LEN);
3092 if (status) {
3093 status = -EINVAL;
3094 break;
3095 }
3096 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
3097 dev->id, i);
3098 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
3099 status = request_irq(irq, ocrdma_irq_handler, flags,
3100 dev->eq_tbl[i].irq_name,
3101 &dev->eq_tbl[i]);
3102 if (status)
3103 goto done;
3104 dev->eq_cnt += 1;
3105 }
3106 /* one eq is sufficient for data path to work */
3107 return 0;
3108 done:
3109 ocrdma_destroy_eqs(dev);
3110 return status;
3111 }
3112
3113 static int ocrdma_mbx_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq,
3114 int num)
3115 {
3116 int i, status = -ENOMEM;
3117 struct ocrdma_modify_eqd_req *cmd;
3118
3119 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_EQ_DELAY, sizeof(*cmd));
3120 if (!cmd)
3121 return status;
3122
3123 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_MODIFY_EQ_DELAY,
3124 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
3125
3126 cmd->cmd.num_eq = num;
3127 for (i = 0; i < num; i++) {
3128 cmd->cmd.set_eqd[i].eq_id = eq[i].q.id;
3129 cmd->cmd.set_eqd[i].phase = 0;
3130 cmd->cmd.set_eqd[i].delay_multiplier =
3131 (eq[i].aic_obj.prev_eqd * 65)/100;
3132 }
3133 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
3134 if (status)
3135 goto mbx_err;
3136 mbx_err:
3137 kfree(cmd);
3138 return status;
3139 }
3140
3141 static int ocrdma_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq,
3142 int num)
3143 {
3144 int num_eqs, i = 0;
3145 if (num > 8) {
3146 while (num) {
3147 num_eqs = min(num, 8);
3148 ocrdma_mbx_modify_eqd(dev, &eq[i], num_eqs);
3149 i += num_eqs;
3150 num -= num_eqs;
3151 }
3152 } else {
3153 ocrdma_mbx_modify_eqd(dev, eq, num);
3154 }
3155 return 0;
3156 }
3157
3158 void ocrdma_eqd_set_task(struct work_struct *work)
3159 {
3160 struct ocrdma_dev *dev =
3161 container_of(work, struct ocrdma_dev, eqd_work.work);
3162 struct ocrdma_eq *eq = 0;
3163 int i, num = 0, status = -EINVAL;
3164 u64 eq_intr;
3165
3166 for (i = 0; i < dev->eq_cnt; i++) {
3167 eq = &dev->eq_tbl[i];
3168 if (eq->aic_obj.eq_intr_cnt > eq->aic_obj.prev_eq_intr_cnt) {
3169 eq_intr = eq->aic_obj.eq_intr_cnt -
3170 eq->aic_obj.prev_eq_intr_cnt;
3171 if ((eq_intr > EQ_INTR_PER_SEC_THRSH_HI) &&
3172 (eq->aic_obj.prev_eqd == EQ_AIC_MIN_EQD)) {
3173 eq->aic_obj.prev_eqd = EQ_AIC_MAX_EQD;
3174 num++;
3175 } else if ((eq_intr < EQ_INTR_PER_SEC_THRSH_LOW) &&
3176 (eq->aic_obj.prev_eqd == EQ_AIC_MAX_EQD)) {
3177 eq->aic_obj.prev_eqd = EQ_AIC_MIN_EQD;
3178 num++;
3179 }
3180 }
3181 eq->aic_obj.prev_eq_intr_cnt = eq->aic_obj.eq_intr_cnt;
3182 }
3183
3184 if (num)
3185 status = ocrdma_modify_eqd(dev, &dev->eq_tbl[0], num);
3186 schedule_delayed_work(&dev->eqd_work, msecs_to_jiffies(1000));
3187 }
3188
3189 int ocrdma_init_hw(struct ocrdma_dev *dev)
3190 {
3191 int status;
3192
3193 /* create the eqs */
3194 status = ocrdma_create_eqs(dev);
3195 if (status)
3196 goto qpeq_err;
3197 status = ocrdma_create_mq(dev);
3198 if (status)
3199 goto mq_err;
3200 status = ocrdma_mbx_query_fw_config(dev);
3201 if (status)
3202 goto conf_err;
3203 status = ocrdma_mbx_query_dev(dev);
3204 if (status)
3205 goto conf_err;
3206 status = ocrdma_mbx_query_fw_ver(dev);
3207 if (status)
3208 goto conf_err;
3209 status = ocrdma_mbx_create_ah_tbl(dev);
3210 if (status)
3211 goto conf_err;
3212 status = ocrdma_mbx_get_phy_info(dev);
3213 if (status)
3214 goto info_attrb_err;
3215 status = ocrdma_mbx_get_ctrl_attribs(dev);
3216 if (status)
3217 goto info_attrb_err;
3218
3219 return 0;
3220
3221 info_attrb_err:
3222 ocrdma_mbx_delete_ah_tbl(dev);
3223 conf_err:
3224 ocrdma_destroy_mq(dev);
3225 mq_err:
3226 ocrdma_destroy_eqs(dev);
3227 qpeq_err:
3228 pr_err("%s() status=%d\n", __func__, status);
3229 return status;
3230 }
3231
3232 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
3233 {
3234 ocrdma_free_pd_pool(dev);
3235 ocrdma_mbx_delete_ah_tbl(dev);
3236
3237 /* cleanup the control path */
3238 ocrdma_destroy_mq(dev);
3239
3240 /* cleanup the eqs */
3241 ocrdma_destroy_eqs(dev);
3242 }
Linux kernel - Deliverables
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