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RDMA/ocrdma: Check resource ids received in Async CQE
[deliverable/linux.git] / drivers / infiniband / hw / ocrdma / ocrdma_hw.c
1 /* This file is part of the Emulex RoCE Device Driver for
2 * RoCE (RDMA over Converged Ethernet) adapters.
3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
4 * EMULEX and SLI are trademarks of Emulex.
5 * www.emulex.com
6 *
7 * This software is available to you under a choice of one of two licenses.
8 * You may choose to be licensed under the terms of the GNU General Public
9 * License (GPL) Version 2, available from the file COPYING in the main
10 * directory of this source tree, or the BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * - Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * Contact Information:
36 * linux-drivers@emulex.com
37 *
38 * Emulex
39 * 3333 Susan Street
40 * Costa Mesa, CA 92626
41 */
42
43 #include <linux/sched.h>
44 #include <linux/interrupt.h>
45 #include <linux/log2.h>
46 #include <linux/dma-mapping.h>
47
48 #include <rdma/ib_verbs.h>
49 #include <rdma/ib_user_verbs.h>
50
51 #include "ocrdma.h"
52 #include "ocrdma_hw.h"
53 #include "ocrdma_verbs.h"
54 #include "ocrdma_ah.h"
55
56 enum mbx_status {
57 OCRDMA_MBX_STATUS_FAILED = 1,
58 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
59 OCRDMA_MBX_STATUS_OOR = 100,
60 OCRDMA_MBX_STATUS_INVALID_PD = 101,
61 OCRDMA_MBX_STATUS_PD_INUSE = 102,
62 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
63 OCRDMA_MBX_STATUS_INVALID_QP = 104,
64 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
65 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
66 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
67 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
68 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
69 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
70 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
71 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
72 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
73 OCRDMA_MBX_STATUS_MW_BOUND = 114,
74 OCRDMA_MBX_STATUS_INVALID_VA = 115,
75 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
76 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
77 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
78 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
79 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
80 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
81 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
82 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
83 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
84 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
85 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
86 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
87 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
88 OCRDMA_MBX_STATUS_QP_BOUND = 130,
89 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
90 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
91 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
92 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
93 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
94 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
95 };
96
97 enum additional_status {
98 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
99 };
100
101 enum cqe_status {
102 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
103 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
104 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
105 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
106 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
107 };
108
109 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
110 {
111 return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
112 }
113
114 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
115 {
116 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
117 }
118
119 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
120 {
121 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
122 (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
123
124 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
125 return NULL;
126 return cqe;
127 }
128
129 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
130 {
131 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
132 }
133
134 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
135 {
136 return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
137 }
138
139 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
140 {
141 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
142 }
143
144 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
145 {
146 return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
147 }
148
149 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
150 {
151 switch (qps) {
152 case OCRDMA_QPS_RST:
153 return IB_QPS_RESET;
154 case OCRDMA_QPS_INIT:
155 return IB_QPS_INIT;
156 case OCRDMA_QPS_RTR:
157 return IB_QPS_RTR;
158 case OCRDMA_QPS_RTS:
159 return IB_QPS_RTS;
160 case OCRDMA_QPS_SQD:
161 case OCRDMA_QPS_SQ_DRAINING:
162 return IB_QPS_SQD;
163 case OCRDMA_QPS_SQE:
164 return IB_QPS_SQE;
165 case OCRDMA_QPS_ERR:
166 return IB_QPS_ERR;
167 }
168 return IB_QPS_ERR;
169 }
170
171 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
172 {
173 switch (qps) {
174 case IB_QPS_RESET:
175 return OCRDMA_QPS_RST;
176 case IB_QPS_INIT:
177 return OCRDMA_QPS_INIT;
178 case IB_QPS_RTR:
179 return OCRDMA_QPS_RTR;
180 case IB_QPS_RTS:
181 return OCRDMA_QPS_RTS;
182 case IB_QPS_SQD:
183 return OCRDMA_QPS_SQD;
184 case IB_QPS_SQE:
185 return OCRDMA_QPS_SQE;
186 case IB_QPS_ERR:
187 return OCRDMA_QPS_ERR;
188 }
189 return OCRDMA_QPS_ERR;
190 }
191
192 static int ocrdma_get_mbx_errno(u32 status)
193 {
194 int err_num;
195 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
196 OCRDMA_MBX_RSP_STATUS_SHIFT;
197 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
198 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
199
200 switch (mbox_status) {
201 case OCRDMA_MBX_STATUS_OOR:
202 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
203 err_num = -EAGAIN;
204 break;
205
206 case OCRDMA_MBX_STATUS_INVALID_PD:
207 case OCRDMA_MBX_STATUS_INVALID_CQ:
208 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
209 case OCRDMA_MBX_STATUS_INVALID_QP:
210 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
211 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
212 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
213 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
214 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
215 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
216 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
217 case OCRDMA_MBX_STATUS_INVALID_LKEY:
218 case OCRDMA_MBX_STATUS_INVALID_VA:
219 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
220 case OCRDMA_MBX_STATUS_INVALID_FBO:
221 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
222 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
223 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
224 case OCRDMA_MBX_STATUS_SRQ_ERROR:
225 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
226 err_num = -EINVAL;
227 break;
228
229 case OCRDMA_MBX_STATUS_PD_INUSE:
230 case OCRDMA_MBX_STATUS_QP_BOUND:
231 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
232 case OCRDMA_MBX_STATUS_MW_BOUND:
233 err_num = -EBUSY;
234 break;
235
236 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
237 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
238 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
239 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
240 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
241 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
242 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
243 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
244 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
245 err_num = -ENOBUFS;
246 break;
247
248 case OCRDMA_MBX_STATUS_FAILED:
249 switch (add_status) {
250 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
251 err_num = -EAGAIN;
252 break;
253 }
254 default:
255 err_num = -EFAULT;
256 }
257 return err_num;
258 }
259
260 char *port_speed_string(struct ocrdma_dev *dev)
261 {
262 char *str = "";
263 u16 speeds_supported;
264
265 speeds_supported = dev->phy.fixed_speeds_supported |
266 dev->phy.auto_speeds_supported;
267 if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
268 str = "40Gbps ";
269 else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
270 str = "10Gbps ";
271 else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
272 str = "1Gbps ";
273
274 return str;
275 }
276
277 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
278 {
279 int err_num = -EINVAL;
280
281 switch (cqe_status) {
282 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
283 err_num = -EPERM;
284 break;
285 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
286 err_num = -EINVAL;
287 break;
288 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
289 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
290 err_num = -EINVAL;
291 break;
292 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
293 default:
294 err_num = -EINVAL;
295 break;
296 }
297 return err_num;
298 }
299
300 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
301 bool solicited, u16 cqe_popped)
302 {
303 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
304
305 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
306 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
307
308 if (armed)
309 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
310 if (solicited)
311 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
312 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
313 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
314 }
315
316 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
317 {
318 u32 val = 0;
319
320 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
321 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
322 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
323 }
324
325 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
326 bool arm, bool clear_int, u16 num_eqe)
327 {
328 u32 val = 0;
329
330 val |= eq_id & OCRDMA_EQ_ID_MASK;
331 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
332 if (arm)
333 val |= (1 << OCRDMA_REARM_SHIFT);
334 if (clear_int)
335 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
336 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
337 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
338 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
339 }
340
341 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
342 u8 opcode, u8 subsys, u32 cmd_len)
343 {
344 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
345 cmd_hdr->timeout = 20; /* seconds */
346 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
347 }
348
349 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
350 {
351 struct ocrdma_mqe *mqe;
352
353 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
354 if (!mqe)
355 return NULL;
356 mqe->hdr.spcl_sge_cnt_emb |=
357 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
358 OCRDMA_MQE_HDR_EMB_MASK;
359 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
360
361 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
362 mqe->hdr.pyld_len);
363 return mqe;
364 }
365
366 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
367 {
368 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
369 }
370
371 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
372 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
373 {
374 memset(q, 0, sizeof(*q));
375 q->len = len;
376 q->entry_size = entry_size;
377 q->size = len * entry_size;
378 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
379 &q->dma, GFP_KERNEL);
380 if (!q->va)
381 return -ENOMEM;
382 memset(q->va, 0, q->size);
383 return 0;
384 }
385
386 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
387 dma_addr_t host_pa, int hw_page_size)
388 {
389 int i;
390
391 for (i = 0; i < cnt; i++) {
392 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
393 q_pa[i].hi = (u32) upper_32_bits(host_pa);
394 host_pa += hw_page_size;
395 }
396 }
397
398 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
399 struct ocrdma_queue_info *q, int queue_type)
400 {
401 u8 opcode = 0;
402 int status;
403 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
404
405 switch (queue_type) {
406 case QTYPE_MCCQ:
407 opcode = OCRDMA_CMD_DELETE_MQ;
408 break;
409 case QTYPE_CQ:
410 opcode = OCRDMA_CMD_DELETE_CQ;
411 break;
412 case QTYPE_EQ:
413 opcode = OCRDMA_CMD_DELETE_EQ;
414 break;
415 default:
416 BUG();
417 }
418 memset(cmd, 0, sizeof(*cmd));
419 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
420 cmd->id = q->id;
421
422 status = be_roce_mcc_cmd(dev->nic_info.netdev,
423 cmd, sizeof(*cmd), NULL, NULL);
424 if (!status)
425 q->created = false;
426 return status;
427 }
428
429 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
430 {
431 int status;
432 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
433 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
434
435 memset(cmd, 0, sizeof(*cmd));
436 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
437 sizeof(*cmd));
438
439 cmd->req.rsvd_version = 2;
440 cmd->num_pages = 4;
441 cmd->valid = OCRDMA_CREATE_EQ_VALID;
442 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
443
444 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
445 PAGE_SIZE_4K);
446 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
447 NULL);
448 if (!status) {
449 eq->q.id = rsp->vector_eqid & 0xffff;
450 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
451 eq->q.created = true;
452 }
453 return status;
454 }
455
456 static int ocrdma_create_eq(struct ocrdma_dev *dev,
457 struct ocrdma_eq *eq, u16 q_len)
458 {
459 int status;
460
461 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
462 sizeof(struct ocrdma_eqe));
463 if (status)
464 return status;
465
466 status = ocrdma_mbx_create_eq(dev, eq);
467 if (status)
468 goto mbx_err;
469 eq->dev = dev;
470 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
471
472 return 0;
473 mbx_err:
474 ocrdma_free_q(dev, &eq->q);
475 return status;
476 }
477
478 int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
479 {
480 int irq;
481
482 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
483 irq = dev->nic_info.pdev->irq;
484 else
485 irq = dev->nic_info.msix.vector_list[eq->vector];
486 return irq;
487 }
488
489 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
490 {
491 if (eq->q.created) {
492 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
493 ocrdma_free_q(dev, &eq->q);
494 }
495 }
496
497 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
498 {
499 int irq;
500
501 /* disarm EQ so that interrupts are not generated
502 * during freeing and EQ delete is in progress.
503 */
504 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
505
506 irq = ocrdma_get_irq(dev, eq);
507 free_irq(irq, eq);
508 _ocrdma_destroy_eq(dev, eq);
509 }
510
511 static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
512 {
513 int i;
514
515 for (i = 0; i < dev->eq_cnt; i++)
516 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
517 }
518
519 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
520 struct ocrdma_queue_info *cq,
521 struct ocrdma_queue_info *eq)
522 {
523 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
524 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
525 int status;
526
527 memset(cmd, 0, sizeof(*cmd));
528 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
529 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
530
531 cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
532 cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
533 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
534 cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
535
536 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
537 cmd->eqn = eq->id;
538 cmd->pdid_cqecnt = cq->size / sizeof(struct ocrdma_mcqe);
539
540 ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
541 cq->dma, PAGE_SIZE_4K);
542 status = be_roce_mcc_cmd(dev->nic_info.netdev,
543 cmd, sizeof(*cmd), NULL, NULL);
544 if (!status) {
545 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
546 cq->created = true;
547 }
548 return status;
549 }
550
551 static u32 ocrdma_encoded_q_len(int q_len)
552 {
553 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
554
555 if (len_encoded == 16)
556 len_encoded = 0;
557 return len_encoded;
558 }
559
560 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
561 struct ocrdma_queue_info *mq,
562 struct ocrdma_queue_info *cq)
563 {
564 int num_pages, status;
565 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
566 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
567 struct ocrdma_pa *pa;
568
569 memset(cmd, 0, sizeof(*cmd));
570 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
571
572 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
573 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
574 cmd->req.rsvd_version = 1;
575 cmd->cqid_pages = num_pages;
576 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
577 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
578
579 cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE);
580 cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE);
581
582 cmd->async_cqid_ringsize = cq->id;
583 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
584 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
585 cmd->valid = OCRDMA_CREATE_MQ_VALID;
586 pa = &cmd->pa[0];
587
588 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
589 status = be_roce_mcc_cmd(dev->nic_info.netdev,
590 cmd, sizeof(*cmd), NULL, NULL);
591 if (!status) {
592 mq->id = rsp->id;
593 mq->created = true;
594 }
595 return status;
596 }
597
598 static int ocrdma_create_mq(struct ocrdma_dev *dev)
599 {
600 int status;
601
602 /* Alloc completion queue for Mailbox queue */
603 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
604 sizeof(struct ocrdma_mcqe));
605 if (status)
606 goto alloc_err;
607
608 dev->eq_tbl[0].cq_cnt++;
609 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
610 if (status)
611 goto mbx_cq_free;
612
613 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
614 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
615 mutex_init(&dev->mqe_ctx.lock);
616
617 /* Alloc Mailbox queue */
618 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
619 sizeof(struct ocrdma_mqe));
620 if (status)
621 goto mbx_cq_destroy;
622 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
623 if (status)
624 goto mbx_q_free;
625 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
626 return 0;
627
628 mbx_q_free:
629 ocrdma_free_q(dev, &dev->mq.sq);
630 mbx_cq_destroy:
631 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
632 mbx_cq_free:
633 ocrdma_free_q(dev, &dev->mq.cq);
634 alloc_err:
635 return status;
636 }
637
638 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
639 {
640 struct ocrdma_queue_info *mbxq, *cq;
641
642 /* mqe_ctx lock synchronizes with any other pending cmds. */
643 mutex_lock(&dev->mqe_ctx.lock);
644 mbxq = &dev->mq.sq;
645 if (mbxq->created) {
646 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
647 ocrdma_free_q(dev, mbxq);
648 }
649 mutex_unlock(&dev->mqe_ctx.lock);
650
651 cq = &dev->mq.cq;
652 if (cq->created) {
653 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
654 ocrdma_free_q(dev, cq);
655 }
656 }
657
658 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
659 struct ocrdma_qp *qp)
660 {
661 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
662 enum ib_qp_state old_ib_qps;
663
664 if (qp == NULL)
665 BUG();
666 ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
667 }
668
669 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
670 struct ocrdma_ae_mcqe *cqe)
671 {
672 struct ocrdma_qp *qp = NULL;
673 struct ocrdma_cq *cq = NULL;
674 struct ib_event ib_evt;
675 int cq_event = 0;
676 int qp_event = 1;
677 int srq_event = 0;
678 int dev_event = 0;
679 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
680 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
681 u16 qpid = cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK;
682 u16 cqid = cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK;
683
684 /*
685 * Some FW version returns wrong qp or cq ids in CQEs.
686 * Checking whether the IDs are valid
687 */
688
689 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID) {
690 if (qpid < dev->attr.max_qp)
691 qp = dev->qp_tbl[qpid];
692 if (qp == NULL) {
693 pr_err("ocrdma%d:Async event - qpid %u is not valid\n",
694 dev->id, qpid);
695 return;
696 }
697 }
698
699 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID) {
700 if (cqid < dev->attr.max_cq)
701 cq = dev->cq_tbl[cqid];
702 if (cq == NULL) {
703 pr_err("ocrdma%d:Async event - cqid %u is not valid\n",
704 dev->id, cqid);
705 return;
706 }
707 }
708
709 memset(&ib_evt, 0, sizeof(ib_evt));
710
711 ib_evt.device = &dev->ibdev;
712
713 switch (type) {
714 case OCRDMA_CQ_ERROR:
715 ib_evt.element.cq = &cq->ibcq;
716 ib_evt.event = IB_EVENT_CQ_ERR;
717 cq_event = 1;
718 qp_event = 0;
719 break;
720 case OCRDMA_CQ_OVERRUN_ERROR:
721 ib_evt.element.cq = &cq->ibcq;
722 ib_evt.event = IB_EVENT_CQ_ERR;
723 cq_event = 1;
724 qp_event = 0;
725 break;
726 case OCRDMA_CQ_QPCAT_ERROR:
727 ib_evt.element.qp = &qp->ibqp;
728 ib_evt.event = IB_EVENT_QP_FATAL;
729 ocrdma_process_qpcat_error(dev, qp);
730 break;
731 case OCRDMA_QP_ACCESS_ERROR:
732 ib_evt.element.qp = &qp->ibqp;
733 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
734 break;
735 case OCRDMA_QP_COMM_EST_EVENT:
736 ib_evt.element.qp = &qp->ibqp;
737 ib_evt.event = IB_EVENT_COMM_EST;
738 break;
739 case OCRDMA_SQ_DRAINED_EVENT:
740 ib_evt.element.qp = &qp->ibqp;
741 ib_evt.event = IB_EVENT_SQ_DRAINED;
742 break;
743 case OCRDMA_DEVICE_FATAL_EVENT:
744 ib_evt.element.port_num = 1;
745 ib_evt.event = IB_EVENT_DEVICE_FATAL;
746 qp_event = 0;
747 dev_event = 1;
748 break;
749 case OCRDMA_SRQCAT_ERROR:
750 ib_evt.element.srq = &qp->srq->ibsrq;
751 ib_evt.event = IB_EVENT_SRQ_ERR;
752 srq_event = 1;
753 qp_event = 0;
754 break;
755 case OCRDMA_SRQ_LIMIT_EVENT:
756 ib_evt.element.srq = &qp->srq->ibsrq;
757 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
758 srq_event = 1;
759 qp_event = 0;
760 break;
761 case OCRDMA_QP_LAST_WQE_EVENT:
762 ib_evt.element.qp = &qp->ibqp;
763 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
764 break;
765 default:
766 cq_event = 0;
767 qp_event = 0;
768 srq_event = 0;
769 dev_event = 0;
770 pr_err("%s() unknown type=0x%x\n", __func__, type);
771 break;
772 }
773
774 if (type < OCRDMA_MAX_ASYNC_ERRORS)
775 atomic_inc(&dev->async_err_stats[type]);
776
777 if (qp_event) {
778 if (qp->ibqp.event_handler)
779 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
780 } else if (cq_event) {
781 if (cq->ibcq.event_handler)
782 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
783 } else if (srq_event) {
784 if (qp->srq->ibsrq.event_handler)
785 qp->srq->ibsrq.event_handler(&ib_evt,
786 qp->srq->ibsrq.
787 srq_context);
788 } else if (dev_event) {
789 pr_err("%s: Fatal event received\n", dev->ibdev.name);
790 ib_dispatch_event(&ib_evt);
791 }
792
793 }
794
795 static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
796 struct ocrdma_ae_mcqe *cqe)
797 {
798 struct ocrdma_ae_pvid_mcqe *evt;
799 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
800 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
801
802 switch (type) {
803 case OCRDMA_ASYNC_EVENT_PVID_STATE:
804 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
805 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
806 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
807 dev->pvid = ((evt->tag_enabled &
808 OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
809 OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
810 break;
811
812 case OCRDMA_ASYNC_EVENT_COS_VALUE:
813 atomic_set(&dev->update_sl, 1);
814 break;
815 default:
816 /* Not interested evts. */
817 break;
818 }
819 }
820
821 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
822 {
823 /* async CQE processing */
824 struct ocrdma_ae_mcqe *cqe = ae_cqe;
825 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
826 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
827
828 if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE)
829 ocrdma_dispatch_ibevent(dev, cqe);
830 else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE)
831 ocrdma_process_grp5_aync(dev, cqe);
832 else
833 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
834 dev->id, evt_code);
835 }
836
837 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
838 {
839 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
840 dev->mqe_ctx.cqe_status = (cqe->status &
841 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
842 dev->mqe_ctx.ext_status =
843 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
844 >> OCRDMA_MCQE_ESTATUS_SHIFT;
845 dev->mqe_ctx.cmd_done = true;
846 wake_up(&dev->mqe_ctx.cmd_wait);
847 } else
848 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
849 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
850 }
851
852 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
853 {
854 u16 cqe_popped = 0;
855 struct ocrdma_mcqe *cqe;
856
857 while (1) {
858 cqe = ocrdma_get_mcqe(dev);
859 if (cqe == NULL)
860 break;
861 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
862 cqe_popped += 1;
863 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
864 ocrdma_process_acqe(dev, cqe);
865 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
866 ocrdma_process_mcqe(dev, cqe);
867 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
868 ocrdma_mcq_inc_tail(dev);
869 }
870 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
871 return 0;
872 }
873
874 static struct ocrdma_cq *_ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
875 struct ocrdma_cq *cq, bool sq)
876 {
877 struct ocrdma_qp *qp;
878 struct list_head *cur;
879 struct ocrdma_cq *bcq = NULL;
880 struct list_head *head = sq?(&cq->sq_head):(&cq->rq_head);
881
882 list_for_each(cur, head) {
883 if (sq)
884 qp = list_entry(cur, struct ocrdma_qp, sq_entry);
885 else
886 qp = list_entry(cur, struct ocrdma_qp, rq_entry);
887
888 if (qp->srq)
889 continue;
890 /* if wq and rq share the same cq, than comp_handler
891 * is already invoked.
892 */
893 if (qp->sq_cq == qp->rq_cq)
894 continue;
895 /* if completion came on sq, rq's cq is buddy cq.
896 * if completion came on rq, sq's cq is buddy cq.
897 */
898 if (qp->sq_cq == cq)
899 bcq = qp->rq_cq;
900 else
901 bcq = qp->sq_cq;
902 return bcq;
903 }
904 return NULL;
905 }
906
907 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
908 struct ocrdma_cq *cq)
909 {
910 unsigned long flags;
911 struct ocrdma_cq *bcq = NULL;
912
913 /* Go through list of QPs in error state which are using this CQ
914 * and invoke its callback handler to trigger CQE processing for
915 * error/flushed CQE. It is rare to find more than few entries in
916 * this list as most consumers stops after getting error CQE.
917 * List is traversed only once when a matching buddy cq found for a QP.
918 */
919 spin_lock_irqsave(&dev->flush_q_lock, flags);
920 /* Check if buddy CQ is present.
921 * true - Check for SQ CQ
922 * false - Check for RQ CQ
923 */
924 bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, true);
925 if (bcq == NULL)
926 bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, false);
927 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
928
929 /* if there is valid buddy cq, look for its completion handler */
930 if (bcq && bcq->ibcq.comp_handler) {
931 spin_lock_irqsave(&bcq->comp_handler_lock, flags);
932 (*bcq->ibcq.comp_handler) (&bcq->ibcq, bcq->ibcq.cq_context);
933 spin_unlock_irqrestore(&bcq->comp_handler_lock, flags);
934 }
935 }
936
937 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
938 {
939 unsigned long flags;
940 struct ocrdma_cq *cq;
941
942 if (cq_idx >= OCRDMA_MAX_CQ)
943 BUG();
944
945 cq = dev->cq_tbl[cq_idx];
946 if (cq == NULL)
947 return;
948
949 if (cq->ibcq.comp_handler) {
950 spin_lock_irqsave(&cq->comp_handler_lock, flags);
951 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
952 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
953 }
954 ocrdma_qp_buddy_cq_handler(dev, cq);
955 }
956
957 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
958 {
959 /* process the MQ-CQE. */
960 if (cq_id == dev->mq.cq.id)
961 ocrdma_mq_cq_handler(dev, cq_id);
962 else
963 ocrdma_qp_cq_handler(dev, cq_id);
964 }
965
966 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
967 {
968 struct ocrdma_eq *eq = handle;
969 struct ocrdma_dev *dev = eq->dev;
970 struct ocrdma_eqe eqe;
971 struct ocrdma_eqe *ptr;
972 u16 cq_id;
973 u8 mcode;
974 int budget = eq->cq_cnt;
975
976 do {
977 ptr = ocrdma_get_eqe(eq);
978 eqe = *ptr;
979 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
980 mcode = (eqe.id_valid & OCRDMA_EQE_MAJOR_CODE_MASK)
981 >> OCRDMA_EQE_MAJOR_CODE_SHIFT;
982 if (mcode == OCRDMA_MAJOR_CODE_SENTINAL)
983 pr_err("EQ full on eqid = 0x%x, eqe = 0x%x\n",
984 eq->q.id, eqe.id_valid);
985 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
986 break;
987
988 ptr->id_valid = 0;
989 /* ring eq doorbell as soon as its consumed. */
990 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
991 /* check whether its CQE or not. */
992 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
993 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
994 ocrdma_cq_handler(dev, cq_id);
995 }
996 ocrdma_eq_inc_tail(eq);
997
998 /* There can be a stale EQE after the last bound CQ is
999 * destroyed. EQE valid and budget == 0 implies this.
1000 */
1001 if (budget)
1002 budget--;
1003
1004 } while (budget);
1005
1006 eq->aic_obj.eq_intr_cnt++;
1007 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
1008 return IRQ_HANDLED;
1009 }
1010
1011 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
1012 {
1013 struct ocrdma_mqe *mqe;
1014
1015 dev->mqe_ctx.tag = dev->mq.sq.head;
1016 dev->mqe_ctx.cmd_done = false;
1017 mqe = ocrdma_get_mqe(dev);
1018 cmd->hdr.tag_lo = dev->mq.sq.head;
1019 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
1020 /* make sure descriptor is written before ringing doorbell */
1021 wmb();
1022 ocrdma_mq_inc_head(dev);
1023 ocrdma_ring_mq_db(dev);
1024 }
1025
1026 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
1027 {
1028 long status;
1029 /* 30 sec timeout */
1030 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
1031 (dev->mqe_ctx.cmd_done != false),
1032 msecs_to_jiffies(30000));
1033 if (status)
1034 return 0;
1035 else {
1036 dev->mqe_ctx.fw_error_state = true;
1037 pr_err("%s(%d) mailbox timeout: fw not responding\n",
1038 __func__, dev->id);
1039 return -1;
1040 }
1041 }
1042
1043 /* issue a mailbox command on the MQ */
1044 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
1045 {
1046 int status = 0;
1047 u16 cqe_status, ext_status;
1048 struct ocrdma_mqe *rsp_mqe;
1049 struct ocrdma_mbx_rsp *rsp = NULL;
1050
1051 mutex_lock(&dev->mqe_ctx.lock);
1052 if (dev->mqe_ctx.fw_error_state)
1053 goto mbx_err;
1054 ocrdma_post_mqe(dev, mqe);
1055 status = ocrdma_wait_mqe_cmpl(dev);
1056 if (status)
1057 goto mbx_err;
1058 cqe_status = dev->mqe_ctx.cqe_status;
1059 ext_status = dev->mqe_ctx.ext_status;
1060 rsp_mqe = ocrdma_get_mqe_rsp(dev);
1061 ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
1062 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1063 OCRDMA_MQE_HDR_EMB_SHIFT)
1064 rsp = &mqe->u.rsp;
1065
1066 if (cqe_status || ext_status) {
1067 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
1068 __func__, cqe_status, ext_status);
1069 if (rsp) {
1070 /* This is for embedded cmds. */
1071 pr_err("opcode=0x%x, subsystem=0x%x\n",
1072 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1073 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1074 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1075 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1076 }
1077 status = ocrdma_get_mbx_cqe_errno(cqe_status);
1078 goto mbx_err;
1079 }
1080 /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1081 if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
1082 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1083 mbx_err:
1084 mutex_unlock(&dev->mqe_ctx.lock);
1085 return status;
1086 }
1087
1088 static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1089 void *payload_va)
1090 {
1091 int status = 0;
1092 struct ocrdma_mbx_rsp *rsp = payload_va;
1093
1094 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1095 OCRDMA_MQE_HDR_EMB_SHIFT)
1096 BUG();
1097
1098 status = ocrdma_mbx_cmd(dev, mqe);
1099 if (!status)
1100 /* For non embedded, only CQE failures are handled in
1101 * ocrdma_mbx_cmd. We need to check for RSP errors.
1102 */
1103 if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1104 status = ocrdma_get_mbx_errno(rsp->status);
1105
1106 if (status)
1107 pr_err("opcode=0x%x, subsystem=0x%x\n",
1108 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1109 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1110 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1111 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1112 return status;
1113 }
1114
1115 static void ocrdma_get_attr(struct ocrdma_dev *dev,
1116 struct ocrdma_dev_attr *attr,
1117 struct ocrdma_mbx_query_config *rsp)
1118 {
1119 attr->max_pd =
1120 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1121 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
1122 attr->max_dpp_pds =
1123 (rsp->max_dpp_pds_credits & OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK) >>
1124 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET;
1125 attr->max_qp =
1126 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1127 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
1128 attr->max_srq =
1129 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1130 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
1131 attr->max_send_sge = ((rsp->max_write_send_sge &
1132 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1133 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1134 attr->max_recv_sge = (rsp->max_write_send_sge &
1135 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1136 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
1137 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1138 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1139 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
1140 attr->max_rdma_sge = (rsp->max_write_send_sge &
1141 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
1142 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
1143 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1144 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1145 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1146 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1147 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1148 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1149 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1150 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1151 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1152 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1153 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1154 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1155 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1156 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1157 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1158 attr->max_mw = rsp->max_mw;
1159 attr->max_mr = rsp->max_mr;
1160 attr->max_mr_size = ((u64)rsp->max_mr_size_hi << 32) |
1161 rsp->max_mr_size_lo;
1162 attr->max_fmr = 0;
1163 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1164 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1165 attr->max_cqe = rsp->max_cq_cqes_per_cq &
1166 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1167 attr->max_cq = (rsp->max_cq_cqes_per_cq &
1168 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1169 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
1170 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1171 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1172 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1173 OCRDMA_WQE_STRIDE;
1174 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1175 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1176 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1177 OCRDMA_WQE_STRIDE;
1178 attr->max_inline_data =
1179 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1180 sizeof(struct ocrdma_sge));
1181 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1182 attr->ird = 1;
1183 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1184 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1185 }
1186 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1187 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1188 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1189 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1190 }
1191
1192 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1193 struct ocrdma_fw_conf_rsp *conf)
1194 {
1195 u32 fn_mode;
1196
1197 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1198 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1199 return -EINVAL;
1200 dev->base_eqid = conf->base_eqid;
1201 dev->max_eq = conf->max_eq;
1202 return 0;
1203 }
1204
1205 /* can be issued only during init time. */
1206 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1207 {
1208 int status = -ENOMEM;
1209 struct ocrdma_mqe *cmd;
1210 struct ocrdma_fw_ver_rsp *rsp;
1211
1212 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1213 if (!cmd)
1214 return -ENOMEM;
1215 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1216 OCRDMA_CMD_GET_FW_VER,
1217 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1218
1219 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1220 if (status)
1221 goto mbx_err;
1222 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1223 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1224 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1225 sizeof(rsp->running_ver));
1226 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1227 mbx_err:
1228 kfree(cmd);
1229 return status;
1230 }
1231
1232 /* can be issued only during init time. */
1233 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1234 {
1235 int status = -ENOMEM;
1236 struct ocrdma_mqe *cmd;
1237 struct ocrdma_fw_conf_rsp *rsp;
1238
1239 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1240 if (!cmd)
1241 return -ENOMEM;
1242 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1243 OCRDMA_CMD_GET_FW_CONFIG,
1244 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1245 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1246 if (status)
1247 goto mbx_err;
1248 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1249 status = ocrdma_check_fw_config(dev, rsp);
1250 mbx_err:
1251 kfree(cmd);
1252 return status;
1253 }
1254
1255 int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1256 {
1257 struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1258 struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
1259 struct ocrdma_rdma_stats_resp *old_stats;
1260 int status;
1261
1262 old_stats = kmalloc(sizeof(*old_stats), GFP_KERNEL);
1263 if (old_stats == NULL)
1264 return -ENOMEM;
1265
1266 memset(mqe, 0, sizeof(*mqe));
1267 mqe->hdr.pyld_len = dev->stats_mem.size;
1268 mqe->hdr.spcl_sge_cnt_emb |=
1269 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1270 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1271 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1272 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1273 mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1274
1275 /* Cache the old stats */
1276 memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1277 memset(req, 0, dev->stats_mem.size);
1278
1279 ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1280 OCRDMA_CMD_GET_RDMA_STATS,
1281 OCRDMA_SUBSYS_ROCE,
1282 dev->stats_mem.size);
1283 if (reset)
1284 req->reset_stats = reset;
1285
1286 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1287 if (status)
1288 /* Copy from cache, if mbox fails */
1289 memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1290 else
1291 ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1292
1293 kfree(old_stats);
1294 return status;
1295 }
1296
1297 static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1298 {
1299 int status = -ENOMEM;
1300 struct ocrdma_dma_mem dma;
1301 struct ocrdma_mqe *mqe;
1302 struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1303 struct mgmt_hba_attribs *hba_attribs;
1304
1305 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
1306 if (!mqe)
1307 return status;
1308
1309 dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1310 dma.va = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1311 dma.size, &dma.pa, GFP_KERNEL);
1312 if (!dma.va)
1313 goto free_mqe;
1314
1315 mqe->hdr.pyld_len = dma.size;
1316 mqe->hdr.spcl_sge_cnt_emb |=
1317 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1318 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1319 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1320 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1321 mqe->u.nonemb_req.sge[0].len = dma.size;
1322
1323 memset(dma.va, 0, dma.size);
1324 ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1325 OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1326 OCRDMA_SUBSYS_COMMON,
1327 dma.size);
1328
1329 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1330 if (!status) {
1331 ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1332 hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1333
1334 dev->hba_port_num = (hba_attribs->ptpnum_maxdoms_hbast_cv &
1335 OCRDMA_HBA_ATTRB_PTNUM_MASK)
1336 >> OCRDMA_HBA_ATTRB_PTNUM_SHIFT;
1337 strncpy(dev->model_number,
1338 hba_attribs->controller_model_number, 31);
1339 }
1340 dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1341 free_mqe:
1342 kfree(mqe);
1343 return status;
1344 }
1345
1346 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1347 {
1348 int status = -ENOMEM;
1349 struct ocrdma_mbx_query_config *rsp;
1350 struct ocrdma_mqe *cmd;
1351
1352 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1353 if (!cmd)
1354 return status;
1355 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1356 if (status)
1357 goto mbx_err;
1358 rsp = (struct ocrdma_mbx_query_config *)cmd;
1359 ocrdma_get_attr(dev, &dev->attr, rsp);
1360 mbx_err:
1361 kfree(cmd);
1362 return status;
1363 }
1364
1365 int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed)
1366 {
1367 int status = -ENOMEM;
1368 struct ocrdma_get_link_speed_rsp *rsp;
1369 struct ocrdma_mqe *cmd;
1370
1371 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1372 sizeof(*cmd));
1373 if (!cmd)
1374 return status;
1375 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1376 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1377 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1378
1379 ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1380
1381 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1382 if (status)
1383 goto mbx_err;
1384
1385 rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1386 *lnk_speed = (rsp->pflt_pps_ld_pnum & OCRDMA_PHY_PS_MASK)
1387 >> OCRDMA_PHY_PS_SHIFT;
1388
1389 mbx_err:
1390 kfree(cmd);
1391 return status;
1392 }
1393
1394 static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1395 {
1396 int status = -ENOMEM;
1397 struct ocrdma_mqe *cmd;
1398 struct ocrdma_get_phy_info_rsp *rsp;
1399
1400 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1401 if (!cmd)
1402 return status;
1403
1404 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1405 OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1406 sizeof(*cmd));
1407
1408 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1409 if (status)
1410 goto mbx_err;
1411
1412 rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
1413 dev->phy.phy_type =
1414 (rsp->ityp_ptyp & OCRDMA_PHY_TYPE_MASK);
1415 dev->phy.interface_type =
1416 (rsp->ityp_ptyp & OCRDMA_IF_TYPE_MASK)
1417 >> OCRDMA_IF_TYPE_SHIFT;
1418 dev->phy.auto_speeds_supported =
1419 (rsp->fspeed_aspeed & OCRDMA_ASPEED_SUPP_MASK);
1420 dev->phy.fixed_speeds_supported =
1421 (rsp->fspeed_aspeed & OCRDMA_FSPEED_SUPP_MASK)
1422 >> OCRDMA_FSPEED_SUPP_SHIFT;
1423 mbx_err:
1424 kfree(cmd);
1425 return status;
1426 }
1427
1428 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1429 {
1430 int status = -ENOMEM;
1431 struct ocrdma_alloc_pd *cmd;
1432 struct ocrdma_alloc_pd_rsp *rsp;
1433
1434 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1435 if (!cmd)
1436 return status;
1437 if (pd->dpp_enabled)
1438 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1439 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1440 if (status)
1441 goto mbx_err;
1442 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1443 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1444 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1445 pd->dpp_enabled = true;
1446 pd->dpp_page = rsp->dpp_page_pdid >>
1447 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1448 } else {
1449 pd->dpp_enabled = false;
1450 pd->num_dpp_qp = 0;
1451 }
1452 mbx_err:
1453 kfree(cmd);
1454 return status;
1455 }
1456
1457 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1458 {
1459 int status = -ENOMEM;
1460 struct ocrdma_dealloc_pd *cmd;
1461
1462 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1463 if (!cmd)
1464 return status;
1465 cmd->id = pd->id;
1466 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1467 kfree(cmd);
1468 return status;
1469 }
1470
1471
1472 static int ocrdma_mbx_alloc_pd_range(struct ocrdma_dev *dev)
1473 {
1474 int status = -ENOMEM;
1475 size_t pd_bitmap_size;
1476 struct ocrdma_alloc_pd_range *cmd;
1477 struct ocrdma_alloc_pd_range_rsp *rsp;
1478
1479 /* Pre allocate the DPP PDs */
1480 if (dev->attr.max_dpp_pds) {
1481 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE,
1482 sizeof(*cmd));
1483 if (!cmd)
1484 return -ENOMEM;
1485 cmd->pd_count = dev->attr.max_dpp_pds;
1486 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1487 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1488 rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1489
1490 if (!status && (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) &&
1491 rsp->pd_count) {
1492 dev->pd_mgr->dpp_page_index = rsp->dpp_page_pdid >>
1493 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1494 dev->pd_mgr->pd_dpp_start = rsp->dpp_page_pdid &
1495 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1496 dev->pd_mgr->max_dpp_pd = rsp->pd_count;
1497 pd_bitmap_size =
1498 BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1499 dev->pd_mgr->pd_dpp_bitmap = kzalloc(pd_bitmap_size,
1500 GFP_KERNEL);
1501 }
1502 kfree(cmd);
1503 }
1504
1505 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd));
1506 if (!cmd)
1507 return -ENOMEM;
1508
1509 cmd->pd_count = dev->attr.max_pd - dev->attr.max_dpp_pds;
1510 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1511 rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1512 if (!status && rsp->pd_count) {
1513 dev->pd_mgr->pd_norm_start = rsp->dpp_page_pdid &
1514 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1515 dev->pd_mgr->max_normal_pd = rsp->pd_count;
1516 pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1517 dev->pd_mgr->pd_norm_bitmap = kzalloc(pd_bitmap_size,
1518 GFP_KERNEL);
1519 }
1520 kfree(cmd);
1521
1522 if (dev->pd_mgr->pd_norm_bitmap || dev->pd_mgr->pd_dpp_bitmap) {
1523 /* Enable PD resource manager */
1524 dev->pd_mgr->pd_prealloc_valid = true;
1525 return 0;
1526 }
1527 return status;
1528 }
1529
1530 static void ocrdma_mbx_dealloc_pd_range(struct ocrdma_dev *dev)
1531 {
1532 struct ocrdma_dealloc_pd_range *cmd;
1533
1534 /* return normal PDs to firmware */
1535 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE, sizeof(*cmd));
1536 if (!cmd)
1537 goto mbx_err;
1538
1539 if (dev->pd_mgr->max_normal_pd) {
1540 cmd->start_pd_id = dev->pd_mgr->pd_norm_start;
1541 cmd->pd_count = dev->pd_mgr->max_normal_pd;
1542 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1543 }
1544
1545 if (dev->pd_mgr->max_dpp_pd) {
1546 kfree(cmd);
1547 /* return DPP PDs to firmware */
1548 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE,
1549 sizeof(*cmd));
1550 if (!cmd)
1551 goto mbx_err;
1552
1553 cmd->start_pd_id = dev->pd_mgr->pd_dpp_start;
1554 cmd->pd_count = dev->pd_mgr->max_dpp_pd;
1555 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1556 }
1557 mbx_err:
1558 kfree(cmd);
1559 }
1560
1561 void ocrdma_alloc_pd_pool(struct ocrdma_dev *dev)
1562 {
1563 int status;
1564
1565 dev->pd_mgr = kzalloc(sizeof(struct ocrdma_pd_resource_mgr),
1566 GFP_KERNEL);
1567 if (!dev->pd_mgr) {
1568 pr_err("%s(%d)Memory allocation failure.\n", __func__, dev->id);
1569 return;
1570 }
1571 status = ocrdma_mbx_alloc_pd_range(dev);
1572 if (status) {
1573 pr_err("%s(%d) Unable to initialize PD pool, using default.\n",
1574 __func__, dev->id);
1575 }
1576 }
1577
1578 static void ocrdma_free_pd_pool(struct ocrdma_dev *dev)
1579 {
1580 ocrdma_mbx_dealloc_pd_range(dev);
1581 kfree(dev->pd_mgr->pd_norm_bitmap);
1582 kfree(dev->pd_mgr->pd_dpp_bitmap);
1583 kfree(dev->pd_mgr);
1584 }
1585
1586 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1587 int *num_pages, int *page_size)
1588 {
1589 int i;
1590 int mem_size;
1591
1592 *num_entries = roundup_pow_of_two(*num_entries);
1593 mem_size = *num_entries * entry_size;
1594 /* find the possible lowest possible multiplier */
1595 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1596 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1597 break;
1598 }
1599 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1600 return -EINVAL;
1601 mem_size = roundup(mem_size,
1602 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1603 *num_pages =
1604 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1605 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1606 *num_entries = mem_size / entry_size;
1607 return 0;
1608 }
1609
1610 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1611 {
1612 int i;
1613 int status = 0;
1614 int max_ah;
1615 struct ocrdma_create_ah_tbl *cmd;
1616 struct ocrdma_create_ah_tbl_rsp *rsp;
1617 struct pci_dev *pdev = dev->nic_info.pdev;
1618 dma_addr_t pa;
1619 struct ocrdma_pbe *pbes;
1620
1621 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1622 if (!cmd)
1623 return status;
1624
1625 max_ah = OCRDMA_MAX_AH;
1626 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1627
1628 /* number of PBEs in PBL */
1629 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1630 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1631 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1632
1633 /* page size */
1634 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1635 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1636 break;
1637 }
1638 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1639 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1640
1641 /* ah_entry size */
1642 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1643 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1644 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1645
1646 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1647 &dev->av_tbl.pbl.pa,
1648 GFP_KERNEL);
1649 if (dev->av_tbl.pbl.va == NULL)
1650 goto mem_err;
1651
1652 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1653 &pa, GFP_KERNEL);
1654 if (dev->av_tbl.va == NULL)
1655 goto mem_err_ah;
1656 dev->av_tbl.pa = pa;
1657 dev->av_tbl.num_ah = max_ah;
1658 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1659
1660 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1661 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1662 pbes[i].pa_lo = (u32)cpu_to_le32(pa & 0xffffffff);
1663 pbes[i].pa_hi = (u32)cpu_to_le32(upper_32_bits(pa));
1664 pa += PAGE_SIZE;
1665 }
1666 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1667 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1668 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1669 if (status)
1670 goto mbx_err;
1671 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1672 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1673 kfree(cmd);
1674 return 0;
1675
1676 mbx_err:
1677 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1678 dev->av_tbl.pa);
1679 dev->av_tbl.va = NULL;
1680 mem_err_ah:
1681 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1682 dev->av_tbl.pbl.pa);
1683 dev->av_tbl.pbl.va = NULL;
1684 dev->av_tbl.size = 0;
1685 mem_err:
1686 kfree(cmd);
1687 return status;
1688 }
1689
1690 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1691 {
1692 struct ocrdma_delete_ah_tbl *cmd;
1693 struct pci_dev *pdev = dev->nic_info.pdev;
1694
1695 if (dev->av_tbl.va == NULL)
1696 return;
1697
1698 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1699 if (!cmd)
1700 return;
1701 cmd->ahid = dev->av_tbl.ahid;
1702
1703 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1704 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1705 dev->av_tbl.pa);
1706 dev->av_tbl.va = NULL;
1707 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1708 dev->av_tbl.pbl.pa);
1709 kfree(cmd);
1710 }
1711
1712 /* Multiple CQs uses the EQ. This routine returns least used
1713 * EQ to associate with CQ. This will distributes the interrupt
1714 * processing and CPU load to associated EQ, vector and so to that CPU.
1715 */
1716 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1717 {
1718 int i, selected_eq = 0, cq_cnt = 0;
1719 u16 eq_id;
1720
1721 mutex_lock(&dev->dev_lock);
1722 cq_cnt = dev->eq_tbl[0].cq_cnt;
1723 eq_id = dev->eq_tbl[0].q.id;
1724 /* find the EQ which is has the least number of
1725 * CQs associated with it.
1726 */
1727 for (i = 0; i < dev->eq_cnt; i++) {
1728 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1729 cq_cnt = dev->eq_tbl[i].cq_cnt;
1730 eq_id = dev->eq_tbl[i].q.id;
1731 selected_eq = i;
1732 }
1733 }
1734 dev->eq_tbl[selected_eq].cq_cnt += 1;
1735 mutex_unlock(&dev->dev_lock);
1736 return eq_id;
1737 }
1738
1739 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1740 {
1741 int i;
1742
1743 mutex_lock(&dev->dev_lock);
1744 i = ocrdma_get_eq_table_index(dev, eq_id);
1745 if (i == -EINVAL)
1746 BUG();
1747 dev->eq_tbl[i].cq_cnt -= 1;
1748 mutex_unlock(&dev->dev_lock);
1749 }
1750
1751 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1752 int entries, int dpp_cq, u16 pd_id)
1753 {
1754 int status = -ENOMEM; int max_hw_cqe;
1755 struct pci_dev *pdev = dev->nic_info.pdev;
1756 struct ocrdma_create_cq *cmd;
1757 struct ocrdma_create_cq_rsp *rsp;
1758 u32 hw_pages, cqe_size, page_size, cqe_count;
1759
1760 if (entries > dev->attr.max_cqe) {
1761 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1762 __func__, dev->id, dev->attr.max_cqe, entries);
1763 return -EINVAL;
1764 }
1765 if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
1766 return -EINVAL;
1767
1768 if (dpp_cq) {
1769 cq->max_hw_cqe = 1;
1770 max_hw_cqe = 1;
1771 cqe_size = OCRDMA_DPP_CQE_SIZE;
1772 hw_pages = 1;
1773 } else {
1774 cq->max_hw_cqe = dev->attr.max_cqe;
1775 max_hw_cqe = dev->attr.max_cqe;
1776 cqe_size = sizeof(struct ocrdma_cqe);
1777 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1778 }
1779
1780 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1781
1782 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1783 if (!cmd)
1784 return -ENOMEM;
1785 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1786 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1787 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1788 if (!cq->va) {
1789 status = -ENOMEM;
1790 goto mem_err;
1791 }
1792 memset(cq->va, 0, cq->len);
1793 page_size = cq->len / hw_pages;
1794 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1795 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1796 cmd->cmd.pgsz_pgcnt |= hw_pages;
1797 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1798
1799 cq->eqn = ocrdma_bind_eq(dev);
1800 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
1801 cqe_count = cq->len / cqe_size;
1802 cq->cqe_cnt = cqe_count;
1803 if (cqe_count > 1024) {
1804 /* Set cnt to 3 to indicate more than 1024 cq entries */
1805 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1806 } else {
1807 u8 count = 0;
1808 switch (cqe_count) {
1809 case 256:
1810 count = 0;
1811 break;
1812 case 512:
1813 count = 1;
1814 break;
1815 case 1024:
1816 count = 2;
1817 break;
1818 default:
1819 goto mbx_err;
1820 }
1821 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1822 }
1823 /* shared eq between all the consumer cqs. */
1824 cmd->cmd.eqn = cq->eqn;
1825 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1826 if (dpp_cq)
1827 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1828 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1829 cq->phase_change = false;
1830 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size);
1831 } else {
1832 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size) - 1;
1833 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1834 cq->phase_change = true;
1835 }
1836
1837 /* pd_id valid only for v3 */
1838 cmd->cmd.pdid_cqecnt |= (pd_id <<
1839 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT);
1840 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1841 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1842 if (status)
1843 goto mbx_err;
1844
1845 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1846 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1847 kfree(cmd);
1848 return 0;
1849 mbx_err:
1850 ocrdma_unbind_eq(dev, cq->eqn);
1851 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1852 mem_err:
1853 kfree(cmd);
1854 return status;
1855 }
1856
1857 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1858 {
1859 int status = -ENOMEM;
1860 struct ocrdma_destroy_cq *cmd;
1861
1862 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1863 if (!cmd)
1864 return status;
1865 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1866 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1867
1868 cmd->bypass_flush_qid |=
1869 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1870 OCRDMA_DESTROY_CQ_QID_MASK;
1871
1872 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1873 ocrdma_unbind_eq(dev, cq->eqn);
1874 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1875 kfree(cmd);
1876 return status;
1877 }
1878
1879 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1880 u32 pdid, int addr_check)
1881 {
1882 int status = -ENOMEM;
1883 struct ocrdma_alloc_lkey *cmd;
1884 struct ocrdma_alloc_lkey_rsp *rsp;
1885
1886 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1887 if (!cmd)
1888 return status;
1889 cmd->pdid = pdid;
1890 cmd->pbl_sz_flags |= addr_check;
1891 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1892 cmd->pbl_sz_flags |=
1893 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1894 cmd->pbl_sz_flags |=
1895 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1896 cmd->pbl_sz_flags |=
1897 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1898 cmd->pbl_sz_flags |=
1899 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1900 cmd->pbl_sz_flags |=
1901 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1902
1903 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1904 if (status)
1905 goto mbx_err;
1906 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1907 hwmr->lkey = rsp->lrkey;
1908 mbx_err:
1909 kfree(cmd);
1910 return status;
1911 }
1912
1913 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1914 {
1915 int status = -ENOMEM;
1916 struct ocrdma_dealloc_lkey *cmd;
1917
1918 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1919 if (!cmd)
1920 return -ENOMEM;
1921 cmd->lkey = lkey;
1922 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1923 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1924 if (status)
1925 goto mbx_err;
1926 mbx_err:
1927 kfree(cmd);
1928 return status;
1929 }
1930
1931 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1932 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1933 {
1934 int status = -ENOMEM;
1935 int i;
1936 struct ocrdma_reg_nsmr *cmd;
1937 struct ocrdma_reg_nsmr_rsp *rsp;
1938
1939 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1940 if (!cmd)
1941 return -ENOMEM;
1942 cmd->num_pbl_pdid =
1943 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1944 cmd->fr_mr = hwmr->fr_mr;
1945
1946 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1947 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1948 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1949 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1950 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1951 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1952 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1953 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1954 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1955 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1956 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1957
1958 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1959 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1960 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1961 cmd->totlen_low = hwmr->len;
1962 cmd->totlen_high = upper_32_bits(hwmr->len);
1963 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1964 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1965 cmd->va_loaddr = (u32) hwmr->va;
1966 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1967
1968 for (i = 0; i < pbl_cnt; i++) {
1969 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1970 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1971 }
1972 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1973 if (status)
1974 goto mbx_err;
1975 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1976 hwmr->lkey = rsp->lrkey;
1977 mbx_err:
1978 kfree(cmd);
1979 return status;
1980 }
1981
1982 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1983 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1984 u32 pbl_offset, u32 last)
1985 {
1986 int status = -ENOMEM;
1987 int i;
1988 struct ocrdma_reg_nsmr_cont *cmd;
1989
1990 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1991 if (!cmd)
1992 return -ENOMEM;
1993 cmd->lrkey = hwmr->lkey;
1994 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1995 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1996 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1997
1998 for (i = 0; i < pbl_cnt; i++) {
1999 cmd->pbl[i].lo =
2000 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
2001 cmd->pbl[i].hi =
2002 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
2003 }
2004 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2005 if (status)
2006 goto mbx_err;
2007 mbx_err:
2008 kfree(cmd);
2009 return status;
2010 }
2011
2012 int ocrdma_reg_mr(struct ocrdma_dev *dev,
2013 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
2014 {
2015 int status;
2016 u32 last = 0;
2017 u32 cur_pbl_cnt, pbl_offset;
2018 u32 pending_pbl_cnt = hwmr->num_pbls;
2019
2020 pbl_offset = 0;
2021 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
2022 if (cur_pbl_cnt == pending_pbl_cnt)
2023 last = 1;
2024
2025 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
2026 cur_pbl_cnt, hwmr->pbe_size, last);
2027 if (status) {
2028 pr_err("%s() status=%d\n", __func__, status);
2029 return status;
2030 }
2031 /* if there is no more pbls to register then exit. */
2032 if (last)
2033 return 0;
2034
2035 while (!last) {
2036 pbl_offset += cur_pbl_cnt;
2037 pending_pbl_cnt -= cur_pbl_cnt;
2038 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
2039 /* if we reach the end of the pbls, then need to set the last
2040 * bit, indicating no more pbls to register for this memory key.
2041 */
2042 if (cur_pbl_cnt == pending_pbl_cnt)
2043 last = 1;
2044
2045 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
2046 pbl_offset, last);
2047 if (status)
2048 break;
2049 }
2050 if (status)
2051 pr_err("%s() err. status=%d\n", __func__, status);
2052
2053 return status;
2054 }
2055
2056 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2057 {
2058 struct ocrdma_qp *tmp;
2059 bool found = false;
2060 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
2061 if (qp == tmp) {
2062 found = true;
2063 break;
2064 }
2065 }
2066 return found;
2067 }
2068
2069 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2070 {
2071 struct ocrdma_qp *tmp;
2072 bool found = false;
2073 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
2074 if (qp == tmp) {
2075 found = true;
2076 break;
2077 }
2078 }
2079 return found;
2080 }
2081
2082 void ocrdma_flush_qp(struct ocrdma_qp *qp)
2083 {
2084 bool found;
2085 unsigned long flags;
2086 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2087
2088 spin_lock_irqsave(&dev->flush_q_lock, flags);
2089 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
2090 if (!found)
2091 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
2092 if (!qp->srq) {
2093 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
2094 if (!found)
2095 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
2096 }
2097 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
2098 }
2099
2100 static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
2101 {
2102 qp->sq.head = 0;
2103 qp->sq.tail = 0;
2104 qp->rq.head = 0;
2105 qp->rq.tail = 0;
2106 }
2107
2108 int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
2109 enum ib_qp_state *old_ib_state)
2110 {
2111 unsigned long flags;
2112 int status = 0;
2113 enum ocrdma_qp_state new_state;
2114 new_state = get_ocrdma_qp_state(new_ib_state);
2115
2116 /* sync with wqe and rqe posting */
2117 spin_lock_irqsave(&qp->q_lock, flags);
2118
2119 if (old_ib_state)
2120 *old_ib_state = get_ibqp_state(qp->state);
2121 if (new_state == qp->state) {
2122 spin_unlock_irqrestore(&qp->q_lock, flags);
2123 return 1;
2124 }
2125
2126
2127 if (new_state == OCRDMA_QPS_INIT) {
2128 ocrdma_init_hwq_ptr(qp);
2129 ocrdma_del_flush_qp(qp);
2130 } else if (new_state == OCRDMA_QPS_ERR) {
2131 ocrdma_flush_qp(qp);
2132 }
2133
2134 qp->state = new_state;
2135
2136 spin_unlock_irqrestore(&qp->q_lock, flags);
2137 return status;
2138 }
2139
2140 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
2141 {
2142 u32 flags = 0;
2143 if (qp->cap_flags & OCRDMA_QP_INB_RD)
2144 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
2145 if (qp->cap_flags & OCRDMA_QP_INB_WR)
2146 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
2147 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
2148 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
2149 if (qp->cap_flags & OCRDMA_QP_LKEY0)
2150 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
2151 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
2152 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
2153 return flags;
2154 }
2155
2156 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
2157 struct ib_qp_init_attr *attrs,
2158 struct ocrdma_qp *qp)
2159 {
2160 int status;
2161 u32 len, hw_pages, hw_page_size;
2162 dma_addr_t pa;
2163 struct ocrdma_pd *pd = qp->pd;
2164 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2165 struct pci_dev *pdev = dev->nic_info.pdev;
2166 u32 max_wqe_allocated;
2167 u32 max_sges = attrs->cap.max_send_sge;
2168
2169 /* QP1 may exceed 127 */
2170 max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
2171 dev->attr.max_wqe);
2172
2173 status = ocrdma_build_q_conf(&max_wqe_allocated,
2174 dev->attr.wqe_size, &hw_pages, &hw_page_size);
2175 if (status) {
2176 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
2177 max_wqe_allocated);
2178 return -EINVAL;
2179 }
2180 qp->sq.max_cnt = max_wqe_allocated;
2181 len = (hw_pages * hw_page_size);
2182
2183 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2184 if (!qp->sq.va)
2185 return -EINVAL;
2186 memset(qp->sq.va, 0, len);
2187 qp->sq.len = len;
2188 qp->sq.pa = pa;
2189 qp->sq.entry_size = dev->attr.wqe_size;
2190 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
2191
2192 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2193 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
2194 cmd->num_wq_rq_pages |= (hw_pages <<
2195 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
2196 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
2197 cmd->max_sge_send_write |= (max_sges <<
2198 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
2199 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
2200 cmd->max_sge_send_write |= (max_sges <<
2201 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
2202 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
2203 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
2204 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
2205 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
2206 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2207 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2208 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2209 return 0;
2210 }
2211
2212 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2213 struct ib_qp_init_attr *attrs,
2214 struct ocrdma_qp *qp)
2215 {
2216 int status;
2217 u32 len, hw_pages, hw_page_size;
2218 dma_addr_t pa = 0;
2219 struct ocrdma_pd *pd = qp->pd;
2220 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2221 struct pci_dev *pdev = dev->nic_info.pdev;
2222 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2223
2224 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2225 &hw_pages, &hw_page_size);
2226 if (status) {
2227 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2228 attrs->cap.max_recv_wr + 1);
2229 return status;
2230 }
2231 qp->rq.max_cnt = max_rqe_allocated;
2232 len = (hw_pages * hw_page_size);
2233
2234 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2235 if (!qp->rq.va)
2236 return -ENOMEM;
2237 memset(qp->rq.va, 0, len);
2238 qp->rq.pa = pa;
2239 qp->rq.len = len;
2240 qp->rq.entry_size = dev->attr.rqe_size;
2241
2242 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2243 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2244 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2245 cmd->num_wq_rq_pages |=
2246 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2247 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2248 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2249 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2250 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2251 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2252 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2253 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2254 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2255 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2256 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2257 return 0;
2258 }
2259
2260 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2261 struct ocrdma_pd *pd,
2262 struct ocrdma_qp *qp,
2263 u8 enable_dpp_cq, u16 dpp_cq_id)
2264 {
2265 pd->num_dpp_qp--;
2266 qp->dpp_enabled = true;
2267 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2268 if (!enable_dpp_cq)
2269 return;
2270 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2271 cmd->dpp_credits_cqid = dpp_cq_id;
2272 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2273 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2274 }
2275
2276 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2277 struct ocrdma_qp *qp)
2278 {
2279 struct ocrdma_pd *pd = qp->pd;
2280 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2281 struct pci_dev *pdev = dev->nic_info.pdev;
2282 dma_addr_t pa = 0;
2283 int ird_page_size = dev->attr.ird_page_size;
2284 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
2285 struct ocrdma_hdr_wqe *rqe;
2286 int i = 0;
2287
2288 if (dev->attr.ird == 0)
2289 return 0;
2290
2291 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
2292 &pa, GFP_KERNEL);
2293 if (!qp->ird_q_va)
2294 return -ENOMEM;
2295 memset(qp->ird_q_va, 0, ird_q_len);
2296 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2297 pa, ird_page_size);
2298 for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2299 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2300 (i * dev->attr.rqe_size));
2301 rqe->cw = 0;
2302 rqe->cw |= 2;
2303 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2304 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2305 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2306 }
2307 return 0;
2308 }
2309
2310 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2311 struct ocrdma_qp *qp,
2312 struct ib_qp_init_attr *attrs,
2313 u16 *dpp_offset, u16 *dpp_credit_lmt)
2314 {
2315 u32 max_wqe_allocated, max_rqe_allocated;
2316 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2317 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2318 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2319 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2320 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2321 qp->dpp_enabled = false;
2322 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2323 qp->dpp_enabled = true;
2324 *dpp_credit_lmt = (rsp->dpp_response &
2325 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2326 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2327 *dpp_offset = (rsp->dpp_response &
2328 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2329 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2330 }
2331 max_wqe_allocated =
2332 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2333 max_wqe_allocated = 1 << max_wqe_allocated;
2334 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2335
2336 qp->sq.max_cnt = max_wqe_allocated;
2337 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2338
2339 if (!attrs->srq) {
2340 qp->rq.max_cnt = max_rqe_allocated;
2341 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
2342 }
2343 }
2344
2345 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2346 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2347 u16 *dpp_credit_lmt)
2348 {
2349 int status = -ENOMEM;
2350 u32 flags = 0;
2351 struct ocrdma_pd *pd = qp->pd;
2352 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2353 struct pci_dev *pdev = dev->nic_info.pdev;
2354 struct ocrdma_cq *cq;
2355 struct ocrdma_create_qp_req *cmd;
2356 struct ocrdma_create_qp_rsp *rsp;
2357 int qptype;
2358
2359 switch (attrs->qp_type) {
2360 case IB_QPT_GSI:
2361 qptype = OCRDMA_QPT_GSI;
2362 break;
2363 case IB_QPT_RC:
2364 qptype = OCRDMA_QPT_RC;
2365 break;
2366 case IB_QPT_UD:
2367 qptype = OCRDMA_QPT_UD;
2368 break;
2369 default:
2370 return -EINVAL;
2371 }
2372
2373 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2374 if (!cmd)
2375 return status;
2376 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2377 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2378 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2379 if (status)
2380 goto sq_err;
2381
2382 if (attrs->srq) {
2383 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2384 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2385 cmd->rq_addr[0].lo = srq->id;
2386 qp->srq = srq;
2387 } else {
2388 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2389 if (status)
2390 goto rq_err;
2391 }
2392
2393 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2394 if (status)
2395 goto mbx_err;
2396
2397 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2398 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2399
2400 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2401
2402 cmd->max_sge_recv_flags |= flags;
2403 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2404 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2405 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2406 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2407 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2408 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2409 cq = get_ocrdma_cq(attrs->send_cq);
2410 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2411 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2412 qp->sq_cq = cq;
2413 cq = get_ocrdma_cq(attrs->recv_cq);
2414 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2415 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2416 qp->rq_cq = cq;
2417
2418 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2419 (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
2420 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2421 dpp_cq_id);
2422 }
2423
2424 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2425 if (status)
2426 goto mbx_err;
2427 rsp = (struct ocrdma_create_qp_rsp *)cmd;
2428 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2429 qp->state = OCRDMA_QPS_RST;
2430 kfree(cmd);
2431 return 0;
2432 mbx_err:
2433 if (qp->rq.va)
2434 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2435 rq_err:
2436 pr_err("%s(%d) rq_err\n", __func__, dev->id);
2437 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2438 sq_err:
2439 pr_err("%s(%d) sq_err\n", __func__, dev->id);
2440 kfree(cmd);
2441 return status;
2442 }
2443
2444 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2445 struct ocrdma_qp_params *param)
2446 {
2447 int status = -ENOMEM;
2448 struct ocrdma_query_qp *cmd;
2449 struct ocrdma_query_qp_rsp *rsp;
2450
2451 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*rsp));
2452 if (!cmd)
2453 return status;
2454 cmd->qp_id = qp->id;
2455 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2456 if (status)
2457 goto mbx_err;
2458 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2459 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2460 mbx_err:
2461 kfree(cmd);
2462 return status;
2463 }
2464
2465 static int ocrdma_set_av_params(struct ocrdma_qp *qp,
2466 struct ocrdma_modify_qp *cmd,
2467 struct ib_qp_attr *attrs,
2468 int attr_mask)
2469 {
2470 int status;
2471 struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2472 union ib_gid sgid, zgid;
2473 u32 vlan_id = 0xFFFF;
2474 u8 mac_addr[6];
2475 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2476
2477 if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2478 return -EINVAL;
2479 if (atomic_cmpxchg(&dev->update_sl, 1, 0))
2480 ocrdma_init_service_level(dev);
2481 cmd->params.tclass_sq_psn |=
2482 (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2483 cmd->params.rnt_rc_sl_fl |=
2484 (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2485 cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
2486 cmd->params.hop_lmt_rq_psn |=
2487 (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2488 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2489 memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2490 sizeof(cmd->params.dgid));
2491 status = ocrdma_query_gid(&dev->ibdev, 1,
2492 ah_attr->grh.sgid_index, &sgid);
2493 if (status)
2494 return status;
2495
2496 memset(&zgid, 0, sizeof(zgid));
2497 if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2498 return -EINVAL;
2499
2500 qp->sgid_idx = ah_attr->grh.sgid_index;
2501 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2502 status = ocrdma_resolve_dmac(dev, ah_attr, &mac_addr[0]);
2503 if (status)
2504 return status;
2505 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2506 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2507 /* convert them to LE format. */
2508 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2509 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2510 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2511 if (attr_mask & IB_QP_VID) {
2512 vlan_id = attrs->vlan_id;
2513 } else if (dev->pfc_state) {
2514 vlan_id = 0;
2515 pr_err("ocrdma%d:Using VLAN with PFC is recommended\n",
2516 dev->id);
2517 pr_err("ocrdma%d:Using VLAN 0 for this connection\n",
2518 dev->id);
2519 }
2520
2521 if (vlan_id < 0x1000) {
2522 cmd->params.vlan_dmac_b4_to_b5 |=
2523 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2524 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2525 cmd->params.rnt_rc_sl_fl |=
2526 (dev->sl & 0x07) << OCRDMA_QP_PARAMS_SL_SHIFT;
2527 }
2528
2529 return 0;
2530 }
2531
2532 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2533 struct ocrdma_modify_qp *cmd,
2534 struct ib_qp_attr *attrs, int attr_mask)
2535 {
2536 int status = 0;
2537 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2538
2539 if (attr_mask & IB_QP_PKEY_INDEX) {
2540 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2541 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2542 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2543 }
2544 if (attr_mask & IB_QP_QKEY) {
2545 qp->qkey = attrs->qkey;
2546 cmd->params.qkey = attrs->qkey;
2547 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2548 }
2549 if (attr_mask & IB_QP_AV) {
2550 status = ocrdma_set_av_params(qp, cmd, attrs, attr_mask);
2551 if (status)
2552 return status;
2553 } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2554 /* set the default mac address for UD, GSI QPs */
2555 cmd->params.dmac_b0_to_b3 = dev->nic_info.mac_addr[0] |
2556 (dev->nic_info.mac_addr[1] << 8) |
2557 (dev->nic_info.mac_addr[2] << 16) |
2558 (dev->nic_info.mac_addr[3] << 24);
2559 cmd->params.vlan_dmac_b4_to_b5 = dev->nic_info.mac_addr[4] |
2560 (dev->nic_info.mac_addr[5] << 8);
2561 }
2562 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2563 attrs->en_sqd_async_notify) {
2564 cmd->params.max_sge_recv_flags |=
2565 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2566 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2567 }
2568 if (attr_mask & IB_QP_DEST_QPN) {
2569 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2570 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2571 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2572 }
2573 if (attr_mask & IB_QP_PATH_MTU) {
2574 if (attrs->path_mtu < IB_MTU_512 ||
2575 attrs->path_mtu > IB_MTU_4096) {
2576 pr_err("ocrdma%d: IB MTU %d is not supported\n",
2577 dev->id, ib_mtu_enum_to_int(attrs->path_mtu));
2578 status = -EINVAL;
2579 goto pmtu_err;
2580 }
2581 cmd->params.path_mtu_pkey_indx |=
2582 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2583 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2584 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2585 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2586 }
2587 if (attr_mask & IB_QP_TIMEOUT) {
2588 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2589 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2590 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2591 }
2592 if (attr_mask & IB_QP_RETRY_CNT) {
2593 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2594 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2595 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2596 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2597 }
2598 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2599 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2600 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2601 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2602 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2603 }
2604 if (attr_mask & IB_QP_RNR_RETRY) {
2605 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2606 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2607 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2608 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2609 }
2610 if (attr_mask & IB_QP_SQ_PSN) {
2611 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2612 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2613 }
2614 if (attr_mask & IB_QP_RQ_PSN) {
2615 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2616 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2617 }
2618 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2619 if (attrs->max_rd_atomic > dev->attr.max_ord_per_qp) {
2620 status = -EINVAL;
2621 goto pmtu_err;
2622 }
2623 qp->max_ord = attrs->max_rd_atomic;
2624 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2625 }
2626 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2627 if (attrs->max_dest_rd_atomic > dev->attr.max_ird_per_qp) {
2628 status = -EINVAL;
2629 goto pmtu_err;
2630 }
2631 qp->max_ird = attrs->max_dest_rd_atomic;
2632 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2633 }
2634 cmd->params.max_ord_ird = (qp->max_ord <<
2635 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2636 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2637 pmtu_err:
2638 return status;
2639 }
2640
2641 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2642 struct ib_qp_attr *attrs, int attr_mask)
2643 {
2644 int status = -ENOMEM;
2645 struct ocrdma_modify_qp *cmd;
2646
2647 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2648 if (!cmd)
2649 return status;
2650
2651 cmd->params.id = qp->id;
2652 cmd->flags = 0;
2653 if (attr_mask & IB_QP_STATE) {
2654 cmd->params.max_sge_recv_flags |=
2655 (get_ocrdma_qp_state(attrs->qp_state) <<
2656 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2657 OCRDMA_QP_PARAMS_STATE_MASK;
2658 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2659 } else {
2660 cmd->params.max_sge_recv_flags |=
2661 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2662 OCRDMA_QP_PARAMS_STATE_MASK;
2663 }
2664
2665 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
2666 if (status)
2667 goto mbx_err;
2668 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2669 if (status)
2670 goto mbx_err;
2671
2672 mbx_err:
2673 kfree(cmd);
2674 return status;
2675 }
2676
2677 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2678 {
2679 int status = -ENOMEM;
2680 struct ocrdma_destroy_qp *cmd;
2681 struct pci_dev *pdev = dev->nic_info.pdev;
2682
2683 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2684 if (!cmd)
2685 return status;
2686 cmd->qp_id = qp->id;
2687 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2688 if (status)
2689 goto mbx_err;
2690
2691 mbx_err:
2692 kfree(cmd);
2693 if (qp->sq.va)
2694 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2695 if (!qp->srq && qp->rq.va)
2696 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2697 if (qp->dpp_enabled)
2698 qp->pd->num_dpp_qp++;
2699 return status;
2700 }
2701
2702 int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
2703 struct ib_srq_init_attr *srq_attr,
2704 struct ocrdma_pd *pd)
2705 {
2706 int status = -ENOMEM;
2707 int hw_pages, hw_page_size;
2708 int len;
2709 struct ocrdma_create_srq_rsp *rsp;
2710 struct ocrdma_create_srq *cmd;
2711 dma_addr_t pa;
2712 struct pci_dev *pdev = dev->nic_info.pdev;
2713 u32 max_rqe_allocated;
2714
2715 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2716 if (!cmd)
2717 return status;
2718
2719 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2720 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2721 status = ocrdma_build_q_conf(&max_rqe_allocated,
2722 dev->attr.rqe_size,
2723 &hw_pages, &hw_page_size);
2724 if (status) {
2725 pr_err("%s() req. max_wr=0x%x\n", __func__,
2726 srq_attr->attr.max_wr);
2727 status = -EINVAL;
2728 goto ret;
2729 }
2730 len = hw_pages * hw_page_size;
2731 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2732 if (!srq->rq.va) {
2733 status = -ENOMEM;
2734 goto ret;
2735 }
2736 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2737
2738 srq->rq.entry_size = dev->attr.rqe_size;
2739 srq->rq.pa = pa;
2740 srq->rq.len = len;
2741 srq->rq.max_cnt = max_rqe_allocated;
2742
2743 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2744 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2745 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2746
2747 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2748 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2749 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2750 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2751 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2752 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2753
2754 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2755 if (status)
2756 goto mbx_err;
2757 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2758 srq->id = rsp->id;
2759 srq->rq.dbid = rsp->id;
2760 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2761 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2762 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2763 max_rqe_allocated = (1 << max_rqe_allocated);
2764 srq->rq.max_cnt = max_rqe_allocated;
2765 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2766 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2767 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2768 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2769 goto ret;
2770 mbx_err:
2771 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2772 ret:
2773 kfree(cmd);
2774 return status;
2775 }
2776
2777 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2778 {
2779 int status = -ENOMEM;
2780 struct ocrdma_modify_srq *cmd;
2781 struct ocrdma_pd *pd = srq->pd;
2782 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2783
2784 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
2785 if (!cmd)
2786 return status;
2787 cmd->id = srq->id;
2788 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2789 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2790 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2791 kfree(cmd);
2792 return status;
2793 }
2794
2795 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2796 {
2797 int status = -ENOMEM;
2798 struct ocrdma_query_srq *cmd;
2799 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2800
2801 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
2802 if (!cmd)
2803 return status;
2804 cmd->id = srq->rq.dbid;
2805 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2806 if (status == 0) {
2807 struct ocrdma_query_srq_rsp *rsp =
2808 (struct ocrdma_query_srq_rsp *)cmd;
2809 srq_attr->max_sge =
2810 rsp->srq_lmt_max_sge &
2811 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2812 srq_attr->max_wr =
2813 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2814 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2815 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2816 }
2817 kfree(cmd);
2818 return status;
2819 }
2820
2821 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2822 {
2823 int status = -ENOMEM;
2824 struct ocrdma_destroy_srq *cmd;
2825 struct pci_dev *pdev = dev->nic_info.pdev;
2826 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2827 if (!cmd)
2828 return status;
2829 cmd->id = srq->id;
2830 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2831 if (srq->rq.va)
2832 dma_free_coherent(&pdev->dev, srq->rq.len,
2833 srq->rq.va, srq->rq.pa);
2834 kfree(cmd);
2835 return status;
2836 }
2837
2838 static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
2839 struct ocrdma_dcbx_cfg *dcbxcfg)
2840 {
2841 int status = 0;
2842 dma_addr_t pa;
2843 struct ocrdma_mqe cmd;
2844
2845 struct ocrdma_get_dcbx_cfg_req *req = NULL;
2846 struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
2847 struct pci_dev *pdev = dev->nic_info.pdev;
2848 struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
2849
2850 memset(&cmd, 0, sizeof(struct ocrdma_mqe));
2851 cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
2852 sizeof(struct ocrdma_get_dcbx_cfg_req));
2853 req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
2854 if (!req) {
2855 status = -ENOMEM;
2856 goto mem_err;
2857 }
2858
2859 cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
2860 OCRDMA_MQE_HDR_SGE_CNT_MASK;
2861 mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
2862 mqe_sge->pa_hi = (u32) upper_32_bits(pa);
2863 mqe_sge->len = cmd.hdr.pyld_len;
2864
2865 memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
2866 ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
2867 OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
2868 req->param_type = ptype;
2869
2870 status = ocrdma_mbx_cmd(dev, &cmd);
2871 if (status)
2872 goto mbx_err;
2873
2874 rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
2875 ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
2876 memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
2877
2878 mbx_err:
2879 dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
2880 mem_err:
2881 return status;
2882 }
2883
2884 #define OCRDMA_MAX_SERVICE_LEVEL_INDEX 0x08
2885 #define OCRDMA_DEFAULT_SERVICE_LEVEL 0x05
2886
2887 static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
2888 struct ocrdma_dcbx_cfg *dcbxcfg,
2889 u8 *srvc_lvl)
2890 {
2891 int status = -EINVAL, indx, slindx;
2892 int ventry_cnt;
2893 struct ocrdma_app_parameter *app_param;
2894 u8 valid, proto_sel;
2895 u8 app_prio, pfc_prio;
2896 u16 proto;
2897
2898 if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
2899 pr_info("%s ocrdma%d DCBX is disabled\n",
2900 dev_name(&dev->nic_info.pdev->dev), dev->id);
2901 goto out;
2902 }
2903
2904 if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
2905 pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2906 dev_name(&dev->nic_info.pdev->dev), dev->id,
2907 (ptype > 0 ? "operational" : "admin"),
2908 (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
2909 "enabled" : "disabled",
2910 (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
2911 "" : ", not sync'ed");
2912 goto out;
2913 } else {
2914 pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2915 dev_name(&dev->nic_info.pdev->dev), dev->id);
2916 }
2917
2918 ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
2919 OCRDMA_DCBX_APP_ENTRY_SHIFT)
2920 & OCRDMA_DCBX_STATE_MASK;
2921
2922 for (indx = 0; indx < ventry_cnt; indx++) {
2923 app_param = &dcbxcfg->app_param[indx];
2924 valid = (app_param->valid_proto_app >>
2925 OCRDMA_APP_PARAM_VALID_SHIFT)
2926 & OCRDMA_APP_PARAM_VALID_MASK;
2927 proto_sel = (app_param->valid_proto_app
2928 >> OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
2929 & OCRDMA_APP_PARAM_PROTO_SEL_MASK;
2930 proto = app_param->valid_proto_app &
2931 OCRDMA_APP_PARAM_APP_PROTO_MASK;
2932
2933 if (
2934 valid && proto == OCRDMA_APP_PROTO_ROCE &&
2935 proto_sel == OCRDMA_PROTO_SELECT_L2) {
2936 for (slindx = 0; slindx <
2937 OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
2938 app_prio = ocrdma_get_app_prio(
2939 (u8 *)app_param->app_prio,
2940 slindx);
2941 pfc_prio = ocrdma_get_pfc_prio(
2942 (u8 *)dcbxcfg->pfc_prio,
2943 slindx);
2944
2945 if (app_prio && pfc_prio) {
2946 *srvc_lvl = slindx;
2947 status = 0;
2948 goto out;
2949 }
2950 }
2951 if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
2952 pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
2953 dev_name(&dev->nic_info.pdev->dev),
2954 dev->id, proto);
2955 }
2956 }
2957 }
2958
2959 out:
2960 return status;
2961 }
2962
2963 void ocrdma_init_service_level(struct ocrdma_dev *dev)
2964 {
2965 int status = 0, indx;
2966 struct ocrdma_dcbx_cfg dcbxcfg;
2967 u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
2968 int ptype = OCRDMA_PARAMETER_TYPE_OPER;
2969
2970 for (indx = 0; indx < 2; indx++) {
2971 status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
2972 if (status) {
2973 pr_err("%s(): status=%d\n", __func__, status);
2974 ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2975 continue;
2976 }
2977
2978 status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
2979 &dcbxcfg, &srvc_lvl);
2980 if (status) {
2981 ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2982 continue;
2983 }
2984
2985 break;
2986 }
2987
2988 if (status)
2989 pr_info("%s ocrdma%d service level default\n",
2990 dev_name(&dev->nic_info.pdev->dev), dev->id);
2991 else
2992 pr_info("%s ocrdma%d service level %d\n",
2993 dev_name(&dev->nic_info.pdev->dev), dev->id,
2994 srvc_lvl);
2995
2996 dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
2997 dev->sl = srvc_lvl;
2998 }
2999
3000 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
3001 {
3002 int i;
3003 int status = -EINVAL;
3004 struct ocrdma_av *av;
3005 unsigned long flags;
3006
3007 av = dev->av_tbl.va;
3008 spin_lock_irqsave(&dev->av_tbl.lock, flags);
3009 for (i = 0; i < dev->av_tbl.num_ah; i++) {
3010 if (av->valid == 0) {
3011 av->valid = OCRDMA_AV_VALID;
3012 ah->av = av;
3013 ah->id = i;
3014 status = 0;
3015 break;
3016 }
3017 av++;
3018 }
3019 if (i == dev->av_tbl.num_ah)
3020 status = -EAGAIN;
3021 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
3022 return status;
3023 }
3024
3025 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
3026 {
3027 unsigned long flags;
3028 spin_lock_irqsave(&dev->av_tbl.lock, flags);
3029 ah->av->valid = 0;
3030 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
3031 return 0;
3032 }
3033
3034 static int ocrdma_create_eqs(struct ocrdma_dev *dev)
3035 {
3036 int num_eq, i, status = 0;
3037 int irq;
3038 unsigned long flags = 0;
3039
3040 num_eq = dev->nic_info.msix.num_vectors -
3041 dev->nic_info.msix.start_vector;
3042 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
3043 num_eq = 1;
3044 flags = IRQF_SHARED;
3045 } else {
3046 num_eq = min_t(u32, num_eq, num_online_cpus());
3047 }
3048
3049 if (!num_eq)
3050 return -EINVAL;
3051
3052 dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
3053 if (!dev->eq_tbl)
3054 return -ENOMEM;
3055
3056 for (i = 0; i < num_eq; i++) {
3057 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
3058 OCRDMA_EQ_LEN);
3059 if (status) {
3060 status = -EINVAL;
3061 break;
3062 }
3063 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
3064 dev->id, i);
3065 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
3066 status = request_irq(irq, ocrdma_irq_handler, flags,
3067 dev->eq_tbl[i].irq_name,
3068 &dev->eq_tbl[i]);
3069 if (status)
3070 goto done;
3071 dev->eq_cnt += 1;
3072 }
3073 /* one eq is sufficient for data path to work */
3074 return 0;
3075 done:
3076 ocrdma_destroy_eqs(dev);
3077 return status;
3078 }
3079
3080 static int ocrdma_mbx_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq,
3081 int num)
3082 {
3083 int i, status = -ENOMEM;
3084 struct ocrdma_modify_eqd_req *cmd;
3085
3086 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_EQ_DELAY, sizeof(*cmd));
3087 if (!cmd)
3088 return status;
3089
3090 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_MODIFY_EQ_DELAY,
3091 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
3092
3093 cmd->cmd.num_eq = num;
3094 for (i = 0; i < num; i++) {
3095 cmd->cmd.set_eqd[i].eq_id = eq[i].q.id;
3096 cmd->cmd.set_eqd[i].phase = 0;
3097 cmd->cmd.set_eqd[i].delay_multiplier =
3098 (eq[i].aic_obj.prev_eqd * 65)/100;
3099 }
3100 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
3101 if (status)
3102 goto mbx_err;
3103 mbx_err:
3104 kfree(cmd);
3105 return status;
3106 }
3107
3108 static int ocrdma_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq,
3109 int num)
3110 {
3111 int num_eqs, i = 0;
3112 if (num > 8) {
3113 while (num) {
3114 num_eqs = min(num, 8);
3115 ocrdma_mbx_modify_eqd(dev, &eq[i], num_eqs);
3116 i += num_eqs;
3117 num -= num_eqs;
3118 }
3119 } else {
3120 ocrdma_mbx_modify_eqd(dev, eq, num);
3121 }
3122 return 0;
3123 }
3124
3125 void ocrdma_eqd_set_task(struct work_struct *work)
3126 {
3127 struct ocrdma_dev *dev =
3128 container_of(work, struct ocrdma_dev, eqd_work.work);
3129 struct ocrdma_eq *eq = 0;
3130 int i, num = 0, status = -EINVAL;
3131 u64 eq_intr;
3132
3133 for (i = 0; i < dev->eq_cnt; i++) {
3134 eq = &dev->eq_tbl[i];
3135 if (eq->aic_obj.eq_intr_cnt > eq->aic_obj.prev_eq_intr_cnt) {
3136 eq_intr = eq->aic_obj.eq_intr_cnt -
3137 eq->aic_obj.prev_eq_intr_cnt;
3138 if ((eq_intr > EQ_INTR_PER_SEC_THRSH_HI) &&
3139 (eq->aic_obj.prev_eqd == EQ_AIC_MIN_EQD)) {
3140 eq->aic_obj.prev_eqd = EQ_AIC_MAX_EQD;
3141 num++;
3142 } else if ((eq_intr < EQ_INTR_PER_SEC_THRSH_LOW) &&
3143 (eq->aic_obj.prev_eqd == EQ_AIC_MAX_EQD)) {
3144 eq->aic_obj.prev_eqd = EQ_AIC_MIN_EQD;
3145 num++;
3146 }
3147 }
3148 eq->aic_obj.prev_eq_intr_cnt = eq->aic_obj.eq_intr_cnt;
3149 }
3150
3151 if (num)
3152 status = ocrdma_modify_eqd(dev, &dev->eq_tbl[0], num);
3153 schedule_delayed_work(&dev->eqd_work, msecs_to_jiffies(1000));
3154 }
3155
3156 int ocrdma_init_hw(struct ocrdma_dev *dev)
3157 {
3158 int status;
3159
3160 /* create the eqs */
3161 status = ocrdma_create_eqs(dev);
3162 if (status)
3163 goto qpeq_err;
3164 status = ocrdma_create_mq(dev);
3165 if (status)
3166 goto mq_err;
3167 status = ocrdma_mbx_query_fw_config(dev);
3168 if (status)
3169 goto conf_err;
3170 status = ocrdma_mbx_query_dev(dev);
3171 if (status)
3172 goto conf_err;
3173 status = ocrdma_mbx_query_fw_ver(dev);
3174 if (status)
3175 goto conf_err;
3176 status = ocrdma_mbx_create_ah_tbl(dev);
3177 if (status)
3178 goto conf_err;
3179 status = ocrdma_mbx_get_phy_info(dev);
3180 if (status)
3181 goto info_attrb_err;
3182 status = ocrdma_mbx_get_ctrl_attribs(dev);
3183 if (status)
3184 goto info_attrb_err;
3185
3186 return 0;
3187
3188 info_attrb_err:
3189 ocrdma_mbx_delete_ah_tbl(dev);
3190 conf_err:
3191 ocrdma_destroy_mq(dev);
3192 mq_err:
3193 ocrdma_destroy_eqs(dev);
3194 qpeq_err:
3195 pr_err("%s() status=%d\n", __func__, status);
3196 return status;
3197 }
3198
3199 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
3200 {
3201 ocrdma_free_pd_pool(dev);
3202 ocrdma_mbx_delete_ah_tbl(dev);
3203
3204 /* cleanup the control path */
3205 ocrdma_destroy_mq(dev);
3206
3207 /* cleanup the eqs */
3208 ocrdma_destroy_eqs(dev);
3209 }
Linux kernel - Deliverables
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