1 /* This file is part of the Emulex RoCE Device Driver for
2 * RoCE (RDMA over Converged Ethernet) adapters.
3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
4 * EMULEX and SLI are trademarks of Emulex.
7 * This software is available to you under a choice of one of two licenses.
8 * You may choose to be licensed under the terms of the GNU General Public
9 * License (GPL) Version 2, available from the file COPYING in the main
10 * directory of this source tree, or the BSD license below:
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
16 * - Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
19 * - Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the distribution.
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 * Contact Information:
36 * linux-drivers@emulex.com
40 * Costa Mesa, CA 92626
43 #include <linux/sched.h>
44 #include <linux/interrupt.h>
45 #include <linux/log2.h>
46 #include <linux/dma-mapping.h>
48 #include <rdma/ib_verbs.h>
49 #include <rdma/ib_user_verbs.h>
52 #include "ocrdma_hw.h"
53 #include "ocrdma_verbs.h"
54 #include "ocrdma_ah.h"
57 OCRDMA_MBX_STATUS_FAILED
= 1,
58 OCRDMA_MBX_STATUS_ILLEGAL_FIELD
= 3,
59 OCRDMA_MBX_STATUS_OOR
= 100,
60 OCRDMA_MBX_STATUS_INVALID_PD
= 101,
61 OCRDMA_MBX_STATUS_PD_INUSE
= 102,
62 OCRDMA_MBX_STATUS_INVALID_CQ
= 103,
63 OCRDMA_MBX_STATUS_INVALID_QP
= 104,
64 OCRDMA_MBX_STATUS_INVALID_LKEY
= 105,
65 OCRDMA_MBX_STATUS_ORD_EXCEEDS
= 106,
66 OCRDMA_MBX_STATUS_IRD_EXCEEDS
= 107,
67 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS
= 108,
68 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS
= 109,
69 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS
= 110,
70 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS
= 111,
71 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS
= 112,
72 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE
= 113,
73 OCRDMA_MBX_STATUS_MW_BOUND
= 114,
74 OCRDMA_MBX_STATUS_INVALID_VA
= 115,
75 OCRDMA_MBX_STATUS_INVALID_LENGTH
= 116,
76 OCRDMA_MBX_STATUS_INVALID_FBO
= 117,
77 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS
= 118,
78 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE
= 119,
79 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY
= 120,
80 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT
= 121,
81 OCRDMA_MBX_STATUS_INVALID_SRQ_ID
= 129,
82 OCRDMA_MBX_STATUS_SRQ_ERROR
= 133,
83 OCRDMA_MBX_STATUS_RQE_EXCEEDS
= 134,
84 OCRDMA_MBX_STATUS_MTU_EXCEEDS
= 135,
85 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS
= 136,
86 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS
= 137,
87 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS
= 138,
88 OCRDMA_MBX_STATUS_QP_BOUND
= 130,
89 OCRDMA_MBX_STATUS_INVALID_CHANGE
= 139,
90 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP
= 140,
91 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER
= 141,
92 OCRDMA_MBX_STATUS_MW_STILL_BOUND
= 142,
93 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID
= 143,
94 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS
= 144
97 enum additional_status
{
98 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES
= 22
102 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES
= 1,
103 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER
= 2,
104 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES
= 3,
105 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING
= 4,
106 OCRDMA_MBX_CQE_STATUS_DMA_FAILED
= 5
109 static inline void *ocrdma_get_eqe(struct ocrdma_eq
*eq
)
111 return eq
->q
.va
+ (eq
->q
.tail
* sizeof(struct ocrdma_eqe
));
114 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq
*eq
)
116 eq
->q
.tail
= (eq
->q
.tail
+ 1) & (OCRDMA_EQ_LEN
- 1);
119 static inline void *ocrdma_get_mcqe(struct ocrdma_dev
*dev
)
121 struct ocrdma_mcqe
*cqe
= (struct ocrdma_mcqe
*)
122 (dev
->mq
.cq
.va
+ (dev
->mq
.cq
.tail
* sizeof(struct ocrdma_mcqe
)));
124 if (!(le32_to_cpu(cqe
->valid_ae_cmpl_cons
) & OCRDMA_MCQE_VALID_MASK
))
129 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev
*dev
)
131 dev
->mq
.cq
.tail
= (dev
->mq
.cq
.tail
+ 1) & (OCRDMA_MQ_CQ_LEN
- 1);
134 static inline struct ocrdma_mqe
*ocrdma_get_mqe(struct ocrdma_dev
*dev
)
136 return dev
->mq
.sq
.va
+ (dev
->mq
.sq
.head
* sizeof(struct ocrdma_mqe
));
139 static inline void ocrdma_mq_inc_head(struct ocrdma_dev
*dev
)
141 dev
->mq
.sq
.head
= (dev
->mq
.sq
.head
+ 1) & (OCRDMA_MQ_LEN
- 1);
144 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev
*dev
)
146 return dev
->mq
.sq
.va
+ (dev
->mqe_ctx
.tag
* sizeof(struct ocrdma_mqe
));
149 enum ib_qp_state
get_ibqp_state(enum ocrdma_qp_state qps
)
154 case OCRDMA_QPS_INIT
:
161 case OCRDMA_QPS_SQ_DRAINING
:
171 static enum ocrdma_qp_state
get_ocrdma_qp_state(enum ib_qp_state qps
)
175 return OCRDMA_QPS_RST
;
177 return OCRDMA_QPS_INIT
;
179 return OCRDMA_QPS_RTR
;
181 return OCRDMA_QPS_RTS
;
183 return OCRDMA_QPS_SQD
;
185 return OCRDMA_QPS_SQE
;
187 return OCRDMA_QPS_ERR
;
189 return OCRDMA_QPS_ERR
;
192 static int ocrdma_get_mbx_errno(u32 status
)
195 u8 mbox_status
= (status
& OCRDMA_MBX_RSP_STATUS_MASK
) >>
196 OCRDMA_MBX_RSP_STATUS_SHIFT
;
197 u8 add_status
= (status
& OCRDMA_MBX_RSP_ASTATUS_MASK
) >>
198 OCRDMA_MBX_RSP_ASTATUS_SHIFT
;
200 switch (mbox_status
) {
201 case OCRDMA_MBX_STATUS_OOR
:
202 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS
:
206 case OCRDMA_MBX_STATUS_INVALID_PD
:
207 case OCRDMA_MBX_STATUS_INVALID_CQ
:
208 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID
:
209 case OCRDMA_MBX_STATUS_INVALID_QP
:
210 case OCRDMA_MBX_STATUS_INVALID_CHANGE
:
211 case OCRDMA_MBX_STATUS_MTU_EXCEEDS
:
212 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER
:
213 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID
:
214 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS
:
215 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD
:
216 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY
:
217 case OCRDMA_MBX_STATUS_INVALID_LKEY
:
218 case OCRDMA_MBX_STATUS_INVALID_VA
:
219 case OCRDMA_MBX_STATUS_INVALID_LENGTH
:
220 case OCRDMA_MBX_STATUS_INVALID_FBO
:
221 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS
:
222 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE
:
223 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP
:
224 case OCRDMA_MBX_STATUS_SRQ_ERROR
:
225 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS
:
229 case OCRDMA_MBX_STATUS_PD_INUSE
:
230 case OCRDMA_MBX_STATUS_QP_BOUND
:
231 case OCRDMA_MBX_STATUS_MW_STILL_BOUND
:
232 case OCRDMA_MBX_STATUS_MW_BOUND
:
236 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS
:
237 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS
:
238 case OCRDMA_MBX_STATUS_RQE_EXCEEDS
:
239 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS
:
240 case OCRDMA_MBX_STATUS_ORD_EXCEEDS
:
241 case OCRDMA_MBX_STATUS_IRD_EXCEEDS
:
242 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS
:
243 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS
:
244 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS
:
248 case OCRDMA_MBX_STATUS_FAILED
:
249 switch (add_status
) {
250 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES
:
260 char *port_speed_string(struct ocrdma_dev
*dev
)
263 u16 speeds_supported
;
265 speeds_supported
= dev
->phy
.fixed_speeds_supported
|
266 dev
->phy
.auto_speeds_supported
;
267 if (speeds_supported
& OCRDMA_PHY_SPEED_40GBPS
)
269 else if (speeds_supported
& OCRDMA_PHY_SPEED_10GBPS
)
271 else if (speeds_supported
& OCRDMA_PHY_SPEED_1GBPS
)
277 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status
)
279 int err_num
= -EINVAL
;
281 switch (cqe_status
) {
282 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES
:
285 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER
:
288 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES
:
289 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING
:
292 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED
:
300 void ocrdma_ring_cq_db(struct ocrdma_dev
*dev
, u16 cq_id
, bool armed
,
301 bool solicited
, u16 cqe_popped
)
303 u32 val
= cq_id
& OCRDMA_DB_CQ_RING_ID_MASK
;
305 val
|= ((cq_id
& OCRDMA_DB_CQ_RING_ID_EXT_MASK
) <<
306 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT
);
309 val
|= (1 << OCRDMA_DB_CQ_REARM_SHIFT
);
311 val
|= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT
);
312 val
|= (cqe_popped
<< OCRDMA_DB_CQ_NUM_POPPED_SHIFT
);
313 iowrite32(val
, dev
->nic_info
.db
+ OCRDMA_DB_CQ_OFFSET
);
316 static void ocrdma_ring_mq_db(struct ocrdma_dev
*dev
)
320 val
|= dev
->mq
.sq
.id
& OCRDMA_MQ_ID_MASK
;
321 val
|= 1 << OCRDMA_MQ_NUM_MQE_SHIFT
;
322 iowrite32(val
, dev
->nic_info
.db
+ OCRDMA_DB_MQ_OFFSET
);
325 static void ocrdma_ring_eq_db(struct ocrdma_dev
*dev
, u16 eq_id
,
326 bool arm
, bool clear_int
, u16 num_eqe
)
330 val
|= eq_id
& OCRDMA_EQ_ID_MASK
;
331 val
|= ((eq_id
& OCRDMA_EQ_ID_EXT_MASK
) << OCRDMA_EQ_ID_EXT_MASK_SHIFT
);
333 val
|= (1 << OCRDMA_REARM_SHIFT
);
335 val
|= (1 << OCRDMA_EQ_CLR_SHIFT
);
336 val
|= (1 << OCRDMA_EQ_TYPE_SHIFT
);
337 val
|= (num_eqe
<< OCRDMA_NUM_EQE_SHIFT
);
338 iowrite32(val
, dev
->nic_info
.db
+ OCRDMA_DB_EQ_OFFSET
);
341 static void ocrdma_init_mch(struct ocrdma_mbx_hdr
*cmd_hdr
,
342 u8 opcode
, u8 subsys
, u32 cmd_len
)
344 cmd_hdr
->subsys_op
= (opcode
| (subsys
<< OCRDMA_MCH_SUBSYS_SHIFT
));
345 cmd_hdr
->timeout
= 20; /* seconds */
346 cmd_hdr
->cmd_len
= cmd_len
- sizeof(struct ocrdma_mbx_hdr
);
349 static void *ocrdma_init_emb_mqe(u8 opcode
, u32 cmd_len
)
351 struct ocrdma_mqe
*mqe
;
353 mqe
= kzalloc(sizeof(struct ocrdma_mqe
), GFP_KERNEL
);
356 mqe
->hdr
.spcl_sge_cnt_emb
|=
357 (OCRDMA_MQE_EMBEDDED
<< OCRDMA_MQE_HDR_EMB_SHIFT
) &
358 OCRDMA_MQE_HDR_EMB_MASK
;
359 mqe
->hdr
.pyld_len
= cmd_len
- sizeof(struct ocrdma_mqe_hdr
);
361 ocrdma_init_mch(&mqe
->u
.emb_req
.mch
, opcode
, OCRDMA_SUBSYS_ROCE
,
366 static void ocrdma_free_q(struct ocrdma_dev
*dev
, struct ocrdma_queue_info
*q
)
368 dma_free_coherent(&dev
->nic_info
.pdev
->dev
, q
->size
, q
->va
, q
->dma
);
371 static int ocrdma_alloc_q(struct ocrdma_dev
*dev
,
372 struct ocrdma_queue_info
*q
, u16 len
, u16 entry_size
)
374 memset(q
, 0, sizeof(*q
));
376 q
->entry_size
= entry_size
;
377 q
->size
= len
* entry_size
;
378 q
->va
= dma_alloc_coherent(&dev
->nic_info
.pdev
->dev
, q
->size
,
379 &q
->dma
, GFP_KERNEL
);
382 memset(q
->va
, 0, q
->size
);
386 static void ocrdma_build_q_pages(struct ocrdma_pa
*q_pa
, int cnt
,
387 dma_addr_t host_pa
, int hw_page_size
)
391 for (i
= 0; i
< cnt
; i
++) {
392 q_pa
[i
].lo
= (u32
) (host_pa
& 0xffffffff);
393 q_pa
[i
].hi
= (u32
) upper_32_bits(host_pa
);
394 host_pa
+= hw_page_size
;
398 static int ocrdma_mbx_delete_q(struct ocrdma_dev
*dev
,
399 struct ocrdma_queue_info
*q
, int queue_type
)
403 struct ocrdma_delete_q_req
*cmd
= dev
->mbx_cmd
;
405 switch (queue_type
) {
407 opcode
= OCRDMA_CMD_DELETE_MQ
;
410 opcode
= OCRDMA_CMD_DELETE_CQ
;
413 opcode
= OCRDMA_CMD_DELETE_EQ
;
418 memset(cmd
, 0, sizeof(*cmd
));
419 ocrdma_init_mch(&cmd
->req
, opcode
, OCRDMA_SUBSYS_COMMON
, sizeof(*cmd
));
422 status
= be_roce_mcc_cmd(dev
->nic_info
.netdev
,
423 cmd
, sizeof(*cmd
), NULL
, NULL
);
429 static int ocrdma_mbx_create_eq(struct ocrdma_dev
*dev
, struct ocrdma_eq
*eq
)
432 struct ocrdma_create_eq_req
*cmd
= dev
->mbx_cmd
;
433 struct ocrdma_create_eq_rsp
*rsp
= dev
->mbx_cmd
;
435 memset(cmd
, 0, sizeof(*cmd
));
436 ocrdma_init_mch(&cmd
->req
, OCRDMA_CMD_CREATE_EQ
, OCRDMA_SUBSYS_COMMON
,
439 cmd
->req
.rsvd_version
= 2;
441 cmd
->valid
= OCRDMA_CREATE_EQ_VALID
;
442 cmd
->cnt
= 4 << OCRDMA_CREATE_EQ_CNT_SHIFT
;
444 ocrdma_build_q_pages(&cmd
->pa
[0], cmd
->num_pages
, eq
->q
.dma
,
446 status
= be_roce_mcc_cmd(dev
->nic_info
.netdev
, cmd
, sizeof(*cmd
), NULL
,
449 eq
->q
.id
= rsp
->vector_eqid
& 0xffff;
450 eq
->vector
= (rsp
->vector_eqid
>> 16) & 0xffff;
451 eq
->q
.created
= true;
456 static int ocrdma_create_eq(struct ocrdma_dev
*dev
,
457 struct ocrdma_eq
*eq
, u16 q_len
)
461 status
= ocrdma_alloc_q(dev
, &eq
->q
, OCRDMA_EQ_LEN
,
462 sizeof(struct ocrdma_eqe
));
466 status
= ocrdma_mbx_create_eq(dev
, eq
);
470 ocrdma_ring_eq_db(dev
, eq
->q
.id
, true, true, 0);
474 ocrdma_free_q(dev
, &eq
->q
);
478 int ocrdma_get_irq(struct ocrdma_dev
*dev
, struct ocrdma_eq
*eq
)
482 if (dev
->nic_info
.intr_mode
== BE_INTERRUPT_MODE_INTX
)
483 irq
= dev
->nic_info
.pdev
->irq
;
485 irq
= dev
->nic_info
.msix
.vector_list
[eq
->vector
];
489 static void _ocrdma_destroy_eq(struct ocrdma_dev
*dev
, struct ocrdma_eq
*eq
)
492 ocrdma_mbx_delete_q(dev
, &eq
->q
, QTYPE_EQ
);
493 ocrdma_free_q(dev
, &eq
->q
);
497 static void ocrdma_destroy_eq(struct ocrdma_dev
*dev
, struct ocrdma_eq
*eq
)
501 /* disarm EQ so that interrupts are not generated
502 * during freeing and EQ delete is in progress.
504 ocrdma_ring_eq_db(dev
, eq
->q
.id
, false, false, 0);
506 irq
= ocrdma_get_irq(dev
, eq
);
508 _ocrdma_destroy_eq(dev
, eq
);
511 static void ocrdma_destroy_eqs(struct ocrdma_dev
*dev
)
515 for (i
= 0; i
< dev
->eq_cnt
; i
++)
516 ocrdma_destroy_eq(dev
, &dev
->eq_tbl
[i
]);
519 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev
*dev
,
520 struct ocrdma_queue_info
*cq
,
521 struct ocrdma_queue_info
*eq
)
523 struct ocrdma_create_cq_cmd
*cmd
= dev
->mbx_cmd
;
524 struct ocrdma_create_cq_cmd_rsp
*rsp
= dev
->mbx_cmd
;
527 memset(cmd
, 0, sizeof(*cmd
));
528 ocrdma_init_mch(&cmd
->req
, OCRDMA_CMD_CREATE_CQ
,
529 OCRDMA_SUBSYS_COMMON
, sizeof(*cmd
));
531 cmd
->req
.rsvd_version
= OCRDMA_CREATE_CQ_VER2
;
532 cmd
->pgsz_pgcnt
= (cq
->size
/ OCRDMA_MIN_Q_PAGE_SIZE
) <<
533 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT
;
534 cmd
->pgsz_pgcnt
|= PAGES_4K_SPANNED(cq
->va
, cq
->size
);
536 cmd
->ev_cnt_flags
= OCRDMA_CREATE_CQ_DEF_FLAGS
;
538 cmd
->pdid_cqecnt
= cq
->size
/ sizeof(struct ocrdma_mcqe
);
540 ocrdma_build_q_pages(&cmd
->pa
[0], cq
->size
/ OCRDMA_MIN_Q_PAGE_SIZE
,
541 cq
->dma
, PAGE_SIZE_4K
);
542 status
= be_roce_mcc_cmd(dev
->nic_info
.netdev
,
543 cmd
, sizeof(*cmd
), NULL
, NULL
);
545 cq
->id
= (u16
) (rsp
->cq_id
& OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK
);
551 static u32
ocrdma_encoded_q_len(int q_len
)
553 u32 len_encoded
= fls(q_len
); /* log2(len) + 1 */
555 if (len_encoded
== 16)
560 static int ocrdma_mbx_create_mq(struct ocrdma_dev
*dev
,
561 struct ocrdma_queue_info
*mq
,
562 struct ocrdma_queue_info
*cq
)
564 int num_pages
, status
;
565 struct ocrdma_create_mq_req
*cmd
= dev
->mbx_cmd
;
566 struct ocrdma_create_mq_rsp
*rsp
= dev
->mbx_cmd
;
567 struct ocrdma_pa
*pa
;
569 memset(cmd
, 0, sizeof(*cmd
));
570 num_pages
= PAGES_4K_SPANNED(mq
->va
, mq
->size
);
572 ocrdma_init_mch(&cmd
->req
, OCRDMA_CMD_CREATE_MQ_EXT
,
573 OCRDMA_SUBSYS_COMMON
, sizeof(*cmd
));
574 cmd
->req
.rsvd_version
= 1;
575 cmd
->cqid_pages
= num_pages
;
576 cmd
->cqid_pages
|= (cq
->id
<< OCRDMA_CREATE_MQ_CQ_ID_SHIFT
);
577 cmd
->async_cqid_valid
= OCRDMA_CREATE_MQ_ASYNC_CQ_VALID
;
579 cmd
->async_event_bitmap
= BIT(OCRDMA_ASYNC_GRP5_EVE_CODE
);
580 cmd
->async_event_bitmap
|= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE
);
582 cmd
->async_cqid_ringsize
= cq
->id
;
583 cmd
->async_cqid_ringsize
|= (ocrdma_encoded_q_len(mq
->len
) <<
584 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT
);
585 cmd
->valid
= OCRDMA_CREATE_MQ_VALID
;
588 ocrdma_build_q_pages(pa
, num_pages
, mq
->dma
, PAGE_SIZE_4K
);
589 status
= be_roce_mcc_cmd(dev
->nic_info
.netdev
,
590 cmd
, sizeof(*cmd
), NULL
, NULL
);
598 static int ocrdma_create_mq(struct ocrdma_dev
*dev
)
602 /* Alloc completion queue for Mailbox queue */
603 status
= ocrdma_alloc_q(dev
, &dev
->mq
.cq
, OCRDMA_MQ_CQ_LEN
,
604 sizeof(struct ocrdma_mcqe
));
608 dev
->eq_tbl
[0].cq_cnt
++;
609 status
= ocrdma_mbx_mq_cq_create(dev
, &dev
->mq
.cq
, &dev
->eq_tbl
[0].q
);
613 memset(&dev
->mqe_ctx
, 0, sizeof(dev
->mqe_ctx
));
614 init_waitqueue_head(&dev
->mqe_ctx
.cmd_wait
);
615 mutex_init(&dev
->mqe_ctx
.lock
);
617 /* Alloc Mailbox queue */
618 status
= ocrdma_alloc_q(dev
, &dev
->mq
.sq
, OCRDMA_MQ_LEN
,
619 sizeof(struct ocrdma_mqe
));
622 status
= ocrdma_mbx_create_mq(dev
, &dev
->mq
.sq
, &dev
->mq
.cq
);
625 ocrdma_ring_cq_db(dev
, dev
->mq
.cq
.id
, true, false, 0);
629 ocrdma_free_q(dev
, &dev
->mq
.sq
);
631 ocrdma_mbx_delete_q(dev
, &dev
->mq
.cq
, QTYPE_CQ
);
633 ocrdma_free_q(dev
, &dev
->mq
.cq
);
638 static void ocrdma_destroy_mq(struct ocrdma_dev
*dev
)
640 struct ocrdma_queue_info
*mbxq
, *cq
;
642 /* mqe_ctx lock synchronizes with any other pending cmds. */
643 mutex_lock(&dev
->mqe_ctx
.lock
);
646 ocrdma_mbx_delete_q(dev
, mbxq
, QTYPE_MCCQ
);
647 ocrdma_free_q(dev
, mbxq
);
649 mutex_unlock(&dev
->mqe_ctx
.lock
);
653 ocrdma_mbx_delete_q(dev
, cq
, QTYPE_CQ
);
654 ocrdma_free_q(dev
, cq
);
658 static void ocrdma_process_qpcat_error(struct ocrdma_dev
*dev
,
659 struct ocrdma_qp
*qp
)
661 enum ib_qp_state new_ib_qps
= IB_QPS_ERR
;
662 enum ib_qp_state old_ib_qps
;
666 ocrdma_qp_state_change(qp
, new_ib_qps
, &old_ib_qps
);
669 static void ocrdma_dispatch_ibevent(struct ocrdma_dev
*dev
,
670 struct ocrdma_ae_mcqe
*cqe
)
672 struct ocrdma_qp
*qp
= NULL
;
673 struct ocrdma_cq
*cq
= NULL
;
674 struct ib_event ib_evt
;
679 int type
= (cqe
->valid_ae_event
& OCRDMA_AE_MCQE_EVENT_TYPE_MASK
) >>
680 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT
;
682 if (cqe
->qpvalid_qpid
& OCRDMA_AE_MCQE_QPVALID
)
683 qp
= dev
->qp_tbl
[cqe
->qpvalid_qpid
& OCRDMA_AE_MCQE_QPID_MASK
];
684 if (cqe
->cqvalid_cqid
& OCRDMA_AE_MCQE_CQVALID
)
685 cq
= dev
->cq_tbl
[cqe
->cqvalid_cqid
& OCRDMA_AE_MCQE_CQID_MASK
];
687 memset(&ib_evt
, 0, sizeof(ib_evt
));
689 ib_evt
.device
= &dev
->ibdev
;
692 case OCRDMA_CQ_ERROR
:
693 ib_evt
.element
.cq
= &cq
->ibcq
;
694 ib_evt
.event
= IB_EVENT_CQ_ERR
;
698 case OCRDMA_CQ_OVERRUN_ERROR
:
699 ib_evt
.element
.cq
= &cq
->ibcq
;
700 ib_evt
.event
= IB_EVENT_CQ_ERR
;
704 case OCRDMA_CQ_QPCAT_ERROR
:
705 ib_evt
.element
.qp
= &qp
->ibqp
;
706 ib_evt
.event
= IB_EVENT_QP_FATAL
;
707 ocrdma_process_qpcat_error(dev
, qp
);
709 case OCRDMA_QP_ACCESS_ERROR
:
710 ib_evt
.element
.qp
= &qp
->ibqp
;
711 ib_evt
.event
= IB_EVENT_QP_ACCESS_ERR
;
713 case OCRDMA_QP_COMM_EST_EVENT
:
714 ib_evt
.element
.qp
= &qp
->ibqp
;
715 ib_evt
.event
= IB_EVENT_COMM_EST
;
717 case OCRDMA_SQ_DRAINED_EVENT
:
718 ib_evt
.element
.qp
= &qp
->ibqp
;
719 ib_evt
.event
= IB_EVENT_SQ_DRAINED
;
721 case OCRDMA_DEVICE_FATAL_EVENT
:
722 ib_evt
.element
.port_num
= 1;
723 ib_evt
.event
= IB_EVENT_DEVICE_FATAL
;
727 case OCRDMA_SRQCAT_ERROR
:
728 ib_evt
.element
.srq
= &qp
->srq
->ibsrq
;
729 ib_evt
.event
= IB_EVENT_SRQ_ERR
;
733 case OCRDMA_SRQ_LIMIT_EVENT
:
734 ib_evt
.element
.srq
= &qp
->srq
->ibsrq
;
735 ib_evt
.event
= IB_EVENT_SRQ_LIMIT_REACHED
;
739 case OCRDMA_QP_LAST_WQE_EVENT
:
740 ib_evt
.element
.qp
= &qp
->ibqp
;
741 ib_evt
.event
= IB_EVENT_QP_LAST_WQE_REACHED
;
748 pr_err("%s() unknown type=0x%x\n", __func__
, type
);
752 if (type
< OCRDMA_MAX_ASYNC_ERRORS
)
753 atomic_inc(&dev
->async_err_stats
[type
]);
756 if (qp
->ibqp
.event_handler
)
757 qp
->ibqp
.event_handler(&ib_evt
, qp
->ibqp
.qp_context
);
758 } else if (cq_event
) {
759 if (cq
->ibcq
.event_handler
)
760 cq
->ibcq
.event_handler(&ib_evt
, cq
->ibcq
.cq_context
);
761 } else if (srq_event
) {
762 if (qp
->srq
->ibsrq
.event_handler
)
763 qp
->srq
->ibsrq
.event_handler(&ib_evt
,
766 } else if (dev_event
) {
767 pr_err("%s: Fatal event received\n", dev
->ibdev
.name
);
768 ib_dispatch_event(&ib_evt
);
773 static void ocrdma_process_grp5_aync(struct ocrdma_dev
*dev
,
774 struct ocrdma_ae_mcqe
*cqe
)
776 struct ocrdma_ae_pvid_mcqe
*evt
;
777 int type
= (cqe
->valid_ae_event
& OCRDMA_AE_MCQE_EVENT_TYPE_MASK
) >>
778 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT
;
781 case OCRDMA_ASYNC_EVENT_PVID_STATE
:
782 evt
= (struct ocrdma_ae_pvid_mcqe
*)cqe
;
783 if ((evt
->tag_enabled
& OCRDMA_AE_PVID_MCQE_ENABLED_MASK
) >>
784 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT
)
785 dev
->pvid
= ((evt
->tag_enabled
&
786 OCRDMA_AE_PVID_MCQE_TAG_MASK
) >>
787 OCRDMA_AE_PVID_MCQE_TAG_SHIFT
);
790 case OCRDMA_ASYNC_EVENT_COS_VALUE
:
791 atomic_set(&dev
->update_sl
, 1);
794 /* Not interested evts. */
799 static void ocrdma_process_acqe(struct ocrdma_dev
*dev
, void *ae_cqe
)
801 /* async CQE processing */
802 struct ocrdma_ae_mcqe
*cqe
= ae_cqe
;
803 u32 evt_code
= (cqe
->valid_ae_event
& OCRDMA_AE_MCQE_EVENT_CODE_MASK
) >>
804 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
;
806 if (evt_code
== OCRDMA_ASYNC_RDMA_EVE_CODE
)
807 ocrdma_dispatch_ibevent(dev
, cqe
);
808 else if (evt_code
== OCRDMA_ASYNC_GRP5_EVE_CODE
)
809 ocrdma_process_grp5_aync(dev
, cqe
);
811 pr_err("%s(%d) invalid evt code=0x%x\n", __func__
,
815 static void ocrdma_process_mcqe(struct ocrdma_dev
*dev
, struct ocrdma_mcqe
*cqe
)
817 if (dev
->mqe_ctx
.tag
== cqe
->tag_lo
&& dev
->mqe_ctx
.cmd_done
== false) {
818 dev
->mqe_ctx
.cqe_status
= (cqe
->status
&
819 OCRDMA_MCQE_STATUS_MASK
) >> OCRDMA_MCQE_STATUS_SHIFT
;
820 dev
->mqe_ctx
.ext_status
=
821 (cqe
->status
& OCRDMA_MCQE_ESTATUS_MASK
)
822 >> OCRDMA_MCQE_ESTATUS_SHIFT
;
823 dev
->mqe_ctx
.cmd_done
= true;
824 wake_up(&dev
->mqe_ctx
.cmd_wait
);
826 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
827 __func__
, cqe
->tag_lo
, dev
->mqe_ctx
.tag
);
830 static int ocrdma_mq_cq_handler(struct ocrdma_dev
*dev
, u16 cq_id
)
833 struct ocrdma_mcqe
*cqe
;
836 cqe
= ocrdma_get_mcqe(dev
);
839 ocrdma_le32_to_cpu(cqe
, sizeof(*cqe
));
841 if (cqe
->valid_ae_cmpl_cons
& OCRDMA_MCQE_AE_MASK
)
842 ocrdma_process_acqe(dev
, cqe
);
843 else if (cqe
->valid_ae_cmpl_cons
& OCRDMA_MCQE_CMPL_MASK
)
844 ocrdma_process_mcqe(dev
, cqe
);
845 memset(cqe
, 0, sizeof(struct ocrdma_mcqe
));
846 ocrdma_mcq_inc_tail(dev
);
848 ocrdma_ring_cq_db(dev
, dev
->mq
.cq
.id
, true, false, cqe_popped
);
852 static struct ocrdma_cq
*_ocrdma_qp_buddy_cq_handler(struct ocrdma_dev
*dev
,
853 struct ocrdma_cq
*cq
, bool sq
)
855 struct ocrdma_qp
*qp
;
856 struct list_head
*cur
;
857 struct ocrdma_cq
*bcq
= NULL
;
858 struct list_head
*head
= sq
?(&cq
->sq_head
):(&cq
->rq_head
);
860 list_for_each(cur
, head
) {
862 qp
= list_entry(cur
, struct ocrdma_qp
, sq_entry
);
864 qp
= list_entry(cur
, struct ocrdma_qp
, rq_entry
);
868 /* if wq and rq share the same cq, than comp_handler
869 * is already invoked.
871 if (qp
->sq_cq
== qp
->rq_cq
)
873 /* if completion came on sq, rq's cq is buddy cq.
874 * if completion came on rq, sq's cq is buddy cq.
885 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev
*dev
,
886 struct ocrdma_cq
*cq
)
889 struct ocrdma_cq
*bcq
= NULL
;
891 /* Go through list of QPs in error state which are using this CQ
892 * and invoke its callback handler to trigger CQE processing for
893 * error/flushed CQE. It is rare to find more than few entries in
894 * this list as most consumers stops after getting error CQE.
895 * List is traversed only once when a matching buddy cq found for a QP.
897 spin_lock_irqsave(&dev
->flush_q_lock
, flags
);
898 /* Check if buddy CQ is present.
899 * true - Check for SQ CQ
900 * false - Check for RQ CQ
902 bcq
= _ocrdma_qp_buddy_cq_handler(dev
, cq
, true);
904 bcq
= _ocrdma_qp_buddy_cq_handler(dev
, cq
, false);
905 spin_unlock_irqrestore(&dev
->flush_q_lock
, flags
);
907 /* if there is valid buddy cq, look for its completion handler */
908 if (bcq
&& bcq
->ibcq
.comp_handler
) {
909 spin_lock_irqsave(&bcq
->comp_handler_lock
, flags
);
910 (*bcq
->ibcq
.comp_handler
) (&bcq
->ibcq
, bcq
->ibcq
.cq_context
);
911 spin_unlock_irqrestore(&bcq
->comp_handler_lock
, flags
);
915 static void ocrdma_qp_cq_handler(struct ocrdma_dev
*dev
, u16 cq_idx
)
918 struct ocrdma_cq
*cq
;
920 if (cq_idx
>= OCRDMA_MAX_CQ
)
923 cq
= dev
->cq_tbl
[cq_idx
];
927 if (cq
->ibcq
.comp_handler
) {
928 spin_lock_irqsave(&cq
->comp_handler_lock
, flags
);
929 (*cq
->ibcq
.comp_handler
) (&cq
->ibcq
, cq
->ibcq
.cq_context
);
930 spin_unlock_irqrestore(&cq
->comp_handler_lock
, flags
);
932 ocrdma_qp_buddy_cq_handler(dev
, cq
);
935 static void ocrdma_cq_handler(struct ocrdma_dev
*dev
, u16 cq_id
)
937 /* process the MQ-CQE. */
938 if (cq_id
== dev
->mq
.cq
.id
)
939 ocrdma_mq_cq_handler(dev
, cq_id
);
941 ocrdma_qp_cq_handler(dev
, cq_id
);
944 static irqreturn_t
ocrdma_irq_handler(int irq
, void *handle
)
946 struct ocrdma_eq
*eq
= handle
;
947 struct ocrdma_dev
*dev
= eq
->dev
;
948 struct ocrdma_eqe eqe
;
949 struct ocrdma_eqe
*ptr
;
952 int budget
= eq
->cq_cnt
;
955 ptr
= ocrdma_get_eqe(eq
);
957 ocrdma_le32_to_cpu(&eqe
, sizeof(eqe
));
958 mcode
= (eqe
.id_valid
& OCRDMA_EQE_MAJOR_CODE_MASK
)
959 >> OCRDMA_EQE_MAJOR_CODE_SHIFT
;
960 if (mcode
== OCRDMA_MAJOR_CODE_SENTINAL
)
961 pr_err("EQ full on eqid = 0x%x, eqe = 0x%x\n",
962 eq
->q
.id
, eqe
.id_valid
);
963 if ((eqe
.id_valid
& OCRDMA_EQE_VALID_MASK
) == 0)
967 /* ring eq doorbell as soon as its consumed. */
968 ocrdma_ring_eq_db(dev
, eq
->q
.id
, false, true, 1);
969 /* check whether its CQE or not. */
970 if ((eqe
.id_valid
& OCRDMA_EQE_FOR_CQE_MASK
) == 0) {
971 cq_id
= eqe
.id_valid
>> OCRDMA_EQE_RESOURCE_ID_SHIFT
;
972 ocrdma_cq_handler(dev
, cq_id
);
974 ocrdma_eq_inc_tail(eq
);
976 /* There can be a stale EQE after the last bound CQ is
977 * destroyed. EQE valid and budget == 0 implies this.
984 eq
->aic_obj
.eq_intr_cnt
++;
985 ocrdma_ring_eq_db(dev
, eq
->q
.id
, true, true, 0);
989 static void ocrdma_post_mqe(struct ocrdma_dev
*dev
, struct ocrdma_mqe
*cmd
)
991 struct ocrdma_mqe
*mqe
;
993 dev
->mqe_ctx
.tag
= dev
->mq
.sq
.head
;
994 dev
->mqe_ctx
.cmd_done
= false;
995 mqe
= ocrdma_get_mqe(dev
);
996 cmd
->hdr
.tag_lo
= dev
->mq
.sq
.head
;
997 ocrdma_copy_cpu_to_le32(mqe
, cmd
, sizeof(*mqe
));
998 /* make sure descriptor is written before ringing doorbell */
1000 ocrdma_mq_inc_head(dev
);
1001 ocrdma_ring_mq_db(dev
);
1004 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev
*dev
)
1007 /* 30 sec timeout */
1008 status
= wait_event_timeout(dev
->mqe_ctx
.cmd_wait
,
1009 (dev
->mqe_ctx
.cmd_done
!= false),
1010 msecs_to_jiffies(30000));
1014 dev
->mqe_ctx
.fw_error_state
= true;
1015 pr_err("%s(%d) mailbox timeout: fw not responding\n",
1021 /* issue a mailbox command on the MQ */
1022 static int ocrdma_mbx_cmd(struct ocrdma_dev
*dev
, struct ocrdma_mqe
*mqe
)
1025 u16 cqe_status
, ext_status
;
1026 struct ocrdma_mqe
*rsp_mqe
;
1027 struct ocrdma_mbx_rsp
*rsp
= NULL
;
1029 mutex_lock(&dev
->mqe_ctx
.lock
);
1030 if (dev
->mqe_ctx
.fw_error_state
)
1032 ocrdma_post_mqe(dev
, mqe
);
1033 status
= ocrdma_wait_mqe_cmpl(dev
);
1036 cqe_status
= dev
->mqe_ctx
.cqe_status
;
1037 ext_status
= dev
->mqe_ctx
.ext_status
;
1038 rsp_mqe
= ocrdma_get_mqe_rsp(dev
);
1039 ocrdma_copy_le32_to_cpu(mqe
, rsp_mqe
, (sizeof(*mqe
)));
1040 if ((mqe
->hdr
.spcl_sge_cnt_emb
& OCRDMA_MQE_HDR_EMB_MASK
) >>
1041 OCRDMA_MQE_HDR_EMB_SHIFT
)
1044 if (cqe_status
|| ext_status
) {
1045 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
1046 __func__
, cqe_status
, ext_status
);
1048 /* This is for embedded cmds. */
1049 pr_err("opcode=0x%x, subsystem=0x%x\n",
1050 (rsp
->subsys_op
& OCRDMA_MBX_RSP_OPCODE_MASK
) >>
1051 OCRDMA_MBX_RSP_OPCODE_SHIFT
,
1052 (rsp
->subsys_op
& OCRDMA_MBX_RSP_SUBSYS_MASK
) >>
1053 OCRDMA_MBX_RSP_SUBSYS_SHIFT
);
1055 status
= ocrdma_get_mbx_cqe_errno(cqe_status
);
1058 /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1059 if (rsp
&& (mqe
->u
.rsp
.status
& OCRDMA_MBX_RSP_STATUS_MASK
))
1060 status
= ocrdma_get_mbx_errno(mqe
->u
.rsp
.status
);
1062 mutex_unlock(&dev
->mqe_ctx
.lock
);
1066 static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev
*dev
, struct ocrdma_mqe
*mqe
,
1070 struct ocrdma_mbx_rsp
*rsp
= payload_va
;
1072 if ((mqe
->hdr
.spcl_sge_cnt_emb
& OCRDMA_MQE_HDR_EMB_MASK
) >>
1073 OCRDMA_MQE_HDR_EMB_SHIFT
)
1076 status
= ocrdma_mbx_cmd(dev
, mqe
);
1078 /* For non embedded, only CQE failures are handled in
1079 * ocrdma_mbx_cmd. We need to check for RSP errors.
1081 if (rsp
->status
& OCRDMA_MBX_RSP_STATUS_MASK
)
1082 status
= ocrdma_get_mbx_errno(rsp
->status
);
1085 pr_err("opcode=0x%x, subsystem=0x%x\n",
1086 (rsp
->subsys_op
& OCRDMA_MBX_RSP_OPCODE_MASK
) >>
1087 OCRDMA_MBX_RSP_OPCODE_SHIFT
,
1088 (rsp
->subsys_op
& OCRDMA_MBX_RSP_SUBSYS_MASK
) >>
1089 OCRDMA_MBX_RSP_SUBSYS_SHIFT
);
1093 static void ocrdma_get_attr(struct ocrdma_dev
*dev
,
1094 struct ocrdma_dev_attr
*attr
,
1095 struct ocrdma_mbx_query_config
*rsp
)
1098 (rsp
->max_pd_ca_ack_delay
& OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK
) >>
1099 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT
;
1101 (rsp
->max_dpp_pds_credits
& OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK
) >>
1102 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET
;
1104 (rsp
->qp_srq_cq_ird_ord
& OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK
) >>
1105 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT
;
1107 (rsp
->max_srq_rpir_qps
& OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK
) >>
1108 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET
;
1109 attr
->max_send_sge
= ((rsp
->max_write_send_sge
&
1110 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK
) >>
1111 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT
);
1112 attr
->max_recv_sge
= (rsp
->max_write_send_sge
&
1113 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK
) >>
1114 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT
;
1115 attr
->max_srq_sge
= (rsp
->max_srq_rqe_sge
&
1116 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK
) >>
1117 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET
;
1118 attr
->max_rdma_sge
= (rsp
->max_write_send_sge
&
1119 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK
) >>
1120 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT
;
1121 attr
->max_ord_per_qp
= (rsp
->max_ird_ord_per_qp
&
1122 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK
) >>
1123 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT
;
1124 attr
->max_ird_per_qp
= (rsp
->max_ird_ord_per_qp
&
1125 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK
) >>
1126 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT
;
1127 attr
->cq_overflow_detect
= (rsp
->qp_srq_cq_ird_ord
&
1128 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK
) >>
1129 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT
;
1130 attr
->srq_supported
= (rsp
->qp_srq_cq_ird_ord
&
1131 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK
) >>
1132 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT
;
1133 attr
->local_ca_ack_delay
= (rsp
->max_pd_ca_ack_delay
&
1134 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK
) >>
1135 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT
;
1136 attr
->max_mw
= rsp
->max_mw
;
1137 attr
->max_mr
= rsp
->max_mr
;
1138 attr
->max_mr_size
= ((u64
)rsp
->max_mr_size_hi
<< 32) |
1139 rsp
->max_mr_size_lo
;
1141 attr
->max_pages_per_frmr
= rsp
->max_pages_per_frmr
;
1142 attr
->max_num_mr_pbl
= rsp
->max_num_mr_pbl
;
1143 attr
->max_cqe
= rsp
->max_cq_cqes_per_cq
&
1144 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK
;
1145 attr
->max_cq
= (rsp
->max_cq_cqes_per_cq
&
1146 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK
) >>
1147 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET
;
1148 attr
->wqe_size
= ((rsp
->wqe_rqe_stride_max_dpp_cqs
&
1149 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK
) >>
1150 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET
) *
1152 attr
->rqe_size
= ((rsp
->wqe_rqe_stride_max_dpp_cqs
&
1153 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK
) >>
1154 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET
) *
1156 attr
->max_inline_data
=
1157 attr
->wqe_size
- (sizeof(struct ocrdma_hdr_wqe
) +
1158 sizeof(struct ocrdma_sge
));
1159 if (ocrdma_get_asic_type(dev
) == OCRDMA_ASIC_GEN_SKH_R
) {
1161 attr
->ird_page_size
= OCRDMA_MIN_Q_PAGE_SIZE
;
1162 attr
->num_ird_pages
= MAX_OCRDMA_IRD_PAGES
;
1164 dev
->attr
.max_wqe
= rsp
->max_wqes_rqes_per_q
>>
1165 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET
;
1166 dev
->attr
.max_rqe
= rsp
->max_wqes_rqes_per_q
&
1167 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK
;
1170 static int ocrdma_check_fw_config(struct ocrdma_dev
*dev
,
1171 struct ocrdma_fw_conf_rsp
*conf
)
1175 fn_mode
= conf
->fn_mode
& OCRDMA_FN_MODE_RDMA
;
1176 if (fn_mode
!= OCRDMA_FN_MODE_RDMA
)
1178 dev
->base_eqid
= conf
->base_eqid
;
1179 dev
->max_eq
= conf
->max_eq
;
1183 /* can be issued only during init time. */
1184 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev
*dev
)
1186 int status
= -ENOMEM
;
1187 struct ocrdma_mqe
*cmd
;
1188 struct ocrdma_fw_ver_rsp
*rsp
;
1190 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER
, sizeof(*cmd
));
1193 ocrdma_init_mch((struct ocrdma_mbx_hdr
*)&cmd
->u
.cmd
[0],
1194 OCRDMA_CMD_GET_FW_VER
,
1195 OCRDMA_SUBSYS_COMMON
, sizeof(*cmd
));
1197 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1200 rsp
= (struct ocrdma_fw_ver_rsp
*)cmd
;
1201 memset(&dev
->attr
.fw_ver
[0], 0, sizeof(dev
->attr
.fw_ver
));
1202 memcpy(&dev
->attr
.fw_ver
[0], &rsp
->running_ver
[0],
1203 sizeof(rsp
->running_ver
));
1204 ocrdma_le32_to_cpu(dev
->attr
.fw_ver
, sizeof(rsp
->running_ver
));
1210 /* can be issued only during init time. */
1211 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev
*dev
)
1213 int status
= -ENOMEM
;
1214 struct ocrdma_mqe
*cmd
;
1215 struct ocrdma_fw_conf_rsp
*rsp
;
1217 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG
, sizeof(*cmd
));
1220 ocrdma_init_mch((struct ocrdma_mbx_hdr
*)&cmd
->u
.cmd
[0],
1221 OCRDMA_CMD_GET_FW_CONFIG
,
1222 OCRDMA_SUBSYS_COMMON
, sizeof(*cmd
));
1223 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1226 rsp
= (struct ocrdma_fw_conf_rsp
*)cmd
;
1227 status
= ocrdma_check_fw_config(dev
, rsp
);
1233 int ocrdma_mbx_rdma_stats(struct ocrdma_dev
*dev
, bool reset
)
1235 struct ocrdma_rdma_stats_req
*req
= dev
->stats_mem
.va
;
1236 struct ocrdma_mqe
*mqe
= &dev
->stats_mem
.mqe
;
1237 struct ocrdma_rdma_stats_resp
*old_stats
;
1240 old_stats
= kmalloc(sizeof(*old_stats
), GFP_KERNEL
);
1241 if (old_stats
== NULL
)
1244 memset(mqe
, 0, sizeof(*mqe
));
1245 mqe
->hdr
.pyld_len
= dev
->stats_mem
.size
;
1246 mqe
->hdr
.spcl_sge_cnt_emb
|=
1247 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT
) &
1248 OCRDMA_MQE_HDR_SGE_CNT_MASK
;
1249 mqe
->u
.nonemb_req
.sge
[0].pa_lo
= (u32
) (dev
->stats_mem
.pa
& 0xffffffff);
1250 mqe
->u
.nonemb_req
.sge
[0].pa_hi
= (u32
) upper_32_bits(dev
->stats_mem
.pa
);
1251 mqe
->u
.nonemb_req
.sge
[0].len
= dev
->stats_mem
.size
;
1253 /* Cache the old stats */
1254 memcpy(old_stats
, req
, sizeof(struct ocrdma_rdma_stats_resp
));
1255 memset(req
, 0, dev
->stats_mem
.size
);
1257 ocrdma_init_mch((struct ocrdma_mbx_hdr
*)req
,
1258 OCRDMA_CMD_GET_RDMA_STATS
,
1260 dev
->stats_mem
.size
);
1262 req
->reset_stats
= reset
;
1264 status
= ocrdma_nonemb_mbx_cmd(dev
, mqe
, dev
->stats_mem
.va
);
1266 /* Copy from cache, if mbox fails */
1267 memcpy(req
, old_stats
, sizeof(struct ocrdma_rdma_stats_resp
));
1269 ocrdma_le32_to_cpu(req
, dev
->stats_mem
.size
);
1275 static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev
*dev
)
1277 int status
= -ENOMEM
;
1278 struct ocrdma_dma_mem dma
;
1279 struct ocrdma_mqe
*mqe
;
1280 struct ocrdma_get_ctrl_attribs_rsp
*ctrl_attr_rsp
;
1281 struct mgmt_hba_attribs
*hba_attribs
;
1283 mqe
= kzalloc(sizeof(struct ocrdma_mqe
), GFP_KERNEL
);
1287 dma
.size
= sizeof(struct ocrdma_get_ctrl_attribs_rsp
);
1288 dma
.va
= dma_alloc_coherent(&dev
->nic_info
.pdev
->dev
,
1289 dma
.size
, &dma
.pa
, GFP_KERNEL
);
1293 mqe
->hdr
.pyld_len
= dma
.size
;
1294 mqe
->hdr
.spcl_sge_cnt_emb
|=
1295 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT
) &
1296 OCRDMA_MQE_HDR_SGE_CNT_MASK
;
1297 mqe
->u
.nonemb_req
.sge
[0].pa_lo
= (u32
) (dma
.pa
& 0xffffffff);
1298 mqe
->u
.nonemb_req
.sge
[0].pa_hi
= (u32
) upper_32_bits(dma
.pa
);
1299 mqe
->u
.nonemb_req
.sge
[0].len
= dma
.size
;
1301 memset(dma
.va
, 0, dma
.size
);
1302 ocrdma_init_mch((struct ocrdma_mbx_hdr
*)dma
.va
,
1303 OCRDMA_CMD_GET_CTRL_ATTRIBUTES
,
1304 OCRDMA_SUBSYS_COMMON
,
1307 status
= ocrdma_nonemb_mbx_cmd(dev
, mqe
, dma
.va
);
1309 ctrl_attr_rsp
= (struct ocrdma_get_ctrl_attribs_rsp
*)dma
.va
;
1310 hba_attribs
= &ctrl_attr_rsp
->ctrl_attribs
.hba_attribs
;
1312 dev
->hba_port_num
= (hba_attribs
->ptpnum_maxdoms_hbast_cv
&
1313 OCRDMA_HBA_ATTRB_PTNUM_MASK
)
1314 >> OCRDMA_HBA_ATTRB_PTNUM_SHIFT
;
1315 strncpy(dev
->model_number
,
1316 hba_attribs
->controller_model_number
, 31);
1318 dma_free_coherent(&dev
->nic_info
.pdev
->dev
, dma
.size
, dma
.va
, dma
.pa
);
1324 static int ocrdma_mbx_query_dev(struct ocrdma_dev
*dev
)
1326 int status
= -ENOMEM
;
1327 struct ocrdma_mbx_query_config
*rsp
;
1328 struct ocrdma_mqe
*cmd
;
1330 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG
, sizeof(*cmd
));
1333 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1336 rsp
= (struct ocrdma_mbx_query_config
*)cmd
;
1337 ocrdma_get_attr(dev
, &dev
->attr
, rsp
);
1343 int ocrdma_mbx_get_link_speed(struct ocrdma_dev
*dev
, u8
*lnk_speed
)
1345 int status
= -ENOMEM
;
1346 struct ocrdma_get_link_speed_rsp
*rsp
;
1347 struct ocrdma_mqe
*cmd
;
1349 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1
,
1353 ocrdma_init_mch((struct ocrdma_mbx_hdr
*)&cmd
->u
.cmd
[0],
1354 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1
,
1355 OCRDMA_SUBSYS_COMMON
, sizeof(*cmd
));
1357 ((struct ocrdma_mbx_hdr
*)cmd
->u
.cmd
)->rsvd_version
= 0x1;
1359 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1363 rsp
= (struct ocrdma_get_link_speed_rsp
*)cmd
;
1364 *lnk_speed
= (rsp
->pflt_pps_ld_pnum
& OCRDMA_PHY_PS_MASK
)
1365 >> OCRDMA_PHY_PS_SHIFT
;
1372 static int ocrdma_mbx_get_phy_info(struct ocrdma_dev
*dev
)
1374 int status
= -ENOMEM
;
1375 struct ocrdma_mqe
*cmd
;
1376 struct ocrdma_get_phy_info_rsp
*rsp
;
1378 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS
, sizeof(*cmd
));
1382 ocrdma_init_mch((struct ocrdma_mbx_hdr
*)&cmd
->u
.cmd
[0],
1383 OCRDMA_CMD_PHY_DETAILS
, OCRDMA_SUBSYS_COMMON
,
1386 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1390 rsp
= (struct ocrdma_get_phy_info_rsp
*)cmd
;
1392 (rsp
->ityp_ptyp
& OCRDMA_PHY_TYPE_MASK
);
1393 dev
->phy
.interface_type
=
1394 (rsp
->ityp_ptyp
& OCRDMA_IF_TYPE_MASK
)
1395 >> OCRDMA_IF_TYPE_SHIFT
;
1396 dev
->phy
.auto_speeds_supported
=
1397 (rsp
->fspeed_aspeed
& OCRDMA_ASPEED_SUPP_MASK
);
1398 dev
->phy
.fixed_speeds_supported
=
1399 (rsp
->fspeed_aspeed
& OCRDMA_FSPEED_SUPP_MASK
)
1400 >> OCRDMA_FSPEED_SUPP_SHIFT
;
1406 int ocrdma_mbx_alloc_pd(struct ocrdma_dev
*dev
, struct ocrdma_pd
*pd
)
1408 int status
= -ENOMEM
;
1409 struct ocrdma_alloc_pd
*cmd
;
1410 struct ocrdma_alloc_pd_rsp
*rsp
;
1412 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD
, sizeof(*cmd
));
1415 if (pd
->dpp_enabled
)
1416 cmd
->enable_dpp_rsvd
|= OCRDMA_ALLOC_PD_ENABLE_DPP
;
1417 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1420 rsp
= (struct ocrdma_alloc_pd_rsp
*)cmd
;
1421 pd
->id
= rsp
->dpp_page_pdid
& OCRDMA_ALLOC_PD_RSP_PDID_MASK
;
1422 if (rsp
->dpp_page_pdid
& OCRDMA_ALLOC_PD_RSP_DPP
) {
1423 pd
->dpp_enabled
= true;
1424 pd
->dpp_page
= rsp
->dpp_page_pdid
>>
1425 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT
;
1427 pd
->dpp_enabled
= false;
1435 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev
*dev
, struct ocrdma_pd
*pd
)
1437 int status
= -ENOMEM
;
1438 struct ocrdma_dealloc_pd
*cmd
;
1440 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD
, sizeof(*cmd
));
1444 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1450 static int ocrdma_mbx_alloc_pd_range(struct ocrdma_dev
*dev
)
1452 int status
= -ENOMEM
;
1453 size_t pd_bitmap_size
;
1454 struct ocrdma_alloc_pd_range
*cmd
;
1455 struct ocrdma_alloc_pd_range_rsp
*rsp
;
1457 /* Pre allocate the DPP PDs */
1458 if (dev
->attr
.max_dpp_pds
) {
1459 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE
,
1463 cmd
->pd_count
= dev
->attr
.max_dpp_pds
;
1464 cmd
->enable_dpp_rsvd
|= OCRDMA_ALLOC_PD_ENABLE_DPP
;
1465 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1466 rsp
= (struct ocrdma_alloc_pd_range_rsp
*)cmd
;
1468 if (!status
&& (rsp
->dpp_page_pdid
& OCRDMA_ALLOC_PD_RSP_DPP
) &&
1470 dev
->pd_mgr
->dpp_page_index
= rsp
->dpp_page_pdid
>>
1471 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT
;
1472 dev
->pd_mgr
->pd_dpp_start
= rsp
->dpp_page_pdid
&
1473 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK
;
1474 dev
->pd_mgr
->max_dpp_pd
= rsp
->pd_count
;
1476 BITS_TO_LONGS(rsp
->pd_count
) * sizeof(long);
1477 dev
->pd_mgr
->pd_dpp_bitmap
= kzalloc(pd_bitmap_size
,
1483 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE
, sizeof(*cmd
));
1487 cmd
->pd_count
= dev
->attr
.max_pd
- dev
->attr
.max_dpp_pds
;
1488 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1489 rsp
= (struct ocrdma_alloc_pd_range_rsp
*)cmd
;
1490 if (!status
&& rsp
->pd_count
) {
1491 dev
->pd_mgr
->pd_norm_start
= rsp
->dpp_page_pdid
&
1492 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK
;
1493 dev
->pd_mgr
->max_normal_pd
= rsp
->pd_count
;
1494 pd_bitmap_size
= BITS_TO_LONGS(rsp
->pd_count
) * sizeof(long);
1495 dev
->pd_mgr
->pd_norm_bitmap
= kzalloc(pd_bitmap_size
,
1500 if (dev
->pd_mgr
->pd_norm_bitmap
|| dev
->pd_mgr
->pd_dpp_bitmap
) {
1501 /* Enable PD resource manager */
1502 dev
->pd_mgr
->pd_prealloc_valid
= true;
1508 static void ocrdma_mbx_dealloc_pd_range(struct ocrdma_dev
*dev
)
1510 struct ocrdma_dealloc_pd_range
*cmd
;
1512 /* return normal PDs to firmware */
1513 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE
, sizeof(*cmd
));
1517 if (dev
->pd_mgr
->max_normal_pd
) {
1518 cmd
->start_pd_id
= dev
->pd_mgr
->pd_norm_start
;
1519 cmd
->pd_count
= dev
->pd_mgr
->max_normal_pd
;
1520 ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1523 if (dev
->pd_mgr
->max_dpp_pd
) {
1525 /* return DPP PDs to firmware */
1526 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE
,
1531 cmd
->start_pd_id
= dev
->pd_mgr
->pd_dpp_start
;
1532 cmd
->pd_count
= dev
->pd_mgr
->max_dpp_pd
;
1533 ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1539 void ocrdma_alloc_pd_pool(struct ocrdma_dev
*dev
)
1543 dev
->pd_mgr
= kzalloc(sizeof(struct ocrdma_pd_resource_mgr
),
1546 pr_err("%s(%d)Memory allocation failure.\n", __func__
, dev
->id
);
1549 status
= ocrdma_mbx_alloc_pd_range(dev
);
1551 pr_err("%s(%d) Unable to initialize PD pool, using default.\n",
1556 static void ocrdma_free_pd_pool(struct ocrdma_dev
*dev
)
1558 ocrdma_mbx_dealloc_pd_range(dev
);
1559 kfree(dev
->pd_mgr
->pd_norm_bitmap
);
1560 kfree(dev
->pd_mgr
->pd_dpp_bitmap
);
1564 static int ocrdma_build_q_conf(u32
*num_entries
, int entry_size
,
1565 int *num_pages
, int *page_size
)
1570 *num_entries
= roundup_pow_of_two(*num_entries
);
1571 mem_size
= *num_entries
* entry_size
;
1572 /* find the possible lowest possible multiplier */
1573 for (i
= 0; i
< OCRDMA_MAX_Q_PAGE_SIZE_CNT
; i
++) {
1574 if (mem_size
<= (OCRDMA_Q_PAGE_BASE_SIZE
<< i
))
1577 if (i
>= OCRDMA_MAX_Q_PAGE_SIZE_CNT
)
1579 mem_size
= roundup(mem_size
,
1580 ((OCRDMA_Q_PAGE_BASE_SIZE
<< i
) / OCRDMA_MAX_Q_PAGES
));
1582 mem_size
/ ((OCRDMA_Q_PAGE_BASE_SIZE
<< i
) / OCRDMA_MAX_Q_PAGES
);
1583 *page_size
= ((OCRDMA_Q_PAGE_BASE_SIZE
<< i
) / OCRDMA_MAX_Q_PAGES
);
1584 *num_entries
= mem_size
/ entry_size
;
1588 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev
*dev
)
1593 struct ocrdma_create_ah_tbl
*cmd
;
1594 struct ocrdma_create_ah_tbl_rsp
*rsp
;
1595 struct pci_dev
*pdev
= dev
->nic_info
.pdev
;
1597 struct ocrdma_pbe
*pbes
;
1599 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL
, sizeof(*cmd
));
1603 max_ah
= OCRDMA_MAX_AH
;
1604 dev
->av_tbl
.size
= sizeof(struct ocrdma_av
) * max_ah
;
1606 /* number of PBEs in PBL */
1607 cmd
->ah_conf
= (OCRDMA_AH_TBL_PAGES
<<
1608 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT
) &
1609 OCRDMA_CREATE_AH_NUM_PAGES_MASK
;
1612 for (i
= 0; i
< OCRDMA_MAX_Q_PAGE_SIZE_CNT
; i
++) {
1613 if (PAGE_SIZE
== (OCRDMA_MIN_Q_PAGE_SIZE
<< i
))
1616 cmd
->ah_conf
|= (i
<< OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT
) &
1617 OCRDMA_CREATE_AH_PAGE_SIZE_MASK
;
1620 cmd
->ah_conf
|= (sizeof(struct ocrdma_av
) <<
1621 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT
) &
1622 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK
;
1624 dev
->av_tbl
.pbl
.va
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
1625 &dev
->av_tbl
.pbl
.pa
,
1627 if (dev
->av_tbl
.pbl
.va
== NULL
)
1630 dev
->av_tbl
.va
= dma_alloc_coherent(&pdev
->dev
, dev
->av_tbl
.size
,
1632 if (dev
->av_tbl
.va
== NULL
)
1634 dev
->av_tbl
.pa
= pa
;
1635 dev
->av_tbl
.num_ah
= max_ah
;
1636 memset(dev
->av_tbl
.va
, 0, dev
->av_tbl
.size
);
1638 pbes
= (struct ocrdma_pbe
*)dev
->av_tbl
.pbl
.va
;
1639 for (i
= 0; i
< dev
->av_tbl
.size
/ OCRDMA_MIN_Q_PAGE_SIZE
; i
++) {
1640 pbes
[i
].pa_lo
= (u32
)cpu_to_le32(pa
& 0xffffffff);
1641 pbes
[i
].pa_hi
= (u32
)cpu_to_le32(upper_32_bits(pa
));
1644 cmd
->tbl_addr
[0].lo
= (u32
)(dev
->av_tbl
.pbl
.pa
& 0xFFFFFFFF);
1645 cmd
->tbl_addr
[0].hi
= (u32
)upper_32_bits(dev
->av_tbl
.pbl
.pa
);
1646 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1649 rsp
= (struct ocrdma_create_ah_tbl_rsp
*)cmd
;
1650 dev
->av_tbl
.ahid
= rsp
->ahid
& 0xFFFF;
1655 dma_free_coherent(&pdev
->dev
, dev
->av_tbl
.size
, dev
->av_tbl
.va
,
1657 dev
->av_tbl
.va
= NULL
;
1659 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, dev
->av_tbl
.pbl
.va
,
1660 dev
->av_tbl
.pbl
.pa
);
1661 dev
->av_tbl
.pbl
.va
= NULL
;
1662 dev
->av_tbl
.size
= 0;
1668 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev
*dev
)
1670 struct ocrdma_delete_ah_tbl
*cmd
;
1671 struct pci_dev
*pdev
= dev
->nic_info
.pdev
;
1673 if (dev
->av_tbl
.va
== NULL
)
1676 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL
, sizeof(*cmd
));
1679 cmd
->ahid
= dev
->av_tbl
.ahid
;
1681 ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1682 dma_free_coherent(&pdev
->dev
, dev
->av_tbl
.size
, dev
->av_tbl
.va
,
1684 dev
->av_tbl
.va
= NULL
;
1685 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, dev
->av_tbl
.pbl
.va
,
1686 dev
->av_tbl
.pbl
.pa
);
1690 /* Multiple CQs uses the EQ. This routine returns least used
1691 * EQ to associate with CQ. This will distributes the interrupt
1692 * processing and CPU load to associated EQ, vector and so to that CPU.
1694 static u16
ocrdma_bind_eq(struct ocrdma_dev
*dev
)
1696 int i
, selected_eq
= 0, cq_cnt
= 0;
1699 mutex_lock(&dev
->dev_lock
);
1700 cq_cnt
= dev
->eq_tbl
[0].cq_cnt
;
1701 eq_id
= dev
->eq_tbl
[0].q
.id
;
1702 /* find the EQ which is has the least number of
1703 * CQs associated with it.
1705 for (i
= 0; i
< dev
->eq_cnt
; i
++) {
1706 if (dev
->eq_tbl
[i
].cq_cnt
< cq_cnt
) {
1707 cq_cnt
= dev
->eq_tbl
[i
].cq_cnt
;
1708 eq_id
= dev
->eq_tbl
[i
].q
.id
;
1712 dev
->eq_tbl
[selected_eq
].cq_cnt
+= 1;
1713 mutex_unlock(&dev
->dev_lock
);
1717 static void ocrdma_unbind_eq(struct ocrdma_dev
*dev
, u16 eq_id
)
1721 mutex_lock(&dev
->dev_lock
);
1722 i
= ocrdma_get_eq_table_index(dev
, eq_id
);
1725 dev
->eq_tbl
[i
].cq_cnt
-= 1;
1726 mutex_unlock(&dev
->dev_lock
);
1729 int ocrdma_mbx_create_cq(struct ocrdma_dev
*dev
, struct ocrdma_cq
*cq
,
1730 int entries
, int dpp_cq
, u16 pd_id
)
1732 int status
= -ENOMEM
; int max_hw_cqe
;
1733 struct pci_dev
*pdev
= dev
->nic_info
.pdev
;
1734 struct ocrdma_create_cq
*cmd
;
1735 struct ocrdma_create_cq_rsp
*rsp
;
1736 u32 hw_pages
, cqe_size
, page_size
, cqe_count
;
1738 if (entries
> dev
->attr
.max_cqe
) {
1739 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1740 __func__
, dev
->id
, dev
->attr
.max_cqe
, entries
);
1743 if (dpp_cq
&& (ocrdma_get_asic_type(dev
) != OCRDMA_ASIC_GEN_SKH_R
))
1749 cqe_size
= OCRDMA_DPP_CQE_SIZE
;
1752 cq
->max_hw_cqe
= dev
->attr
.max_cqe
;
1753 max_hw_cqe
= dev
->attr
.max_cqe
;
1754 cqe_size
= sizeof(struct ocrdma_cqe
);
1755 hw_pages
= OCRDMA_CREATE_CQ_MAX_PAGES
;
1758 cq
->len
= roundup(max_hw_cqe
* cqe_size
, OCRDMA_MIN_Q_PAGE_SIZE
);
1760 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ
, sizeof(*cmd
));
1763 ocrdma_init_mch(&cmd
->cmd
.req
, OCRDMA_CMD_CREATE_CQ
,
1764 OCRDMA_SUBSYS_COMMON
, sizeof(*cmd
));
1765 cq
->va
= dma_alloc_coherent(&pdev
->dev
, cq
->len
, &cq
->pa
, GFP_KERNEL
);
1770 memset(cq
->va
, 0, cq
->len
);
1771 page_size
= cq
->len
/ hw_pages
;
1772 cmd
->cmd
.pgsz_pgcnt
= (page_size
/ OCRDMA_MIN_Q_PAGE_SIZE
) <<
1773 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT
;
1774 cmd
->cmd
.pgsz_pgcnt
|= hw_pages
;
1775 cmd
->cmd
.ev_cnt_flags
= OCRDMA_CREATE_CQ_DEF_FLAGS
;
1777 cq
->eqn
= ocrdma_bind_eq(dev
);
1778 cmd
->cmd
.req
.rsvd_version
= OCRDMA_CREATE_CQ_VER3
;
1779 cqe_count
= cq
->len
/ cqe_size
;
1780 cq
->cqe_cnt
= cqe_count
;
1781 if (cqe_count
> 1024) {
1782 /* Set cnt to 3 to indicate more than 1024 cq entries */
1783 cmd
->cmd
.ev_cnt_flags
|= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT
);
1786 switch (cqe_count
) {
1799 cmd
->cmd
.ev_cnt_flags
|= (count
<< OCRDMA_CREATE_CQ_CNT_SHIFT
);
1801 /* shared eq between all the consumer cqs. */
1802 cmd
->cmd
.eqn
= cq
->eqn
;
1803 if (ocrdma_get_asic_type(dev
) == OCRDMA_ASIC_GEN_SKH_R
) {
1805 cmd
->cmd
.pgsz_pgcnt
|= OCRDMA_CREATE_CQ_DPP
<<
1806 OCRDMA_CREATE_CQ_TYPE_SHIFT
;
1807 cq
->phase_change
= false;
1808 cmd
->cmd
.pdid_cqecnt
= (cq
->len
/ cqe_size
);
1810 cmd
->cmd
.pdid_cqecnt
= (cq
->len
/ cqe_size
) - 1;
1811 cmd
->cmd
.ev_cnt_flags
|= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID
;
1812 cq
->phase_change
= true;
1815 /* pd_id valid only for v3 */
1816 cmd
->cmd
.pdid_cqecnt
|= (pd_id
<<
1817 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT
);
1818 ocrdma_build_q_pages(&cmd
->cmd
.pa
[0], hw_pages
, cq
->pa
, page_size
);
1819 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1823 rsp
= (struct ocrdma_create_cq_rsp
*)cmd
;
1824 cq
->id
= (u16
) (rsp
->rsp
.cq_id
& OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK
);
1828 ocrdma_unbind_eq(dev
, cq
->eqn
);
1829 dma_free_coherent(&pdev
->dev
, cq
->len
, cq
->va
, cq
->pa
);
1835 int ocrdma_mbx_destroy_cq(struct ocrdma_dev
*dev
, struct ocrdma_cq
*cq
)
1837 int status
= -ENOMEM
;
1838 struct ocrdma_destroy_cq
*cmd
;
1840 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ
, sizeof(*cmd
));
1843 ocrdma_init_mch(&cmd
->req
, OCRDMA_CMD_DELETE_CQ
,
1844 OCRDMA_SUBSYS_COMMON
, sizeof(*cmd
));
1846 cmd
->bypass_flush_qid
|=
1847 (cq
->id
<< OCRDMA_DESTROY_CQ_QID_SHIFT
) &
1848 OCRDMA_DESTROY_CQ_QID_MASK
;
1850 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1851 ocrdma_unbind_eq(dev
, cq
->eqn
);
1852 dma_free_coherent(&dev
->nic_info
.pdev
->dev
, cq
->len
, cq
->va
, cq
->pa
);
1857 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev
*dev
, struct ocrdma_hw_mr
*hwmr
,
1858 u32 pdid
, int addr_check
)
1860 int status
= -ENOMEM
;
1861 struct ocrdma_alloc_lkey
*cmd
;
1862 struct ocrdma_alloc_lkey_rsp
*rsp
;
1864 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY
, sizeof(*cmd
));
1868 cmd
->pbl_sz_flags
|= addr_check
;
1869 cmd
->pbl_sz_flags
|= (hwmr
->fr_mr
<< OCRDMA_ALLOC_LKEY_FMR_SHIFT
);
1870 cmd
->pbl_sz_flags
|=
1871 (hwmr
->remote_wr
<< OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT
);
1872 cmd
->pbl_sz_flags
|=
1873 (hwmr
->remote_rd
<< OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT
);
1874 cmd
->pbl_sz_flags
|=
1875 (hwmr
->local_wr
<< OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT
);
1876 cmd
->pbl_sz_flags
|=
1877 (hwmr
->remote_atomic
<< OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT
);
1878 cmd
->pbl_sz_flags
|=
1879 (hwmr
->num_pbls
<< OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
);
1881 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1884 rsp
= (struct ocrdma_alloc_lkey_rsp
*)cmd
;
1885 hwmr
->lkey
= rsp
->lrkey
;
1891 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev
*dev
, int fr_mr
, u32 lkey
)
1893 int status
= -ENOMEM
;
1894 struct ocrdma_dealloc_lkey
*cmd
;
1896 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY
, sizeof(*cmd
));
1900 cmd
->rsvd_frmr
= fr_mr
? 1 : 0;
1901 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1909 static int ocrdma_mbx_reg_mr(struct ocrdma_dev
*dev
, struct ocrdma_hw_mr
*hwmr
,
1910 u32 pdid
, u32 pbl_cnt
, u32 pbe_size
, u32 last
)
1912 int status
= -ENOMEM
;
1914 struct ocrdma_reg_nsmr
*cmd
;
1915 struct ocrdma_reg_nsmr_rsp
*rsp
;
1917 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR
, sizeof(*cmd
));
1921 pdid
| (hwmr
->num_pbls
<< OCRDMA_REG_NSMR_NUM_PBL_SHIFT
);
1922 cmd
->fr_mr
= hwmr
->fr_mr
;
1924 cmd
->flags_hpage_pbe_sz
|= (hwmr
->remote_wr
<<
1925 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT
);
1926 cmd
->flags_hpage_pbe_sz
|= (hwmr
->remote_rd
<<
1927 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT
);
1928 cmd
->flags_hpage_pbe_sz
|= (hwmr
->local_wr
<<
1929 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT
);
1930 cmd
->flags_hpage_pbe_sz
|= (hwmr
->remote_atomic
<<
1931 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT
);
1932 cmd
->flags_hpage_pbe_sz
|= (hwmr
->mw_bind
<<
1933 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT
);
1934 cmd
->flags_hpage_pbe_sz
|= (last
<< OCRDMA_REG_NSMR_LAST_SHIFT
);
1936 cmd
->flags_hpage_pbe_sz
|= (hwmr
->pbe_size
/ OCRDMA_MIN_HPAGE_SIZE
);
1937 cmd
->flags_hpage_pbe_sz
|= (hwmr
->pbl_size
/ OCRDMA_MIN_HPAGE_SIZE
) <<
1938 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT
;
1939 cmd
->totlen_low
= hwmr
->len
;
1940 cmd
->totlen_high
= upper_32_bits(hwmr
->len
);
1941 cmd
->fbo_low
= (u32
) (hwmr
->fbo
& 0xffffffff);
1942 cmd
->fbo_high
= (u32
) upper_32_bits(hwmr
->fbo
);
1943 cmd
->va_loaddr
= (u32
) hwmr
->va
;
1944 cmd
->va_hiaddr
= (u32
) upper_32_bits(hwmr
->va
);
1946 for (i
= 0; i
< pbl_cnt
; i
++) {
1947 cmd
->pbl
[i
].lo
= (u32
) (hwmr
->pbl_table
[i
].pa
& 0xffffffff);
1948 cmd
->pbl
[i
].hi
= upper_32_bits(hwmr
->pbl_table
[i
].pa
);
1950 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1953 rsp
= (struct ocrdma_reg_nsmr_rsp
*)cmd
;
1954 hwmr
->lkey
= rsp
->lrkey
;
1960 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev
*dev
,
1961 struct ocrdma_hw_mr
*hwmr
, u32 pbl_cnt
,
1962 u32 pbl_offset
, u32 last
)
1964 int status
= -ENOMEM
;
1966 struct ocrdma_reg_nsmr_cont
*cmd
;
1968 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT
, sizeof(*cmd
));
1971 cmd
->lrkey
= hwmr
->lkey
;
1972 cmd
->num_pbl_offset
= (pbl_cnt
<< OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT
) |
1973 (pbl_offset
& OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK
);
1974 cmd
->last
= last
<< OCRDMA_REG_NSMR_CONT_LAST_SHIFT
;
1976 for (i
= 0; i
< pbl_cnt
; i
++) {
1978 (u32
) (hwmr
->pbl_table
[i
+ pbl_offset
].pa
& 0xffffffff);
1980 upper_32_bits(hwmr
->pbl_table
[i
+ pbl_offset
].pa
);
1982 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
1990 int ocrdma_reg_mr(struct ocrdma_dev
*dev
,
1991 struct ocrdma_hw_mr
*hwmr
, u32 pdid
, int acc
)
1995 u32 cur_pbl_cnt
, pbl_offset
;
1996 u32 pending_pbl_cnt
= hwmr
->num_pbls
;
1999 cur_pbl_cnt
= min(pending_pbl_cnt
, MAX_OCRDMA_NSMR_PBL
);
2000 if (cur_pbl_cnt
== pending_pbl_cnt
)
2003 status
= ocrdma_mbx_reg_mr(dev
, hwmr
, pdid
,
2004 cur_pbl_cnt
, hwmr
->pbe_size
, last
);
2006 pr_err("%s() status=%d\n", __func__
, status
);
2009 /* if there is no more pbls to register then exit. */
2014 pbl_offset
+= cur_pbl_cnt
;
2015 pending_pbl_cnt
-= cur_pbl_cnt
;
2016 cur_pbl_cnt
= min(pending_pbl_cnt
, MAX_OCRDMA_NSMR_PBL
);
2017 /* if we reach the end of the pbls, then need to set the last
2018 * bit, indicating no more pbls to register for this memory key.
2020 if (cur_pbl_cnt
== pending_pbl_cnt
)
2023 status
= ocrdma_mbx_reg_mr_cont(dev
, hwmr
, cur_pbl_cnt
,
2029 pr_err("%s() err. status=%d\n", __func__
, status
);
2034 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq
*cq
, struct ocrdma_qp
*qp
)
2036 struct ocrdma_qp
*tmp
;
2038 list_for_each_entry(tmp
, &cq
->sq_head
, sq_entry
) {
2047 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq
*cq
, struct ocrdma_qp
*qp
)
2049 struct ocrdma_qp
*tmp
;
2051 list_for_each_entry(tmp
, &cq
->rq_head
, rq_entry
) {
2060 void ocrdma_flush_qp(struct ocrdma_qp
*qp
)
2063 unsigned long flags
;
2064 struct ocrdma_dev
*dev
= get_ocrdma_dev(qp
->ibqp
.device
);
2066 spin_lock_irqsave(&dev
->flush_q_lock
, flags
);
2067 found
= ocrdma_is_qp_in_sq_flushlist(qp
->sq_cq
, qp
);
2069 list_add_tail(&qp
->sq_entry
, &qp
->sq_cq
->sq_head
);
2071 found
= ocrdma_is_qp_in_rq_flushlist(qp
->rq_cq
, qp
);
2073 list_add_tail(&qp
->rq_entry
, &qp
->rq_cq
->rq_head
);
2075 spin_unlock_irqrestore(&dev
->flush_q_lock
, flags
);
2078 static void ocrdma_init_hwq_ptr(struct ocrdma_qp
*qp
)
2086 int ocrdma_qp_state_change(struct ocrdma_qp
*qp
, enum ib_qp_state new_ib_state
,
2087 enum ib_qp_state
*old_ib_state
)
2089 unsigned long flags
;
2091 enum ocrdma_qp_state new_state
;
2092 new_state
= get_ocrdma_qp_state(new_ib_state
);
2094 /* sync with wqe and rqe posting */
2095 spin_lock_irqsave(&qp
->q_lock
, flags
);
2098 *old_ib_state
= get_ibqp_state(qp
->state
);
2099 if (new_state
== qp
->state
) {
2100 spin_unlock_irqrestore(&qp
->q_lock
, flags
);
2105 if (new_state
== OCRDMA_QPS_INIT
) {
2106 ocrdma_init_hwq_ptr(qp
);
2107 ocrdma_del_flush_qp(qp
);
2108 } else if (new_state
== OCRDMA_QPS_ERR
) {
2109 ocrdma_flush_qp(qp
);
2112 qp
->state
= new_state
;
2114 spin_unlock_irqrestore(&qp
->q_lock
, flags
);
2118 static u32
ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp
*qp
)
2121 if (qp
->cap_flags
& OCRDMA_QP_INB_RD
)
2122 flags
|= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK
;
2123 if (qp
->cap_flags
& OCRDMA_QP_INB_WR
)
2124 flags
|= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK
;
2125 if (qp
->cap_flags
& OCRDMA_QP_MW_BIND
)
2126 flags
|= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK
;
2127 if (qp
->cap_flags
& OCRDMA_QP_LKEY0
)
2128 flags
|= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK
;
2129 if (qp
->cap_flags
& OCRDMA_QP_FAST_REG
)
2130 flags
|= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK
;
2134 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req
*cmd
,
2135 struct ib_qp_init_attr
*attrs
,
2136 struct ocrdma_qp
*qp
)
2139 u32 len
, hw_pages
, hw_page_size
;
2141 struct ocrdma_pd
*pd
= qp
->pd
;
2142 struct ocrdma_dev
*dev
= get_ocrdma_dev(pd
->ibpd
.device
);
2143 struct pci_dev
*pdev
= dev
->nic_info
.pdev
;
2144 u32 max_wqe_allocated
;
2145 u32 max_sges
= attrs
->cap
.max_send_sge
;
2147 /* QP1 may exceed 127 */
2148 max_wqe_allocated
= min_t(u32
, attrs
->cap
.max_send_wr
+ 1,
2151 status
= ocrdma_build_q_conf(&max_wqe_allocated
,
2152 dev
->attr
.wqe_size
, &hw_pages
, &hw_page_size
);
2154 pr_err("%s() req. max_send_wr=0x%x\n", __func__
,
2158 qp
->sq
.max_cnt
= max_wqe_allocated
;
2159 len
= (hw_pages
* hw_page_size
);
2161 qp
->sq
.va
= dma_alloc_coherent(&pdev
->dev
, len
, &pa
, GFP_KERNEL
);
2164 memset(qp
->sq
.va
, 0, len
);
2167 qp
->sq
.entry_size
= dev
->attr
.wqe_size
;
2168 ocrdma_build_q_pages(&cmd
->wq_addr
[0], hw_pages
, pa
, hw_page_size
);
2170 cmd
->type_pgsz_pdn
|= (ilog2(hw_page_size
/ OCRDMA_MIN_Q_PAGE_SIZE
)
2171 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT
);
2172 cmd
->num_wq_rq_pages
|= (hw_pages
<<
2173 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT
) &
2174 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK
;
2175 cmd
->max_sge_send_write
|= (max_sges
<<
2176 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT
) &
2177 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK
;
2178 cmd
->max_sge_send_write
|= (max_sges
<<
2179 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT
) &
2180 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK
;
2181 cmd
->max_wqe_rqe
|= (ilog2(qp
->sq
.max_cnt
) <<
2182 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT
) &
2183 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK
;
2184 cmd
->wqe_rqe_size
|= (dev
->attr
.wqe_size
<<
2185 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT
) &
2186 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK
;
2190 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req
*cmd
,
2191 struct ib_qp_init_attr
*attrs
,
2192 struct ocrdma_qp
*qp
)
2195 u32 len
, hw_pages
, hw_page_size
;
2197 struct ocrdma_pd
*pd
= qp
->pd
;
2198 struct ocrdma_dev
*dev
= get_ocrdma_dev(pd
->ibpd
.device
);
2199 struct pci_dev
*pdev
= dev
->nic_info
.pdev
;
2200 u32 max_rqe_allocated
= attrs
->cap
.max_recv_wr
+ 1;
2202 status
= ocrdma_build_q_conf(&max_rqe_allocated
, dev
->attr
.rqe_size
,
2203 &hw_pages
, &hw_page_size
);
2205 pr_err("%s() req. max_recv_wr=0x%x\n", __func__
,
2206 attrs
->cap
.max_recv_wr
+ 1);
2209 qp
->rq
.max_cnt
= max_rqe_allocated
;
2210 len
= (hw_pages
* hw_page_size
);
2212 qp
->rq
.va
= dma_alloc_coherent(&pdev
->dev
, len
, &pa
, GFP_KERNEL
);
2215 memset(qp
->rq
.va
, 0, len
);
2218 qp
->rq
.entry_size
= dev
->attr
.rqe_size
;
2220 ocrdma_build_q_pages(&cmd
->rq_addr
[0], hw_pages
, pa
, hw_page_size
);
2221 cmd
->type_pgsz_pdn
|= (ilog2(hw_page_size
/ OCRDMA_MIN_Q_PAGE_SIZE
) <<
2222 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT
);
2223 cmd
->num_wq_rq_pages
|=
2224 (hw_pages
<< OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT
) &
2225 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK
;
2226 cmd
->max_sge_recv_flags
|= (attrs
->cap
.max_recv_sge
<<
2227 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT
) &
2228 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK
;
2229 cmd
->max_wqe_rqe
|= (ilog2(qp
->rq
.max_cnt
) <<
2230 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT
) &
2231 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK
;
2232 cmd
->wqe_rqe_size
|= (dev
->attr
.rqe_size
<<
2233 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT
) &
2234 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK
;
2238 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req
*cmd
,
2239 struct ocrdma_pd
*pd
,
2240 struct ocrdma_qp
*qp
,
2241 u8 enable_dpp_cq
, u16 dpp_cq_id
)
2244 qp
->dpp_enabled
= true;
2245 cmd
->max_sge_recv_flags
|= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK
;
2248 cmd
->max_sge_recv_flags
|= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK
;
2249 cmd
->dpp_credits_cqid
= dpp_cq_id
;
2250 cmd
->dpp_credits_cqid
|= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT
<<
2251 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
;
2254 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req
*cmd
,
2255 struct ocrdma_qp
*qp
)
2257 struct ocrdma_pd
*pd
= qp
->pd
;
2258 struct ocrdma_dev
*dev
= get_ocrdma_dev(pd
->ibpd
.device
);
2259 struct pci_dev
*pdev
= dev
->nic_info
.pdev
;
2261 int ird_page_size
= dev
->attr
.ird_page_size
;
2262 int ird_q_len
= dev
->attr
.num_ird_pages
* ird_page_size
;
2263 struct ocrdma_hdr_wqe
*rqe
;
2266 if (dev
->attr
.ird
== 0)
2269 qp
->ird_q_va
= dma_alloc_coherent(&pdev
->dev
, ird_q_len
,
2273 memset(qp
->ird_q_va
, 0, ird_q_len
);
2274 ocrdma_build_q_pages(&cmd
->ird_addr
[0], dev
->attr
.num_ird_pages
,
2276 for (; i
< ird_q_len
/ dev
->attr
.rqe_size
; i
++) {
2277 rqe
= (struct ocrdma_hdr_wqe
*)(qp
->ird_q_va
+
2278 (i
* dev
->attr
.rqe_size
));
2281 rqe
->cw
|= (OCRDMA_TYPE_LKEY
<< OCRDMA_WQE_TYPE_SHIFT
);
2282 rqe
->cw
|= (8 << OCRDMA_WQE_SIZE_SHIFT
);
2283 rqe
->cw
|= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT
);
2288 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp
*rsp
,
2289 struct ocrdma_qp
*qp
,
2290 struct ib_qp_init_attr
*attrs
,
2291 u16
*dpp_offset
, u16
*dpp_credit_lmt
)
2293 u32 max_wqe_allocated
, max_rqe_allocated
;
2294 qp
->id
= rsp
->qp_id
& OCRDMA_CREATE_QP_RSP_QP_ID_MASK
;
2295 qp
->rq
.dbid
= rsp
->sq_rq_id
& OCRDMA_CREATE_QP_RSP_RQ_ID_MASK
;
2296 qp
->sq
.dbid
= rsp
->sq_rq_id
>> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT
;
2297 qp
->max_ird
= rsp
->max_ord_ird
& OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK
;
2298 qp
->max_ord
= (rsp
->max_ord_ird
>> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT
);
2299 qp
->dpp_enabled
= false;
2300 if (rsp
->dpp_response
& OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK
) {
2301 qp
->dpp_enabled
= true;
2302 *dpp_credit_lmt
= (rsp
->dpp_response
&
2303 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK
) >>
2304 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT
;
2305 *dpp_offset
= (rsp
->dpp_response
&
2306 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK
) >>
2307 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT
;
2310 rsp
->max_wqe_rqe
>> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT
;
2311 max_wqe_allocated
= 1 << max_wqe_allocated
;
2312 max_rqe_allocated
= 1 << ((u16
)rsp
->max_wqe_rqe
);
2314 qp
->sq
.max_cnt
= max_wqe_allocated
;
2315 qp
->sq
.max_wqe_idx
= max_wqe_allocated
- 1;
2318 qp
->rq
.max_cnt
= max_rqe_allocated
;
2319 qp
->rq
.max_wqe_idx
= max_rqe_allocated
- 1;
2323 int ocrdma_mbx_create_qp(struct ocrdma_qp
*qp
, struct ib_qp_init_attr
*attrs
,
2324 u8 enable_dpp_cq
, u16 dpp_cq_id
, u16
*dpp_offset
,
2325 u16
*dpp_credit_lmt
)
2327 int status
= -ENOMEM
;
2329 struct ocrdma_pd
*pd
= qp
->pd
;
2330 struct ocrdma_dev
*dev
= get_ocrdma_dev(pd
->ibpd
.device
);
2331 struct pci_dev
*pdev
= dev
->nic_info
.pdev
;
2332 struct ocrdma_cq
*cq
;
2333 struct ocrdma_create_qp_req
*cmd
;
2334 struct ocrdma_create_qp_rsp
*rsp
;
2337 switch (attrs
->qp_type
) {
2339 qptype
= OCRDMA_QPT_GSI
;
2342 qptype
= OCRDMA_QPT_RC
;
2345 qptype
= OCRDMA_QPT_UD
;
2351 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP
, sizeof(*cmd
));
2354 cmd
->type_pgsz_pdn
|= (qptype
<< OCRDMA_CREATE_QP_REQ_QPT_SHIFT
) &
2355 OCRDMA_CREATE_QP_REQ_QPT_MASK
;
2356 status
= ocrdma_set_create_qp_sq_cmd(cmd
, attrs
, qp
);
2361 struct ocrdma_srq
*srq
= get_ocrdma_srq(attrs
->srq
);
2362 cmd
->max_sge_recv_flags
|= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK
;
2363 cmd
->rq_addr
[0].lo
= srq
->id
;
2366 status
= ocrdma_set_create_qp_rq_cmd(cmd
, attrs
, qp
);
2371 status
= ocrdma_set_create_qp_ird_cmd(cmd
, qp
);
2375 cmd
->type_pgsz_pdn
|= (pd
->id
<< OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT
) &
2376 OCRDMA_CREATE_QP_REQ_PD_ID_MASK
;
2378 flags
= ocrdma_set_create_qp_mbx_access_flags(qp
);
2380 cmd
->max_sge_recv_flags
|= flags
;
2381 cmd
->max_ord_ird
|= (dev
->attr
.max_ord_per_qp
<<
2382 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT
) &
2383 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK
;
2384 cmd
->max_ord_ird
|= (dev
->attr
.max_ird_per_qp
<<
2385 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT
) &
2386 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK
;
2387 cq
= get_ocrdma_cq(attrs
->send_cq
);
2388 cmd
->wq_rq_cqid
|= (cq
->id
<< OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT
) &
2389 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK
;
2391 cq
= get_ocrdma_cq(attrs
->recv_cq
);
2392 cmd
->wq_rq_cqid
|= (cq
->id
<< OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT
) &
2393 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK
;
2396 if (pd
->dpp_enabled
&& attrs
->cap
.max_inline_data
&& pd
->num_dpp_qp
&&
2397 (attrs
->cap
.max_inline_data
<= dev
->attr
.max_inline_data
)) {
2398 ocrdma_set_create_qp_dpp_cmd(cmd
, pd
, qp
, enable_dpp_cq
,
2402 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
2405 rsp
= (struct ocrdma_create_qp_rsp
*)cmd
;
2406 ocrdma_get_create_qp_rsp(rsp
, qp
, attrs
, dpp_offset
, dpp_credit_lmt
);
2407 qp
->state
= OCRDMA_QPS_RST
;
2412 dma_free_coherent(&pdev
->dev
, qp
->rq
.len
, qp
->rq
.va
, qp
->rq
.pa
);
2414 pr_err("%s(%d) rq_err\n", __func__
, dev
->id
);
2415 dma_free_coherent(&pdev
->dev
, qp
->sq
.len
, qp
->sq
.va
, qp
->sq
.pa
);
2417 pr_err("%s(%d) sq_err\n", __func__
, dev
->id
);
2422 int ocrdma_mbx_query_qp(struct ocrdma_dev
*dev
, struct ocrdma_qp
*qp
,
2423 struct ocrdma_qp_params
*param
)
2425 int status
= -ENOMEM
;
2426 struct ocrdma_query_qp
*cmd
;
2427 struct ocrdma_query_qp_rsp
*rsp
;
2429 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP
, sizeof(*rsp
));
2432 cmd
->qp_id
= qp
->id
;
2433 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
2436 rsp
= (struct ocrdma_query_qp_rsp
*)cmd
;
2437 memcpy(param
, &rsp
->params
, sizeof(struct ocrdma_qp_params
));
2443 static int ocrdma_set_av_params(struct ocrdma_qp
*qp
,
2444 struct ocrdma_modify_qp
*cmd
,
2445 struct ib_qp_attr
*attrs
,
2449 struct ib_ah_attr
*ah_attr
= &attrs
->ah_attr
;
2450 union ib_gid sgid
, zgid
;
2451 u32 vlan_id
= 0xFFFF;
2453 struct ocrdma_dev
*dev
= get_ocrdma_dev(qp
->ibqp
.device
);
2455 if ((ah_attr
->ah_flags
& IB_AH_GRH
) == 0)
2457 if (atomic_cmpxchg(&dev
->update_sl
, 1, 0))
2458 ocrdma_init_service_level(dev
);
2459 cmd
->params
.tclass_sq_psn
|=
2460 (ah_attr
->grh
.traffic_class
<< OCRDMA_QP_PARAMS_TCLASS_SHIFT
);
2461 cmd
->params
.rnt_rc_sl_fl
|=
2462 (ah_attr
->grh
.flow_label
& OCRDMA_QP_PARAMS_FLOW_LABEL_MASK
);
2463 cmd
->params
.rnt_rc_sl_fl
|= (ah_attr
->sl
<< OCRDMA_QP_PARAMS_SL_SHIFT
);
2464 cmd
->params
.hop_lmt_rq_psn
|=
2465 (ah_attr
->grh
.hop_limit
<< OCRDMA_QP_PARAMS_HOP_LMT_SHIFT
);
2466 cmd
->flags
|= OCRDMA_QP_PARA_FLOW_LBL_VALID
;
2467 memcpy(&cmd
->params
.dgid
[0], &ah_attr
->grh
.dgid
.raw
[0],
2468 sizeof(cmd
->params
.dgid
));
2469 status
= ocrdma_query_gid(&dev
->ibdev
, 1,
2470 ah_attr
->grh
.sgid_index
, &sgid
);
2474 memset(&zgid
, 0, sizeof(zgid
));
2475 if (!memcmp(&sgid
, &zgid
, sizeof(zgid
)))
2478 qp
->sgid_idx
= ah_attr
->grh
.sgid_index
;
2479 memcpy(&cmd
->params
.sgid
[0], &sgid
.raw
[0], sizeof(cmd
->params
.sgid
));
2480 status
= ocrdma_resolve_dmac(dev
, ah_attr
, &mac_addr
[0]);
2483 cmd
->params
.dmac_b0_to_b3
= mac_addr
[0] | (mac_addr
[1] << 8) |
2484 (mac_addr
[2] << 16) | (mac_addr
[3] << 24);
2485 /* convert them to LE format. */
2486 ocrdma_cpu_to_le32(&cmd
->params
.dgid
[0], sizeof(cmd
->params
.dgid
));
2487 ocrdma_cpu_to_le32(&cmd
->params
.sgid
[0], sizeof(cmd
->params
.sgid
));
2488 cmd
->params
.vlan_dmac_b4_to_b5
= mac_addr
[4] | (mac_addr
[5] << 8);
2489 if (attr_mask
& IB_QP_VID
) {
2490 vlan_id
= attrs
->vlan_id
;
2491 } else if (dev
->pfc_state
) {
2493 pr_err("ocrdma%d:Using VLAN with PFC is recommended\n",
2495 pr_err("ocrdma%d:Using VLAN 0 for this connection\n",
2499 if (vlan_id
< 0x1000) {
2500 cmd
->params
.vlan_dmac_b4_to_b5
|=
2501 vlan_id
<< OCRDMA_QP_PARAMS_VLAN_SHIFT
;
2502 cmd
->flags
|= OCRDMA_QP_PARA_VLAN_EN_VALID
;
2503 cmd
->params
.rnt_rc_sl_fl
|=
2504 (dev
->sl
& 0x07) << OCRDMA_QP_PARAMS_SL_SHIFT
;
2510 static int ocrdma_set_qp_params(struct ocrdma_qp
*qp
,
2511 struct ocrdma_modify_qp
*cmd
,
2512 struct ib_qp_attr
*attrs
, int attr_mask
)
2515 struct ocrdma_dev
*dev
= get_ocrdma_dev(qp
->ibqp
.device
);
2517 if (attr_mask
& IB_QP_PKEY_INDEX
) {
2518 cmd
->params
.path_mtu_pkey_indx
|= (attrs
->pkey_index
&
2519 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK
);
2520 cmd
->flags
|= OCRDMA_QP_PARA_PKEY_VALID
;
2522 if (attr_mask
& IB_QP_QKEY
) {
2523 qp
->qkey
= attrs
->qkey
;
2524 cmd
->params
.qkey
= attrs
->qkey
;
2525 cmd
->flags
|= OCRDMA_QP_PARA_QKEY_VALID
;
2527 if (attr_mask
& IB_QP_AV
) {
2528 status
= ocrdma_set_av_params(qp
, cmd
, attrs
, attr_mask
);
2531 } else if (qp
->qp_type
== IB_QPT_GSI
|| qp
->qp_type
== IB_QPT_UD
) {
2532 /* set the default mac address for UD, GSI QPs */
2533 cmd
->params
.dmac_b0_to_b3
= dev
->nic_info
.mac_addr
[0] |
2534 (dev
->nic_info
.mac_addr
[1] << 8) |
2535 (dev
->nic_info
.mac_addr
[2] << 16) |
2536 (dev
->nic_info
.mac_addr
[3] << 24);
2537 cmd
->params
.vlan_dmac_b4_to_b5
= dev
->nic_info
.mac_addr
[4] |
2538 (dev
->nic_info
.mac_addr
[5] << 8);
2540 if ((attr_mask
& IB_QP_EN_SQD_ASYNC_NOTIFY
) &&
2541 attrs
->en_sqd_async_notify
) {
2542 cmd
->params
.max_sge_recv_flags
|=
2543 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC
;
2544 cmd
->flags
|= OCRDMA_QP_PARA_DST_QPN_VALID
;
2546 if (attr_mask
& IB_QP_DEST_QPN
) {
2547 cmd
->params
.ack_to_rnr_rtc_dest_qpn
|= (attrs
->dest_qp_num
&
2548 OCRDMA_QP_PARAMS_DEST_QPN_MASK
);
2549 cmd
->flags
|= OCRDMA_QP_PARA_DST_QPN_VALID
;
2551 if (attr_mask
& IB_QP_PATH_MTU
) {
2552 if (attrs
->path_mtu
< IB_MTU_512
||
2553 attrs
->path_mtu
> IB_MTU_4096
) {
2554 pr_err("ocrdma%d: IB MTU %d is not supported\n",
2555 dev
->id
, ib_mtu_enum_to_int(attrs
->path_mtu
));
2559 cmd
->params
.path_mtu_pkey_indx
|=
2560 (ib_mtu_enum_to_int(attrs
->path_mtu
) <<
2561 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT
) &
2562 OCRDMA_QP_PARAMS_PATH_MTU_MASK
;
2563 cmd
->flags
|= OCRDMA_QP_PARA_PMTU_VALID
;
2565 if (attr_mask
& IB_QP_TIMEOUT
) {
2566 cmd
->params
.ack_to_rnr_rtc_dest_qpn
|= attrs
->timeout
<<
2567 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT
;
2568 cmd
->flags
|= OCRDMA_QP_PARA_ACK_TO_VALID
;
2570 if (attr_mask
& IB_QP_RETRY_CNT
) {
2571 cmd
->params
.rnt_rc_sl_fl
|= (attrs
->retry_cnt
<<
2572 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT
) &
2573 OCRDMA_QP_PARAMS_RETRY_CNT_MASK
;
2574 cmd
->flags
|= OCRDMA_QP_PARA_RETRY_CNT_VALID
;
2576 if (attr_mask
& IB_QP_MIN_RNR_TIMER
) {
2577 cmd
->params
.rnt_rc_sl_fl
|= (attrs
->min_rnr_timer
<<
2578 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT
) &
2579 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK
;
2580 cmd
->flags
|= OCRDMA_QP_PARA_RNT_VALID
;
2582 if (attr_mask
& IB_QP_RNR_RETRY
) {
2583 cmd
->params
.ack_to_rnr_rtc_dest_qpn
|= (attrs
->rnr_retry
<<
2584 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT
)
2585 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK
;
2586 cmd
->flags
|= OCRDMA_QP_PARA_RRC_VALID
;
2588 if (attr_mask
& IB_QP_SQ_PSN
) {
2589 cmd
->params
.tclass_sq_psn
|= (attrs
->sq_psn
& 0x00ffffff);
2590 cmd
->flags
|= OCRDMA_QP_PARA_SQPSN_VALID
;
2592 if (attr_mask
& IB_QP_RQ_PSN
) {
2593 cmd
->params
.hop_lmt_rq_psn
|= (attrs
->rq_psn
& 0x00ffffff);
2594 cmd
->flags
|= OCRDMA_QP_PARA_RQPSN_VALID
;
2596 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
) {
2597 if (attrs
->max_rd_atomic
> dev
->attr
.max_ord_per_qp
) {
2601 qp
->max_ord
= attrs
->max_rd_atomic
;
2602 cmd
->flags
|= OCRDMA_QP_PARA_MAX_ORD_VALID
;
2604 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
) {
2605 if (attrs
->max_dest_rd_atomic
> dev
->attr
.max_ird_per_qp
) {
2609 qp
->max_ird
= attrs
->max_dest_rd_atomic
;
2610 cmd
->flags
|= OCRDMA_QP_PARA_MAX_IRD_VALID
;
2612 cmd
->params
.max_ord_ird
= (qp
->max_ord
<<
2613 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT
) |
2614 (qp
->max_ird
& OCRDMA_QP_PARAMS_MAX_IRD_MASK
);
2619 int ocrdma_mbx_modify_qp(struct ocrdma_dev
*dev
, struct ocrdma_qp
*qp
,
2620 struct ib_qp_attr
*attrs
, int attr_mask
)
2622 int status
= -ENOMEM
;
2623 struct ocrdma_modify_qp
*cmd
;
2625 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP
, sizeof(*cmd
));
2629 cmd
->params
.id
= qp
->id
;
2631 if (attr_mask
& IB_QP_STATE
) {
2632 cmd
->params
.max_sge_recv_flags
|=
2633 (get_ocrdma_qp_state(attrs
->qp_state
) <<
2634 OCRDMA_QP_PARAMS_STATE_SHIFT
) &
2635 OCRDMA_QP_PARAMS_STATE_MASK
;
2636 cmd
->flags
|= OCRDMA_QP_PARA_QPS_VALID
;
2638 cmd
->params
.max_sge_recv_flags
|=
2639 (qp
->state
<< OCRDMA_QP_PARAMS_STATE_SHIFT
) &
2640 OCRDMA_QP_PARAMS_STATE_MASK
;
2643 status
= ocrdma_set_qp_params(qp
, cmd
, attrs
, attr_mask
);
2646 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
2655 int ocrdma_mbx_destroy_qp(struct ocrdma_dev
*dev
, struct ocrdma_qp
*qp
)
2657 int status
= -ENOMEM
;
2658 struct ocrdma_destroy_qp
*cmd
;
2659 struct pci_dev
*pdev
= dev
->nic_info
.pdev
;
2661 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP
, sizeof(*cmd
));
2664 cmd
->qp_id
= qp
->id
;
2665 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
2672 dma_free_coherent(&pdev
->dev
, qp
->sq
.len
, qp
->sq
.va
, qp
->sq
.pa
);
2673 if (!qp
->srq
&& qp
->rq
.va
)
2674 dma_free_coherent(&pdev
->dev
, qp
->rq
.len
, qp
->rq
.va
, qp
->rq
.pa
);
2675 if (qp
->dpp_enabled
)
2676 qp
->pd
->num_dpp_qp
++;
2680 int ocrdma_mbx_create_srq(struct ocrdma_dev
*dev
, struct ocrdma_srq
*srq
,
2681 struct ib_srq_init_attr
*srq_attr
,
2682 struct ocrdma_pd
*pd
)
2684 int status
= -ENOMEM
;
2685 int hw_pages
, hw_page_size
;
2687 struct ocrdma_create_srq_rsp
*rsp
;
2688 struct ocrdma_create_srq
*cmd
;
2690 struct pci_dev
*pdev
= dev
->nic_info
.pdev
;
2691 u32 max_rqe_allocated
;
2693 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ
, sizeof(*cmd
));
2697 cmd
->pgsz_pdid
= pd
->id
& OCRDMA_CREATE_SRQ_PD_ID_MASK
;
2698 max_rqe_allocated
= srq_attr
->attr
.max_wr
+ 1;
2699 status
= ocrdma_build_q_conf(&max_rqe_allocated
,
2701 &hw_pages
, &hw_page_size
);
2703 pr_err("%s() req. max_wr=0x%x\n", __func__
,
2704 srq_attr
->attr
.max_wr
);
2708 len
= hw_pages
* hw_page_size
;
2709 srq
->rq
.va
= dma_alloc_coherent(&pdev
->dev
, len
, &pa
, GFP_KERNEL
);
2714 ocrdma_build_q_pages(&cmd
->rq_addr
[0], hw_pages
, pa
, hw_page_size
);
2716 srq
->rq
.entry_size
= dev
->attr
.rqe_size
;
2719 srq
->rq
.max_cnt
= max_rqe_allocated
;
2721 cmd
->max_sge_rqe
= ilog2(max_rqe_allocated
);
2722 cmd
->max_sge_rqe
|= srq_attr
->attr
.max_sge
<<
2723 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT
;
2725 cmd
->pgsz_pdid
|= (ilog2(hw_page_size
/ OCRDMA_MIN_Q_PAGE_SIZE
)
2726 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT
);
2727 cmd
->pages_rqe_sz
|= (dev
->attr
.rqe_size
2728 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT
)
2729 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK
;
2730 cmd
->pages_rqe_sz
|= hw_pages
<< OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
;
2732 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
2735 rsp
= (struct ocrdma_create_srq_rsp
*)cmd
;
2737 srq
->rq
.dbid
= rsp
->id
;
2738 max_rqe_allocated
= ((rsp
->max_sge_rqe_allocated
&
2739 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK
) >>
2740 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT
);
2741 max_rqe_allocated
= (1 << max_rqe_allocated
);
2742 srq
->rq
.max_cnt
= max_rqe_allocated
;
2743 srq
->rq
.max_wqe_idx
= max_rqe_allocated
- 1;
2744 srq
->rq
.max_sges
= (rsp
->max_sge_rqe_allocated
&
2745 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK
) >>
2746 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
;
2749 dma_free_coherent(&pdev
->dev
, srq
->rq
.len
, srq
->rq
.va
, pa
);
2755 int ocrdma_mbx_modify_srq(struct ocrdma_srq
*srq
, struct ib_srq_attr
*srq_attr
)
2757 int status
= -ENOMEM
;
2758 struct ocrdma_modify_srq
*cmd
;
2759 struct ocrdma_pd
*pd
= srq
->pd
;
2760 struct ocrdma_dev
*dev
= get_ocrdma_dev(pd
->ibpd
.device
);
2762 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ
, sizeof(*cmd
));
2766 cmd
->limit_max_rqe
|= srq_attr
->srq_limit
<<
2767 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
;
2768 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
2773 int ocrdma_mbx_query_srq(struct ocrdma_srq
*srq
, struct ib_srq_attr
*srq_attr
)
2775 int status
= -ENOMEM
;
2776 struct ocrdma_query_srq
*cmd
;
2777 struct ocrdma_dev
*dev
= get_ocrdma_dev(srq
->ibsrq
.device
);
2779 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ
, sizeof(*cmd
));
2782 cmd
->id
= srq
->rq
.dbid
;
2783 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
2785 struct ocrdma_query_srq_rsp
*rsp
=
2786 (struct ocrdma_query_srq_rsp
*)cmd
;
2788 rsp
->srq_lmt_max_sge
&
2789 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK
;
2791 rsp
->max_rqe_pdid
>> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT
;
2792 srq_attr
->srq_limit
= rsp
->srq_lmt_max_sge
>>
2793 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
;
2799 int ocrdma_mbx_destroy_srq(struct ocrdma_dev
*dev
, struct ocrdma_srq
*srq
)
2801 int status
= -ENOMEM
;
2802 struct ocrdma_destroy_srq
*cmd
;
2803 struct pci_dev
*pdev
= dev
->nic_info
.pdev
;
2804 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ
, sizeof(*cmd
));
2808 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
2810 dma_free_coherent(&pdev
->dev
, srq
->rq
.len
,
2811 srq
->rq
.va
, srq
->rq
.pa
);
2816 static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev
*dev
, u32 ptype
,
2817 struct ocrdma_dcbx_cfg
*dcbxcfg
)
2821 struct ocrdma_mqe cmd
;
2823 struct ocrdma_get_dcbx_cfg_req
*req
= NULL
;
2824 struct ocrdma_get_dcbx_cfg_rsp
*rsp
= NULL
;
2825 struct pci_dev
*pdev
= dev
->nic_info
.pdev
;
2826 struct ocrdma_mqe_sge
*mqe_sge
= cmd
.u
.nonemb_req
.sge
;
2828 memset(&cmd
, 0, sizeof(struct ocrdma_mqe
));
2829 cmd
.hdr
.pyld_len
= max_t (u32
, sizeof(struct ocrdma_get_dcbx_cfg_rsp
),
2830 sizeof(struct ocrdma_get_dcbx_cfg_req
));
2831 req
= dma_alloc_coherent(&pdev
->dev
, cmd
.hdr
.pyld_len
, &pa
, GFP_KERNEL
);
2837 cmd
.hdr
.spcl_sge_cnt_emb
|= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT
) &
2838 OCRDMA_MQE_HDR_SGE_CNT_MASK
;
2839 mqe_sge
->pa_lo
= (u32
) (pa
& 0xFFFFFFFFUL
);
2840 mqe_sge
->pa_hi
= (u32
) upper_32_bits(pa
);
2841 mqe_sge
->len
= cmd
.hdr
.pyld_len
;
2843 memset(req
, 0, sizeof(struct ocrdma_get_dcbx_cfg_req
));
2844 ocrdma_init_mch(&req
->hdr
, OCRDMA_CMD_GET_DCBX_CONFIG
,
2845 OCRDMA_SUBSYS_DCBX
, cmd
.hdr
.pyld_len
);
2846 req
->param_type
= ptype
;
2848 status
= ocrdma_mbx_cmd(dev
, &cmd
);
2852 rsp
= (struct ocrdma_get_dcbx_cfg_rsp
*)req
;
2853 ocrdma_le32_to_cpu(rsp
, sizeof(struct ocrdma_get_dcbx_cfg_rsp
));
2854 memcpy(dcbxcfg
, &rsp
->cfg
, sizeof(struct ocrdma_dcbx_cfg
));
2857 dma_free_coherent(&pdev
->dev
, cmd
.hdr
.pyld_len
, req
, pa
);
2862 #define OCRDMA_MAX_SERVICE_LEVEL_INDEX 0x08
2863 #define OCRDMA_DEFAULT_SERVICE_LEVEL 0x05
2865 static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev
*dev
, int ptype
,
2866 struct ocrdma_dcbx_cfg
*dcbxcfg
,
2869 int status
= -EINVAL
, indx
, slindx
;
2871 struct ocrdma_app_parameter
*app_param
;
2872 u8 valid
, proto_sel
;
2873 u8 app_prio
, pfc_prio
;
2876 if (!(dcbxcfg
->tcv_aev_opv_st
& OCRDMA_DCBX_STATE_MASK
)) {
2877 pr_info("%s ocrdma%d DCBX is disabled\n",
2878 dev_name(&dev
->nic_info
.pdev
->dev
), dev
->id
);
2882 if (!ocrdma_is_enabled_and_synced(dcbxcfg
->pfc_state
)) {
2883 pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2884 dev_name(&dev
->nic_info
.pdev
->dev
), dev
->id
,
2885 (ptype
> 0 ? "operational" : "admin"),
2886 (dcbxcfg
->pfc_state
& OCRDMA_STATE_FLAG_ENABLED
) ?
2887 "enabled" : "disabled",
2888 (dcbxcfg
->pfc_state
& OCRDMA_STATE_FLAG_SYNC
) ?
2889 "" : ", not sync'ed");
2892 pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2893 dev_name(&dev
->nic_info
.pdev
->dev
), dev
->id
);
2896 ventry_cnt
= (dcbxcfg
->tcv_aev_opv_st
>>
2897 OCRDMA_DCBX_APP_ENTRY_SHIFT
)
2898 & OCRDMA_DCBX_STATE_MASK
;
2900 for (indx
= 0; indx
< ventry_cnt
; indx
++) {
2901 app_param
= &dcbxcfg
->app_param
[indx
];
2902 valid
= (app_param
->valid_proto_app
>>
2903 OCRDMA_APP_PARAM_VALID_SHIFT
)
2904 & OCRDMA_APP_PARAM_VALID_MASK
;
2905 proto_sel
= (app_param
->valid_proto_app
2906 >> OCRDMA_APP_PARAM_PROTO_SEL_SHIFT
)
2907 & OCRDMA_APP_PARAM_PROTO_SEL_MASK
;
2908 proto
= app_param
->valid_proto_app
&
2909 OCRDMA_APP_PARAM_APP_PROTO_MASK
;
2912 valid
&& proto
== OCRDMA_APP_PROTO_ROCE
&&
2913 proto_sel
== OCRDMA_PROTO_SELECT_L2
) {
2914 for (slindx
= 0; slindx
<
2915 OCRDMA_MAX_SERVICE_LEVEL_INDEX
; slindx
++) {
2916 app_prio
= ocrdma_get_app_prio(
2917 (u8
*)app_param
->app_prio
,
2919 pfc_prio
= ocrdma_get_pfc_prio(
2920 (u8
*)dcbxcfg
->pfc_prio
,
2923 if (app_prio
&& pfc_prio
) {
2929 if (slindx
== OCRDMA_MAX_SERVICE_LEVEL_INDEX
) {
2930 pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
2931 dev_name(&dev
->nic_info
.pdev
->dev
),
2941 void ocrdma_init_service_level(struct ocrdma_dev
*dev
)
2943 int status
= 0, indx
;
2944 struct ocrdma_dcbx_cfg dcbxcfg
;
2945 u8 srvc_lvl
= OCRDMA_DEFAULT_SERVICE_LEVEL
;
2946 int ptype
= OCRDMA_PARAMETER_TYPE_OPER
;
2948 for (indx
= 0; indx
< 2; indx
++) {
2949 status
= ocrdma_mbx_get_dcbx_config(dev
, ptype
, &dcbxcfg
);
2951 pr_err("%s(): status=%d\n", __func__
, status
);
2952 ptype
= OCRDMA_PARAMETER_TYPE_ADMIN
;
2956 status
= ocrdma_parse_dcbxcfg_rsp(dev
, ptype
,
2957 &dcbxcfg
, &srvc_lvl
);
2959 ptype
= OCRDMA_PARAMETER_TYPE_ADMIN
;
2967 pr_info("%s ocrdma%d service level default\n",
2968 dev_name(&dev
->nic_info
.pdev
->dev
), dev
->id
);
2970 pr_info("%s ocrdma%d service level %d\n",
2971 dev_name(&dev
->nic_info
.pdev
->dev
), dev
->id
,
2974 dev
->pfc_state
= ocrdma_is_enabled_and_synced(dcbxcfg
.pfc_state
);
2978 int ocrdma_alloc_av(struct ocrdma_dev
*dev
, struct ocrdma_ah
*ah
)
2981 int status
= -EINVAL
;
2982 struct ocrdma_av
*av
;
2983 unsigned long flags
;
2985 av
= dev
->av_tbl
.va
;
2986 spin_lock_irqsave(&dev
->av_tbl
.lock
, flags
);
2987 for (i
= 0; i
< dev
->av_tbl
.num_ah
; i
++) {
2988 if (av
->valid
== 0) {
2989 av
->valid
= OCRDMA_AV_VALID
;
2997 if (i
== dev
->av_tbl
.num_ah
)
2999 spin_unlock_irqrestore(&dev
->av_tbl
.lock
, flags
);
3003 int ocrdma_free_av(struct ocrdma_dev
*dev
, struct ocrdma_ah
*ah
)
3005 unsigned long flags
;
3006 spin_lock_irqsave(&dev
->av_tbl
.lock
, flags
);
3008 spin_unlock_irqrestore(&dev
->av_tbl
.lock
, flags
);
3012 static int ocrdma_create_eqs(struct ocrdma_dev
*dev
)
3014 int num_eq
, i
, status
= 0;
3016 unsigned long flags
= 0;
3018 num_eq
= dev
->nic_info
.msix
.num_vectors
-
3019 dev
->nic_info
.msix
.start_vector
;
3020 if (dev
->nic_info
.intr_mode
== BE_INTERRUPT_MODE_INTX
) {
3022 flags
= IRQF_SHARED
;
3024 num_eq
= min_t(u32
, num_eq
, num_online_cpus());
3030 dev
->eq_tbl
= kzalloc(sizeof(struct ocrdma_eq
) * num_eq
, GFP_KERNEL
);
3034 for (i
= 0; i
< num_eq
; i
++) {
3035 status
= ocrdma_create_eq(dev
, &dev
->eq_tbl
[i
],
3041 sprintf(dev
->eq_tbl
[i
].irq_name
, "ocrdma%d-%d",
3043 irq
= ocrdma_get_irq(dev
, &dev
->eq_tbl
[i
]);
3044 status
= request_irq(irq
, ocrdma_irq_handler
, flags
,
3045 dev
->eq_tbl
[i
].irq_name
,
3051 /* one eq is sufficient for data path to work */
3054 ocrdma_destroy_eqs(dev
);
3058 static int ocrdma_mbx_modify_eqd(struct ocrdma_dev
*dev
, struct ocrdma_eq
*eq
,
3061 int i
, status
= -ENOMEM
;
3062 struct ocrdma_modify_eqd_req
*cmd
;
3064 cmd
= ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_EQ_DELAY
, sizeof(*cmd
));
3068 ocrdma_init_mch(&cmd
->cmd
.req
, OCRDMA_CMD_MODIFY_EQ_DELAY
,
3069 OCRDMA_SUBSYS_COMMON
, sizeof(*cmd
));
3071 cmd
->cmd
.num_eq
= num
;
3072 for (i
= 0; i
< num
; i
++) {
3073 cmd
->cmd
.set_eqd
[i
].eq_id
= eq
[i
].q
.id
;
3074 cmd
->cmd
.set_eqd
[i
].phase
= 0;
3075 cmd
->cmd
.set_eqd
[i
].delay_multiplier
=
3076 (eq
[i
].aic_obj
.prev_eqd
* 65)/100;
3078 status
= ocrdma_mbx_cmd(dev
, (struct ocrdma_mqe
*)cmd
);
3086 static int ocrdma_modify_eqd(struct ocrdma_dev
*dev
, struct ocrdma_eq
*eq
,
3092 num_eqs
= min(num
, 8);
3093 ocrdma_mbx_modify_eqd(dev
, &eq
[i
], num_eqs
);
3098 ocrdma_mbx_modify_eqd(dev
, eq
, num
);
3103 void ocrdma_eqd_set_task(struct work_struct
*work
)
3105 struct ocrdma_dev
*dev
=
3106 container_of(work
, struct ocrdma_dev
, eqd_work
.work
);
3107 struct ocrdma_eq
*eq
= 0;
3108 int i
, num
= 0, status
= -EINVAL
;
3111 for (i
= 0; i
< dev
->eq_cnt
; i
++) {
3112 eq
= &dev
->eq_tbl
[i
];
3113 if (eq
->aic_obj
.eq_intr_cnt
> eq
->aic_obj
.prev_eq_intr_cnt
) {
3114 eq_intr
= eq
->aic_obj
.eq_intr_cnt
-
3115 eq
->aic_obj
.prev_eq_intr_cnt
;
3116 if ((eq_intr
> EQ_INTR_PER_SEC_THRSH_HI
) &&
3117 (eq
->aic_obj
.prev_eqd
== EQ_AIC_MIN_EQD
)) {
3118 eq
->aic_obj
.prev_eqd
= EQ_AIC_MAX_EQD
;
3120 } else if ((eq_intr
< EQ_INTR_PER_SEC_THRSH_LOW
) &&
3121 (eq
->aic_obj
.prev_eqd
== EQ_AIC_MAX_EQD
)) {
3122 eq
->aic_obj
.prev_eqd
= EQ_AIC_MIN_EQD
;
3126 eq
->aic_obj
.prev_eq_intr_cnt
= eq
->aic_obj
.eq_intr_cnt
;
3130 status
= ocrdma_modify_eqd(dev
, &dev
->eq_tbl
[0], num
);
3131 schedule_delayed_work(&dev
->eqd_work
, msecs_to_jiffies(1000));
3134 int ocrdma_init_hw(struct ocrdma_dev
*dev
)
3138 /* create the eqs */
3139 status
= ocrdma_create_eqs(dev
);
3142 status
= ocrdma_create_mq(dev
);
3145 status
= ocrdma_mbx_query_fw_config(dev
);
3148 status
= ocrdma_mbx_query_dev(dev
);
3151 status
= ocrdma_mbx_query_fw_ver(dev
);
3154 status
= ocrdma_mbx_create_ah_tbl(dev
);
3157 status
= ocrdma_mbx_get_phy_info(dev
);
3159 goto info_attrb_err
;
3160 status
= ocrdma_mbx_get_ctrl_attribs(dev
);
3162 goto info_attrb_err
;
3167 ocrdma_mbx_delete_ah_tbl(dev
);
3169 ocrdma_destroy_mq(dev
);
3171 ocrdma_destroy_eqs(dev
);
3173 pr_err("%s() status=%d\n", __func__
, status
);
3177 void ocrdma_cleanup_hw(struct ocrdma_dev
*dev
)
3179 ocrdma_free_pd_pool(dev
);
3180 ocrdma_mbx_delete_ah_tbl(dev
);
3182 /* cleanup the control path */
3183 ocrdma_destroy_mq(dev
);
3185 /* cleanup the eqs */
3186 ocrdma_destroy_eqs(dev
);