1 /*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
20 * Contact Information:
21 * linux-drivers@emulex.com
25 * Costa Mesa, CA 92626
26 *******************************************************************/
28 #ifndef __OCRDMA_SLI_H__
29 #define __OCRDMA_SLI_H__
32 OCRDMA_ASIC_GEN_SKH_R
= 0x04,
33 OCRDMA_ASIC_GEN_LANCER
= 0x0B
37 OCRDMA_ASIC_REV_A0
= 0x00,
38 OCRDMA_ASIC_REV_B0
= 0x10,
39 OCRDMA_ASIC_REV_C0
= 0x20
42 #define OCRDMA_SUBSYS_ROCE 10
44 OCRDMA_CMD_QUERY_CONFIG
= 1,
45 OCRDMA_CMD_ALLOC_PD
= 2,
46 OCRDMA_CMD_DEALLOC_PD
= 3,
48 OCRDMA_CMD_CREATE_AH_TBL
= 4,
49 OCRDMA_CMD_DELETE_AH_TBL
= 5,
51 OCRDMA_CMD_CREATE_QP
= 6,
52 OCRDMA_CMD_QUERY_QP
= 7,
53 OCRDMA_CMD_MODIFY_QP
= 8 ,
54 OCRDMA_CMD_DELETE_QP
= 9,
56 OCRDMA_CMD_RSVD1
= 10,
57 OCRDMA_CMD_ALLOC_LKEY
= 11,
58 OCRDMA_CMD_DEALLOC_LKEY
= 12,
59 OCRDMA_CMD_REGISTER_NSMR
= 13,
60 OCRDMA_CMD_REREGISTER_NSMR
= 14,
61 OCRDMA_CMD_REGISTER_NSMR_CONT
= 15,
62 OCRDMA_CMD_QUERY_NSMR
= 16,
63 OCRDMA_CMD_ALLOC_MW
= 17,
64 OCRDMA_CMD_QUERY_MW
= 18,
66 OCRDMA_CMD_CREATE_SRQ
= 19,
67 OCRDMA_CMD_QUERY_SRQ
= 20,
68 OCRDMA_CMD_MODIFY_SRQ
= 21,
69 OCRDMA_CMD_DELETE_SRQ
= 22,
71 OCRDMA_CMD_ATTACH_MCAST
= 23,
72 OCRDMA_CMD_DETACH_MCAST
= 24,
74 OCRDMA_CMD_CREATE_RBQ
= 25,
75 OCRDMA_CMD_DESTROY_RBQ
= 26,
77 OCRDMA_CMD_GET_RDMA_STATS
= 27,
78 OCRDMA_CMD_ALLOC_PD_RANGE
= 28,
79 OCRDMA_CMD_DEALLOC_PD_RANGE
= 29,
84 #define OCRDMA_SUBSYS_COMMON 1
86 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1
= 5,
87 OCRDMA_CMD_CREATE_CQ
= 12,
88 OCRDMA_CMD_CREATE_EQ
= 13,
89 OCRDMA_CMD_CREATE_MQ
= 21,
90 OCRDMA_CMD_GET_CTRL_ATTRIBUTES
= 32,
91 OCRDMA_CMD_GET_FW_VER
= 35,
92 OCRDMA_CMD_MODIFY_EQ_DELAY
= 41,
93 OCRDMA_CMD_DELETE_MQ
= 53,
94 OCRDMA_CMD_DELETE_CQ
= 54,
95 OCRDMA_CMD_DELETE_EQ
= 55,
96 OCRDMA_CMD_GET_FW_CONFIG
= 58,
97 OCRDMA_CMD_CREATE_MQ_EXT
= 90,
98 OCRDMA_CMD_PHY_DETAILS
= 102
107 #define OCRDMA_MAX_SGID 16
109 #define OCRDMA_MAX_QP 2048
110 #define OCRDMA_MAX_CQ 2048
111 #define OCRDMA_MAX_STAG 16384
114 OCRDMA_DB_RQ_OFFSET
= 0xE0,
115 OCRDMA_DB_GEN2_RQ_OFFSET
= 0x100,
116 OCRDMA_DB_SQ_OFFSET
= 0x60,
117 OCRDMA_DB_GEN2_SQ_OFFSET
= 0x1C0,
118 OCRDMA_DB_SRQ_OFFSET
= OCRDMA_DB_RQ_OFFSET
,
119 OCRDMA_DB_GEN2_SRQ_OFFSET
= OCRDMA_DB_GEN2_RQ_OFFSET
,
120 OCRDMA_DB_CQ_OFFSET
= 0x120,
121 OCRDMA_DB_EQ_OFFSET
= OCRDMA_DB_CQ_OFFSET
,
122 OCRDMA_DB_MQ_OFFSET
= 0x140,
124 OCRDMA_DB_SQ_SHIFT
= 16,
125 OCRDMA_DB_RQ_SHIFT
= 24
128 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
129 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */
130 /* qid #2 msbits at 12-11 */
131 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1
132 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT 16 /* bits 16 - 28 */
134 #define OCRDMA_DB_CQ_REARM_SHIFT 29 /* bit 29 */
136 #define OCRDMA_DB_CQ_SOLICIT_SHIFT 31 /* bit 31 */
138 #define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */
139 #define OCRDMA_EQ_ID_EXT_MASK 0x3e00 /* bits 9-13 */
140 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT 2 /* qid bits 9-13 at 11-15 */
142 /* Clear the interrupt for this eq */
143 #define OCRDMA_EQ_CLR_SHIFT 9 /* bit 9 */
145 #define OCRDMA_EQ_TYPE_SHIFT 10 /* bit 10 */
146 /* Number of event entries processed */
147 #define OCRDMA_NUM_EQE_SHIFT 16 /* bits 16 - 28 */
149 #define OCRDMA_REARM_SHIFT 29 /* bit 29 */
151 #define OCRDMA_MQ_ID_MASK 0x7FF /* bits 0 - 10 */
152 /* Number of entries posted */
153 #define OCRDMA_MQ_NUM_MQE_SHIFT 16 /* bits 16 - 29 */
155 #define OCRDMA_MIN_HPAGE_SIZE 4096
157 #define OCRDMA_MIN_Q_PAGE_SIZE 4096
158 #define OCRDMA_MAX_Q_PAGES 8
160 #define OCRDMA_SLI_ASIC_ID_OFFSET 0x9C
161 #define OCRDMA_SLI_ASIC_REV_MASK 0x000000FF
162 #define OCRDMA_SLI_ASIC_GEN_NUM_MASK 0x0000FF00
163 #define OCRDMA_SLI_ASIC_GEN_NUM_SHIFT 0x08
174 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT 8
175 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
177 #define MAX_OCRDMA_QP_PAGES 8
178 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)
180 #define OCRDMA_CREATE_CQ_MAX_PAGES 4
181 #define OCRDMA_DPP_CQE_SIZE 4
183 #define OCRDMA_GEN2_MAX_CQE 1024
184 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
185 #define OCRDMA_GEN2_WQE_SIZE 256
186 #define OCRDMA_MAX_CQE 4095
187 #define OCRDMA_CQ_PAGE_SIZE 16384
188 #define OCRDMA_WQE_SIZE 128
189 #define OCRDMA_WQE_STRIDE 8
190 #define OCRDMA_WQE_ALIGN_BYTES 16
192 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES
195 OCRDMA_MCH_OPCODE_SHIFT
= 0,
196 OCRDMA_MCH_OPCODE_MASK
= 0xFF,
197 OCRDMA_MCH_SUBSYS_SHIFT
= 8,
198 OCRDMA_MCH_SUBSYS_MASK
= 0xFF00
201 /* mailbox cmd header */
202 struct ocrdma_mbx_hdr
{
204 u32 timeout
; /* in seconds */
210 OCRDMA_MBX_RSP_OPCODE_SHIFT
= 0,
211 OCRDMA_MBX_RSP_OPCODE_MASK
= 0xFF,
212 OCRDMA_MBX_RSP_SUBSYS_SHIFT
= 8,
213 OCRDMA_MBX_RSP_SUBSYS_MASK
= 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT
,
215 OCRDMA_MBX_RSP_STATUS_SHIFT
= 0,
216 OCRDMA_MBX_RSP_STATUS_MASK
= 0xFF,
217 OCRDMA_MBX_RSP_ASTATUS_SHIFT
= 8,
218 OCRDMA_MBX_RSP_ASTATUS_MASK
= 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT
221 /* mailbox cmd response */
222 struct ocrdma_mbx_rsp
{
230 OCRDMA_MQE_EMBEDDED
= 1,
231 OCRDMA_MQE_NONEMBEDDED
= 0
234 struct ocrdma_mqe_sge
{
241 OCRDMA_MQE_HDR_EMB_SHIFT
= 0,
242 OCRDMA_MQE_HDR_EMB_MASK
= BIT(0),
243 OCRDMA_MQE_HDR_SGE_CNT_SHIFT
= 3,
244 OCRDMA_MQE_HDR_SGE_CNT_MASK
= 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT
,
245 OCRDMA_MQE_HDR_SPECIAL_SHIFT
= 24,
246 OCRDMA_MQE_HDR_SPECIAL_MASK
= 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT
249 struct ocrdma_mqe_hdr
{
250 u32 spcl_sge_cnt_emb
;
257 struct ocrdma_mqe_emb_cmd
{
258 struct ocrdma_mbx_hdr mch
;
263 struct ocrdma_mqe_hdr hdr
;
265 struct ocrdma_mqe_emb_cmd emb_req
;
267 struct ocrdma_mqe_sge sge
[19];
270 struct ocrdma_mbx_rsp rsp
;
274 #define OCRDMA_EQ_LEN 4096
275 #define OCRDMA_MQ_CQ_LEN 256
276 #define OCRDMA_MQ_LEN 128
278 #define PAGE_SHIFT_4K 12
279 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
281 /* Returns number of pages spanned by the data starting at the given addr */
282 #define PAGES_4K_SPANNED(_address, size) \
283 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
284 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
286 struct ocrdma_delete_q_req
{
287 struct ocrdma_mbx_hdr req
;
296 #define MAX_OCRDMA_EQ_PAGES 8
297 struct ocrdma_create_eq_req
{
298 struct ocrdma_mbx_hdr req
;
304 struct ocrdma_pa pa
[MAX_OCRDMA_EQ_PAGES
];
308 OCRDMA_CREATE_EQ_VALID
= BIT(29),
309 OCRDMA_CREATE_EQ_CNT_SHIFT
= 26,
310 OCRDMA_CREATE_CQ_DELAY_SHIFT
= 13,
313 struct ocrdma_create_eq_rsp
{
314 struct ocrdma_mbx_rsp rsp
;
318 #define OCRDMA_EQ_MINOR_OTHER 0x1
320 struct ocrmda_set_eqd
{
323 u32 delay_multiplier
;
326 struct ocrdma_modify_eqd_cmd
{
327 struct ocrdma_mbx_hdr req
;
329 struct ocrmda_set_eqd set_eqd
[8];
332 struct ocrdma_modify_eqd_req
{
333 struct ocrdma_mqe_hdr hdr
;
334 struct ocrdma_modify_eqd_cmd cmd
;
338 struct ocrdma_modify_eq_delay_rsp
{
339 struct ocrdma_mbx_rsp hdr
;
344 OCRDMA_MCQE_STATUS_SHIFT
= 0,
345 OCRDMA_MCQE_STATUS_MASK
= 0xFFFF,
346 OCRDMA_MCQE_ESTATUS_SHIFT
= 16,
347 OCRDMA_MCQE_ESTATUS_MASK
= 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT
,
348 OCRDMA_MCQE_CONS_SHIFT
= 27,
349 OCRDMA_MCQE_CONS_MASK
= BIT(27),
350 OCRDMA_MCQE_CMPL_SHIFT
= 28,
351 OCRDMA_MCQE_CMPL_MASK
= BIT(28),
352 OCRDMA_MCQE_AE_SHIFT
= 30,
353 OCRDMA_MCQE_AE_MASK
= BIT(30),
354 OCRDMA_MCQE_VALID_SHIFT
= 31,
355 OCRDMA_MCQE_VALID_MASK
= BIT(31)
362 u32 valid_ae_cmpl_cons
;
366 OCRDMA_AE_MCQE_QPVALID
= BIT(31),
367 OCRDMA_AE_MCQE_QPID_MASK
= 0xFFFF,
369 OCRDMA_AE_MCQE_CQVALID
= BIT(31),
370 OCRDMA_AE_MCQE_CQID_MASK
= 0xFFFF,
371 OCRDMA_AE_MCQE_VALID
= BIT(31),
372 OCRDMA_AE_MCQE_AE
= BIT(30),
373 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT
= 16,
374 OCRDMA_AE_MCQE_EVENT_TYPE_MASK
=
375 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT
,
376 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
= 8,
377 OCRDMA_AE_MCQE_EVENT_CODE_MASK
=
378 0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
380 struct ocrdma_ae_mcqe
{
388 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT
= 0,
389 OCRDMA_AE_PVID_MCQE_ENABLED_MASK
= 0xFF,
390 OCRDMA_AE_PVID_MCQE_TAG_SHIFT
= 16,
391 OCRDMA_AE_PVID_MCQE_TAG_MASK
= 0xFFFF << OCRDMA_AE_PVID_MCQE_TAG_SHIFT
394 struct ocrdma_ae_pvid_mcqe
{
402 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT
= 16,
403 OCRDMA_AE_MPA_MCQE_REQ_ID_MASK
= 0xFFFF <<
404 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT
,
406 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT
= 8,
407 OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK
= 0xFF <<
408 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT
,
409 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT
= 16,
410 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK
= 0xFF <<
411 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT
,
412 OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT
= 30,
413 OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK
= BIT(30),
414 OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT
= 31,
415 OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK
= BIT(31)
418 struct ocrdma_ae_mpa_mcqe
{
426 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT
= 0,
427 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK
= 0xFFFF,
428 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT
= 16,
429 OCRDMA_AE_QP_MCQE_QP_ID_MASK
= 0xFFFF <<
430 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT
,
432 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT
= 8,
433 OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK
= 0xFF <<
434 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT
,
435 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT
= 16,
436 OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK
= 0xFF <<
437 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT
,
438 OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT
= 30,
439 OCRDMA_AE_QP_MCQE_EVENT_AE_MASK
= BIT(30),
440 OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT
= 31,
441 OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK
= BIT(31)
444 struct ocrdma_ae_qp_mcqe
{
451 #define OCRDMA_ASYNC_RDMA_EVE_CODE 0x14
452 #define OCRDMA_ASYNC_GRP5_EVE_CODE 0x5
454 enum ocrdma_async_grp5_events
{
455 OCRDMA_ASYNC_EVENT_QOS_VALUE
= 0x01,
456 OCRDMA_ASYNC_EVENT_COS_VALUE
= 0x02,
457 OCRDMA_ASYNC_EVENT_PVID_STATE
= 0x03
460 enum OCRDMA_ASYNC_EVENT_TYPE
{
461 OCRDMA_CQ_ERROR
= 0x00,
462 OCRDMA_CQ_OVERRUN_ERROR
= 0x01,
463 OCRDMA_CQ_QPCAT_ERROR
= 0x02,
464 OCRDMA_QP_ACCESS_ERROR
= 0x03,
465 OCRDMA_QP_COMM_EST_EVENT
= 0x04,
466 OCRDMA_SQ_DRAINED_EVENT
= 0x05,
467 OCRDMA_DEVICE_FATAL_EVENT
= 0x08,
468 OCRDMA_SRQCAT_ERROR
= 0x0E,
469 OCRDMA_SRQ_LIMIT_EVENT
= 0x0F,
470 OCRDMA_QP_LAST_WQE_EVENT
= 0x10,
472 OCRDMA_MAX_ASYNC_ERRORS
475 /* mailbox command request and responses */
477 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT
= 2,
478 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK
= BIT(2),
479 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT
= 3,
480 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK
= BIT(3),
481 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT
= 8,
482 OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK
= 0xFFFFFF <<
483 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT
,
485 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT
= 16,
486 OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK
= 0xFFFF <<
487 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT
,
488 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT
= 8,
489 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK
= 0xFF <<
490 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT
,
492 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT
= 0,
493 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK
= 0xFFFF,
494 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT
= 16,
495 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK
= 0xFFFF <<
496 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT
,
498 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT
= 0,
499 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK
= 0xFFFF,
500 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT
= 16,
501 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK
= 0xFFFF <<
502 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT
,
504 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET
= 24,
505 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK
= 0xFF <<
506 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET
,
507 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET
= 16,
508 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK
= 0xFF <<
509 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET
,
510 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET
= 0,
511 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK
= 0xFFFF <<
512 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET
,
514 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET
= 16,
515 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK
= 0xFFFF <<
516 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET
,
517 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET
= 0,
518 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK
= 0xFFFF <<
519 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET
,
521 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET
= 16,
522 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK
= 0xFFFF <<
523 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET
,
524 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET
= 0,
525 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK
= 0xFFFF <<
526 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET
,
528 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET
= 0,
529 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK
= 0xFFFF <<
530 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET
,
532 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET
= 16,
533 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK
= 0xFFFF <<
534 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET
,
535 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET
= 0,
536 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK
= 0xFFFF <<
537 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET
,
539 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET
= 16,
540 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK
= 0xFFFF <<
541 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET
,
542 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET
= 0,
543 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK
= 0xFFFF <<
544 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET
,
546 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET
= 16,
547 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK
= 0xFFFF <<
548 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET
,
549 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET
= 0,
550 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK
= 0xFFFF <<
551 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET
,
554 struct ocrdma_mbx_query_config
{
555 struct ocrdma_mqe_hdr hdr
;
556 struct ocrdma_mbx_rsp rsp
;
557 u32 qp_srq_cq_ird_ord
;
558 u32 max_pd_ca_ack_delay
;
559 u32 max_write_send_sge
;
560 u32 max_ird_ord_per_qp
;
561 u32 max_shared_ird_ord
;
568 u32 max_pages_per_frmr
;
570 u32 max_mcast_qp_attach
;
571 u32 max_total_mcast_qp_attach
;
572 u32 wqe_rqe_stride_max_dpp_cqs
;
573 u32 max_srq_rpir_qps
;
574 u32 max_dpp_pds_credits
;
575 u32 max_dpp_credits_pds_per_pd
;
576 u32 max_wqes_rqes_per_q
;
577 u32 max_cq_cqes_per_cq
;
581 struct ocrdma_fw_ver_rsp
{
582 struct ocrdma_mqe_hdr hdr
;
583 struct ocrdma_mbx_rsp rsp
;
588 struct ocrdma_fw_conf_rsp
{
589 struct ocrdma_mqe_hdr hdr
;
590 struct ocrdma_mbx_rsp rsp
;
615 OCRDMA_FN_MODE_RDMA
= 0x4
619 OCRDMA_IF_TYPE_MASK
= 0xFFFF0000,
620 OCRDMA_IF_TYPE_SHIFT
= 0x10,
621 OCRDMA_PHY_TYPE_MASK
= 0x0000FFFF,
622 OCRDMA_FUTURE_DETAILS_MASK
= 0xFFFF0000,
623 OCRDMA_FUTURE_DETAILS_SHIFT
= 0x10,
624 OCRDMA_EX_PHY_DETAILS_MASK
= 0x0000FFFF,
625 OCRDMA_FSPEED_SUPP_MASK
= 0xFFFF0000,
626 OCRDMA_FSPEED_SUPP_SHIFT
= 0x10,
627 OCRDMA_ASPEED_SUPP_MASK
= 0x0000FFFF
630 struct ocrdma_get_phy_info_rsp
{
631 struct ocrdma_mqe_hdr hdr
;
632 struct ocrdma_mbx_rsp rsp
;
642 OCRDMA_PHY_SPEED_ZERO
= 0x0,
643 OCRDMA_PHY_SPEED_10MBPS
= 0x1,
644 OCRDMA_PHY_SPEED_100MBPS
= 0x2,
645 OCRDMA_PHY_SPEED_1GBPS
= 0x4,
646 OCRDMA_PHY_SPEED_10GBPS
= 0x8,
647 OCRDMA_PHY_SPEED_40GBPS
= 0x20
651 OCRDMA_PORT_NUM_MASK
= 0x3F,
652 OCRDMA_PT_MASK
= 0xC0,
653 OCRDMA_PT_SHIFT
= 0x6,
654 OCRDMA_LINK_DUP_MASK
= 0x0000FF00,
655 OCRDMA_LINK_DUP_SHIFT
= 0x8,
656 OCRDMA_PHY_PS_MASK
= 0x00FF0000,
657 OCRDMA_PHY_PS_SHIFT
= 0x10,
658 OCRDMA_PHY_PFLT_MASK
= 0xFF000000,
659 OCRDMA_PHY_PFLT_SHIFT
= 0x18,
660 OCRDMA_QOS_LNKSP_MASK
= 0xFFFF0000,
661 OCRDMA_QOS_LNKSP_SHIFT
= 0x10,
662 OCRDMA_LLST_MASK
= 0xFF,
663 OCRDMA_PLFC_MASK
= 0x00000400,
664 OCRDMA_PLFC_SHIFT
= 0x8,
665 OCRDMA_PLRFC_MASK
= 0x00000200,
666 OCRDMA_PLRFC_SHIFT
= 0x8,
667 OCRDMA_PLTFC_MASK
= 0x00000100,
668 OCRDMA_PLTFC_SHIFT
= 0x8
671 struct ocrdma_get_link_speed_rsp
{
672 struct ocrdma_mqe_hdr hdr
;
673 struct ocrdma_mbx_rsp rsp
;
675 u32 pflt_pps_ld_pnum
;
681 OCRDMA_PHYS_LINK_SPEED_ZERO
= 0x0,
682 OCRDMA_PHYS_LINK_SPEED_10MBPS
= 0x1,
683 OCRDMA_PHYS_LINK_SPEED_100MBPS
= 0x2,
684 OCRDMA_PHYS_LINK_SPEED_1GBPS
= 0x3,
685 OCRDMA_PHYS_LINK_SPEED_10GBPS
= 0x4,
686 OCRDMA_PHYS_LINK_SPEED_20GBPS
= 0x5,
687 OCRDMA_PHYS_LINK_SPEED_25GBPS
= 0x6,
688 OCRDMA_PHYS_LINK_SPEED_40GBPS
= 0x7,
689 OCRDMA_PHYS_LINK_SPEED_100GBPS
= 0x8
693 OCRDMA_CREATE_CQ_VER2
= 2,
694 OCRDMA_CREATE_CQ_VER3
= 3,
696 OCRDMA_CREATE_CQ_PAGE_CNT_MASK
= 0xFFFF,
697 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT
= 16,
698 OCRDMA_CREATE_CQ_PAGE_SIZE_MASK
= 0xFF,
700 OCRDMA_CREATE_CQ_COALESCWM_SHIFT
= 12,
701 OCRDMA_CREATE_CQ_COALESCWM_MASK
= BIT(13) | BIT(12),
702 OCRDMA_CREATE_CQ_FLAGS_NODELAY
= BIT(14),
703 OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID
= BIT(15),
705 OCRDMA_CREATE_CQ_EQ_ID_MASK
= 0xFFFF,
706 OCRDMA_CREATE_CQ_CQE_COUNT_MASK
= 0xFFFF
710 OCRDMA_CREATE_CQ_VER0
= 0,
711 OCRDMA_CREATE_CQ_DPP
= 1,
712 OCRDMA_CREATE_CQ_TYPE_SHIFT
= 24,
713 OCRDMA_CREATE_CQ_EQID_SHIFT
= 22,
715 OCRDMA_CREATE_CQ_CNT_SHIFT
= 27,
716 OCRDMA_CREATE_CQ_FLAGS_VALID
= BIT(29),
717 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE
= BIT(31),
718 OCRDMA_CREATE_CQ_DEF_FLAGS
= OCRDMA_CREATE_CQ_FLAGS_VALID
|
719 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE
|
720 OCRDMA_CREATE_CQ_FLAGS_NODELAY
723 struct ocrdma_create_cq_cmd
{
724 struct ocrdma_mbx_hdr req
;
730 struct ocrdma_pa pa
[OCRDMA_CREATE_CQ_MAX_PAGES
];
733 struct ocrdma_create_cq
{
734 struct ocrdma_mqe_hdr hdr
;
735 struct ocrdma_create_cq_cmd cmd
;
739 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT
= 0x10
743 OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK
= 0xFFFF
746 struct ocrdma_create_cq_cmd_rsp
{
747 struct ocrdma_mbx_rsp rsp
;
751 struct ocrdma_create_cq_rsp
{
752 struct ocrdma_mqe_hdr hdr
;
753 struct ocrdma_create_cq_cmd_rsp rsp
;
757 OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT
= 22,
758 OCRDMA_CREATE_MQ_CQ_ID_SHIFT
= 16,
759 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT
= 16,
760 OCRDMA_CREATE_MQ_VALID
= BIT(31),
761 OCRDMA_CREATE_MQ_ASYNC_CQ_VALID
= BIT(0)
764 struct ocrdma_create_mq_req
{
765 struct ocrdma_mbx_hdr req
;
767 u32 async_event_bitmap
;
768 u32 async_cqid_ringsize
;
770 u32 async_cqid_valid
;
772 struct ocrdma_pa pa
[8];
775 struct ocrdma_create_mq_rsp
{
776 struct ocrdma_mbx_rsp rsp
;
781 OCRDMA_DESTROY_CQ_QID_SHIFT
= 0,
782 OCRDMA_DESTROY_CQ_QID_MASK
= 0xFFFF,
783 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
= 16,
784 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK
= 0xFFFF <<
785 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
788 struct ocrdma_destroy_cq
{
789 struct ocrdma_mqe_hdr hdr
;
790 struct ocrdma_mbx_hdr req
;
792 u32 bypass_flush_qid
;
795 struct ocrdma_destroy_cq_rsp
{
796 struct ocrdma_mqe_hdr hdr
;
797 struct ocrdma_mbx_rsp rsp
;
807 OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT
= 0,
808 OCRDMA_CREATE_QP_REQ_PD_ID_MASK
= 0xFFFF,
809 OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT
= 16,
810 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT
= 19,
811 OCRDMA_CREATE_QP_REQ_QPT_SHIFT
= 29,
812 OCRDMA_CREATE_QP_REQ_QPT_MASK
= BIT(31) | BIT(30) | BIT(29),
814 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT
= 0,
815 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK
= 0xFFFF,
816 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT
= 16,
817 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK
= 0xFFFF <<
818 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT
,
820 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT
= 0,
821 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK
= 0xFFFF,
822 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT
= 16,
823 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK
= 0xFFFF <<
824 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT
,
826 OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT
= 0,
827 OCRDMA_CREATE_QP_REQ_FMR_EN_MASK
= BIT(0),
828 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT
= 1,
829 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK
= BIT(1),
830 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT
= 2,
831 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK
= BIT(2),
832 OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT
= 3,
833 OCRDMA_CREATE_QP_REQ_INB_WREN_MASK
= BIT(3),
834 OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT
= 4,
835 OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK
= BIT(4),
836 OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT
= 5,
837 OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK
= BIT(5),
838 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT
= 6,
839 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK
= BIT(6),
840 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT
= 7,
841 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK
= BIT(7),
842 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT
= 8,
843 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK
= BIT(8),
844 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT
= 16,
845 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK
= 0xFFFF <<
846 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT
,
848 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT
= 0,
849 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK
= 0xFFFF,
850 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT
= 16,
851 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK
= 0xFFFF <<
852 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT
,
854 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT
= 0,
855 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK
= 0xFFFF,
856 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT
= 16,
857 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK
= 0xFFFF <<
858 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT
,
860 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT
= 0,
861 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK
= 0xFFFF,
862 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT
= 16,
863 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK
= 0xFFFF <<
864 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT
,
866 OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT
= 0,
867 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK
= 0xFFFF,
868 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT
= 16,
869 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK
= 0xFFFF <<
870 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT
,
872 OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT
= 0,
873 OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK
= 0xFFFF,
874 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
= 16,
875 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK
= 0xFFFF <<
876 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
880 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT
= 16,
881 OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT
= 1
884 #define MAX_OCRDMA_IRD_PAGES 4
886 enum ocrdma_qp_flags
{
887 OCRDMA_QP_MW_BIND
= 1,
888 OCRDMA_QP_LKEY0
= (1 << 1),
889 OCRDMA_QP_FAST_REG
= (1 << 2),
890 OCRDMA_QP_INB_RD
= (1 << 6),
891 OCRDMA_QP_INB_WR
= (1 << 7),
894 enum ocrdma_qp_state
{
900 OCRDMA_QPS_SQ_DRAINING
= 5,
905 struct ocrdma_create_qp_req
{
906 struct ocrdma_mqe_hdr hdr
;
907 struct ocrdma_mbx_hdr req
;
911 u32 max_sge_send_write
;
912 u32 max_sge_recv_flags
;
917 struct ocrdma_pa wq_addr
[MAX_OCRDMA_QP_PAGES
];
918 struct ocrdma_pa rq_addr
[MAX_OCRDMA_QP_PAGES
];
919 u32 dpp_credits_cqid
;
921 struct ocrdma_pa ird_addr
[MAX_OCRDMA_IRD_PAGES
];
925 OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT
= 0,
926 OCRDMA_CREATE_QP_RSP_QP_ID_MASK
= 0xFFFF,
928 OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT
= 0,
929 OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK
= 0xFFFF,
930 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT
= 16,
931 OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK
= 0xFFFF <<
932 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT
,
934 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT
= 0,
935 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK
= 0xFFFF,
936 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT
= 16,
937 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK
= 0xFFFF <<
938 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT
,
940 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT
= 16,
941 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK
= 0xFFFF <<
942 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT
,
944 OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT
= 0,
945 OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK
= 0xFFFF,
946 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT
= 16,
947 OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK
= 0xFFFF <<
948 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT
,
950 OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT
= 0,
951 OCRDMA_CREATE_QP_RSP_RQ_ID_MASK
= 0xFFFF,
952 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT
= 16,
953 OCRDMA_CREATE_QP_RSP_SQ_ID_MASK
= 0xFFFF <<
954 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT
,
956 OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK
= BIT(0),
957 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT
= 1,
958 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK
= 0x7FFF <<
959 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT
,
960 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT
= 16,
961 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK
= 0xFFFF <<
962 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT
,
965 struct ocrdma_create_qp_rsp
{
966 struct ocrdma_mqe_hdr hdr
;
967 struct ocrdma_mbx_rsp rsp
;
971 u32 max_sge_send_write
;
978 struct ocrdma_destroy_qp
{
979 struct ocrdma_mqe_hdr hdr
;
980 struct ocrdma_mbx_hdr req
;
984 struct ocrdma_destroy_qp_rsp
{
985 struct ocrdma_mqe_hdr hdr
;
986 struct ocrdma_mbx_rsp rsp
;
990 OCRDMA_MODIFY_QP_ID_SHIFT
= 0,
991 OCRDMA_MODIFY_QP_ID_MASK
= 0xFFFF,
993 OCRDMA_QP_PARA_QPS_VALID
= BIT(0),
994 OCRDMA_QP_PARA_SQD_ASYNC_VALID
= BIT(1),
995 OCRDMA_QP_PARA_PKEY_VALID
= BIT(2),
996 OCRDMA_QP_PARA_QKEY_VALID
= BIT(3),
997 OCRDMA_QP_PARA_PMTU_VALID
= BIT(4),
998 OCRDMA_QP_PARA_ACK_TO_VALID
= BIT(5),
999 OCRDMA_QP_PARA_RETRY_CNT_VALID
= BIT(6),
1000 OCRDMA_QP_PARA_RRC_VALID
= BIT(7),
1001 OCRDMA_QP_PARA_RQPSN_VALID
= BIT(8),
1002 OCRDMA_QP_PARA_MAX_IRD_VALID
= BIT(9),
1003 OCRDMA_QP_PARA_MAX_ORD_VALID
= BIT(10),
1004 OCRDMA_QP_PARA_RNT_VALID
= BIT(11),
1005 OCRDMA_QP_PARA_SQPSN_VALID
= BIT(12),
1006 OCRDMA_QP_PARA_DST_QPN_VALID
= BIT(13),
1007 OCRDMA_QP_PARA_MAX_WQE_VALID
= BIT(14),
1008 OCRDMA_QP_PARA_MAX_RQE_VALID
= BIT(15),
1009 OCRDMA_QP_PARA_SGE_SEND_VALID
= BIT(16),
1010 OCRDMA_QP_PARA_SGE_RECV_VALID
= BIT(17),
1011 OCRDMA_QP_PARA_SGE_WR_VALID
= BIT(18),
1012 OCRDMA_QP_PARA_INB_RDEN_VALID
= BIT(19),
1013 OCRDMA_QP_PARA_INB_WREN_VALID
= BIT(20),
1014 OCRDMA_QP_PARA_FLOW_LBL_VALID
= BIT(21),
1015 OCRDMA_QP_PARA_BIND_EN_VALID
= BIT(22),
1016 OCRDMA_QP_PARA_ZLKEY_EN_VALID
= BIT(23),
1017 OCRDMA_QP_PARA_FMR_EN_VALID
= BIT(24),
1018 OCRDMA_QP_PARA_INBAT_EN_VALID
= BIT(25),
1019 OCRDMA_QP_PARA_VLAN_EN_VALID
= BIT(26),
1021 OCRDMA_MODIFY_QP_FLAGS_RD
= BIT(0),
1022 OCRDMA_MODIFY_QP_FLAGS_WR
= BIT(1),
1023 OCRDMA_MODIFY_QP_FLAGS_SEND
= BIT(2),
1024 OCRDMA_MODIFY_QP_FLAGS_ATOMIC
= BIT(3)
1028 OCRDMA_QP_PARAMS_SRQ_ID_SHIFT
= 0,
1029 OCRDMA_QP_PARAMS_SRQ_ID_MASK
= 0xFFFF,
1031 OCRDMA_QP_PARAMS_MAX_RQE_SHIFT
= 0,
1032 OCRDMA_QP_PARAMS_MAX_RQE_MASK
= 0xFFFF,
1033 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT
= 16,
1034 OCRDMA_QP_PARAMS_MAX_WQE_MASK
= 0xFFFF <<
1035 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT
,
1037 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT
= 0,
1038 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK
= 0xFFFF,
1039 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT
= 16,
1040 OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK
= 0xFFFF <<
1041 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT
,
1043 OCRDMA_QP_PARAMS_FLAGS_FMR_EN
= BIT(0),
1044 OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN
= BIT(1),
1045 OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN
= BIT(2),
1046 OCRDMA_QP_PARAMS_FLAGS_INBWR_EN
= BIT(3),
1047 OCRDMA_QP_PARAMS_FLAGS_INBRD_EN
= BIT(4),
1048 OCRDMA_QP_PARAMS_STATE_SHIFT
= 5,
1049 OCRDMA_QP_PARAMS_STATE_MASK
= BIT(5) | BIT(6) | BIT(7),
1050 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC
= BIT(8),
1051 OCRDMA_QP_PARAMS_FLAGS_INB_ATEN
= BIT(9),
1052 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT
= 16,
1053 OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK
= 0xFFFF <<
1054 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT
,
1056 OCRDMA_QP_PARAMS_MAX_IRD_SHIFT
= 0,
1057 OCRDMA_QP_PARAMS_MAX_IRD_MASK
= 0xFFFF,
1058 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT
= 16,
1059 OCRDMA_QP_PARAMS_MAX_ORD_MASK
= 0xFFFF <<
1060 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT
,
1062 OCRDMA_QP_PARAMS_RQ_CQID_SHIFT
= 0,
1063 OCRDMA_QP_PARAMS_RQ_CQID_MASK
= 0xFFFF,
1064 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT
= 16,
1065 OCRDMA_QP_PARAMS_WQ_CQID_MASK
= 0xFFFF <<
1066 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT
,
1068 OCRDMA_QP_PARAMS_RQ_PSN_SHIFT
= 0,
1069 OCRDMA_QP_PARAMS_RQ_PSN_MASK
= 0xFFFFFF,
1070 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT
= 24,
1071 OCRDMA_QP_PARAMS_HOP_LMT_MASK
= 0xFF <<
1072 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT
,
1074 OCRDMA_QP_PARAMS_SQ_PSN_SHIFT
= 0,
1075 OCRDMA_QP_PARAMS_SQ_PSN_MASK
= 0xFFFFFF,
1076 OCRDMA_QP_PARAMS_TCLASS_SHIFT
= 24,
1077 OCRDMA_QP_PARAMS_TCLASS_MASK
= 0xFF <<
1078 OCRDMA_QP_PARAMS_TCLASS_SHIFT
,
1080 OCRDMA_QP_PARAMS_DEST_QPN_SHIFT
= 0,
1081 OCRDMA_QP_PARAMS_DEST_QPN_MASK
= 0xFFFFFF,
1082 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT
= 24,
1083 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK
= 0x7 <<
1084 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT
,
1085 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT
= 27,
1086 OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK
= 0x1F <<
1087 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT
,
1089 OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT
= 0,
1090 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK
= 0xFFFF,
1091 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT
= 18,
1092 OCRDMA_QP_PARAMS_PATH_MTU_MASK
= 0x3FFF <<
1093 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT
,
1095 OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT
= 0,
1096 OCRDMA_QP_PARAMS_FLOW_LABEL_MASK
= 0xFFFFF,
1097 OCRDMA_QP_PARAMS_SL_SHIFT
= 20,
1098 OCRDMA_QP_PARAMS_SL_MASK
= 0xF <<
1099 OCRDMA_QP_PARAMS_SL_SHIFT
,
1100 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT
= 24,
1101 OCRDMA_QP_PARAMS_RETRY_CNT_MASK
= 0x7 <<
1102 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT
,
1103 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT
= 27,
1104 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK
= 0x1F <<
1105 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT
,
1107 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT
= 0,
1108 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK
= 0xFFFF,
1109 OCRDMA_QP_PARAMS_VLAN_SHIFT
= 16,
1110 OCRDMA_QP_PARAMS_VLAN_MASK
= 0xFFFF <<
1111 OCRDMA_QP_PARAMS_VLAN_SHIFT
1114 struct ocrdma_qp_params
{
1117 u32 max_sge_send_write
;
1118 u32 max_sge_recv_flags
;
1123 u32 ack_to_rnr_rtc_dest_qpn
;
1124 u32 path_mtu_pkey_indx
;
1129 u32 vlan_dmac_b4_to_b5
;
1134 struct ocrdma_modify_qp
{
1135 struct ocrdma_mqe_hdr hdr
;
1136 struct ocrdma_mbx_hdr req
;
1138 struct ocrdma_qp_params params
;
1141 u32 num_outstanding_atomic_rd
;
1145 OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT
= 0,
1146 OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK
= 0xFFFF,
1147 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT
= 16,
1148 OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK
= 0xFFFF <<
1149 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT
,
1151 OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT
= 0,
1152 OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK
= 0xFFFF,
1153 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
= 16,
1154 OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK
= 0xFFFF <<
1155 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
1158 struct ocrdma_modify_qp_rsp
{
1159 struct ocrdma_mqe_hdr hdr
;
1160 struct ocrdma_mbx_rsp rsp
;
1166 struct ocrdma_query_qp
{
1167 struct ocrdma_mqe_hdr hdr
;
1168 struct ocrdma_mbx_hdr req
;
1170 #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0
1171 #define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF
1175 struct ocrdma_query_qp_rsp
{
1176 struct ocrdma_mqe_hdr hdr
;
1177 struct ocrdma_mbx_rsp rsp
;
1178 struct ocrdma_qp_params params
;
1179 u32 dpp_credits_cqid
;
1184 OCRDMA_CREATE_SRQ_PD_ID_SHIFT
= 0,
1185 OCRDMA_CREATE_SRQ_PD_ID_MASK
= 0xFFFF,
1186 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT
= 16,
1187 OCRDMA_CREATE_SRQ_PG_SZ_MASK
= 0x3 <<
1188 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT
,
1190 OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT
= 0,
1191 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT
= 16,
1192 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK
= 0xFFFF <<
1193 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT
,
1195 OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT
= 0,
1196 OCRDMA_CREATE_SRQ_RQE_SIZE_MASK
= 0xFFFF,
1197 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
= 16,
1198 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK
= 0xFFFF <<
1199 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
1202 struct ocrdma_create_srq
{
1203 struct ocrdma_mqe_hdr hdr
;
1204 struct ocrdma_mbx_hdr req
;
1209 struct ocrdma_pa rq_addr
[MAX_OCRDMA_SRQ_PAGES
];
1213 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT
= 0,
1214 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK
= 0xFFFFFF,
1216 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT
= 0,
1217 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK
= 0xFFFF,
1218 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
= 16,
1219 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK
= 0xFFFF <<
1220 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
1223 struct ocrdma_create_srq_rsp
{
1224 struct ocrdma_mqe_hdr hdr
;
1225 struct ocrdma_mbx_rsp rsp
;
1228 u32 max_sge_rqe_allocated
;
1232 OCRDMA_MODIFY_SRQ_ID_SHIFT
= 0,
1233 OCRDMA_MODIFY_SRQ_ID_MASK
= 0xFFFFFF,
1235 OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT
= 0,
1236 OCRDMA_MODIFY_SRQ_MAX_RQE_MASK
= 0xFFFF,
1237 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
= 16,
1238 OCRDMA_MODIFY_SRQ__LIMIT_MASK
= 0xFFFF <<
1239 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
1242 struct ocrdma_modify_srq
{
1243 struct ocrdma_mqe_hdr hdr
;
1244 struct ocrdma_mbx_rsp rep
;
1251 OCRDMA_QUERY_SRQ_ID_SHIFT
= 0,
1252 OCRDMA_QUERY_SRQ_ID_MASK
= 0xFFFFFF
1255 struct ocrdma_query_srq
{
1256 struct ocrdma_mqe_hdr hdr
;
1257 struct ocrdma_mbx_rsp req
;
1263 OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT
= 0,
1264 OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK
= 0xFFFF,
1265 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT
= 16,
1266 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK
= 0xFFFF <<
1267 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT
,
1269 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT
= 0,
1270 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK
= 0xFFFF,
1271 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
= 16,
1272 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK
= 0xFFFF <<
1273 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
1276 struct ocrdma_query_srq_rsp
{
1277 struct ocrdma_mqe_hdr hdr
;
1278 struct ocrdma_mbx_rsp req
;
1281 u32 srq_lmt_max_sge
;
1285 OCRDMA_DESTROY_SRQ_ID_SHIFT
= 0,
1286 OCRDMA_DESTROY_SRQ_ID_MASK
= 0xFFFFFF
1289 struct ocrdma_destroy_srq
{
1290 struct ocrdma_mqe_hdr hdr
;
1291 struct ocrdma_mbx_rsp req
;
1297 OCRDMA_ALLOC_PD_ENABLE_DPP
= BIT(16),
1298 OCRDMA_DPP_PAGE_SIZE
= 4096
1301 struct ocrdma_alloc_pd
{
1302 struct ocrdma_mqe_hdr hdr
;
1303 struct ocrdma_mbx_hdr req
;
1304 u32 enable_dpp_rsvd
;
1308 OCRDMA_ALLOC_PD_RSP_DPP
= BIT(16),
1309 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT
= 20,
1310 OCRDMA_ALLOC_PD_RSP_PDID_MASK
= 0xFFFF,
1313 struct ocrdma_alloc_pd_rsp
{
1314 struct ocrdma_mqe_hdr hdr
;
1315 struct ocrdma_mbx_rsp rsp
;
1319 struct ocrdma_dealloc_pd
{
1320 struct ocrdma_mqe_hdr hdr
;
1321 struct ocrdma_mbx_hdr req
;
1325 struct ocrdma_dealloc_pd_rsp
{
1326 struct ocrdma_mqe_hdr hdr
;
1327 struct ocrdma_mbx_rsp rsp
;
1330 struct ocrdma_alloc_pd_range
{
1331 struct ocrdma_mqe_hdr hdr
;
1332 struct ocrdma_mbx_hdr req
;
1333 u32 enable_dpp_rsvd
;
1337 struct ocrdma_alloc_pd_range_rsp
{
1338 struct ocrdma_mqe_hdr hdr
;
1339 struct ocrdma_mbx_rsp rsp
;
1345 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK
= 0xFFFF,
1348 struct ocrdma_dealloc_pd_range
{
1349 struct ocrdma_mqe_hdr hdr
;
1350 struct ocrdma_mbx_hdr req
;
1355 struct ocrdma_dealloc_pd_range_rsp
{
1356 struct ocrdma_mqe_hdr hdr
;
1357 struct ocrdma_mbx_hdr req
;
1362 OCRDMA_ADDR_CHECK_ENABLE
= 1,
1363 OCRDMA_ADDR_CHECK_DISABLE
= 0
1367 OCRDMA_ALLOC_LKEY_PD_ID_SHIFT
= 0,
1368 OCRDMA_ALLOC_LKEY_PD_ID_MASK
= 0xFFFF,
1370 OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT
= 0,
1371 OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK
= BIT(0),
1372 OCRDMA_ALLOC_LKEY_FMR_SHIFT
= 1,
1373 OCRDMA_ALLOC_LKEY_FMR_MASK
= BIT(1),
1374 OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT
= 2,
1375 OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK
= BIT(2),
1376 OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT
= 3,
1377 OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK
= BIT(3),
1378 OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT
= 4,
1379 OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK
= BIT(4),
1380 OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT
= 5,
1381 OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK
= BIT(5),
1382 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK
= BIT(6),
1383 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT
= 6,
1384 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
= 16,
1385 OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK
= 0xFFFF <<
1386 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
1389 struct ocrdma_alloc_lkey
{
1390 struct ocrdma_mqe_hdr hdr
;
1391 struct ocrdma_mbx_hdr req
;
1397 struct ocrdma_alloc_lkey_rsp
{
1398 struct ocrdma_mqe_hdr hdr
;
1399 struct ocrdma_mbx_rsp rsp
;
1405 struct ocrdma_dealloc_lkey
{
1406 struct ocrdma_mqe_hdr hdr
;
1407 struct ocrdma_mbx_hdr req
;
1413 struct ocrdma_dealloc_lkey_rsp
{
1414 struct ocrdma_mqe_hdr hdr
;
1415 struct ocrdma_mbx_rsp rsp
;
1418 #define MAX_OCRDMA_NSMR_PBL (u32)22
1419 #define MAX_OCRDMA_PBL_SIZE 65536
1420 #define MAX_OCRDMA_PBL_PER_LKEY 32767
1423 OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT
= 0,
1424 OCRDMA_REG_NSMR_LRKEY_INDEX_MASK
= 0xFFFFFF,
1425 OCRDMA_REG_NSMR_LRKEY_SHIFT
= 24,
1426 OCRDMA_REG_NSMR_LRKEY_MASK
= 0xFF <<
1427 OCRDMA_REG_NSMR_LRKEY_SHIFT
,
1429 OCRDMA_REG_NSMR_PD_ID_SHIFT
= 0,
1430 OCRDMA_REG_NSMR_PD_ID_MASK
= 0xFFFF,
1431 OCRDMA_REG_NSMR_NUM_PBL_SHIFT
= 16,
1432 OCRDMA_REG_NSMR_NUM_PBL_MASK
= 0xFFFF <<
1433 OCRDMA_REG_NSMR_NUM_PBL_SHIFT
,
1435 OCRDMA_REG_NSMR_PBE_SIZE_SHIFT
= 0,
1436 OCRDMA_REG_NSMR_PBE_SIZE_MASK
= 0xFFFF,
1437 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT
= 16,
1438 OCRDMA_REG_NSMR_HPAGE_SIZE_MASK
= 0xFF <<
1439 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT
,
1440 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT
= 24,
1441 OCRDMA_REG_NSMR_BIND_MEMWIN_MASK
= BIT(24),
1442 OCRDMA_REG_NSMR_ZB_SHIFT
= 25,
1443 OCRDMA_REG_NSMR_ZB_SHIFT_MASK
= BIT(25),
1444 OCRDMA_REG_NSMR_REMOTE_INV_SHIFT
= 26,
1445 OCRDMA_REG_NSMR_REMOTE_INV_MASK
= BIT(26),
1446 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT
= 27,
1447 OCRDMA_REG_NSMR_REMOTE_WR_MASK
= BIT(27),
1448 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT
= 28,
1449 OCRDMA_REG_NSMR_REMOTE_RD_MASK
= BIT(28),
1450 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT
= 29,
1451 OCRDMA_REG_NSMR_LOCAL_WR_MASK
= BIT(29),
1452 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT
= 30,
1453 OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK
= BIT(30),
1454 OCRDMA_REG_NSMR_LAST_SHIFT
= 31,
1455 OCRDMA_REG_NSMR_LAST_MASK
= BIT(31)
1458 struct ocrdma_reg_nsmr
{
1459 struct ocrdma_mqe_hdr hdr
;
1460 struct ocrdma_mbx_hdr cmd
;
1464 u32 flags_hpage_pbe_sz
;
1471 struct ocrdma_pa pbl
[MAX_OCRDMA_NSMR_PBL
];
1475 OCRDMA_REG_NSMR_CONT_PBL_SHIFT
= 0,
1476 OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK
= 0xFFFF,
1477 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT
= 16,
1478 OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK
= 0xFFFF <<
1479 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT
,
1481 OCRDMA_REG_NSMR_CONT_LAST_SHIFT
= 31,
1482 OCRDMA_REG_NSMR_CONT_LAST_MASK
= BIT(31)
1485 struct ocrdma_reg_nsmr_cont
{
1486 struct ocrdma_mqe_hdr hdr
;
1487 struct ocrdma_mbx_hdr cmd
;
1493 struct ocrdma_pa pbl
[MAX_OCRDMA_NSMR_PBL
];
1502 OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT
= 16,
1503 OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK
= 0xFFFF0000
1505 struct ocrdma_reg_nsmr_rsp
{
1506 struct ocrdma_mqe_hdr hdr
;
1507 struct ocrdma_mbx_rsp rsp
;
1514 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT
= 0,
1515 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK
= 0xFFFFFF,
1516 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT
= 24,
1517 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK
= 0xFF <<
1518 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT
,
1520 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
= 16,
1521 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK
= 0xFFFF <<
1522 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
1525 struct ocrdma_reg_nsmr_cont_rsp
{
1526 struct ocrdma_mqe_hdr hdr
;
1527 struct ocrdma_mbx_rsp rsp
;
1529 u32 lrkey_key_index
;
1534 OCRDMA_ALLOC_MW_PD_ID_SHIFT
= 0,
1535 OCRDMA_ALLOC_MW_PD_ID_MASK
= 0xFFFF
1538 struct ocrdma_alloc_mw
{
1539 struct ocrdma_mqe_hdr hdr
;
1540 struct ocrdma_mbx_hdr req
;
1546 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT
= 0,
1547 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK
= 0xFFFFFF
1550 struct ocrdma_alloc_mw_rsp
{
1551 struct ocrdma_mqe_hdr hdr
;
1552 struct ocrdma_mbx_rsp rsp
;
1557 struct ocrdma_attach_mcast
{
1558 struct ocrdma_mqe_hdr hdr
;
1559 struct ocrdma_mbx_hdr req
;
1563 u32 vlan_mac_b4_to_b5
;
1566 struct ocrdma_attach_mcast_rsp
{
1567 struct ocrdma_mqe_hdr hdr
;
1568 struct ocrdma_mbx_rsp rsp
;
1571 struct ocrdma_detach_mcast
{
1572 struct ocrdma_mqe_hdr hdr
;
1573 struct ocrdma_mbx_hdr req
;
1577 u32 vlan_mac_b4_to_b5
;
1580 struct ocrdma_detach_mcast_rsp
{
1581 struct ocrdma_mqe_hdr hdr
;
1582 struct ocrdma_mbx_rsp rsp
;
1586 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT
= 19,
1587 OCRDMA_CREATE_AH_NUM_PAGES_MASK
= 0xF <<
1588 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT
,
1590 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT
= 16,
1591 OCRDMA_CREATE_AH_PAGE_SIZE_MASK
= 0x7 <<
1592 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT
,
1594 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT
= 23,
1595 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK
= 0x1FF <<
1596 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT
,
1599 #define OCRDMA_AH_TBL_PAGES 8
1601 struct ocrdma_create_ah_tbl
{
1602 struct ocrdma_mqe_hdr hdr
;
1603 struct ocrdma_mbx_hdr req
;
1606 struct ocrdma_pa tbl_addr
[8];
1609 struct ocrdma_create_ah_tbl_rsp
{
1610 struct ocrdma_mqe_hdr hdr
;
1611 struct ocrdma_mbx_rsp rsp
;
1615 struct ocrdma_delete_ah_tbl
{
1616 struct ocrdma_mqe_hdr hdr
;
1617 struct ocrdma_mbx_hdr req
;
1621 struct ocrdma_delete_ah_tbl_rsp
{
1622 struct ocrdma_mqe_hdr hdr
;
1623 struct ocrdma_mbx_rsp rsp
;
1627 OCRDMA_EQE_VALID_SHIFT
= 0,
1628 OCRDMA_EQE_VALID_MASK
= BIT(0),
1629 OCRDMA_EQE_MAJOR_CODE_MASK
= 0x0E,
1630 OCRDMA_EQE_MAJOR_CODE_SHIFT
= 0x01,
1631 OCRDMA_EQE_FOR_CQE_MASK
= 0xFFFE,
1632 OCRDMA_EQE_RESOURCE_ID_SHIFT
= 16,
1633 OCRDMA_EQE_RESOURCE_ID_MASK
= 0xFFFF <<
1634 OCRDMA_EQE_RESOURCE_ID_SHIFT
,
1638 OCRDMA_MAJOR_CODE_COMPLETION
= 0x00,
1639 OCRDMA_MAJOR_CODE_SENTINAL
= 0x01
1646 enum OCRDMA_CQE_STATUS
{
1647 OCRDMA_CQE_SUCCESS
= 0,
1648 OCRDMA_CQE_LOC_LEN_ERR
,
1649 OCRDMA_CQE_LOC_QP_OP_ERR
,
1650 OCRDMA_CQE_LOC_EEC_OP_ERR
,
1651 OCRDMA_CQE_LOC_PROT_ERR
,
1652 OCRDMA_CQE_WR_FLUSH_ERR
,
1653 OCRDMA_CQE_MW_BIND_ERR
,
1654 OCRDMA_CQE_BAD_RESP_ERR
,
1655 OCRDMA_CQE_LOC_ACCESS_ERR
,
1656 OCRDMA_CQE_REM_INV_REQ_ERR
,
1657 OCRDMA_CQE_REM_ACCESS_ERR
,
1658 OCRDMA_CQE_REM_OP_ERR
,
1659 OCRDMA_CQE_RETRY_EXC_ERR
,
1660 OCRDMA_CQE_RNR_RETRY_EXC_ERR
,
1661 OCRDMA_CQE_LOC_RDD_VIOL_ERR
,
1662 OCRDMA_CQE_REM_INV_RD_REQ_ERR
,
1663 OCRDMA_CQE_REM_ABORT_ERR
,
1664 OCRDMA_CQE_INV_EECN_ERR
,
1665 OCRDMA_CQE_INV_EEC_STATE_ERR
,
1666 OCRDMA_CQE_FATAL_ERR
,
1667 OCRDMA_CQE_RESP_TIMEOUT_ERR
,
1668 OCRDMA_CQE_GENERAL_ERR
,
1675 OCRDMA_CQE_WQEIDX_SHIFT
= 0,
1676 OCRDMA_CQE_WQEIDX_MASK
= 0xFFFF,
1679 OCRDMA_CQE_UD_XFER_LEN_SHIFT
= 16,
1680 OCRDMA_CQE_PKEY_SHIFT
= 0,
1681 OCRDMA_CQE_PKEY_MASK
= 0xFFFF,
1684 OCRDMA_CQE_QPN_SHIFT
= 0,
1685 OCRDMA_CQE_QPN_MASK
= 0x0000FFFF,
1687 OCRDMA_CQE_BUFTAG_SHIFT
= 16,
1688 OCRDMA_CQE_BUFTAG_MASK
= 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT
,
1691 OCRDMA_CQE_UD_STATUS_SHIFT
= 24,
1692 OCRDMA_CQE_UD_STATUS_MASK
= 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT
,
1693 OCRDMA_CQE_STATUS_SHIFT
= 16,
1694 OCRDMA_CQE_STATUS_MASK
= 0xFF << OCRDMA_CQE_STATUS_SHIFT
,
1695 OCRDMA_CQE_VALID
= BIT(31),
1696 OCRDMA_CQE_INVALIDATE
= BIT(30),
1697 OCRDMA_CQE_QTYPE
= BIT(29),
1698 OCRDMA_CQE_IMM
= BIT(28),
1699 OCRDMA_CQE_WRITE_IMM
= BIT(27),
1700 OCRDMA_CQE_QTYPE_SQ
= 0,
1701 OCRDMA_CQE_QTYPE_RQ
= 1,
1702 OCRDMA_CQE_SRCQP_MASK
= 0xFFFFFF
1729 u32 flags_status_srcqpn
; /* w3 */
1740 OCRDMA_FLAG_SIG
= 0x1,
1741 OCRDMA_FLAG_INV
= 0x2,
1742 OCRDMA_FLAG_FENCE_L
= 0x4,
1743 OCRDMA_FLAG_FENCE_R
= 0x8,
1744 OCRDMA_FLAG_SOLICIT
= 0x10,
1745 OCRDMA_FLAG_IMM
= 0x20,
1746 OCRDMA_FLAG_AH_VLAN_PR
= 0x40,
1749 OCRDMA_LKEY_FLAG_LOCAL_WR
= 0x1,
1750 OCRDMA_LKEY_FLAG_REMOTE_RD
= 0x2,
1751 OCRDMA_LKEY_FLAG_REMOTE_WR
= 0x4,
1752 OCRDMA_LKEY_FLAG_VATO
= 0x8,
1755 enum OCRDMA_WQE_OPCODE
{
1756 OCRDMA_WRITE
= 0x06,
1758 OCRDMA_RESV0
= 0x02,
1760 OCRDMA_CMP_SWP
= 0x14,
1761 OCRDMA_BIND_MW
= 0x10,
1762 OCRDMA_FR_MR
= 0x11,
1763 OCRDMA_RESV1
= 0x0A,
1764 OCRDMA_LKEY_INV
= 0x15,
1765 OCRDMA_FETCH_ADD
= 0x13,
1766 OCRDMA_POST_RQ
= 0x12
1770 OCRDMA_TYPE_INLINE
= 0x0,
1771 OCRDMA_TYPE_LKEY
= 0x1,
1775 OCRDMA_WQE_OPCODE_SHIFT
= 0,
1776 OCRDMA_WQE_OPCODE_MASK
= 0x0000001F,
1777 OCRDMA_WQE_FLAGS_SHIFT
= 5,
1778 OCRDMA_WQE_TYPE_SHIFT
= 16,
1779 OCRDMA_WQE_TYPE_MASK
= 0x00030000,
1780 OCRDMA_WQE_SIZE_SHIFT
= 18,
1781 OCRDMA_WQE_SIZE_MASK
= 0xFF,
1782 OCRDMA_WQE_NXT_WQE_SIZE_SHIFT
= 25,
1784 OCRDMA_WQE_LKEY_FLAGS_SHIFT
= 0,
1785 OCRDMA_WQE_LKEY_FLAGS_MASK
= 0xF
1788 /* header WQE for all the SQ and RQ operations */
1789 struct ocrdma_hdr_wqe
{
1793 u32 rsvd_lkey_flags
;
1802 struct ocrdma_ewqe_ud_hdr
{
1809 /* extended wqe followed by hdr_wqe for Fast Memory register */
1810 struct ocrdma_ewqe_fr
{
1821 struct ocrdma_eth_basic
{
1827 struct ocrdma_eth_vlan
{
1832 #define OCRDMA_ROCE_ETH_TYPE 0x8915
1833 __be16 roce_eth_type
;
1838 __be32 pdid_hoplimit
;
1844 #define OCRDMA_AV_VALID BIT(7)
1845 #define OCRDMA_AV_VLAN_VALID BIT(1)
1848 struct ocrdma_eth_vlan eth_hdr
;
1849 struct ocrdma_grh grh
;
1853 struct ocrdma_rsrc_stats
{
1867 u32 r64K_to_2M_nsmr
;
1868 u32 r2M_to_44M_nsmr
;
1869 u32 r44M_to_1G_nsmr
;
1871 u32 nsmr_count_4G_to_32G
;
1872 u32 r32G_to_64G_nsmr
;
1873 u32 r64G_to_128G_nsmr
;
1874 u32 r128G_to_higher_nsmr
;
1884 struct ocrdma_db_err_stats
{
1885 u32 sq_doorbell_errors
;
1886 u32 cq_doorbell_errors
;
1887 u32 rq_srq_doorbell_errors
;
1888 u32 cq_overflow_errors
;
1892 struct ocrdma_wqe_stats
{
1893 u32 large_send_rc_wqes_lo
;
1894 u32 large_send_rc_wqes_hi
;
1895 u32 large_write_rc_wqes_lo
;
1896 u32 large_write_rc_wqes_hi
;
1902 u32 mw_bind_wqes_lo
;
1903 u32 mw_bind_wqes_hi
;
1904 u32 invalidate_wqes_lo
;
1905 u32 invalidate_wqes_hi
;
1911 struct ocrdma_tx_stats
{
1918 u32 read_rsp_pkts_lo
;
1919 u32 read_rsp_pkts_hi
;
1926 u32 read_req_bytes_lo
;
1927 u32 read_req_bytes_hi
;
1928 u32 read_rsp_bytes_lo
;
1929 u32 read_rsp_bytes_hi
;
1935 struct ocrdma_tx_qp_err_stats
{
1936 u32 local_length_errors
;
1937 u32 local_protection_errors
;
1938 u32 local_qp_operation_errors
;
1939 u32 retry_count_exceeded_errors
;
1940 u32 rnr_retry_count_exceeded_errors
;
1944 struct ocrdma_rx_stats
{
1945 u32 roce_frame_bytes_lo
;
1946 u32 roce_frame_bytes_hi
;
1947 u32 roce_frame_icrc_drops
;
1948 u32 roce_frame_payload_len_drops
;
1951 u32 psn_error_request_packets
;
1952 u32 psn_error_resp_packets
;
1953 u32 rnr_nak_timeouts
;
1954 u32 rnr_nak_receives
;
1955 u32 roce_frame_rxmt_drops
;
1956 u32 nak_count_psn_sequence_errors
;
1957 u32 rc_drop_count_lookup_errors
;
1965 struct ocrdma_rx_qp_err_stats
{
1966 u32 nak_invalid_requst_errors
;
1967 u32 nak_remote_operation_errors
;
1968 u32 nak_count_remote_access_errors
;
1969 u32 local_length_errors
;
1970 u32 local_protection_errors
;
1971 u32 local_qp_operation_errors
;
1975 struct ocrdma_tx_dbg_stats
{
1979 struct ocrdma_rx_dbg_stats
{
1983 struct ocrdma_rdma_stats_req
{
1984 struct ocrdma_mbx_hdr hdr
;
1989 struct ocrdma_rdma_stats_resp
{
1990 struct ocrdma_mbx_hdr hdr
;
1991 struct ocrdma_rsrc_stats act_rsrc_stats
;
1992 struct ocrdma_rsrc_stats th_rsrc_stats
;
1993 struct ocrdma_db_err_stats db_err_stats
;
1994 struct ocrdma_wqe_stats wqe_stats
;
1995 struct ocrdma_tx_stats tx_stats
;
1996 struct ocrdma_tx_qp_err_stats tx_qp_err_stats
;
1997 struct ocrdma_rx_stats rx_stats
;
1998 struct ocrdma_rx_qp_err_stats rx_qp_err_stats
;
1999 struct ocrdma_tx_dbg_stats tx_dbg_stats
;
2000 struct ocrdma_rx_dbg_stats rx_dbg_stats
;
2004 OCRDMA_HBA_ATTRB_EPROM_VER_LO_MASK
= 0xFF,
2005 OCRDMA_HBA_ATTRB_EPROM_VER_HI_MASK
= 0xFF00,
2006 OCRDMA_HBA_ATTRB_EPROM_VER_HI_SHIFT
= 0x08,
2007 OCRDMA_HBA_ATTRB_CDBLEN_MASK
= 0xFFFF,
2008 OCRDMA_HBA_ATTRB_ASIC_REV_MASK
= 0xFF0000,
2009 OCRDMA_HBA_ATTRB_ASIC_REV_SHIFT
= 0x10,
2010 OCRDMA_HBA_ATTRB_GUID0_MASK
= 0xFF000000,
2011 OCRDMA_HBA_ATTRB_GUID0_SHIFT
= 0x18,
2012 OCRDMA_HBA_ATTRB_GUID13_MASK
= 0xFF,
2013 OCRDMA_HBA_ATTRB_GUID14_MASK
= 0xFF00,
2014 OCRDMA_HBA_ATTRB_GUID14_SHIFT
= 0x08,
2015 OCRDMA_HBA_ATTRB_GUID15_MASK
= 0xFF0000,
2016 OCRDMA_HBA_ATTRB_GUID15_SHIFT
= 0x10,
2017 OCRDMA_HBA_ATTRB_PCNT_MASK
= 0xFF000000,
2018 OCRDMA_HBA_ATTRB_PCNT_SHIFT
= 0x18,
2019 OCRDMA_HBA_ATTRB_LDTOUT_MASK
= 0xFFFF,
2020 OCRDMA_HBA_ATTRB_ISCSI_VER_MASK
= 0xFF0000,
2021 OCRDMA_HBA_ATTRB_ISCSI_VER_SHIFT
= 0x10,
2022 OCRDMA_HBA_ATTRB_MFUNC_DEV_MASK
= 0xFF000000,
2023 OCRDMA_HBA_ATTRB_MFUNC_DEV_SHIFT
= 0x18,
2024 OCRDMA_HBA_ATTRB_CV_MASK
= 0xFF,
2025 OCRDMA_HBA_ATTRB_HBA_ST_MASK
= 0xFF00,
2026 OCRDMA_HBA_ATTRB_HBA_ST_SHIFT
= 0x08,
2027 OCRDMA_HBA_ATTRB_MAX_DOMS_MASK
= 0xFF0000,
2028 OCRDMA_HBA_ATTRB_MAX_DOMS_SHIFT
= 0x10,
2029 OCRDMA_HBA_ATTRB_PTNUM_MASK
= 0x3F000000,
2030 OCRDMA_HBA_ATTRB_PTNUM_SHIFT
= 0x18,
2031 OCRDMA_HBA_ATTRB_PT_MASK
= 0xC0000000,
2032 OCRDMA_HBA_ATTRB_PT_SHIFT
= 0x1E,
2033 OCRDMA_HBA_ATTRB_ISCSI_FET_MASK
= 0xFF,
2034 OCRDMA_HBA_ATTRB_ASIC_GEN_MASK
= 0xFF00,
2035 OCRDMA_HBA_ATTRB_ASIC_GEN_SHIFT
= 0x08,
2036 OCRDMA_HBA_ATTRB_PCI_VID_MASK
= 0xFFFF,
2037 OCRDMA_HBA_ATTRB_PCI_DID_MASK
= 0xFFFF0000,
2038 OCRDMA_HBA_ATTRB_PCI_DID_SHIFT
= 0x10,
2039 OCRDMA_HBA_ATTRB_PCI_SVID_MASK
= 0xFFFF,
2040 OCRDMA_HBA_ATTRB_PCI_SSID_MASK
= 0xFFFF0000,
2041 OCRDMA_HBA_ATTRB_PCI_SSID_SHIFT
= 0x10,
2042 OCRDMA_HBA_ATTRB_PCI_BUSNUM_MASK
= 0xFF,
2043 OCRDMA_HBA_ATTRB_PCI_DEVNUM_MASK
= 0xFF00,
2044 OCRDMA_HBA_ATTRB_PCI_DEVNUM_SHIFT
= 0x08,
2045 OCRDMA_HBA_ATTRB_PCI_FUNCNUM_MASK
= 0xFF0000,
2046 OCRDMA_HBA_ATTRB_PCI_FUNCNUM_SHIFT
= 0x10,
2047 OCRDMA_HBA_ATTRB_IF_TYPE_MASK
= 0xFF000000,
2048 OCRDMA_HBA_ATTRB_IF_TYPE_SHIFT
= 0x18,
2049 OCRDMA_HBA_ATTRB_NETFIL_MASK
=0xFF
2052 struct mgmt_hba_attribs
{
2053 u8 flashrom_version_string
[32];
2054 u8 manufacturer_name
[32];
2055 u32 supported_modes
;
2056 u32 rsvd_eprom_verhi_verlo
;
2059 u8 ncsi_ver_string
[12];
2060 u32 default_extended_timeout
;
2061 u8 controller_model_number
[32];
2062 u8 controller_description
[64];
2063 u8 controller_serial_number
[32];
2064 u8 ip_version_string
[32];
2065 u8 firmware_version_string
[32];
2066 u8 bios_version_string
[32];
2067 u8 redboot_version_string
[32];
2068 u8 driver_version_string
[32];
2069 u8 fw_on_flash_version_string
[32];
2070 u32 functionalities_supported
;
2071 u32 guid0_asicrev_cdblen
;
2072 u8 generational_guid
[12];
2074 u32 mfuncdev_iscsi_ldtout
;
2075 u32 ptpnum_maxdoms_hbast_cv
;
2076 u32 firmware_post_status
;
2078 u32 res_asicgen_iscsi_feaures
;
2082 struct mgmt_controller_attrib
{
2083 struct mgmt_hba_attribs hba_attribs
;
2086 u32 ityp_fnum_devnum_bnum
;
2093 struct ocrdma_get_ctrl_attribs_rsp
{
2094 struct ocrdma_mbx_hdr hdr
;
2095 struct mgmt_controller_attrib ctrl_attribs
;
2098 #define OCRDMA_SUBSYS_DCBX 0x10
2100 enum OCRDMA_DCBX_OPCODE
{
2101 OCRDMA_CMD_GET_DCBX_CONFIG
= 0x01
2104 enum OCRDMA_DCBX_PARAM_TYPE
{
2105 OCRDMA_PARAMETER_TYPE_ADMIN
= 0x00,
2106 OCRDMA_PARAMETER_TYPE_OPER
= 0x01,
2107 OCRDMA_PARAMETER_TYPE_PEER
= 0x02
2110 enum OCRDMA_DCBX_APP_PROTO
{
2111 OCRDMA_APP_PROTO_ROCE
= 0x8915
2114 enum OCRDMA_DCBX_PROTO
{
2115 OCRDMA_PROTO_SELECT_L2
= 0x00,
2116 OCRDMA_PROTO_SELECT_L4
= 0x01
2119 enum OCRDMA_DCBX_APP_PARAM
{
2120 OCRDMA_APP_PARAM_APP_PROTO_MASK
= 0xFFFF,
2121 OCRDMA_APP_PARAM_PROTO_SEL_MASK
= 0xFF,
2122 OCRDMA_APP_PARAM_PROTO_SEL_SHIFT
= 0x10,
2123 OCRDMA_APP_PARAM_VALID_MASK
= 0xFF,
2124 OCRDMA_APP_PARAM_VALID_SHIFT
= 0x18
2127 enum OCRDMA_DCBX_STATE_FLAGS
{
2128 OCRDMA_STATE_FLAG_ENABLED
= 0x01,
2129 OCRDMA_STATE_FLAG_ADDVERTISED
= 0x02,
2130 OCRDMA_STATE_FLAG_WILLING
= 0x04,
2131 OCRDMA_STATE_FLAG_SYNC
= 0x08,
2132 OCRDMA_STATE_FLAG_UNSUPPORTED
= 0x40000000,
2133 OCRDMA_STATE_FLAG_NEG_FAILD
= 0x80000000
2136 enum OCRDMA_TCV_AEV_OPV_ST
{
2137 OCRDMA_DCBX_TC_SUPPORT_MASK
= 0xFF,
2138 OCRDMA_DCBX_TC_SUPPORT_SHIFT
= 0x18,
2139 OCRDMA_DCBX_APP_ENTRY_SHIFT
= 0x10,
2140 OCRDMA_DCBX_OP_PARAM_SHIFT
= 0x08,
2141 OCRDMA_DCBX_STATE_MASK
= 0xFF
2144 struct ocrdma_app_parameter
{
2145 u32 valid_proto_app
;
2150 struct ocrdma_dcbx_cfg
{
2160 struct ocrdma_app_parameter app_param
[15];
2163 struct ocrdma_get_dcbx_cfg_req
{
2164 struct ocrdma_mbx_hdr hdr
;
2168 struct ocrdma_get_dcbx_cfg_rsp
{
2169 struct ocrdma_mbx_rsp hdr
;
2170 struct ocrdma_dcbx_cfg cfg
;
2173 #endif /* __OCRDMA_SLI_H__ */