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irq_domain: correct a minor wrong comment for linear revmap
[deliverable/linux.git] / drivers / infiniband / hw / ocrdma / ocrdma_sli.h
1 /*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *
20 * Contact Information:
21 * linux-drivers@emulex.com
22 *
23 * Emulex
24 * 3333 Susan Street
25 * Costa Mesa, CA 92626
26 *******************************************************************/
27
28 #ifndef __OCRDMA_SLI_H__
29 #define __OCRDMA_SLI_H__
30
31 #define Bit(_b) (1 << (_b))
32
33 #define OCRDMA_GEN1_FAMILY 0xB
34 #define OCRDMA_GEN2_FAMILY 0x2
35
36 #define OCRDMA_SUBSYS_ROCE 10
37 enum {
38 OCRDMA_CMD_QUERY_CONFIG = 1,
39 OCRDMA_CMD_ALLOC_PD,
40 OCRDMA_CMD_DEALLOC_PD,
41
42 OCRDMA_CMD_CREATE_AH_TBL,
43 OCRDMA_CMD_DELETE_AH_TBL,
44
45 OCRDMA_CMD_CREATE_QP,
46 OCRDMA_CMD_QUERY_QP,
47 OCRDMA_CMD_MODIFY_QP,
48 OCRDMA_CMD_DELETE_QP,
49
50 OCRDMA_CMD_RSVD1,
51 OCRDMA_CMD_ALLOC_LKEY,
52 OCRDMA_CMD_DEALLOC_LKEY,
53 OCRDMA_CMD_REGISTER_NSMR,
54 OCRDMA_CMD_REREGISTER_NSMR,
55 OCRDMA_CMD_REGISTER_NSMR_CONT,
56 OCRDMA_CMD_QUERY_NSMR,
57 OCRDMA_CMD_ALLOC_MW,
58 OCRDMA_CMD_QUERY_MW,
59
60 OCRDMA_CMD_CREATE_SRQ,
61 OCRDMA_CMD_QUERY_SRQ,
62 OCRDMA_CMD_MODIFY_SRQ,
63 OCRDMA_CMD_DELETE_SRQ,
64
65 OCRDMA_CMD_ATTACH_MCAST,
66 OCRDMA_CMD_DETACH_MCAST,
67
68 OCRDMA_CMD_MAX
69 };
70
71 #define OCRDMA_SUBSYS_COMMON 1
72 enum {
73 OCRDMA_CMD_CREATE_CQ = 12,
74 OCRDMA_CMD_CREATE_EQ = 13,
75 OCRDMA_CMD_CREATE_MQ = 21,
76 OCRDMA_CMD_GET_FW_VER = 35,
77 OCRDMA_CMD_DELETE_MQ = 53,
78 OCRDMA_CMD_DELETE_CQ = 54,
79 OCRDMA_CMD_DELETE_EQ = 55,
80 OCRDMA_CMD_GET_FW_CONFIG = 58,
81 OCRDMA_CMD_CREATE_MQ_EXT = 90
82 };
83
84 enum {
85 QTYPE_EQ = 1,
86 QTYPE_CQ = 2,
87 QTYPE_MCCQ = 3
88 };
89
90 #define OCRDMA_MAX_SGID (8)
91
92 #define OCRDMA_MAX_QP 2048
93 #define OCRDMA_MAX_CQ 2048
94
95 enum {
96 OCRDMA_DB_RQ_OFFSET = 0xE0,
97 OCRDMA_DB_GEN2_RQ1_OFFSET = 0x100,
98 OCRDMA_DB_GEN2_RQ2_OFFSET = 0xC0,
99 OCRDMA_DB_SQ_OFFSET = 0x60,
100 OCRDMA_DB_GEN2_SQ_OFFSET = 0x1C0,
101 OCRDMA_DB_SRQ_OFFSET = OCRDMA_DB_RQ_OFFSET,
102 OCRDMA_DB_GEN2_SRQ_OFFSET = OCRDMA_DB_GEN2_RQ1_OFFSET,
103 OCRDMA_DB_CQ_OFFSET = 0x120,
104 OCRDMA_DB_EQ_OFFSET = OCRDMA_DB_CQ_OFFSET,
105 OCRDMA_DB_MQ_OFFSET = 0x140
106 };
107
108 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
109 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */
110 /* qid #2 msbits at 12-11 */
111 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1
112 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
113 /* Rearm bit */
114 #define OCRDMA_DB_CQ_REARM_SHIFT (29) /* bit 29 */
115 /* solicited bit */
116 #define OCRDMA_DB_CQ_SOLICIT_SHIFT (31) /* bit 31 */
117
118 #define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */
119 #define OCRDMA_EQ_ID_EXT_MASK 0x3e00 /* bits 9-13 */
120 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 at 11-15 */
121
122 /* Clear the interrupt for this eq */
123 #define OCRDMA_EQ_CLR_SHIFT (9) /* bit 9 */
124 /* Must be 1 */
125 #define OCRDMA_EQ_TYPE_SHIFT (10) /* bit 10 */
126 /* Number of event entries processed */
127 #define OCRDMA_NUM_EQE_SHIFT (16) /* bits 16 - 28 */
128 /* Rearm bit */
129 #define OCRDMA_REARM_SHIFT (29) /* bit 29 */
130
131 #define OCRDMA_MQ_ID_MASK 0x7FF /* bits 0 - 10 */
132 /* Number of entries posted */
133 #define OCRDMA_MQ_NUM_MQE_SHIFT (16) /* bits 16 - 29 */
134
135 #define OCRDMA_MIN_HPAGE_SIZE (4096)
136
137 #define OCRDMA_MIN_Q_PAGE_SIZE (4096)
138 #define OCRDMA_MAX_Q_PAGES (8)
139
140 /*
141 # 0: 4K Bytes
142 # 1: 8K Bytes
143 # 2: 16K Bytes
144 # 3: 32K Bytes
145 # 4: 64K Bytes
146 */
147 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT (5)
148 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
149
150 #define MAX_OCRDMA_QP_PAGES (8)
151 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)
152
153 #define OCRDMA_CREATE_CQ_MAX_PAGES (4)
154 #define OCRDMA_DPP_CQE_SIZE (4)
155
156 #define OCRDMA_GEN2_MAX_CQE 1024
157 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
158 #define OCRDMA_GEN2_WQE_SIZE 256
159 #define OCRDMA_MAX_CQE 4095
160 #define OCRDMA_CQ_PAGE_SIZE 16384
161 #define OCRDMA_WQE_SIZE 128
162 #define OCRDMA_WQE_STRIDE 8
163 #define OCRDMA_WQE_ALIGN_BYTES 16
164
165 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES
166
167 enum {
168 OCRDMA_MCH_OPCODE_SHIFT = 0,
169 OCRDMA_MCH_OPCODE_MASK = 0xFF,
170 OCRDMA_MCH_SUBSYS_SHIFT = 8,
171 OCRDMA_MCH_SUBSYS_MASK = 0xFF00
172 };
173
174 /* mailbox cmd header */
175 struct ocrdma_mbx_hdr {
176 u32 subsys_op;
177 u32 timeout; /* in seconds */
178 u32 cmd_len;
179 u32 rsvd_version;
180 } __packed;
181
182 enum {
183 OCRDMA_MBX_RSP_OPCODE_SHIFT = 0,
184 OCRDMA_MBX_RSP_OPCODE_MASK = 0xFF,
185 OCRDMA_MBX_RSP_SUBSYS_SHIFT = 8,
186 OCRDMA_MBX_RSP_SUBSYS_MASK = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT,
187
188 OCRDMA_MBX_RSP_STATUS_SHIFT = 0,
189 OCRDMA_MBX_RSP_STATUS_MASK = 0xFF,
190 OCRDMA_MBX_RSP_ASTATUS_SHIFT = 8,
191 OCRDMA_MBX_RSP_ASTATUS_MASK = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT
192 };
193
194 /* mailbox cmd response */
195 struct ocrdma_mbx_rsp {
196 u32 subsys_op;
197 u32 status;
198 u32 rsp_len;
199 u32 add_rsp_len;
200 } __packed;
201
202 enum {
203 OCRDMA_MQE_EMBEDDED = 1,
204 OCRDMA_MQE_NONEMBEDDED = 0
205 };
206
207 struct ocrdma_mqe_sge {
208 u32 pa_lo;
209 u32 pa_hi;
210 u32 len;
211 } __packed;
212
213 enum {
214 OCRDMA_MQE_HDR_EMB_SHIFT = 0,
215 OCRDMA_MQE_HDR_EMB_MASK = Bit(0),
216 OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3,
217 OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
218 OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24,
219 OCRDMA_MQE_HDR_SPECIAL_MASK = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT
220 };
221
222 struct ocrdma_mqe_hdr {
223 u32 spcl_sge_cnt_emb;
224 u32 pyld_len;
225 u32 tag_lo;
226 u32 tag_hi;
227 u32 rsvd3;
228 } __packed;
229
230 struct ocrdma_mqe_emb_cmd {
231 struct ocrdma_mbx_hdr mch;
232 u8 pyld[220];
233 } __packed;
234
235 struct ocrdma_mqe {
236 struct ocrdma_mqe_hdr hdr;
237 union {
238 struct ocrdma_mqe_emb_cmd emb_req;
239 struct {
240 struct ocrdma_mqe_sge sge[19];
241 } nonemb_req;
242 u8 cmd[236];
243 struct ocrdma_mbx_rsp rsp;
244 } u;
245 } __packed;
246
247 #define OCRDMA_EQ_LEN 4096
248 #define OCRDMA_MQ_CQ_LEN 256
249 #define OCRDMA_MQ_LEN 128
250
251 #define PAGE_SHIFT_4K 12
252 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
253
254 /* Returns number of pages spanned by the data starting at the given addr */
255 #define PAGES_4K_SPANNED(_address, size) \
256 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
257 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
258
259 struct ocrdma_delete_q_req {
260 struct ocrdma_mbx_hdr req;
261 u32 id;
262 } __packed;
263
264 struct ocrdma_pa {
265 u32 lo;
266 u32 hi;
267 } __packed;
268
269 #define MAX_OCRDMA_EQ_PAGES (8)
270 struct ocrdma_create_eq_req {
271 struct ocrdma_mbx_hdr req;
272 u32 num_pages;
273 u32 valid;
274 u32 cnt;
275 u32 delay;
276 u32 rsvd;
277 struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES];
278 } __packed;
279
280 enum {
281 OCRDMA_CREATE_EQ_VALID = Bit(29),
282 OCRDMA_CREATE_EQ_CNT_SHIFT = 26,
283 OCRDMA_CREATE_CQ_DELAY_SHIFT = 13,
284 };
285
286 struct ocrdma_create_eq_rsp {
287 struct ocrdma_mbx_rsp rsp;
288 u32 vector_eqid;
289 };
290
291 #define OCRDMA_EQ_MINOR_OTHER (0x1)
292
293 enum {
294 OCRDMA_MCQE_STATUS_SHIFT = 0,
295 OCRDMA_MCQE_STATUS_MASK = 0xFFFF,
296 OCRDMA_MCQE_ESTATUS_SHIFT = 16,
297 OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
298 OCRDMA_MCQE_CONS_SHIFT = 27,
299 OCRDMA_MCQE_CONS_MASK = Bit(27),
300 OCRDMA_MCQE_CMPL_SHIFT = 28,
301 OCRDMA_MCQE_CMPL_MASK = Bit(28),
302 OCRDMA_MCQE_AE_SHIFT = 30,
303 OCRDMA_MCQE_AE_MASK = Bit(30),
304 OCRDMA_MCQE_VALID_SHIFT = 31,
305 OCRDMA_MCQE_VALID_MASK = Bit(31)
306 };
307
308 struct ocrdma_mcqe {
309 u32 status;
310 u32 tag_lo;
311 u32 tag_hi;
312 u32 valid_ae_cmpl_cons;
313 } __packed;
314
315 enum {
316 OCRDMA_AE_MCQE_QPVALID = Bit(31),
317 OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF,
318
319 OCRDMA_AE_MCQE_CQVALID = Bit(31),
320 OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF,
321 OCRDMA_AE_MCQE_VALID = Bit(31),
322 OCRDMA_AE_MCQE_AE = Bit(30),
323 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
324 OCRDMA_AE_MCQE_EVENT_TYPE_MASK =
325 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,
326 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8,
327 OCRDMA_AE_MCQE_EVENT_CODE_MASK =
328 0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
329 };
330 struct ocrdma_ae_mcqe {
331 u32 qpvalid_qpid;
332 u32 cqvalid_cqid;
333 u32 evt_tag;
334 u32 valid_ae_event;
335 } __packed;
336
337 enum {
338 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT = 16,
339 OCRDMA_AE_MPA_MCQE_REQ_ID_MASK = 0xFFFF <<
340 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,
341
342 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT = 8,
343 OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK = 0xFF <<
344 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,
345 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT = 16,
346 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK = 0xFF <<
347 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
348 OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30,
349 OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = Bit(30),
350 OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31,
351 OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = Bit(31)
352 };
353
354 struct ocrdma_ae_mpa_mcqe {
355 u32 req_id;
356 u32 w1;
357 u32 w2;
358 u32 valid_ae_event;
359 } __packed;
360
361 enum {
362 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT = 0,
363 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK = 0xFFFF,
364 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT = 16,
365 OCRDMA_AE_QP_MCQE_QP_ID_MASK = 0xFFFF <<
366 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,
367
368 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT = 8,
369 OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK = 0xFF <<
370 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,
371 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT = 16,
372 OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK = 0xFF <<
373 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
374 OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30,
375 OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = Bit(30),
376 OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31,
377 OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = Bit(31)
378 };
379
380 struct ocrdma_ae_qp_mcqe {
381 u32 qp_id_state;
382 u32 w1;
383 u32 w2;
384 u32 valid_ae_event;
385 } __packed;
386
387 #define OCRDMA_ASYNC_EVE_CODE 0x14
388
389 enum OCRDMA_ASYNC_EVENT_TYPE {
390 OCRDMA_CQ_ERROR = 0x00,
391 OCRDMA_CQ_OVERRUN_ERROR = 0x01,
392 OCRDMA_CQ_QPCAT_ERROR = 0x02,
393 OCRDMA_QP_ACCESS_ERROR = 0x03,
394 OCRDMA_QP_COMM_EST_EVENT = 0x04,
395 OCRDMA_SQ_DRAINED_EVENT = 0x05,
396 OCRDMA_DEVICE_FATAL_EVENT = 0x08,
397 OCRDMA_SRQCAT_ERROR = 0x0E,
398 OCRDMA_SRQ_LIMIT_EVENT = 0x0F,
399 OCRDMA_QP_LAST_WQE_EVENT = 0x10
400 };
401
402 /* mailbox command request and responses */
403 enum {
404 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2,
405 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = Bit(2),
406 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3,
407 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = Bit(3),
408 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8,
409 OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK = 0xFFFFFF <<
410 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
411
412 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT = 16,
413 OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK = 0xFFFF <<
414 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,
415 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT = 8,
416 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK = 0xFF <<
417 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,
418
419 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT = 0,
420 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK = 0xFFFF,
421
422 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT = 0,
423 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK = 0xFFFF,
424 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT = 16,
425 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK = 0xFFFF <<
426 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,
427
428 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET = 24,
429 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK = 0xFF <<
430 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,
431 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET = 16,
432 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK = 0xFF <<
433 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,
434 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET = 0,
435 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK = 0xFFFF <<
436 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,
437
438 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET = 16,
439 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK = 0xFFFF <<
440 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,
441 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET = 0,
442 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK = 0xFFFF <<
443 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,
444
445 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET = 16,
446 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK = 0xFFFF <<
447 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,
448 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET = 0,
449 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK = 0xFFFF <<
450 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,
451
452 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET = 0,
453 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK = 0xFFFF <<
454 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,
455
456 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET = 16,
457 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK = 0xFFFF <<
458 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
459 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET = 0,
460 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK = 0xFFFF <<
461 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
462
463 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET = 16,
464 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK = 0xFFFF <<
465 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,
466 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET = 0,
467 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK = 0xFFFF <<
468 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,
469
470 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET = 16,
471 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK = 0xFFFF <<
472 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,
473 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET = 0,
474 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK = 0xFFFF <<
475 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,
476 };
477
478 struct ocrdma_mbx_query_config {
479 struct ocrdma_mqe_hdr hdr;
480 struct ocrdma_mbx_rsp rsp;
481 u32 qp_srq_cq_ird_ord;
482 u32 max_pd_ca_ack_delay;
483 u32 max_write_send_sge;
484 u32 max_ird_ord_per_qp;
485 u32 max_shared_ird_ord;
486 u32 max_mr;
487 u64 max_mr_size;
488 u32 max_num_mr_pbl;
489 u32 max_mw;
490 u32 max_fmr;
491 u32 max_pages_per_frmr;
492 u32 max_mcast_group;
493 u32 max_mcast_qp_attach;
494 u32 max_total_mcast_qp_attach;
495 u32 wqe_rqe_stride_max_dpp_cqs;
496 u32 max_srq_rpir_qps;
497 u32 max_dpp_pds_credits;
498 u32 max_dpp_credits_pds_per_pd;
499 u32 max_wqes_rqes_per_q;
500 u32 max_cq_cqes_per_cq;
501 u32 max_srq_rqe_sge;
502 } __packed;
503
504 struct ocrdma_fw_ver_rsp {
505 struct ocrdma_mqe_hdr hdr;
506 struct ocrdma_mbx_rsp rsp;
507
508 u8 running_ver[32];
509 } __packed;
510
511 struct ocrdma_fw_conf_rsp {
512 struct ocrdma_mqe_hdr hdr;
513 struct ocrdma_mbx_rsp rsp;
514
515 u32 config_num;
516 u32 asic_revision;
517 u32 phy_port;
518 u32 fn_mode;
519 struct {
520 u32 mode;
521 u32 nic_wqid_base;
522 u32 nic_wq_tot;
523 u32 prot_wqid_base;
524 u32 prot_wq_tot;
525 u32 prot_rqid_base;
526 u32 prot_rqid_tot;
527 u32 rsvd[6];
528 } ulp[2];
529 u32 fn_capabilities;
530 u32 rsvd1;
531 u32 rsvd2;
532 u32 base_eqid;
533 u32 max_eq;
534
535 } __packed;
536
537 enum {
538 OCRDMA_FN_MODE_RDMA = 0x4
539 };
540
541 enum {
542 OCRDMA_CREATE_CQ_VER2 = 2,
543
544 OCRDMA_CREATE_CQ_PAGE_CNT_MASK = 0xFFFF,
545 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT = 16,
546 OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF,
547
548 OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12,
549 OCRDMA_CREATE_CQ_COALESCWM_MASK = Bit(13) | Bit(12),
550 OCRDMA_CREATE_CQ_FLAGS_NODELAY = Bit(14),
551 OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = Bit(15),
552
553 OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF,
554 OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF
555 };
556
557 enum {
558 OCRDMA_CREATE_CQ_VER0 = 0,
559 OCRDMA_CREATE_CQ_DPP = 1,
560 OCRDMA_CREATE_CQ_TYPE_SHIFT = 24,
561 OCRDMA_CREATE_CQ_EQID_SHIFT = 22,
562
563 OCRDMA_CREATE_CQ_CNT_SHIFT = 27,
564 OCRDMA_CREATE_CQ_FLAGS_VALID = Bit(29),
565 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = Bit(31),
566 OCRDMA_CREATE_CQ_DEF_FLAGS = OCRDMA_CREATE_CQ_FLAGS_VALID |
567 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
568 OCRDMA_CREATE_CQ_FLAGS_NODELAY
569 };
570
571 struct ocrdma_create_cq_cmd {
572 struct ocrdma_mbx_hdr req;
573 u32 pgsz_pgcnt;
574 u32 ev_cnt_flags;
575 u32 eqn;
576 u32 cqe_count;
577 u32 rsvd6;
578 struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES];
579 };
580
581 struct ocrdma_create_cq {
582 struct ocrdma_mqe_hdr hdr;
583 struct ocrdma_create_cq_cmd cmd;
584 } __packed;
585
586 enum {
587 OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF
588 };
589
590 struct ocrdma_create_cq_cmd_rsp {
591 struct ocrdma_mbx_rsp rsp;
592 u32 cq_id;
593 } __packed;
594
595 struct ocrdma_create_cq_rsp {
596 struct ocrdma_mqe_hdr hdr;
597 struct ocrdma_create_cq_cmd_rsp rsp;
598 } __packed;
599
600 enum {
601 OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22,
602 OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16,
603 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16,
604 OCRDMA_CREATE_MQ_VALID = Bit(31),
605 OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = Bit(0)
606 };
607
608 struct ocrdma_create_mq_v0 {
609 u32 pages;
610 u32 cqid_ringsize;
611 u32 valid;
612 u32 async_cqid_valid;
613 u32 rsvd;
614 struct ocrdma_pa pa[8];
615 } __packed;
616
617 struct ocrdma_create_mq_v1 {
618 u32 cqid_pages;
619 u32 async_event_bitmap;
620 u32 async_cqid_ringsize;
621 u32 valid;
622 u32 async_cqid_valid;
623 u32 rsvd;
624 struct ocrdma_pa pa[8];
625 } __packed;
626
627 struct ocrdma_create_mq_req {
628 struct ocrdma_mbx_hdr req;
629 union {
630 struct ocrdma_create_mq_v0 v0;
631 struct ocrdma_create_mq_v1 v1;
632 };
633 } __packed;
634
635 struct ocrdma_create_mq_rsp {
636 struct ocrdma_mbx_rsp rsp;
637 u32 id;
638 } __packed;
639
640 enum {
641 OCRDMA_DESTROY_CQ_QID_SHIFT = 0,
642 OCRDMA_DESTROY_CQ_QID_MASK = 0xFFFF,
643 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT = 16,
644 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK = 0xFFFF <<
645 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
646 };
647
648 struct ocrdma_destroy_cq {
649 struct ocrdma_mqe_hdr hdr;
650 struct ocrdma_mbx_hdr req;
651
652 u32 bypass_flush_qid;
653 } __packed;
654
655 struct ocrdma_destroy_cq_rsp {
656 struct ocrdma_mqe_hdr hdr;
657 struct ocrdma_mbx_rsp rsp;
658 } __packed;
659
660 enum {
661 OCRDMA_QPT_GSI = 1,
662 OCRDMA_QPT_RC = 2,
663 OCRDMA_QPT_UD = 4,
664 };
665
666 enum {
667 OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT = 0,
668 OCRDMA_CREATE_QP_REQ_PD_ID_MASK = 0xFFFF,
669 OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
670 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,
671 OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29,
672 OCRDMA_CREATE_QP_REQ_QPT_MASK = Bit(31) | Bit(30) | Bit(29),
673
674 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0,
675 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF,
676 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT = 16,
677 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK = 0xFFFF <<
678 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,
679
680 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT = 0,
681 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK = 0xFFFF,
682 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT = 16,
683 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK = 0xFFFF <<
684 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
685
686 OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0,
687 OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = Bit(0),
688 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1,
689 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = Bit(1),
690 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2,
691 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = Bit(2),
692 OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3,
693 OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = Bit(3),
694 OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4,
695 OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = Bit(4),
696 OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5,
697 OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = Bit(5),
698 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6,
699 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = Bit(6),
700 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7,
701 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = Bit(7),
702 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8,
703 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = Bit(8),
704 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16,
705 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK = 0xFFFF <<
706 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
707
708 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT = 0,
709 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK = 0xFFFF,
710 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT = 16,
711 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK = 0xFFFF <<
712 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,
713
714 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT = 0,
715 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK = 0xFFFF,
716 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT = 16,
717 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK = 0xFFFF <<
718 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,
719
720 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT = 0,
721 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK = 0xFFFF,
722 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT = 16,
723 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK = 0xFFFF <<
724 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,
725
726 OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT = 0,
727 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK = 0xFFFF,
728 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT = 16,
729 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK = 0xFFFF <<
730 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,
731
732 OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT = 0,
733 OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK = 0xFFFF,
734 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT = 16,
735 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK = 0xFFFF <<
736 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
737 };
738
739 enum {
740 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT = 16,
741 OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT = 1
742 };
743
744 #define MAX_OCRDMA_IRD_PAGES 4
745
746 enum ocrdma_qp_flags {
747 OCRDMA_QP_MW_BIND = 1,
748 OCRDMA_QP_LKEY0 = (1 << 1),
749 OCRDMA_QP_FAST_REG = (1 << 2),
750 OCRDMA_QP_INB_RD = (1 << 6),
751 OCRDMA_QP_INB_WR = (1 << 7),
752 };
753
754 enum ocrdma_qp_state {
755 OCRDMA_QPS_RST = 0,
756 OCRDMA_QPS_INIT = 1,
757 OCRDMA_QPS_RTR = 2,
758 OCRDMA_QPS_RTS = 3,
759 OCRDMA_QPS_SQE = 4,
760 OCRDMA_QPS_SQ_DRAINING = 5,
761 OCRDMA_QPS_ERR = 6,
762 OCRDMA_QPS_SQD = 7
763 };
764
765 struct ocrdma_create_qp_req {
766 struct ocrdma_mqe_hdr hdr;
767 struct ocrdma_mbx_hdr req;
768
769 u32 type_pgsz_pdn;
770 u32 max_wqe_rqe;
771 u32 max_sge_send_write;
772 u32 max_sge_recv_flags;
773 u32 max_ord_ird;
774 u32 num_wq_rq_pages;
775 u32 wqe_rqe_size;
776 u32 wq_rq_cqid;
777 struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES];
778 struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES];
779 u32 dpp_credits_cqid;
780 u32 rpir_lkey;
781 struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES];
782 } __packed;
783
784 enum {
785 OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT = 0,
786 OCRDMA_CREATE_QP_RSP_QP_ID_MASK = 0xFFFF,
787
788 OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT = 0,
789 OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK = 0xFFFF,
790 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT = 16,
791 OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK = 0xFFFF <<
792 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,
793
794 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT = 0,
795 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK = 0xFFFF,
796 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT = 16,
797 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK = 0xFFFF <<
798 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,
799
800 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT = 16,
801 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK = 0xFFFF <<
802 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,
803
804 OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT = 0,
805 OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK = 0xFFFF,
806 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT = 16,
807 OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK = 0xFFFF <<
808 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,
809
810 OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT = 0,
811 OCRDMA_CREATE_QP_RSP_RQ_ID_MASK = 0xFFFF,
812 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT = 16,
813 OCRDMA_CREATE_QP_RSP_SQ_ID_MASK = 0xFFFF <<
814 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
815
816 OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = Bit(0),
817 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1,
818 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK = 0x7FFF <<
819 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
820 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT = 16,
821 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK = 0xFFFF <<
822 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,
823 };
824
825 struct ocrdma_create_qp_rsp {
826 struct ocrdma_mqe_hdr hdr;
827 struct ocrdma_mbx_rsp rsp;
828
829 u32 qp_id;
830 u32 max_wqe_rqe;
831 u32 max_sge_send_write;
832 u32 max_sge_recv;
833 u32 max_ord_ird;
834 u32 sq_rq_id;
835 u32 dpp_response;
836 } __packed;
837
838 struct ocrdma_destroy_qp {
839 struct ocrdma_mqe_hdr hdr;
840 struct ocrdma_mbx_hdr req;
841 u32 qp_id;
842 } __packed;
843
844 struct ocrdma_destroy_qp_rsp {
845 struct ocrdma_mqe_hdr hdr;
846 struct ocrdma_mbx_rsp rsp;
847 } __packed;
848
849 enum {
850 OCRDMA_MODIFY_QP_ID_SHIFT = 0,
851 OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF,
852
853 OCRDMA_QP_PARA_QPS_VALID = Bit(0),
854 OCRDMA_QP_PARA_SQD_ASYNC_VALID = Bit(1),
855 OCRDMA_QP_PARA_PKEY_VALID = Bit(2),
856 OCRDMA_QP_PARA_QKEY_VALID = Bit(3),
857 OCRDMA_QP_PARA_PMTU_VALID = Bit(4),
858 OCRDMA_QP_PARA_ACK_TO_VALID = Bit(5),
859 OCRDMA_QP_PARA_RETRY_CNT_VALID = Bit(6),
860 OCRDMA_QP_PARA_RRC_VALID = Bit(7),
861 OCRDMA_QP_PARA_RQPSN_VALID = Bit(8),
862 OCRDMA_QP_PARA_MAX_IRD_VALID = Bit(9),
863 OCRDMA_QP_PARA_MAX_ORD_VALID = Bit(10),
864 OCRDMA_QP_PARA_RNT_VALID = Bit(11),
865 OCRDMA_QP_PARA_SQPSN_VALID = Bit(12),
866 OCRDMA_QP_PARA_DST_QPN_VALID = Bit(13),
867 OCRDMA_QP_PARA_MAX_WQE_VALID = Bit(14),
868 OCRDMA_QP_PARA_MAX_RQE_VALID = Bit(15),
869 OCRDMA_QP_PARA_SGE_SEND_VALID = Bit(16),
870 OCRDMA_QP_PARA_SGE_RECV_VALID = Bit(17),
871 OCRDMA_QP_PARA_SGE_WR_VALID = Bit(18),
872 OCRDMA_QP_PARA_INB_RDEN_VALID = Bit(19),
873 OCRDMA_QP_PARA_INB_WREN_VALID = Bit(20),
874 OCRDMA_QP_PARA_FLOW_LBL_VALID = Bit(21),
875 OCRDMA_QP_PARA_BIND_EN_VALID = Bit(22),
876 OCRDMA_QP_PARA_ZLKEY_EN_VALID = Bit(23),
877 OCRDMA_QP_PARA_FMR_EN_VALID = Bit(24),
878 OCRDMA_QP_PARA_INBAT_EN_VALID = Bit(25),
879 OCRDMA_QP_PARA_VLAN_EN_VALID = Bit(26),
880
881 OCRDMA_MODIFY_QP_FLAGS_RD = Bit(0),
882 OCRDMA_MODIFY_QP_FLAGS_WR = Bit(1),
883 OCRDMA_MODIFY_QP_FLAGS_SEND = Bit(2),
884 OCRDMA_MODIFY_QP_FLAGS_ATOMIC = Bit(3)
885 };
886
887 enum {
888 OCRDMA_QP_PARAMS_SRQ_ID_SHIFT = 0,
889 OCRDMA_QP_PARAMS_SRQ_ID_MASK = 0xFFFF,
890
891 OCRDMA_QP_PARAMS_MAX_RQE_SHIFT = 0,
892 OCRDMA_QP_PARAMS_MAX_RQE_MASK = 0xFFFF,
893 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT = 16,
894 OCRDMA_QP_PARAMS_MAX_WQE_MASK = 0xFFFF <<
895 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,
896
897 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT = 0,
898 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK = 0xFFFF,
899 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT = 16,
900 OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK = 0xFFFF <<
901 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
902
903 OCRDMA_QP_PARAMS_FLAGS_FMR_EN = Bit(0),
904 OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = Bit(1),
905 OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = Bit(2),
906 OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = Bit(3),
907 OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = Bit(4),
908 OCRDMA_QP_PARAMS_STATE_SHIFT = 5,
909 OCRDMA_QP_PARAMS_STATE_MASK = Bit(5) | Bit(6) | Bit(7),
910 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = Bit(8),
911 OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = Bit(9),
912 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16,
913 OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK = 0xFFFF <<
914 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
915
916 OCRDMA_QP_PARAMS_MAX_IRD_SHIFT = 0,
917 OCRDMA_QP_PARAMS_MAX_IRD_MASK = 0xFFFF,
918 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT = 16,
919 OCRDMA_QP_PARAMS_MAX_ORD_MASK = 0xFFFF <<
920 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,
921
922 OCRDMA_QP_PARAMS_RQ_CQID_SHIFT = 0,
923 OCRDMA_QP_PARAMS_RQ_CQID_MASK = 0xFFFF,
924 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT = 16,
925 OCRDMA_QP_PARAMS_WQ_CQID_MASK = 0xFFFF <<
926 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,
927
928 OCRDMA_QP_PARAMS_RQ_PSN_SHIFT = 0,
929 OCRDMA_QP_PARAMS_RQ_PSN_MASK = 0xFFFFFF,
930 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT = 24,
931 OCRDMA_QP_PARAMS_HOP_LMT_MASK = 0xFF <<
932 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
933
934 OCRDMA_QP_PARAMS_SQ_PSN_SHIFT = 0,
935 OCRDMA_QP_PARAMS_SQ_PSN_MASK = 0xFFFFFF,
936 OCRDMA_QP_PARAMS_TCLASS_SHIFT = 24,
937 OCRDMA_QP_PARAMS_TCLASS_MASK = 0xFF <<
938 OCRDMA_QP_PARAMS_TCLASS_SHIFT,
939
940 OCRDMA_QP_PARAMS_DEST_QPN_SHIFT = 0,
941 OCRDMA_QP_PARAMS_DEST_QPN_MASK = 0xFFFFFF,
942 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT = 24,
943 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK = 0x7 <<
944 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,
945 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT = 27,
946 OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK = 0x1F <<
947 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,
948
949 OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT = 0,
950 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK = 0xFFFF,
951 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT = 18,
952 OCRDMA_QP_PARAMS_PATH_MTU_MASK = 0x3FFF <<
953 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,
954
955 OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT = 0,
956 OCRDMA_QP_PARAMS_FLOW_LABEL_MASK = 0xFFFFF,
957 OCRDMA_QP_PARAMS_SL_SHIFT = 20,
958 OCRDMA_QP_PARAMS_SL_MASK = 0xF <<
959 OCRDMA_QP_PARAMS_SL_SHIFT,
960 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT = 24,
961 OCRDMA_QP_PARAMS_RETRY_CNT_MASK = 0x7 <<
962 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,
963 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT = 27,
964 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK = 0x1F <<
965 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,
966
967 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT = 0,
968 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK = 0xFFFF,
969 OCRDMA_QP_PARAMS_VLAN_SHIFT = 16,
970 OCRDMA_QP_PARAMS_VLAN_MASK = 0xFFFF <<
971 OCRDMA_QP_PARAMS_VLAN_SHIFT
972 };
973
974 struct ocrdma_qp_params {
975 u32 id;
976 u32 max_wqe_rqe;
977 u32 max_sge_send_write;
978 u32 max_sge_recv_flags;
979 u32 max_ord_ird;
980 u32 wq_rq_cqid;
981 u32 hop_lmt_rq_psn;
982 u32 tclass_sq_psn;
983 u32 ack_to_rnr_rtc_dest_qpn;
984 u32 path_mtu_pkey_indx;
985 u32 rnt_rc_sl_fl;
986 u8 sgid[16];
987 u8 dgid[16];
988 u32 dmac_b0_to_b3;
989 u32 vlan_dmac_b4_to_b5;
990 u32 qkey;
991 } __packed;
992
993
994 struct ocrdma_modify_qp {
995 struct ocrdma_mqe_hdr hdr;
996 struct ocrdma_mbx_hdr req;
997
998 struct ocrdma_qp_params params;
999 u32 flags;
1000 u32 rdma_flags;
1001 u32 num_outstanding_atomic_rd;
1002 } __packed;
1003
1004 enum {
1005 OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT = 0,
1006 OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK = 0xFFFF,
1007 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT = 16,
1008 OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK = 0xFFFF <<
1009 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,
1010
1011 OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT = 0,
1012 OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK = 0xFFFF,
1013 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT = 16,
1014 OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK = 0xFFFF <<
1015 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
1016 };
1017 struct ocrdma_modify_qp_rsp {
1018 struct ocrdma_mqe_hdr hdr;
1019 struct ocrdma_mbx_rsp rsp;
1020
1021 u32 max_wqe_rqe;
1022 u32 max_ord_ird;
1023 } __packed;
1024
1025 struct ocrdma_query_qp {
1026 struct ocrdma_mqe_hdr hdr;
1027 struct ocrdma_mbx_hdr req;
1028
1029 #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0
1030 #define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF
1031 u32 qp_id;
1032 } __packed;
1033
1034 struct ocrdma_query_qp_rsp {
1035 struct ocrdma_mqe_hdr hdr;
1036 struct ocrdma_mbx_rsp rsp;
1037 struct ocrdma_qp_params params;
1038 } __packed;
1039
1040 enum {
1041 OCRDMA_CREATE_SRQ_PD_ID_SHIFT = 0,
1042 OCRDMA_CREATE_SRQ_PD_ID_MASK = 0xFFFF,
1043 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT = 16,
1044 OCRDMA_CREATE_SRQ_PG_SZ_MASK = 0x3 <<
1045 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,
1046
1047 OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT = 0,
1048 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT = 16,
1049 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK = 0xFFFF <<
1050 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,
1051
1052 OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT = 0,
1053 OCRDMA_CREATE_SRQ_RQE_SIZE_MASK = 0xFFFF,
1054 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT = 16,
1055 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK = 0xFFFF <<
1056 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
1057 };
1058
1059 struct ocrdma_create_srq {
1060 struct ocrdma_mqe_hdr hdr;
1061 struct ocrdma_mbx_hdr req;
1062
1063 u32 pgsz_pdid;
1064 u32 max_sge_rqe;
1065 u32 pages_rqe_sz;
1066 struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES];
1067 } __packed;
1068
1069 enum {
1070 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT = 0,
1071 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK = 0xFFFFFF,
1072
1073 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT = 0,
1074 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK = 0xFFFF,
1075 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT = 16,
1076 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK = 0xFFFF <<
1077 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
1078 };
1079
1080 struct ocrdma_create_srq_rsp {
1081 struct ocrdma_mqe_hdr hdr;
1082 struct ocrdma_mbx_rsp rsp;
1083
1084 u32 id;
1085 u32 max_sge_rqe_allocated;
1086 } __packed;
1087
1088 enum {
1089 OCRDMA_MODIFY_SRQ_ID_SHIFT = 0,
1090 OCRDMA_MODIFY_SRQ_ID_MASK = 0xFFFFFF,
1091
1092 OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0,
1093 OCRDMA_MODIFY_SRQ_MAX_RQE_MASK = 0xFFFF,
1094 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT = 16,
1095 OCRDMA_MODIFY_SRQ__LIMIT_MASK = 0xFFFF <<
1096 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
1097 };
1098
1099 struct ocrdma_modify_srq {
1100 struct ocrdma_mqe_hdr hdr;
1101 struct ocrdma_mbx_rsp rep;
1102
1103 u32 id;
1104 u32 limit_max_rqe;
1105 } __packed;
1106
1107 enum {
1108 OCRDMA_QUERY_SRQ_ID_SHIFT = 0,
1109 OCRDMA_QUERY_SRQ_ID_MASK = 0xFFFFFF
1110 };
1111
1112 struct ocrdma_query_srq {
1113 struct ocrdma_mqe_hdr hdr;
1114 struct ocrdma_mbx_rsp req;
1115
1116 u32 id;
1117 } __packed;
1118
1119 enum {
1120 OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT = 0,
1121 OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK = 0xFFFF,
1122 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT = 16,
1123 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK = 0xFFFF <<
1124 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,
1125
1126 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0,
1127 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK = 0xFFFF,
1128 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT = 16,
1129 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK = 0xFFFF <<
1130 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
1131 };
1132
1133 struct ocrdma_query_srq_rsp {
1134 struct ocrdma_mqe_hdr hdr;
1135 struct ocrdma_mbx_rsp req;
1136
1137 u32 max_rqe_pdid;
1138 u32 srq_lmt_max_sge;
1139 } __packed;
1140
1141 enum {
1142 OCRDMA_DESTROY_SRQ_ID_SHIFT = 0,
1143 OCRDMA_DESTROY_SRQ_ID_MASK = 0xFFFFFF
1144 };
1145
1146 struct ocrdma_destroy_srq {
1147 struct ocrdma_mqe_hdr hdr;
1148 struct ocrdma_mbx_rsp req;
1149
1150 u32 id;
1151 } __packed;
1152
1153 enum {
1154 OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16),
1155 OCRDMA_PD_MAX_DPP_ENABLED_QP = 8,
1156 OCRDMA_DPP_PAGE_SIZE = 4096
1157 };
1158
1159 struct ocrdma_alloc_pd {
1160 struct ocrdma_mqe_hdr hdr;
1161 struct ocrdma_mbx_hdr req;
1162 u32 enable_dpp_rsvd;
1163 } __packed;
1164
1165 enum {
1166 OCRDMA_ALLOC_PD_RSP_DPP = Bit(16),
1167 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20,
1168 OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF,
1169 };
1170
1171 struct ocrdma_alloc_pd_rsp {
1172 struct ocrdma_mqe_hdr hdr;
1173 struct ocrdma_mbx_rsp rsp;
1174 u32 dpp_page_pdid;
1175 } __packed;
1176
1177 struct ocrdma_dealloc_pd {
1178 struct ocrdma_mqe_hdr hdr;
1179 struct ocrdma_mbx_hdr req;
1180 u32 id;
1181 } __packed;
1182
1183 struct ocrdma_dealloc_pd_rsp {
1184 struct ocrdma_mqe_hdr hdr;
1185 struct ocrdma_mbx_rsp rsp;
1186 } __packed;
1187
1188 enum {
1189 OCRDMA_ADDR_CHECK_ENABLE = 1,
1190 OCRDMA_ADDR_CHECK_DISABLE = 0
1191 };
1192
1193 enum {
1194 OCRDMA_ALLOC_LKEY_PD_ID_SHIFT = 0,
1195 OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF,
1196
1197 OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0,
1198 OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = Bit(0),
1199 OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1,
1200 OCRDMA_ALLOC_LKEY_FMR_MASK = Bit(1),
1201 OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2,
1202 OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = Bit(2),
1203 OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3,
1204 OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = Bit(3),
1205 OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4,
1206 OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = Bit(4),
1207 OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5,
1208 OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = Bit(5),
1209 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = Bit(6),
1210 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6,
1211 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16,
1212 OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK = 0xFFFF <<
1213 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
1214 };
1215
1216 struct ocrdma_alloc_lkey {
1217 struct ocrdma_mqe_hdr hdr;
1218 struct ocrdma_mbx_hdr req;
1219
1220 u32 pdid;
1221 u32 pbl_sz_flags;
1222 } __packed;
1223
1224 struct ocrdma_alloc_lkey_rsp {
1225 struct ocrdma_mqe_hdr hdr;
1226 struct ocrdma_mbx_rsp rsp;
1227
1228 u32 lrkey;
1229 u32 num_pbl_rsvd;
1230 } __packed;
1231
1232 struct ocrdma_dealloc_lkey {
1233 struct ocrdma_mqe_hdr hdr;
1234 struct ocrdma_mbx_hdr req;
1235
1236 u32 lkey;
1237 u32 rsvd_frmr;
1238 } __packed;
1239
1240 struct ocrdma_dealloc_lkey_rsp {
1241 struct ocrdma_mqe_hdr hdr;
1242 struct ocrdma_mbx_rsp rsp;
1243 } __packed;
1244
1245 #define MAX_OCRDMA_NSMR_PBL (u32)22
1246 #define MAX_OCRDMA_PBL_SIZE 65536
1247 #define MAX_OCRDMA_PBL_PER_LKEY 32767
1248
1249 enum {
1250 OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT = 0,
1251 OCRDMA_REG_NSMR_LRKEY_INDEX_MASK = 0xFFFFFF,
1252 OCRDMA_REG_NSMR_LRKEY_SHIFT = 24,
1253 OCRDMA_REG_NSMR_LRKEY_MASK = 0xFF <<
1254 OCRDMA_REG_NSMR_LRKEY_SHIFT,
1255
1256 OCRDMA_REG_NSMR_PD_ID_SHIFT = 0,
1257 OCRDMA_REG_NSMR_PD_ID_MASK = 0xFFFF,
1258 OCRDMA_REG_NSMR_NUM_PBL_SHIFT = 16,
1259 OCRDMA_REG_NSMR_NUM_PBL_MASK = 0xFFFF <<
1260 OCRDMA_REG_NSMR_NUM_PBL_SHIFT,
1261
1262 OCRDMA_REG_NSMR_PBE_SIZE_SHIFT = 0,
1263 OCRDMA_REG_NSMR_PBE_SIZE_MASK = 0xFFFF,
1264 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT = 16,
1265 OCRDMA_REG_NSMR_HPAGE_SIZE_MASK = 0xFF <<
1266 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
1267 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24,
1268 OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = Bit(24),
1269 OCRDMA_REG_NSMR_ZB_SHIFT = 25,
1270 OCRDMA_REG_NSMR_ZB_SHIFT_MASK = Bit(25),
1271 OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26,
1272 OCRDMA_REG_NSMR_REMOTE_INV_MASK = Bit(26),
1273 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27,
1274 OCRDMA_REG_NSMR_REMOTE_WR_MASK = Bit(27),
1275 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28,
1276 OCRDMA_REG_NSMR_REMOTE_RD_MASK = Bit(28),
1277 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29,
1278 OCRDMA_REG_NSMR_LOCAL_WR_MASK = Bit(29),
1279 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30,
1280 OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = Bit(30),
1281 OCRDMA_REG_NSMR_LAST_SHIFT = 31,
1282 OCRDMA_REG_NSMR_LAST_MASK = Bit(31)
1283 };
1284
1285 struct ocrdma_reg_nsmr {
1286 struct ocrdma_mqe_hdr hdr;
1287 struct ocrdma_mbx_hdr cmd;
1288
1289 u32 lrkey_key_index;
1290 u32 num_pbl_pdid;
1291 u32 flags_hpage_pbe_sz;
1292 u32 totlen_low;
1293 u32 totlen_high;
1294 u32 fbo_low;
1295 u32 fbo_high;
1296 u32 va_loaddr;
1297 u32 va_hiaddr;
1298 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1299 } __packed;
1300
1301 enum {
1302 OCRDMA_REG_NSMR_CONT_PBL_SHIFT = 0,
1303 OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK = 0xFFFF,
1304 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT = 16,
1305 OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK = 0xFFFF <<
1306 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
1307
1308 OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31,
1309 OCRDMA_REG_NSMR_CONT_LAST_MASK = Bit(31)
1310 };
1311
1312 struct ocrdma_reg_nsmr_cont {
1313 struct ocrdma_mqe_hdr hdr;
1314 struct ocrdma_mbx_hdr cmd;
1315
1316 u32 lrkey;
1317 u32 num_pbl_offset;
1318 u32 last;
1319
1320 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1321 } __packed;
1322
1323 struct ocrdma_pbe {
1324 u32 pa_hi;
1325 u32 pa_lo;
1326 } __packed;
1327
1328 enum {
1329 OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT = 16,
1330 OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK = 0xFFFF0000
1331 };
1332 struct ocrdma_reg_nsmr_rsp {
1333 struct ocrdma_mqe_hdr hdr;
1334 struct ocrdma_mbx_rsp rsp;
1335
1336 u32 lrkey;
1337 u32 num_pbl;
1338 } __packed;
1339
1340 enum {
1341 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT = 0,
1342 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK = 0xFFFFFF,
1343 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT = 24,
1344 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK = 0xFF <<
1345 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,
1346
1347 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT = 16,
1348 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK = 0xFFFF <<
1349 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
1350 };
1351
1352 struct ocrdma_reg_nsmr_cont_rsp {
1353 struct ocrdma_mqe_hdr hdr;
1354 struct ocrdma_mbx_rsp rsp;
1355
1356 u32 lrkey_key_index;
1357 u32 num_pbl;
1358 } __packed;
1359
1360 enum {
1361 OCRDMA_ALLOC_MW_PD_ID_SHIFT = 0,
1362 OCRDMA_ALLOC_MW_PD_ID_MASK = 0xFFFF
1363 };
1364
1365 struct ocrdma_alloc_mw {
1366 struct ocrdma_mqe_hdr hdr;
1367 struct ocrdma_mbx_hdr req;
1368
1369 u32 pdid;
1370 } __packed;
1371
1372 enum {
1373 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT = 0,
1374 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK = 0xFFFFFF
1375 };
1376
1377 struct ocrdma_alloc_mw_rsp {
1378 struct ocrdma_mqe_hdr hdr;
1379 struct ocrdma_mbx_rsp rsp;
1380
1381 u32 lrkey_index;
1382 } __packed;
1383
1384 struct ocrdma_attach_mcast {
1385 struct ocrdma_mqe_hdr hdr;
1386 struct ocrdma_mbx_hdr req;
1387 u32 qp_id;
1388 u8 mgid[16];
1389 u32 mac_b0_to_b3;
1390 u32 vlan_mac_b4_to_b5;
1391 } __packed;
1392
1393 struct ocrdma_attach_mcast_rsp {
1394 struct ocrdma_mqe_hdr hdr;
1395 struct ocrdma_mbx_rsp rsp;
1396 } __packed;
1397
1398 struct ocrdma_detach_mcast {
1399 struct ocrdma_mqe_hdr hdr;
1400 struct ocrdma_mbx_hdr req;
1401 u32 qp_id;
1402 u8 mgid[16];
1403 u32 mac_b0_to_b3;
1404 u32 vlan_mac_b4_to_b5;
1405 } __packed;
1406
1407 struct ocrdma_detach_mcast_rsp {
1408 struct ocrdma_mqe_hdr hdr;
1409 struct ocrdma_mbx_rsp rsp;
1410 } __packed;
1411
1412 enum {
1413 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT = 19,
1414 OCRDMA_CREATE_AH_NUM_PAGES_MASK = 0xF <<
1415 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,
1416
1417 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT = 16,
1418 OCRDMA_CREATE_AH_PAGE_SIZE_MASK = 0x7 <<
1419 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,
1420
1421 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT = 23,
1422 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK = 0x1FF <<
1423 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,
1424 };
1425
1426 #define OCRDMA_AH_TBL_PAGES 8
1427
1428 struct ocrdma_create_ah_tbl {
1429 struct ocrdma_mqe_hdr hdr;
1430 struct ocrdma_mbx_hdr req;
1431
1432 u32 ah_conf;
1433 struct ocrdma_pa tbl_addr[8];
1434 } __packed;
1435
1436 struct ocrdma_create_ah_tbl_rsp {
1437 struct ocrdma_mqe_hdr hdr;
1438 struct ocrdma_mbx_rsp rsp;
1439 u32 ahid;
1440 } __packed;
1441
1442 struct ocrdma_delete_ah_tbl {
1443 struct ocrdma_mqe_hdr hdr;
1444 struct ocrdma_mbx_hdr req;
1445 u32 ahid;
1446 } __packed;
1447
1448 struct ocrdma_delete_ah_tbl_rsp {
1449 struct ocrdma_mqe_hdr hdr;
1450 struct ocrdma_mbx_rsp rsp;
1451 } __packed;
1452
1453 enum {
1454 OCRDMA_EQE_VALID_SHIFT = 0,
1455 OCRDMA_EQE_VALID_MASK = Bit(0),
1456 OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE,
1457 OCRDMA_EQE_RESOURCE_ID_SHIFT = 16,
1458 OCRDMA_EQE_RESOURCE_ID_MASK = 0xFFFF <<
1459 OCRDMA_EQE_RESOURCE_ID_SHIFT,
1460 };
1461
1462 struct ocrdma_eqe {
1463 u32 id_valid;
1464 } __packed;
1465
1466 enum OCRDMA_CQE_STATUS {
1467 OCRDMA_CQE_SUCCESS = 0,
1468 OCRDMA_CQE_LOC_LEN_ERR,
1469 OCRDMA_CQE_LOC_QP_OP_ERR,
1470 OCRDMA_CQE_LOC_EEC_OP_ERR,
1471 OCRDMA_CQE_LOC_PROT_ERR,
1472 OCRDMA_CQE_WR_FLUSH_ERR,
1473 OCRDMA_CQE_MW_BIND_ERR,
1474 OCRDMA_CQE_BAD_RESP_ERR,
1475 OCRDMA_CQE_LOC_ACCESS_ERR,
1476 OCRDMA_CQE_REM_INV_REQ_ERR,
1477 OCRDMA_CQE_REM_ACCESS_ERR,
1478 OCRDMA_CQE_REM_OP_ERR,
1479 OCRDMA_CQE_RETRY_EXC_ERR,
1480 OCRDMA_CQE_RNR_RETRY_EXC_ERR,
1481 OCRDMA_CQE_LOC_RDD_VIOL_ERR,
1482 OCRDMA_CQE_REM_INV_RD_REQ_ERR,
1483 OCRDMA_CQE_REM_ABORT_ERR,
1484 OCRDMA_CQE_INV_EECN_ERR,
1485 OCRDMA_CQE_INV_EEC_STATE_ERR,
1486 OCRDMA_CQE_FATAL_ERR,
1487 OCRDMA_CQE_RESP_TIMEOUT_ERR,
1488 OCRDMA_CQE_GENERAL_ERR
1489 };
1490
1491 enum {
1492 /* w0 */
1493 OCRDMA_CQE_WQEIDX_SHIFT = 0,
1494 OCRDMA_CQE_WQEIDX_MASK = 0xFFFF,
1495
1496 /* w1 */
1497 OCRDMA_CQE_UD_XFER_LEN_SHIFT = 16,
1498 OCRDMA_CQE_PKEY_SHIFT = 0,
1499 OCRDMA_CQE_PKEY_MASK = 0xFFFF,
1500
1501 /* w2 */
1502 OCRDMA_CQE_QPN_SHIFT = 0,
1503 OCRDMA_CQE_QPN_MASK = 0x0000FFFF,
1504
1505 OCRDMA_CQE_BUFTAG_SHIFT = 16,
1506 OCRDMA_CQE_BUFTAG_MASK = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT,
1507
1508 /* w3 */
1509 OCRDMA_CQE_UD_STATUS_SHIFT = 24,
1510 OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
1511 OCRDMA_CQE_STATUS_SHIFT = 16,
1512 OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT,
1513 OCRDMA_CQE_VALID = Bit(31),
1514 OCRDMA_CQE_INVALIDATE = Bit(30),
1515 OCRDMA_CQE_QTYPE = Bit(29),
1516 OCRDMA_CQE_IMM = Bit(28),
1517 OCRDMA_CQE_WRITE_IMM = Bit(27),
1518 OCRDMA_CQE_QTYPE_SQ = 0,
1519 OCRDMA_CQE_QTYPE_RQ = 1,
1520 OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF
1521 };
1522
1523 struct ocrdma_cqe {
1524 union {
1525 /* w0 to w2 */
1526 struct {
1527 u32 wqeidx;
1528 u32 bytes_xfered;
1529 u32 qpn;
1530 } wq;
1531 struct {
1532 u32 lkey_immdt;
1533 u32 rxlen;
1534 u32 buftag_qpn;
1535 } rq;
1536 struct {
1537 u32 lkey_immdt;
1538 u32 rxlen_pkey;
1539 u32 buftag_qpn;
1540 } ud;
1541 struct {
1542 u32 word_0;
1543 u32 word_1;
1544 u32 qpn;
1545 } cmn;
1546 };
1547 u32 flags_status_srcqpn; /* w3 */
1548 } __packed;
1549
1550 #define is_cqe_valid(cq, cqe) \
1551 (((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_VALID)\
1552 == cq->phase) ? 1 : 0)
1553 #define is_cqe_for_sq(cqe) \
1554 ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_QTYPE) ? 0 : 1)
1555 #define is_cqe_for_rq(cqe) \
1556 ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_QTYPE) ? 1 : 0)
1557 #define is_cqe_invalidated(cqe) \
1558 ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_INVALIDATE) ? \
1559 1 : 0)
1560 #define is_cqe_imm(cqe) \
1561 ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_IMM) ? 1 : 0)
1562 #define is_cqe_wr_imm(cqe) \
1563 ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_WRITE_IMM) ? 1 : 0)
1564
1565 struct ocrdma_sge {
1566 u32 addr_hi;
1567 u32 addr_lo;
1568 u32 lrkey;
1569 u32 len;
1570 } __packed;
1571
1572 enum {
1573 OCRDMA_FLAG_SIG = 0x1,
1574 OCRDMA_FLAG_INV = 0x2,
1575 OCRDMA_FLAG_FENCE_L = 0x4,
1576 OCRDMA_FLAG_FENCE_R = 0x8,
1577 OCRDMA_FLAG_SOLICIT = 0x10,
1578 OCRDMA_FLAG_IMM = 0x20,
1579
1580 /* Stag flags */
1581 OCRDMA_LKEY_FLAG_LOCAL_WR = 0x1,
1582 OCRDMA_LKEY_FLAG_REMOTE_RD = 0x2,
1583 OCRDMA_LKEY_FLAG_REMOTE_WR = 0x4,
1584 OCRDMA_LKEY_FLAG_VATO = 0x8,
1585 };
1586
1587 enum OCRDMA_WQE_OPCODE {
1588 OCRDMA_WRITE = 0x06,
1589 OCRDMA_READ = 0x0C,
1590 OCRDMA_RESV0 = 0x02,
1591 OCRDMA_SEND = 0x00,
1592 OCRDMA_CMP_SWP = 0x14,
1593 OCRDMA_BIND_MW = 0x10,
1594 OCRDMA_RESV1 = 0x0A,
1595 OCRDMA_LKEY_INV = 0x15,
1596 OCRDMA_FETCH_ADD = 0x13,
1597 OCRDMA_POST_RQ = 0x12
1598 };
1599
1600 enum {
1601 OCRDMA_TYPE_INLINE = 0x0,
1602 OCRDMA_TYPE_LKEY = 0x1,
1603 };
1604
1605 enum {
1606 OCRDMA_WQE_OPCODE_SHIFT = 0,
1607 OCRDMA_WQE_OPCODE_MASK = 0x0000001F,
1608 OCRDMA_WQE_FLAGS_SHIFT = 5,
1609 OCRDMA_WQE_TYPE_SHIFT = 16,
1610 OCRDMA_WQE_TYPE_MASK = 0x00030000,
1611 OCRDMA_WQE_SIZE_SHIFT = 18,
1612 OCRDMA_WQE_SIZE_MASK = 0xFF,
1613 OCRDMA_WQE_NXT_WQE_SIZE_SHIFT = 25,
1614
1615 OCRDMA_WQE_LKEY_FLAGS_SHIFT = 0,
1616 OCRDMA_WQE_LKEY_FLAGS_MASK = 0xF
1617 };
1618
1619 /* header WQE for all the SQ and RQ operations */
1620 struct ocrdma_hdr_wqe {
1621 u32 cw;
1622 union {
1623 u32 rsvd_tag;
1624 u32 rsvd_lkey_flags;
1625 };
1626 union {
1627 u32 immdt;
1628 u32 lkey;
1629 };
1630 u32 total_len;
1631 } __packed;
1632
1633 struct ocrdma_ewqe_ud_hdr {
1634 u32 rsvd_dest_qpn;
1635 u32 qkey;
1636 u32 rsvd_ahid;
1637 u32 rsvd;
1638 } __packed;
1639
1640 struct ocrdma_eth_basic {
1641 u8 dmac[6];
1642 u8 smac[6];
1643 __be16 eth_type;
1644 } __packed;
1645
1646 struct ocrdma_eth_vlan {
1647 u8 dmac[6];
1648 u8 smac[6];
1649 __be16 eth_type;
1650 __be16 vlan_tag;
1651 #define OCRDMA_ROCE_ETH_TYPE 0x8915
1652 __be16 roce_eth_type;
1653 } __packed;
1654
1655 struct ocrdma_grh {
1656 __be32 tclass_flow;
1657 __be32 pdid_hoplimit;
1658 u8 sgid[16];
1659 u8 dgid[16];
1660 u16 rsvd;
1661 } __packed;
1662
1663 #define OCRDMA_AV_VALID Bit(0)
1664 #define OCRDMA_AV_VLAN_VALID Bit(1)
1665
1666 struct ocrdma_av {
1667 struct ocrdma_eth_vlan eth_hdr;
1668 struct ocrdma_grh grh;
1669 u32 valid;
1670 } __packed;
1671
1672 #endif /* __OCRDMA_SLI_H__ */
Linux kernel - Deliverables
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