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[deliverable/linux.git] / drivers / infiniband / hw / qib / qib_iba7322.c
1 /*
2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 /*
34 * This file contains all of the code that is specific to the
35 * InfiniPath 7322 chip
36 */
37
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/io.h>
42 #include <linux/jiffies.h>
43 #include <rdma/ib_verbs.h>
44 #include <rdma/ib_smi.h>
45
46 #include "qib.h"
47 #include "qib_7322_regs.h"
48 #include "qib_qsfp.h"
49
50 #include "qib_mad.h"
51
52 static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
53 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
54 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
55 static irqreturn_t qib_7322intr(int irq, void *data);
56 static irqreturn_t qib_7322bufavail(int irq, void *data);
57 static irqreturn_t sdma_intr(int irq, void *data);
58 static irqreturn_t sdma_idle_intr(int irq, void *data);
59 static irqreturn_t sdma_progress_intr(int irq, void *data);
60 static irqreturn_t sdma_cleanup_intr(int irq, void *data);
61 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
62 struct qib_ctxtdata *rcd);
63 static u8 qib_7322_phys_portstate(u64);
64 static u32 qib_7322_iblink_state(u64);
65 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
66 u16 linitcmd);
67 static void force_h1(struct qib_pportdata *);
68 static void adj_tx_serdes(struct qib_pportdata *);
69 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
70 static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
71
72 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
73 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
74 static void serdes_7322_los_enable(struct qib_pportdata *, int);
75 static int serdes_7322_init_old(struct qib_pportdata *);
76 static int serdes_7322_init_new(struct qib_pportdata *);
77
78 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
79
80 /* LE2 serdes values for different cases */
81 #define LE2_DEFAULT 5
82 #define LE2_5m 4
83 #define LE2_QME 0
84
85 /* Below is special-purpose, so only really works for the IB SerDes blocks. */
86 #define IBSD(hw_pidx) (hw_pidx + 2)
87
88 /* these are variables for documentation and experimentation purposes */
89 static const unsigned rcv_int_timeout = 375;
90 static const unsigned rcv_int_count = 16;
91 static const unsigned sdma_idle_cnt = 64;
92
93 /* Time to stop altering Rx Equalization parameters, after link up. */
94 #define RXEQ_DISABLE_MSECS 2500
95
96 /*
97 * Number of VLs we are configured to use (to allow for more
98 * credits per vl, etc.)
99 */
100 ushort qib_num_cfg_vls = 2;
101 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
102 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
103
104 static ushort qib_chase = 1;
105 module_param_named(chase, qib_chase, ushort, S_IRUGO);
106 MODULE_PARM_DESC(chase, "Enable state chase handling");
107
108 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
109 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
110 MODULE_PARM_DESC(long_attenuation, \
111 "attenuation cutoff (dB) for long copper cable setup");
112
113 static ushort qib_singleport;
114 module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
115 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
116
117 /*
118 * Receive header queue sizes
119 */
120 static unsigned qib_rcvhdrcnt;
121 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
122 MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
123
124 static unsigned qib_rcvhdrsize;
125 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
126 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
127
128 static unsigned qib_rcvhdrentsize;
129 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
130 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
131
132 #define MAX_ATTEN_LEN 64 /* plenty for any real system */
133 /* for read back, default index is ~5m copper cable */
134 static char txselect_list[MAX_ATTEN_LEN] = "10";
135 static struct kparam_string kp_txselect = {
136 .string = txselect_list,
137 .maxlen = MAX_ATTEN_LEN
138 };
139 static int setup_txselect(const char *, struct kernel_param *);
140 module_param_call(txselect, setup_txselect, param_get_string,
141 &kp_txselect, S_IWUSR | S_IRUGO);
142 MODULE_PARM_DESC(txselect, \
143 "Tx serdes indices (for no QSFP or invalid QSFP data)");
144
145 #define BOARD_QME7342 5
146 #define BOARD_QMH7342 6
147 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
148 BOARD_QMH7342)
149 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
150 BOARD_QME7342)
151
152 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
153
154 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
155
156 #define MASK_ACROSS(lsb, msb) \
157 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
158
159 #define SYM_RMASK(regname, fldname) ((u64) \
160 QIB_7322_##regname##_##fldname##_RMASK)
161
162 #define SYM_MASK(regname, fldname) ((u64) \
163 QIB_7322_##regname##_##fldname##_RMASK << \
164 QIB_7322_##regname##_##fldname##_LSB)
165
166 #define SYM_FIELD(value, regname, fldname) ((u64) \
167 (((value) >> SYM_LSB(regname, fldname)) & \
168 SYM_RMASK(regname, fldname)))
169
170 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
171 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
172 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
173
174 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
175 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
176 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
177 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
178 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
179 /* Below because most, but not all, fields of IntMask have that full suffix */
180 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
181
182
183 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
184
185 /*
186 * the size bits give us 2^N, in KB units. 0 marks as invalid,
187 * and 7 is reserved. We currently use only 2KB and 4KB
188 */
189 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
190 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
191 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
192 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
193
194 #define SendIBSLIDAssignMask \
195 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
196 #define SendIBSLMCMask \
197 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
198
199 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
200 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
201 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
202 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
203 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
204 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
205
206 #define _QIB_GPIO_SDA_NUM 1
207 #define _QIB_GPIO_SCL_NUM 0
208 #define QIB_EEPROM_WEN_NUM 14
209 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
210
211 /* HW counter clock is at 4nsec */
212 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
213
214 /* full speed IB port 1 only */
215 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
216 #define PORT_SPD_CAP_SHIFT 3
217
218 /* full speed featuremask, both ports */
219 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
220
221 /*
222 * This file contains almost all the chip-specific register information and
223 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
224 */
225
226 /* Use defines to tie machine-generated names to lower-case names */
227 #define kr_contextcnt KREG_IDX(ContextCnt)
228 #define kr_control KREG_IDX(Control)
229 #define kr_counterregbase KREG_IDX(CntrRegBase)
230 #define kr_errclear KREG_IDX(ErrClear)
231 #define kr_errmask KREG_IDX(ErrMask)
232 #define kr_errstatus KREG_IDX(ErrStatus)
233 #define kr_extctrl KREG_IDX(EXTCtrl)
234 #define kr_extstatus KREG_IDX(EXTStatus)
235 #define kr_gpio_clear KREG_IDX(GPIOClear)
236 #define kr_gpio_mask KREG_IDX(GPIOMask)
237 #define kr_gpio_out KREG_IDX(GPIOOut)
238 #define kr_gpio_status KREG_IDX(GPIOStatus)
239 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
240 #define kr_debugportval KREG_IDX(DebugPortValueReg)
241 #define kr_fmask KREG_IDX(feature_mask)
242 #define kr_act_fmask KREG_IDX(active_feature_mask)
243 #define kr_hwerrclear KREG_IDX(HwErrClear)
244 #define kr_hwerrmask KREG_IDX(HwErrMask)
245 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
246 #define kr_intclear KREG_IDX(IntClear)
247 #define kr_intmask KREG_IDX(IntMask)
248 #define kr_intredirect KREG_IDX(IntRedirect0)
249 #define kr_intstatus KREG_IDX(IntStatus)
250 #define kr_pagealign KREG_IDX(PageAlign)
251 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
252 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
253 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
254 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
255 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
256 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
257 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
258 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
259 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
260 #define kr_revision KREG_IDX(Revision)
261 #define kr_scratch KREG_IDX(Scratch)
262 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
263 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
264 #define kr_sendctrl KREG_IDX(SendCtrl)
265 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
266 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
267 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
268 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
269 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
270 #define kr_sendpiosize KREG_IDX(SendBufSize)
271 #define kr_sendregbase KREG_IDX(SendRegBase)
272 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
273 #define kr_userregbase KREG_IDX(UserRegBase)
274 #define kr_intgranted KREG_IDX(Int_Granted)
275 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
276 #define kr_intblocked KREG_IDX(IntBlocked)
277 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
278
279 /*
280 * per-port kernel registers. Access only with qib_read_kreg_port()
281 * or qib_write_kreg_port()
282 */
283 #define krp_errclear KREG_IBPORT_IDX(ErrClear)
284 #define krp_errmask KREG_IBPORT_IDX(ErrMask)
285 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
286 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
287 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
288 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
289 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
290 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
291 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
292 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
293 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
294 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
295 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
296 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
297 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
298 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
299 #define krp_psinterval KREG_IBPORT_IDX(PSInterval)
300 #define krp_psstart KREG_IBPORT_IDX(PSStart)
301 #define krp_psstat KREG_IBPORT_IDX(PSStat)
302 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
303 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
304 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
305 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
306 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
307 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
308 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
309 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
310 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
311 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
312 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
313 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
314 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
315 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
316 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
317 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
318 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
319 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
320 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
321 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
322 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
323 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
324 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
325 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
326 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
327 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
328 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
329 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
330 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
331 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
332 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
333
334 /*
335 * Per-context kernel registers. Access only with qib_read_kreg_ctxt()
336 * or qib_write_kreg_ctxt()
337 */
338 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
339 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
340
341 /*
342 * TID Flow table, per context. Reduces
343 * number of hdrq updates to one per flow (or on errors).
344 * context 0 and 1 share same memory, but have distinct
345 * addresses. Since for now, we never use expected sends
346 * on kernel contexts, we don't worry about that (we initialize
347 * those entries for ctxt 0/1 on driver load twice, for example).
348 */
349 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
350 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
351
352 /* these are the error bits in the tid flows, and are W1C */
353 #define TIDFLOW_ERRBITS ( \
354 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
355 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
356 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
357 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
358
359 /* Most (not all) Counters are per-IBport.
360 * Requires LBIntCnt is at offset 0 in the group
361 */
362 #define CREG_IDX(regname) \
363 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
364
365 #define crp_badformat CREG_IDX(RxVersionErrCnt)
366 #define crp_err_rlen CREG_IDX(RxLenErrCnt)
367 #define crp_erricrc CREG_IDX(RxICRCErrCnt)
368 #define crp_errlink CREG_IDX(RxLinkMalformCnt)
369 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
370 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
371 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
372 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
373 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
374 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
375 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
376 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
377 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
378 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
379 #define crp_pktrcv CREG_IDX(RxDataPktCnt)
380 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
381 #define crp_pktsend CREG_IDX(TxDataPktCnt)
382 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
383 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
384 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
385 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
386 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
387 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
388 #define crp_rcvebp CREG_IDX(RxEBPCnt)
389 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
390 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
391 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
392 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
393 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
394 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
395 #define crp_rxvlerr CREG_IDX(RxVlErrCnt)
396 #define crp_sendstall CREG_IDX(TxFlowStallCnt)
397 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
398 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
399 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
400 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
401 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
402 #define crp_txunderrun CREG_IDX(TxUnderrunCnt)
403 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
404 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
405 #define crp_wordrcv CREG_IDX(RxDwordCnt)
406 #define crp_wordsend CREG_IDX(TxDwordCnt)
407 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
408
409 /* these are the (few) counters that are not port-specific */
410 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
411 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
412 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
413 #define cr_lbint CREG_DEVIDX(LBIntCnt)
414 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
415 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
416 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
417 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
418 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
419
420 /* no chip register for # of IB ports supported, so define */
421 #define NUM_IB_PORTS 2
422
423 /* 1 VL15 buffer per hardware IB port, no register for this, so define */
424 #define NUM_VL15_BUFS NUM_IB_PORTS
425
426 /*
427 * context 0 and 1 are special, and there is no chip register that
428 * defines this value, so we have to define it here.
429 * These are all allocated to either 0 or 1 for single port
430 * hardware configuration, otherwise each gets half
431 */
432 #define KCTXT0_EGRCNT 2048
433
434 /* values for vl and port fields in PBC, 7322-specific */
435 #define PBC_PORT_SEL_LSB 26
436 #define PBC_PORT_SEL_RMASK 1
437 #define PBC_VL_NUM_LSB 27
438 #define PBC_VL_NUM_RMASK 7
439 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
440 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
441
442 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
443 [IB_RATE_2_5_GBPS] = 16,
444 [IB_RATE_5_GBPS] = 8,
445 [IB_RATE_10_GBPS] = 4,
446 [IB_RATE_20_GBPS] = 2,
447 [IB_RATE_30_GBPS] = 2,
448 [IB_RATE_40_GBPS] = 1
449 };
450
451 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
452 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
453
454 /* link training states, from IBC */
455 #define IB_7322_LT_STATE_DISABLED 0x00
456 #define IB_7322_LT_STATE_LINKUP 0x01
457 #define IB_7322_LT_STATE_POLLACTIVE 0x02
458 #define IB_7322_LT_STATE_POLLQUIET 0x03
459 #define IB_7322_LT_STATE_SLEEPDELAY 0x04
460 #define IB_7322_LT_STATE_SLEEPQUIET 0x05
461 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
462 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09
463 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a
464 #define IB_7322_LT_STATE_CFGIDLE 0x0b
465 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
466 #define IB_7322_LT_STATE_TXREVLANES 0x0d
467 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
468 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f
469 #define IB_7322_LT_STATE_CFGENH 0x10
470 #define IB_7322_LT_STATE_CFGTEST 0x11
471 #define IB_7322_LT_STATE_CFGWAITRMTTEST 0x12
472 #define IB_7322_LT_STATE_CFGWAITENH 0x13
473
474 /* link state machine states from IBC */
475 #define IB_7322_L_STATE_DOWN 0x0
476 #define IB_7322_L_STATE_INIT 0x1
477 #define IB_7322_L_STATE_ARM 0x2
478 #define IB_7322_L_STATE_ACTIVE 0x3
479 #define IB_7322_L_STATE_ACT_DEFER 0x4
480
481 static const u8 qib_7322_physportstate[0x20] = {
482 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
483 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
484 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
485 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
486 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
487 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
488 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
489 [IB_7322_LT_STATE_CFGRCVFCFG] =
490 IB_PHYSPORTSTATE_CFG_TRAIN,
491 [IB_7322_LT_STATE_CFGWAITRMT] =
492 IB_PHYSPORTSTATE_CFG_TRAIN,
493 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
494 [IB_7322_LT_STATE_RECOVERRETRAIN] =
495 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
496 [IB_7322_LT_STATE_RECOVERWAITRMT] =
497 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
498 [IB_7322_LT_STATE_RECOVERIDLE] =
499 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
500 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
501 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
502 [IB_7322_LT_STATE_CFGWAITRMTTEST] =
503 IB_PHYSPORTSTATE_CFG_TRAIN,
504 [IB_7322_LT_STATE_CFGWAITENH] =
505 IB_PHYSPORTSTATE_CFG_WAIT_ENH,
506 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
507 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
508 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
509 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
510 };
511
512 struct qib_chip_specific {
513 u64 __iomem *cregbase;
514 u64 *cntrs;
515 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
516 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
517 u64 main_int_mask; /* clear bits which have dedicated handlers */
518 u64 int_enable_mask; /* for per port interrupts in single port mode */
519 u64 errormask;
520 u64 hwerrmask;
521 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
522 u64 gpio_mask; /* shadow the gpio mask register */
523 u64 extctrl; /* shadow the gpio output enable, etc... */
524 u32 ncntrs;
525 u32 nportcntrs;
526 u32 cntrnamelen;
527 u32 portcntrnamelen;
528 u32 numctxts;
529 u32 rcvegrcnt;
530 u32 updthresh; /* current AvailUpdThld */
531 u32 updthresh_dflt; /* default AvailUpdThld */
532 u32 r1;
533 int irq;
534 u32 num_msix_entries;
535 u32 sdmabufcnt;
536 u32 lastbuf_for_pio;
537 u32 stay_in_freeze;
538 u32 recovery_ports_initted;
539 struct msix_entry *msix_entries;
540 void **msix_arg;
541 unsigned long *sendchkenable;
542 unsigned long *sendgrhchk;
543 unsigned long *sendibchk;
544 u32 rcvavail_timeout[18];
545 char emsgbuf[128]; /* for device error interrupt msg buffer */
546 };
547
548 /* Table of entries in "human readable" form Tx Emphasis. */
549 struct txdds_ent {
550 u8 amp;
551 u8 pre;
552 u8 main;
553 u8 post;
554 };
555
556 struct vendor_txdds_ent {
557 u8 oui[QSFP_VOUI_LEN];
558 u8 *partnum;
559 struct txdds_ent sdr;
560 struct txdds_ent ddr;
561 struct txdds_ent qdr;
562 };
563
564 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
565
566 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
567 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */
568 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */
569 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
570
571 #define H1_FORCE_VAL 8
572 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
573 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
574
575 /* The static and dynamic registers are paired, and the pairs indexed by spd */
576 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
577 + ((spd) * 2))
578
579 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
580 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
581 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
582 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
583 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
584
585 struct qib_chippport_specific {
586 u64 __iomem *kpregbase;
587 u64 __iomem *cpregbase;
588 u64 *portcntrs;
589 struct qib_pportdata *ppd;
590 wait_queue_head_t autoneg_wait;
591 struct delayed_work autoneg_work;
592 struct delayed_work ipg_work;
593 struct timer_list chase_timer;
594 /*
595 * these 5 fields are used to establish deltas for IB symbol
596 * errors and linkrecovery errors. They can be reported on
597 * some chips during link negotiation prior to INIT, and with
598 * DDR when faking DDR negotiations with non-IBTA switches.
599 * The chip counters are adjusted at driver unload if there is
600 * a non-zero delta.
601 */
602 u64 ibdeltainprog;
603 u64 ibsymdelta;
604 u64 ibsymsnap;
605 u64 iblnkerrdelta;
606 u64 iblnkerrsnap;
607 u64 iblnkdownsnap;
608 u64 iblnkdowndelta;
609 u64 ibmalfdelta;
610 u64 ibmalfsnap;
611 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
612 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
613 u64 qdr_dfe_time;
614 u64 chase_end;
615 u32 autoneg_tries;
616 u32 recovery_init;
617 u32 qdr_dfe_on;
618 u32 qdr_reforce;
619 /*
620 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
621 * entry zero is unused, to simplify indexing
622 */
623 u8 h1_val;
624 u8 no_eep; /* txselect table index to use if no qsfp info */
625 u8 ipg_tries;
626 u8 ibmalfusesnap;
627 struct qib_qsfp_data qsfp_data;
628 char epmsgbuf[192]; /* for port error interrupt msg buffer */
629 };
630
631 static struct {
632 const char *name;
633 irq_handler_t handler;
634 int lsb;
635 int port; /* 0 if not port-specific, else port # */
636 } irq_table[] = {
637 { QIB_DRV_NAME, qib_7322intr, -1, 0 },
638 { QIB_DRV_NAME " (buf avail)", qib_7322bufavail,
639 SYM_LSB(IntStatus, SendBufAvail), 0 },
640 { QIB_DRV_NAME " (sdma 0)", sdma_intr,
641 SYM_LSB(IntStatus, SDmaInt_0), 1 },
642 { QIB_DRV_NAME " (sdma 1)", sdma_intr,
643 SYM_LSB(IntStatus, SDmaInt_1), 2 },
644 { QIB_DRV_NAME " (sdmaI 0)", sdma_idle_intr,
645 SYM_LSB(IntStatus, SDmaIdleInt_0), 1 },
646 { QIB_DRV_NAME " (sdmaI 1)", sdma_idle_intr,
647 SYM_LSB(IntStatus, SDmaIdleInt_1), 2 },
648 { QIB_DRV_NAME " (sdmaP 0)", sdma_progress_intr,
649 SYM_LSB(IntStatus, SDmaProgressInt_0), 1 },
650 { QIB_DRV_NAME " (sdmaP 1)", sdma_progress_intr,
651 SYM_LSB(IntStatus, SDmaProgressInt_1), 2 },
652 { QIB_DRV_NAME " (sdmaC 0)", sdma_cleanup_intr,
653 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1 },
654 { QIB_DRV_NAME " (sdmaC 1)", sdma_cleanup_intr,
655 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 },
656 };
657
658 /* ibcctrl bits */
659 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
660 /* cycle through TS1/TS2 till OK */
661 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
662 /* wait for TS1, then go on */
663 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
664 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
665
666 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
667 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
668 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
669
670 #define BLOB_7322_IBCHG 0x101
671
672 static inline void qib_write_kreg(const struct qib_devdata *dd,
673 const u32 regno, u64 value);
674 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
675 static void write_7322_initregs(struct qib_devdata *);
676 static void write_7322_init_portregs(struct qib_pportdata *);
677 static void setup_7322_link_recovery(struct qib_pportdata *, u32);
678 static void check_7322_rxe_status(struct qib_pportdata *);
679 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
680
681 /**
682 * qib_read_ureg32 - read 32-bit virtualized per-context register
683 * @dd: device
684 * @regno: register number
685 * @ctxt: context number
686 *
687 * Return the contents of a register that is virtualized to be per context.
688 * Returns -1 on errors (not distinguishable from valid contents at
689 * runtime; we may add a separate error variable at some point).
690 */
691 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
692 enum qib_ureg regno, int ctxt)
693 {
694 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
695 return 0;
696 return readl(regno + (u64 __iomem *)(
697 (dd->ureg_align * ctxt) + (dd->userbase ?
698 (char __iomem *)dd->userbase :
699 (char __iomem *)dd->kregbase + dd->uregbase)));
700 }
701
702 /**
703 * qib_read_ureg - read virtualized per-context register
704 * @dd: device
705 * @regno: register number
706 * @ctxt: context number
707 *
708 * Return the contents of a register that is virtualized to be per context.
709 * Returns -1 on errors (not distinguishable from valid contents at
710 * runtime; we may add a separate error variable at some point).
711 */
712 static inline u64 qib_read_ureg(const struct qib_devdata *dd,
713 enum qib_ureg regno, int ctxt)
714 {
715
716 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
717 return 0;
718 return readq(regno + (u64 __iomem *)(
719 (dd->ureg_align * ctxt) + (dd->userbase ?
720 (char __iomem *)dd->userbase :
721 (char __iomem *)dd->kregbase + dd->uregbase)));
722 }
723
724 /**
725 * qib_write_ureg - write virtualized per-context register
726 * @dd: device
727 * @regno: register number
728 * @value: value
729 * @ctxt: context
730 *
731 * Write the contents of a register that is virtualized to be per context.
732 */
733 static inline void qib_write_ureg(const struct qib_devdata *dd,
734 enum qib_ureg regno, u64 value, int ctxt)
735 {
736 u64 __iomem *ubase;
737 if (dd->userbase)
738 ubase = (u64 __iomem *)
739 ((char __iomem *) dd->userbase +
740 dd->ureg_align * ctxt);
741 else
742 ubase = (u64 __iomem *)
743 (dd->uregbase +
744 (char __iomem *) dd->kregbase +
745 dd->ureg_align * ctxt);
746
747 if (dd->kregbase && (dd->flags & QIB_PRESENT))
748 writeq(value, &ubase[regno]);
749 }
750
751 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
752 const u32 regno)
753 {
754 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
755 return -1;
756 return readl((u32 __iomem *) &dd->kregbase[regno]);
757 }
758
759 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
760 const u32 regno)
761 {
762 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
763 return -1;
764 return readq(&dd->kregbase[regno]);
765 }
766
767 static inline void qib_write_kreg(const struct qib_devdata *dd,
768 const u32 regno, u64 value)
769 {
770 if (dd->kregbase && (dd->flags & QIB_PRESENT))
771 writeq(value, &dd->kregbase[regno]);
772 }
773
774 /*
775 * not many sanity checks for the port-specific kernel register routines,
776 * since they are only used when it's known to be safe.
777 */
778 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
779 const u16 regno)
780 {
781 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
782 return 0ULL;
783 return readq(&ppd->cpspec->kpregbase[regno]);
784 }
785
786 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
787 const u16 regno, u64 value)
788 {
789 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
790 (ppd->dd->flags & QIB_PRESENT))
791 writeq(value, &ppd->cpspec->kpregbase[regno]);
792 }
793
794 /**
795 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
796 * @dd: the qlogic_ib device
797 * @regno: the register number to write
798 * @ctxt: the context containing the register
799 * @value: the value to write
800 */
801 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
802 const u16 regno, unsigned ctxt,
803 u64 value)
804 {
805 qib_write_kreg(dd, regno + ctxt, value);
806 }
807
808 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
809 {
810 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
811 return 0;
812 return readq(&dd->cspec->cregbase[regno]);
813
814
815 }
816
817 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
818 {
819 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
820 return 0;
821 return readl(&dd->cspec->cregbase[regno]);
822
823
824 }
825
826 static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
827 u16 regno, u64 value)
828 {
829 if (ppd->cpspec && ppd->cpspec->cpregbase &&
830 (ppd->dd->flags & QIB_PRESENT))
831 writeq(value, &ppd->cpspec->cpregbase[regno]);
832 }
833
834 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
835 u16 regno)
836 {
837 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
838 !(ppd->dd->flags & QIB_PRESENT))
839 return 0;
840 return readq(&ppd->cpspec->cpregbase[regno]);
841 }
842
843 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
844 u16 regno)
845 {
846 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
847 !(ppd->dd->flags & QIB_PRESENT))
848 return 0;
849 return readl(&ppd->cpspec->cpregbase[regno]);
850 }
851
852 /* bits in Control register */
853 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
854 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
855
856 /* bits in general interrupt regs */
857 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
858 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
859 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
860 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
861 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
862 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
863 #define QIB_I_C_ERROR INT_MASK(Err)
864
865 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
866 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
867 #define QIB_I_GPIO INT_MASK(AssertGPIO)
868 #define QIB_I_P_SDMAINT(pidx) \
869 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
870 INT_MASK_P(SDmaProgress, pidx) | \
871 INT_MASK_PM(SDmaCleanupDone, pidx))
872
873 /* Interrupt bits that are "per port" */
874 #define QIB_I_P_BITSEXTANT(pidx) \
875 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
876 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
877 INT_MASK_P(SDmaProgress, pidx) | \
878 INT_MASK_PM(SDmaCleanupDone, pidx))
879
880 /* Interrupt bits that are common to a device */
881 /* currently unused: QIB_I_SPIOSENT */
882 #define QIB_I_C_BITSEXTANT \
883 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
884 QIB_I_SPIOSENT | \
885 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
886
887 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
888 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
889
890 /*
891 * Error bits that are "per port".
892 */
893 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
894 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
895 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
896 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
897 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
898 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
899 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
900 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
901 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
902 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
903 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
904 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
905 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
906 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
907 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
908 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
909 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
910 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
911 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
912 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
913 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
914 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
915 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
916 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
917 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
918 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
919 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
920 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
921
922 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
923 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
924 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
925 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
926 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
927 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
928 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
929 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
930 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
931 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
932 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
933
934 /* Error bits that are common to a device */
935 #define QIB_E_RESET ERR_MASK(ResetNegated)
936 #define QIB_E_HARDWARE ERR_MASK(HardwareErr)
937 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
938
939
940 /*
941 * Per chip (rather than per-port) errors. Most either do
942 * nothing but trigger a print (because they self-recover, or
943 * always occur in tandem with other errors that handle the
944 * issue), or because they indicate errors with no recovery,
945 * but we want to know that they happened.
946 */
947 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
948 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
949 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
950 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
951 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
952 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
953 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
954 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
955
956 /* SDMA chip errors (not per port)
957 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
958 * the SDMAHALT error immediately, so we just print the dup error via the
959 * E_AUTO mechanism. This is true of most of the per-port fatal errors
960 * as well, but since this is port-independent, by definition, it's
961 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
962 * packet send errors, and so are handled in the same manner as other
963 * per-packet errors.
964 */
965 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
966 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
967 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
968
969 /*
970 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
971 * it is used to print "common" packet errors.
972 */
973 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
974 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
975 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
976 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
977 QIB_E_P_REBP)
978
979 /* Error Bits that Packet-related (Receive, per-port) */
980 #define QIB_E_P_RPKTERRS (\
981 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
982 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
983 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
984 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
985 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
986 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
987
988 /*
989 * Error bits that are Send-related (per port)
990 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
991 * All of these potentially need to have a buffer disarmed
992 */
993 #define QIB_E_P_SPKTERRS (\
994 QIB_E_P_SUNEXP_PKTNUM |\
995 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
996 QIB_E_P_SMAXPKTLEN |\
997 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
998 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
999 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
1000
1001 #define QIB_E_SPKTERRS ( \
1002 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1003 ERR_MASK_N(SendUnsupportedVLErr) | \
1004 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1005
1006 #define QIB_E_P_SDMAERRS ( \
1007 QIB_E_P_SDMAHALT | \
1008 QIB_E_P_SDMADESCADDRMISALIGN | \
1009 QIB_E_P_SDMAUNEXPDATA | \
1010 QIB_E_P_SDMAMISSINGDW | \
1011 QIB_E_P_SDMADWEN | \
1012 QIB_E_P_SDMARPYTAG | \
1013 QIB_E_P_SDMA1STDESC | \
1014 QIB_E_P_SDMABASE | \
1015 QIB_E_P_SDMATAILOUTOFBOUND | \
1016 QIB_E_P_SDMAOUTOFBOUND | \
1017 QIB_E_P_SDMAGENMISMATCH)
1018
1019 /*
1020 * This sets some bits more than once, but makes it more obvious which
1021 * bits are not handled under other categories, and the repeat definition
1022 * is not a problem.
1023 */
1024 #define QIB_E_P_BITSEXTANT ( \
1025 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1026 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1027 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1028 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1029 )
1030
1031 /*
1032 * These are errors that can occur when the link
1033 * changes state while a packet is being sent or received. This doesn't
1034 * cover things like EBP or VCRC that can be the result of a sending
1035 * having the link change state, so we receive a "known bad" packet.
1036 * All of these are "per port", so renamed:
1037 */
1038 #define QIB_E_P_LINK_PKTERRS (\
1039 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1040 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1041 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1042 QIB_E_P_RUNEXPCHAR)
1043
1044 /*
1045 * This sets some bits more than once, but makes it more obvious which
1046 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1047 * and the repeat definition is not a problem.
1048 */
1049 #define QIB_E_C_BITSEXTANT (\
1050 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1051 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1052 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1053
1054 /* Likewise Neuter E_SPKT_ERRS_IGNORE */
1055 #define E_SPKT_ERRS_IGNORE 0
1056
1057 #define QIB_EXTS_MEMBIST_DISABLED \
1058 SYM_MASK(EXTStatus, MemBISTDisabled)
1059 #define QIB_EXTS_MEMBIST_ENDTEST \
1060 SYM_MASK(EXTStatus, MemBISTEndTest)
1061
1062 #define QIB_E_SPIOARMLAUNCH \
1063 ERR_MASK(SendArmLaunchErr)
1064
1065 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1066 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1067
1068 /*
1069 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1070 * and also if forced QDR (only QDR enabled). It's enabled for the
1071 * forced QDR case so that scrambling will be enabled by the TS3
1072 * exchange, when supported by both sides of the link.
1073 */
1074 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1075 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1076 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1077 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1078 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1079 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1080 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1081 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1082
1083 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1084 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1085
1086 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1087 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1088 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1089
1090 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1091 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1092 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1093 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1094 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1095 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1096 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1097
1098 #define IBA7322_REDIRECT_VEC_PER_REG 12
1099
1100 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1101 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1102 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1103 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1104 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1105
1106 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1107
1108 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1109 .msg = #fldname }
1110 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1111 fldname##Mask##_##port), .msg = #fldname }
1112 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1113 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1114 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1115 HWE_AUTO(PCIESerdesPClkNotDetect),
1116 HWE_AUTO(PowerOnBISTFailed),
1117 HWE_AUTO(TempsenseTholdReached),
1118 HWE_AUTO(MemoryErr),
1119 HWE_AUTO(PCIeBusParityErr),
1120 HWE_AUTO(PcieCplTimeout),
1121 HWE_AUTO(PciePoisonedTLP),
1122 HWE_AUTO_P(SDmaMemReadErr, 1),
1123 HWE_AUTO_P(SDmaMemReadErr, 0),
1124 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1125 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
1126 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1127 HWE_AUTO(statusValidNoEop),
1128 HWE_AUTO(LATriggered),
1129 { .mask = 0 }
1130 };
1131
1132 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1133 .msg = #fldname }
1134 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1135 .msg = #fldname }
1136 static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
1137 E_AUTO(ResetNegated),
1138 E_AUTO(HardwareErr),
1139 E_AUTO(InvalidAddrErr),
1140 E_AUTO(SDmaVL15Err),
1141 E_AUTO(SBufVL15MisUseErr),
1142 E_AUTO(InvalidEEPCmd),
1143 E_AUTO(RcvContextShareErr),
1144 E_AUTO(SendVLMismatchErr),
1145 E_AUTO(SendArmLaunchErr),
1146 E_AUTO(SendSpecialTriggerErr),
1147 E_AUTO(SDmaWrongPortErr),
1148 E_AUTO(SDmaBufMaskDuplicateErr),
1149 E_AUTO(RcvHdrFullErr),
1150 E_AUTO(RcvEgrFullErr),
1151 { .mask = 0 }
1152 };
1153
1154 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1155 E_P_AUTO(IBStatusChanged),
1156 E_P_AUTO(SHeadersErr),
1157 E_P_AUTO(VL15BufMisuseErr),
1158 /*
1159 * SDmaHaltErr is not really an error, make it clearer;
1160 */
1161 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted"},
1162 E_P_AUTO(SDmaDescAddrMisalignErr),
1163 E_P_AUTO(SDmaUnexpDataErr),
1164 E_P_AUTO(SDmaMissingDwErr),
1165 E_P_AUTO(SDmaDwEnErr),
1166 E_P_AUTO(SDmaRpyTagErr),
1167 E_P_AUTO(SDma1stDescErr),
1168 E_P_AUTO(SDmaBaseErr),
1169 E_P_AUTO(SDmaTailOutOfBoundErr),
1170 E_P_AUTO(SDmaOutOfBoundErr),
1171 E_P_AUTO(SDmaGenMismatchErr),
1172 E_P_AUTO(SendBufMisuseErr),
1173 E_P_AUTO(SendUnsupportedVLErr),
1174 E_P_AUTO(SendUnexpectedPktNumErr),
1175 E_P_AUTO(SendDroppedDataPktErr),
1176 E_P_AUTO(SendDroppedSmpPktErr),
1177 E_P_AUTO(SendPktLenErr),
1178 E_P_AUTO(SendUnderRunErr),
1179 E_P_AUTO(SendMaxPktLenErr),
1180 E_P_AUTO(SendMinPktLenErr),
1181 E_P_AUTO(RcvIBLostLinkErr),
1182 E_P_AUTO(RcvHdrErr),
1183 E_P_AUTO(RcvHdrLenErr),
1184 E_P_AUTO(RcvBadTidErr),
1185 E_P_AUTO(RcvBadVersionErr),
1186 E_P_AUTO(RcvIBFlowErr),
1187 E_P_AUTO(RcvEBPErr),
1188 E_P_AUTO(RcvUnsupportedVLErr),
1189 E_P_AUTO(RcvUnexpectedCharErr),
1190 E_P_AUTO(RcvShortPktLenErr),
1191 E_P_AUTO(RcvLongPktLenErr),
1192 E_P_AUTO(RcvMaxPktLenErr),
1193 E_P_AUTO(RcvMinPktLenErr),
1194 E_P_AUTO(RcvICRCErr),
1195 E_P_AUTO(RcvVCRCErr),
1196 E_P_AUTO(RcvFormatErr),
1197 { .mask = 0 }
1198 };
1199
1200 /*
1201 * Below generates "auto-message" for interrupts not specific to any port or
1202 * context
1203 */
1204 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1205 .msg = #fldname }
1206 /* Below generates "auto-message" for interrupts specific to a port */
1207 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1208 SYM_LSB(IntMask, fldname##Mask##_0), \
1209 SYM_LSB(IntMask, fldname##Mask##_1)), \
1210 .msg = #fldname "_P" }
1211 /* For some reason, the SerDesTrimDone bits are reversed */
1212 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1213 SYM_LSB(IntMask, fldname##Mask##_1), \
1214 SYM_LSB(IntMask, fldname##Mask##_0)), \
1215 .msg = #fldname "_P" }
1216 /*
1217 * Below generates "auto-message" for interrupts specific to a context,
1218 * with ctxt-number appended
1219 */
1220 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1221 SYM_LSB(IntMask, fldname##0IntMask), \
1222 SYM_LSB(IntMask, fldname##17IntMask)), \
1223 .msg = #fldname "_C"}
1224
1225 static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = {
1226 INTR_AUTO_P(SDmaInt),
1227 INTR_AUTO_P(SDmaProgressInt),
1228 INTR_AUTO_P(SDmaIdleInt),
1229 INTR_AUTO_P(SDmaCleanupDone),
1230 INTR_AUTO_C(RcvUrg),
1231 INTR_AUTO_P(ErrInt),
1232 INTR_AUTO(ErrInt), /* non-port-specific errs */
1233 INTR_AUTO(AssertGPIOInt),
1234 INTR_AUTO_P(SendDoneInt),
1235 INTR_AUTO(SendBufAvailInt),
1236 INTR_AUTO_C(RcvAvail),
1237 { .mask = 0 }
1238 };
1239
1240 #define TXSYMPTOM_AUTO_P(fldname) \
1241 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), .msg = #fldname }
1242 static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1243 TXSYMPTOM_AUTO_P(NonKeyPacket),
1244 TXSYMPTOM_AUTO_P(GRHFail),
1245 TXSYMPTOM_AUTO_P(PkeyFail),
1246 TXSYMPTOM_AUTO_P(QPFail),
1247 TXSYMPTOM_AUTO_P(SLIDFail),
1248 TXSYMPTOM_AUTO_P(RawIPV6),
1249 TXSYMPTOM_AUTO_P(PacketTooSmall),
1250 { .mask = 0 }
1251 };
1252
1253 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1254
1255 /*
1256 * Called when we might have an error that is specific to a particular
1257 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1258 * because we don't need to force the update of pioavail
1259 */
1260 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1261 {
1262 struct qib_devdata *dd = ppd->dd;
1263 u32 i;
1264 int any;
1265 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1266 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1267 unsigned long sbuf[4];
1268
1269 /*
1270 * It's possible that sendbuffererror could have bits set; might
1271 * have already done this as a result of hardware error handling.
1272 */
1273 any = 0;
1274 for (i = 0; i < regcnt; ++i) {
1275 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1276 if (sbuf[i]) {
1277 any = 1;
1278 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1279 }
1280 }
1281
1282 if (any)
1283 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1284 }
1285
1286 /* No txe_recover yet, if ever */
1287
1288 /* No decode__errors yet */
1289 static void err_decode(char *msg, size_t len, u64 errs,
1290 const struct qib_hwerror_msgs *msp)
1291 {
1292 u64 these, lmask;
1293 int took, multi, n = 0;
1294
1295 while (msp && msp->mask) {
1296 multi = (msp->mask & (msp->mask - 1));
1297 while (errs & msp->mask) {
1298 these = (errs & msp->mask);
1299 lmask = (these & (these - 1)) ^ these;
1300 if (len) {
1301 if (n++) {
1302 /* separate the strings */
1303 *msg++ = ',';
1304 len--;
1305 }
1306 took = scnprintf(msg, len, "%s", msp->msg);
1307 len -= took;
1308 msg += took;
1309 }
1310 errs &= ~lmask;
1311 if (len && multi) {
1312 /* More than one bit this mask */
1313 int idx = -1;
1314
1315 while (lmask & msp->mask) {
1316 ++idx;
1317 lmask >>= 1;
1318 }
1319 took = scnprintf(msg, len, "_%d", idx);
1320 len -= took;
1321 msg += took;
1322 }
1323 }
1324 ++msp;
1325 }
1326 /* If some bits are left, show in hex. */
1327 if (len && errs)
1328 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1329 (unsigned long long) errs);
1330 }
1331
1332 /* only called if r1 set */
1333 static void flush_fifo(struct qib_pportdata *ppd)
1334 {
1335 struct qib_devdata *dd = ppd->dd;
1336 u32 __iomem *piobuf;
1337 u32 bufn;
1338 u32 *hdr;
1339 u64 pbc;
1340 const unsigned hdrwords = 7;
1341 static struct qib_ib_header ibhdr = {
1342 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1343 .lrh[1] = IB_LID_PERMISSIVE,
1344 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1345 .lrh[3] = IB_LID_PERMISSIVE,
1346 .u.oth.bth[0] = cpu_to_be32(
1347 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1348 .u.oth.bth[1] = cpu_to_be32(0),
1349 .u.oth.bth[2] = cpu_to_be32(0),
1350 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1351 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1352 };
1353
1354 /*
1355 * Send a dummy VL15 packet to flush the launch FIFO.
1356 * This will not actually be sent since the TxeBypassIbc bit is set.
1357 */
1358 pbc = PBC_7322_VL15_SEND |
1359 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1360 (hdrwords + SIZE_OF_CRC);
1361 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1362 if (!piobuf)
1363 return;
1364 writeq(pbc, piobuf);
1365 hdr = (u32 *) &ibhdr;
1366 if (dd->flags & QIB_PIO_FLUSH_WC) {
1367 qib_flush_wc();
1368 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1369 qib_flush_wc();
1370 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1371 qib_flush_wc();
1372 } else
1373 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1374 qib_sendbuf_done(dd, bufn);
1375 }
1376
1377 /*
1378 * This is called with interrupts disabled and sdma_lock held.
1379 */
1380 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1381 {
1382 struct qib_devdata *dd = ppd->dd;
1383 u64 set_sendctrl = 0;
1384 u64 clr_sendctrl = 0;
1385
1386 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1387 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1388 else
1389 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1390
1391 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1392 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1393 else
1394 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1395
1396 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1397 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1398 else
1399 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1400
1401 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1402 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1403 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1404 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1405 else
1406 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1407 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1408 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1409
1410 spin_lock(&dd->sendctrl_lock);
1411
1412 /* If we are draining everything, block sends first */
1413 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1414 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1415 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1416 qib_write_kreg(dd, kr_scratch, 0);
1417 }
1418
1419 ppd->p_sendctrl |= set_sendctrl;
1420 ppd->p_sendctrl &= ~clr_sendctrl;
1421
1422 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1423 qib_write_kreg_port(ppd, krp_sendctrl,
1424 ppd->p_sendctrl |
1425 SYM_MASK(SendCtrl_0, SDmaCleanup));
1426 else
1427 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1428 qib_write_kreg(dd, kr_scratch, 0);
1429
1430 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1431 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1432 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1433 qib_write_kreg(dd, kr_scratch, 0);
1434 }
1435
1436 spin_unlock(&dd->sendctrl_lock);
1437
1438 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1439 flush_fifo(ppd);
1440 }
1441
1442 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1443 {
1444 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1445 }
1446
1447 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1448 {
1449 /*
1450 * Set SendDmaLenGen and clear and set
1451 * the MSB of the generation count to enable generation checking
1452 * and load the internal generation counter.
1453 */
1454 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1455 qib_write_kreg_port(ppd, krp_senddmalengen,
1456 ppd->sdma_descq_cnt |
1457 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1458 }
1459
1460 /*
1461 * Must be called with sdma_lock held, or before init finished.
1462 */
1463 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1464 {
1465 /* Commit writes to memory and advance the tail on the chip */
1466 wmb();
1467 ppd->sdma_descq_tail = tail;
1468 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1469 }
1470
1471 /*
1472 * This is called with interrupts disabled and sdma_lock held.
1473 */
1474 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1475 {
1476 /*
1477 * Drain all FIFOs.
1478 * The hardware doesn't require this but we do it so that verbs
1479 * and user applications don't wait for link active to send stale
1480 * data.
1481 */
1482 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1483
1484 qib_sdma_7322_setlengen(ppd);
1485 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
1486 ppd->sdma_head_dma[0] = 0;
1487 qib_7322_sdma_sendctrl(ppd,
1488 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1489 }
1490
1491 #define DISABLES_SDMA ( \
1492 QIB_E_P_SDMAHALT | \
1493 QIB_E_P_SDMADESCADDRMISALIGN | \
1494 QIB_E_P_SDMAMISSINGDW | \
1495 QIB_E_P_SDMADWEN | \
1496 QIB_E_P_SDMARPYTAG | \
1497 QIB_E_P_SDMA1STDESC | \
1498 QIB_E_P_SDMABASE | \
1499 QIB_E_P_SDMATAILOUTOFBOUND | \
1500 QIB_E_P_SDMAOUTOFBOUND | \
1501 QIB_E_P_SDMAGENMISMATCH)
1502
1503 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1504 {
1505 unsigned long flags;
1506 struct qib_devdata *dd = ppd->dd;
1507
1508 errs &= QIB_E_P_SDMAERRS;
1509
1510 if (errs & QIB_E_P_SDMAUNEXPDATA)
1511 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1512 ppd->port);
1513
1514 spin_lock_irqsave(&ppd->sdma_lock, flags);
1515
1516 switch (ppd->sdma_state.current_state) {
1517 case qib_sdma_state_s00_hw_down:
1518 break;
1519
1520 case qib_sdma_state_s10_hw_start_up_wait:
1521 if (errs & QIB_E_P_SDMAHALT)
1522 __qib_sdma_process_event(ppd,
1523 qib_sdma_event_e20_hw_started);
1524 break;
1525
1526 case qib_sdma_state_s20_idle:
1527 break;
1528
1529 case qib_sdma_state_s30_sw_clean_up_wait:
1530 break;
1531
1532 case qib_sdma_state_s40_hw_clean_up_wait:
1533 if (errs & QIB_E_P_SDMAHALT)
1534 __qib_sdma_process_event(ppd,
1535 qib_sdma_event_e50_hw_cleaned);
1536 break;
1537
1538 case qib_sdma_state_s50_hw_halt_wait:
1539 if (errs & QIB_E_P_SDMAHALT)
1540 __qib_sdma_process_event(ppd,
1541 qib_sdma_event_e60_hw_halted);
1542 break;
1543
1544 case qib_sdma_state_s99_running:
1545 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1546 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1547 break;
1548 }
1549
1550 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1551 }
1552
1553 /*
1554 * handle per-device errors (not per-port errors)
1555 */
1556 static noinline void handle_7322_errors(struct qib_devdata *dd)
1557 {
1558 char *msg;
1559 u64 iserr = 0;
1560 u64 errs;
1561 u64 mask;
1562 int log_idx;
1563
1564 qib_stats.sps_errints++;
1565 errs = qib_read_kreg64(dd, kr_errstatus);
1566 if (!errs) {
1567 qib_devinfo(dd->pcidev, "device error interrupt, "
1568 "but no error bits set!\n");
1569 goto done;
1570 }
1571
1572 /* don't report errors that are masked */
1573 errs &= dd->cspec->errormask;
1574 msg = dd->cspec->emsgbuf;
1575
1576 /* do these first, they are most important */
1577 if (errs & QIB_E_HARDWARE) {
1578 *msg = '\0';
1579 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1580 } else
1581 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1582 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1583 qib_inc_eeprom_err(dd, log_idx, 1);
1584
1585 if (errs & QIB_E_SPKTERRS) {
1586 qib_disarm_7322_senderrbufs(dd->pport);
1587 qib_stats.sps_txerrs++;
1588 } else if (errs & QIB_E_INVALIDADDR)
1589 qib_stats.sps_txerrs++;
1590 else if (errs & QIB_E_ARMLAUNCH) {
1591 qib_stats.sps_txerrs++;
1592 qib_disarm_7322_senderrbufs(dd->pport);
1593 }
1594 qib_write_kreg(dd, kr_errclear, errs);
1595
1596 /*
1597 * The ones we mask off are handled specially below
1598 * or above. Also mask SDMADISABLED by default as it
1599 * is too chatty.
1600 */
1601 mask = QIB_E_HARDWARE;
1602 *msg = '\0';
1603
1604 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask,
1605 qib_7322error_msgs);
1606
1607 /*
1608 * Getting reset is a tragedy for all ports. Mark the device
1609 * _and_ the ports as "offline" in way meaningful to each.
1610 */
1611 if (errs & QIB_E_RESET) {
1612 int pidx;
1613
1614 qib_dev_err(dd, "Got reset, requires re-init "
1615 "(unload and reload driver)\n");
1616 dd->flags &= ~QIB_INITTED; /* needs re-init */
1617 /* mark as having had error */
1618 *dd->devstatusp |= QIB_STATUS_HWERROR;
1619 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1620 if (dd->pport[pidx].link_speed_supported)
1621 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1622 }
1623
1624 if (*msg && iserr)
1625 qib_dev_err(dd, "%s error\n", msg);
1626
1627 /*
1628 * If there were hdrq or egrfull errors, wake up any processes
1629 * waiting in poll. We used to try to check which contexts had
1630 * the overflow, but given the cost of that and the chip reads
1631 * to support it, it's better to just wake everybody up if we
1632 * get an overflow; waiters can poll again if it's not them.
1633 */
1634 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1635 qib_handle_urcv(dd, ~0U);
1636 if (errs & ERR_MASK(RcvEgrFullErr))
1637 qib_stats.sps_buffull++;
1638 else
1639 qib_stats.sps_hdrfull++;
1640 }
1641
1642 done:
1643 return;
1644 }
1645
1646 static void reenable_chase(unsigned long opaque)
1647 {
1648 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1649
1650 ppd->cpspec->chase_timer.expires = 0;
1651 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1652 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1653 }
1654
1655 static void disable_chase(struct qib_pportdata *ppd, u64 tnow, u8 ibclt)
1656 {
1657 ppd->cpspec->chase_end = 0;
1658
1659 if (!qib_chase)
1660 return;
1661
1662 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1663 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1664 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1665 add_timer(&ppd->cpspec->chase_timer);
1666 }
1667
1668 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1669 {
1670 u8 ibclt;
1671 u64 tnow;
1672
1673 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1674
1675 /*
1676 * Detect and handle the state chase issue, where we can
1677 * get stuck if we are unlucky on timing on both sides of
1678 * the link. If we are, we disable, set a timer, and
1679 * then re-enable.
1680 */
1681 switch (ibclt) {
1682 case IB_7322_LT_STATE_CFGRCVFCFG:
1683 case IB_7322_LT_STATE_CFGWAITRMT:
1684 case IB_7322_LT_STATE_TXREVLANES:
1685 case IB_7322_LT_STATE_CFGENH:
1686 tnow = get_jiffies_64();
1687 if (ppd->cpspec->chase_end &&
1688 time_after64(tnow, ppd->cpspec->chase_end))
1689 disable_chase(ppd, tnow, ibclt);
1690 else if (!ppd->cpspec->chase_end)
1691 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1692 break;
1693 default:
1694 ppd->cpspec->chase_end = 0;
1695 break;
1696 }
1697
1698 if (((ibclt >= IB_7322_LT_STATE_CFGTEST &&
1699 ibclt <= IB_7322_LT_STATE_CFGWAITENH) ||
1700 ibclt == IB_7322_LT_STATE_LINKUP) &&
1701 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1702 force_h1(ppd);
1703 ppd->cpspec->qdr_reforce = 1;
1704 if (!ppd->dd->cspec->r1)
1705 serdes_7322_los_enable(ppd, 0);
1706 } else if (ppd->cpspec->qdr_reforce &&
1707 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1708 (ibclt == IB_7322_LT_STATE_CFGENH ||
1709 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1710 ibclt == IB_7322_LT_STATE_LINKUP))
1711 force_h1(ppd);
1712
1713 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1714 ppd->link_speed_enabled == QIB_IB_QDR &&
1715 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1716 ibclt == IB_7322_LT_STATE_CFGENH ||
1717 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1718 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1719 adj_tx_serdes(ppd);
1720
1721 if (ibclt != IB_7322_LT_STATE_LINKUP) {
1722 u8 ltstate = qib_7322_phys_portstate(ibcst);
1723 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
1724 LinkTrainingState);
1725 if (!ppd->dd->cspec->r1 &&
1726 pibclt == IB_7322_LT_STATE_LINKUP &&
1727 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1728 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1729 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1730 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1731 /* If the link went down (but no into recovery,
1732 * turn LOS back on */
1733 serdes_7322_los_enable(ppd, 1);
1734 if (!ppd->cpspec->qdr_dfe_on &&
1735 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1736 ppd->cpspec->qdr_dfe_on = 1;
1737 ppd->cpspec->qdr_dfe_time = 0;
1738 /* On link down, reenable QDR adaptation */
1739 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1740 ppd->dd->cspec->r1 ?
1741 QDR_STATIC_ADAPT_DOWN_R1 :
1742 QDR_STATIC_ADAPT_DOWN);
1743 printk(KERN_INFO QIB_DRV_NAME
1744 " IB%u:%u re-enabled QDR adaptation "
1745 "ibclt %x\n", ppd->dd->unit, ppd->port, ibclt);
1746 }
1747 }
1748 }
1749
1750 static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32);
1751
1752 /*
1753 * This is per-pport error handling.
1754 * will likely get it's own MSIx interrupt (one for each port,
1755 * although just a single handler).
1756 */
1757 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1758 {
1759 char *msg;
1760 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1761 struct qib_devdata *dd = ppd->dd;
1762
1763 /* do this as soon as possible */
1764 fmask = qib_read_kreg64(dd, kr_act_fmask);
1765 if (!fmask)
1766 check_7322_rxe_status(ppd);
1767
1768 errs = qib_read_kreg_port(ppd, krp_errstatus);
1769 if (!errs)
1770 qib_devinfo(dd->pcidev,
1771 "Port%d error interrupt, but no error bits set!\n",
1772 ppd->port);
1773 if (!fmask)
1774 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1775 if (!errs)
1776 goto done;
1777
1778 msg = ppd->cpspec->epmsgbuf;
1779 *msg = '\0';
1780
1781 if (errs & ~QIB_E_P_BITSEXTANT) {
1782 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1783 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1784 if (!*msg)
1785 snprintf(msg, sizeof ppd->cpspec->epmsgbuf,
1786 "no others");
1787 qib_dev_porterr(dd, ppd->port, "error interrupt with unknown"
1788 " errors 0x%016Lx set (and %s)\n",
1789 (errs & ~QIB_E_P_BITSEXTANT), msg);
1790 *msg = '\0';
1791 }
1792
1793 if (errs & QIB_E_P_SHDR) {
1794 u64 symptom;
1795
1796 /* determine cause, then write to clear */
1797 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1798 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
1799 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, symptom,
1800 hdrchk_msgs);
1801 *msg = '\0';
1802 /* senderrbuf cleared in SPKTERRS below */
1803 }
1804
1805 if (errs & QIB_E_P_SPKTERRS) {
1806 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1807 !(ppd->lflags & QIBL_LINKACTIVE)) {
1808 /*
1809 * This can happen when trying to bring the link
1810 * up, but the IB link changes state at the "wrong"
1811 * time. The IB logic then complains that the packet
1812 * isn't valid. We don't want to confuse people, so
1813 * we just don't print them, except at debug
1814 */
1815 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1816 (errs & QIB_E_P_LINK_PKTERRS),
1817 qib_7322p_error_msgs);
1818 *msg = '\0';
1819 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1820 }
1821 qib_disarm_7322_senderrbufs(ppd);
1822 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1823 !(ppd->lflags & QIBL_LINKACTIVE)) {
1824 /*
1825 * This can happen when SMA is trying to bring the link
1826 * up, but the IB link changes state at the "wrong" time.
1827 * The IB logic then complains that the packet isn't
1828 * valid. We don't want to confuse people, so we just
1829 * don't print them, except at debug
1830 */
1831 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, errs,
1832 qib_7322p_error_msgs);
1833 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1834 *msg = '\0';
1835 }
1836
1837 qib_write_kreg_port(ppd, krp_errclear, errs);
1838
1839 errs &= ~ignore_this_time;
1840 if (!errs)
1841 goto done;
1842
1843 if (errs & QIB_E_P_RPKTERRS)
1844 qib_stats.sps_rcverrs++;
1845 if (errs & QIB_E_P_SPKTERRS)
1846 qib_stats.sps_txerrs++;
1847
1848 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1849
1850 if (errs & QIB_E_P_SDMAERRS)
1851 sdma_7322_p_errors(ppd, errs);
1852
1853 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1854 u64 ibcs;
1855 u8 ltstate;
1856
1857 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1858 ltstate = qib_7322_phys_portstate(ibcs);
1859
1860 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1861 handle_serdes_issues(ppd, ibcs);
1862 if (!(ppd->cpspec->ibcctrl_a &
1863 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1864 /*
1865 * We got our interrupt, so init code should be
1866 * happy and not try alternatives. Now squelch
1867 * other "chatter" from link-negotiation (pre Init)
1868 */
1869 ppd->cpspec->ibcctrl_a |=
1870 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1871 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1872 ppd->cpspec->ibcctrl_a);
1873 }
1874
1875 /* Update our picture of width and speed from chip */
1876 ppd->link_width_active =
1877 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1878 IB_WIDTH_4X : IB_WIDTH_1X;
1879 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1880 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1881 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1882 QIB_IB_DDR : QIB_IB_SDR;
1883
1884 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1885 IB_PHYSPORTSTATE_DISABLED)
1886 qib_set_ib_7322_lstate(ppd, 0,
1887 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1888 else
1889 /*
1890 * Since going into a recovery state causes the link
1891 * state to go down and since recovery is transitory,
1892 * it is better if we "miss" ever seeing the link
1893 * training state go into recovery (i.e., ignore this
1894 * transition for link state special handling purposes)
1895 * without updating lastibcstat.
1896 */
1897 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1898 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1899 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1900 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1901 qib_handle_e_ibstatuschanged(ppd, ibcs);
1902 }
1903 if (*msg && iserr)
1904 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1905
1906 if (ppd->state_wanted & ppd->lflags)
1907 wake_up_interruptible(&ppd->state_wait);
1908 done:
1909 return;
1910 }
1911
1912 /* enable/disable chip from delivering interrupts */
1913 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
1914 {
1915 if (enable) {
1916 if (dd->flags & QIB_BADINTR)
1917 return;
1918 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
1919 /* cause any pending enabled interrupts to be re-delivered */
1920 qib_write_kreg(dd, kr_intclear, 0ULL);
1921 if (dd->cspec->num_msix_entries) {
1922 /* and same for MSIx */
1923 u64 val = qib_read_kreg64(dd, kr_intgranted);
1924 if (val)
1925 qib_write_kreg(dd, kr_intgranted, val);
1926 }
1927 } else
1928 qib_write_kreg(dd, kr_intmask, 0ULL);
1929 }
1930
1931 /*
1932 * Try to cleanup as much as possible for anything that might have gone
1933 * wrong while in freeze mode, such as pio buffers being written by user
1934 * processes (causing armlaunch), send errors due to going into freeze mode,
1935 * etc., and try to avoid causing extra interrupts while doing so.
1936 * Forcibly update the in-memory pioavail register copies after cleanup
1937 * because the chip won't do it while in freeze mode (the register values
1938 * themselves are kept correct).
1939 * Make sure that we don't lose any important interrupts by using the chip
1940 * feature that says that writing 0 to a bit in *clear that is set in
1941 * *status will cause an interrupt to be generated again (if allowed by
1942 * the *mask value).
1943 * This is in chip-specific code because of all of the register accesses,
1944 * even though the details are similar on most chips.
1945 */
1946 static void qib_7322_clear_freeze(struct qib_devdata *dd)
1947 {
1948 int pidx;
1949
1950 /* disable error interrupts, to avoid confusion */
1951 qib_write_kreg(dd, kr_errmask, 0ULL);
1952
1953 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1954 if (dd->pport[pidx].link_speed_supported)
1955 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
1956 0ULL);
1957
1958 /* also disable interrupts; errormask is sometimes overwriten */
1959 qib_7322_set_intr_state(dd, 0);
1960
1961 /* clear the freeze, and be sure chip saw it */
1962 qib_write_kreg(dd, kr_control, dd->control);
1963 qib_read_kreg32(dd, kr_scratch);
1964
1965 /*
1966 * Force new interrupt if any hwerr, error or interrupt bits are
1967 * still set, and clear "safe" send packet errors related to freeze
1968 * and cancelling sends. Re-enable error interrupts before possible
1969 * force of re-interrupt on pending interrupts.
1970 */
1971 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1972 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1973 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1974 /* We need to purge per-port errs and reset mask, too */
1975 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1976 if (!dd->pport[pidx].link_speed_supported)
1977 continue;
1978 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
1979 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
1980 }
1981 qib_7322_set_intr_state(dd, 1);
1982 }
1983
1984 /* no error handling to speak of */
1985 /**
1986 * qib_7322_handle_hwerrors - display hardware errors.
1987 * @dd: the qlogic_ib device
1988 * @msg: the output buffer
1989 * @msgl: the size of the output buffer
1990 *
1991 * Use same msg buffer as regular errors to avoid excessive stack
1992 * use. Most hardware errors are catastrophic, but for right now,
1993 * we'll print them and continue. We reuse the same message buffer as
1994 * qib_handle_errors() to avoid excessive stack usage.
1995 */
1996 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
1997 size_t msgl)
1998 {
1999 u64 hwerrs;
2000 u32 ctrl;
2001 int isfatal = 0;
2002
2003 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2004 if (!hwerrs)
2005 goto bail;
2006 if (hwerrs == ~0ULL) {
2007 qib_dev_err(dd, "Read of hardware error status failed "
2008 "(all bits set); ignoring\n");
2009 goto bail;
2010 }
2011 qib_stats.sps_hwerrs++;
2012
2013 /* Always clear the error status register, except BIST fail */
2014 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
2015 ~HWE_MASK(PowerOnBISTFailed));
2016
2017 hwerrs &= dd->cspec->hwerrmask;
2018
2019 /* no EEPROM logging, yet */
2020
2021 if (hwerrs)
2022 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx "
2023 "(cleared)\n", (unsigned long long) hwerrs);
2024
2025 ctrl = qib_read_kreg32(dd, kr_control);
2026 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2027 /*
2028 * No recovery yet...
2029 */
2030 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2031 dd->cspec->stay_in_freeze) {
2032 /*
2033 * If any set that we aren't ignoring only make the
2034 * complaint once, in case it's stuck or recurring,
2035 * and we get here multiple times
2036 * Force link down, so switch knows, and
2037 * LEDs are turned off.
2038 */
2039 if (dd->flags & QIB_INITTED)
2040 isfatal = 1;
2041 } else
2042 qib_7322_clear_freeze(dd);
2043 }
2044
2045 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2046 isfatal = 1;
2047 strlcpy(msg, "[Memory BIST test failed, "
2048 "InfiniPath hardware unusable]", msgl);
2049 /* ignore from now on, so disable until driver reloaded */
2050 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2051 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2052 }
2053
2054 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2055
2056 /* Ignore esoteric PLL failures et al. */
2057
2058 qib_dev_err(dd, "%s hardware error\n", msg);
2059
2060 if (isfatal && !dd->diag_client) {
2061 qib_dev_err(dd, "Fatal Hardware Error, no longer"
2062 " usable, SN %.16s\n", dd->serial);
2063 /*
2064 * for /sys status file and user programs to print; if no
2065 * trailing brace is copied, we'll know it was truncated.
2066 */
2067 if (dd->freezemsg)
2068 snprintf(dd->freezemsg, dd->freezelen,
2069 "{%s}", msg);
2070 qib_disable_after_error(dd);
2071 }
2072 bail:;
2073 }
2074
2075 /**
2076 * qib_7322_init_hwerrors - enable hardware errors
2077 * @dd: the qlogic_ib device
2078 *
2079 * now that we have finished initializing everything that might reasonably
2080 * cause a hardware error, and cleared those errors bits as they occur,
2081 * we can enable hardware errors in the mask (potentially enabling
2082 * freeze mode), and enable hardware errors as errors (along with
2083 * everything else) in errormask
2084 */
2085 static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2086 {
2087 int pidx;
2088 u64 extsval;
2089
2090 extsval = qib_read_kreg64(dd, kr_extstatus);
2091 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2092 QIB_EXTS_MEMBIST_ENDTEST)))
2093 qib_dev_err(dd, "MemBIST did not complete!\n");
2094
2095 /* never clear BIST failure, so reported on each driver load */
2096 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2097 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2098
2099 /* clear all */
2100 qib_write_kreg(dd, kr_errclear, ~0ULL);
2101 /* enable errors that are masked, at least this first time. */
2102 qib_write_kreg(dd, kr_errmask, ~0ULL);
2103 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2104 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2105 if (dd->pport[pidx].link_speed_supported)
2106 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2107 ~0ULL);
2108 }
2109
2110 /*
2111 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2112 * on chips that are count-based, rather than trigger-based. There is no
2113 * reference counting, but that's also fine, given the intended use.
2114 * Only chip-specific because it's all register accesses
2115 */
2116 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2117 {
2118 if (enable) {
2119 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2120 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2121 } else
2122 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2123 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2124 }
2125
2126 /*
2127 * Formerly took parameter <which> in pre-shifted,
2128 * pre-merged form with LinkCmd and LinkInitCmd
2129 * together, and assuming the zero was NOP.
2130 */
2131 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2132 u16 linitcmd)
2133 {
2134 u64 mod_wd;
2135 struct qib_devdata *dd = ppd->dd;
2136 unsigned long flags;
2137
2138 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2139 /*
2140 * If we are told to disable, note that so link-recovery
2141 * code does not attempt to bring us back up.
2142 * Also reset everything that we can, so we start
2143 * completely clean when re-enabled (before we
2144 * actually issue the disable to the IBC)
2145 */
2146 qib_7322_mini_pcs_reset(ppd);
2147 spin_lock_irqsave(&ppd->lflags_lock, flags);
2148 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2149 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2150 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2151 /*
2152 * Any other linkinitcmd will lead to LINKDOWN and then
2153 * to INIT (if all is well), so clear flag to let
2154 * link-recovery code attempt to bring us back up.
2155 */
2156 spin_lock_irqsave(&ppd->lflags_lock, flags);
2157 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2158 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2159 /*
2160 * Clear status change interrupt reduction so the
2161 * new state is seen.
2162 */
2163 ppd->cpspec->ibcctrl_a &=
2164 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2165 }
2166
2167 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2168 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2169
2170 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2171 mod_wd);
2172 /* write to chip to prevent back-to-back writes of ibc reg */
2173 qib_write_kreg(dd, kr_scratch, 0);
2174
2175 }
2176
2177 /*
2178 * The total RCV buffer memory is 64KB, used for both ports, and is
2179 * in units of 64 bytes (same as IB flow control credit unit).
2180 * The consumedVL unit in the same registers are in 32 byte units!
2181 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2182 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2183 * in krp_rxcreditvl15, rather than 10.
2184 */
2185 #define RCV_BUF_UNITSZ 64
2186 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2187
2188 static void set_vls(struct qib_pportdata *ppd)
2189 {
2190 int i, numvls, totcred, cred_vl, vl0extra;
2191 struct qib_devdata *dd = ppd->dd;
2192 u64 val;
2193
2194 numvls = qib_num_vls(ppd->vls_operational);
2195
2196 /*
2197 * Set up per-VL credits. Below is kluge based on these assumptions:
2198 * 1) port is disabled at the time early_init is called.
2199 * 2) give VL15 17 credits, for two max-plausible packets.
2200 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2201 */
2202 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2203 totcred = NUM_RCV_BUF_UNITS(dd);
2204 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2205 totcred -= cred_vl;
2206 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2207 cred_vl = totcred / numvls;
2208 vl0extra = totcred - cred_vl * numvls;
2209 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2210 for (i = 1; i < numvls; i++)
2211 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2212 for (; i < 8; i++) /* no buffer space for other VLs */
2213 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2214
2215 /* Notify IBC that credits need to be recalculated */
2216 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2217 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2218 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2219 qib_write_kreg(dd, kr_scratch, 0ULL);
2220 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2221 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2222
2223 for (i = 0; i < numvls; i++)
2224 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2225 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2226
2227 /* Change the number of operational VLs */
2228 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2229 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2230 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2231 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2232 qib_write_kreg(dd, kr_scratch, 0ULL);
2233 }
2234
2235 /*
2236 * The code that deals with actual SerDes is in serdes_7322_init().
2237 * Compared to the code for iba7220, it is minimal.
2238 */
2239 static int serdes_7322_init(struct qib_pportdata *ppd);
2240
2241 /**
2242 * qib_7322_bringup_serdes - bring up the serdes
2243 * @ppd: physical port on the qlogic_ib device
2244 */
2245 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2246 {
2247 struct qib_devdata *dd = ppd->dd;
2248 u64 val, guid, ibc;
2249 unsigned long flags;
2250 int ret = 0;
2251
2252 /*
2253 * SerDes model not in Pd, but still need to
2254 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2255 * eventually.
2256 */
2257 /* Put IBC in reset, sends disabled (should be in reset already) */
2258 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2259 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2260 qib_write_kreg(dd, kr_scratch, 0ULL);
2261
2262 if (qib_compat_ddr_negotiate) {
2263 ppd->cpspec->ibdeltainprog = 1;
2264 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2265 crp_ibsymbolerr);
2266 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2267 crp_iblinkerrrecov);
2268 }
2269
2270 /* flowcontrolwatermark is in units of KBytes */
2271 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2272 /*
2273 * Flow control is sent this often, even if no changes in
2274 * buffer space occur. Units are 128ns for this chip.
2275 * Set to 3usec.
2276 */
2277 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2278 /* max error tolerance */
2279 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2280 /* IB credit flow control. */
2281 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2282 /*
2283 * set initial max size pkt IBC will send, including ICRC; it's the
2284 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2285 */
2286 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2287 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2288 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */
2289
2290 /* initially come up waiting for TS1, without sending anything. */
2291 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2292 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2293
2294 /*
2295 * Reset the PCS interface to the serdes (and also ibc, which is still
2296 * in reset from above). Writes new value of ibcctrl_a as last step.
2297 */
2298 qib_7322_mini_pcs_reset(ppd);
2299 qib_write_kreg(dd, kr_scratch, 0ULL);
2300
2301 if (!ppd->cpspec->ibcctrl_b) {
2302 unsigned lse = ppd->link_speed_enabled;
2303
2304 /*
2305 * Not on re-init after reset, establish shadow
2306 * and force initial config.
2307 */
2308 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2309 krp_ibcctrl_b);
2310 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2311 IBA7322_IBC_SPEED_DDR |
2312 IBA7322_IBC_SPEED_SDR |
2313 IBA7322_IBC_WIDTH_AUTONEG |
2314 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2315 if (lse & (lse - 1)) /* Muliple speeds enabled */
2316 ppd->cpspec->ibcctrl_b |=
2317 (lse << IBA7322_IBC_SPEED_LSB) |
2318 IBA7322_IBC_IBTA_1_2_MASK |
2319 IBA7322_IBC_MAX_SPEED_MASK;
2320 else
2321 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2322 IBA7322_IBC_SPEED_QDR |
2323 IBA7322_IBC_IBTA_1_2_MASK :
2324 (lse == QIB_IB_DDR) ?
2325 IBA7322_IBC_SPEED_DDR :
2326 IBA7322_IBC_SPEED_SDR;
2327 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2328 (IB_WIDTH_1X | IB_WIDTH_4X))
2329 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2330 else
2331 ppd->cpspec->ibcctrl_b |=
2332 ppd->link_width_enabled == IB_WIDTH_4X ?
2333 IBA7322_IBC_WIDTH_4X_ONLY :
2334 IBA7322_IBC_WIDTH_1X_ONLY;
2335
2336 /* always enable these on driver reload, not sticky */
2337 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2338 IBA7322_IBC_HRTBT_MASK);
2339 }
2340 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2341
2342 /* setup so we have more time at CFGTEST to change H1 */
2343 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2344 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2345 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2346 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2347
2348 serdes_7322_init(ppd);
2349
2350 guid = be64_to_cpu(ppd->guid);
2351 if (!guid) {
2352 if (dd->base_guid)
2353 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2354 ppd->guid = cpu_to_be64(guid);
2355 }
2356
2357 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2358 /* write to chip to prevent back-to-back writes of ibc reg */
2359 qib_write_kreg(dd, kr_scratch, 0);
2360
2361 /* Enable port */
2362 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2363 set_vls(ppd);
2364
2365 /* be paranoid against later code motion, etc. */
2366 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2367 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2368 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2369 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2370
2371 /* Hold the link state machine for mezz boards */
2372 if (IS_QMH(dd) || IS_QME(dd))
2373 qib_set_ib_7322_lstate(ppd, 0,
2374 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2375
2376 /* Also enable IBSTATUSCHG interrupt. */
2377 val = qib_read_kreg_port(ppd, krp_errmask);
2378 qib_write_kreg_port(ppd, krp_errmask,
2379 val | ERR_MASK_N(IBStatusChanged));
2380
2381 /* Always zero until we start messing with SerDes for real */
2382 return ret;
2383 }
2384
2385 /**
2386 * qib_7322_quiet_serdes - set serdes to txidle
2387 * @dd: the qlogic_ib device
2388 * Called when driver is being unloaded
2389 */
2390 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2391 {
2392 u64 val;
2393 unsigned long flags;
2394
2395 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2396
2397 spin_lock_irqsave(&ppd->lflags_lock, flags);
2398 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2399 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2400 wake_up(&ppd->cpspec->autoneg_wait);
2401 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
2402 if (ppd->dd->cspec->r1)
2403 cancel_delayed_work_sync(&ppd->cpspec->ipg_work);
2404
2405 ppd->cpspec->chase_end = 0;
2406 if (ppd->cpspec->chase_timer.data) /* if initted */
2407 del_timer_sync(&ppd->cpspec->chase_timer);
2408
2409 /*
2410 * Despite the name, actually disables IBC as well. Do it when
2411 * we are as sure as possible that no more packets can be
2412 * received, following the down and the PCS reset.
2413 * The actual disabling happens in qib_7322_mini_pci_reset(),
2414 * along with the PCS being reset.
2415 */
2416 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2417 qib_7322_mini_pcs_reset(ppd);
2418
2419 /*
2420 * Update the adjusted counters so the adjustment persists
2421 * across driver reload.
2422 */
2423 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2424 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2425 struct qib_devdata *dd = ppd->dd;
2426 u64 diagc;
2427
2428 /* enable counter writes */
2429 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2430 qib_write_kreg(dd, kr_hwdiagctrl,
2431 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2432
2433 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2434 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2435 if (ppd->cpspec->ibdeltainprog)
2436 val -= val - ppd->cpspec->ibsymsnap;
2437 val -= ppd->cpspec->ibsymdelta;
2438 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2439 }
2440 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2441 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2442 if (ppd->cpspec->ibdeltainprog)
2443 val -= val - ppd->cpspec->iblnkerrsnap;
2444 val -= ppd->cpspec->iblnkerrdelta;
2445 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2446 }
2447 if (ppd->cpspec->iblnkdowndelta) {
2448 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2449 val += ppd->cpspec->iblnkdowndelta;
2450 write_7322_creg_port(ppd, crp_iblinkdown, val);
2451 }
2452 /*
2453 * No need to save ibmalfdelta since IB perfcounters
2454 * are cleared on driver reload.
2455 */
2456
2457 /* and disable counter writes */
2458 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2459 }
2460 }
2461
2462 /**
2463 * qib_setup_7322_setextled - set the state of the two external LEDs
2464 * @ppd: physical port on the qlogic_ib device
2465 * @on: whether the link is up or not
2466 *
2467 * The exact combo of LEDs if on is true is determined by looking
2468 * at the ibcstatus.
2469 *
2470 * These LEDs indicate the physical and logical state of IB link.
2471 * For this chip (at least with recommended board pinouts), LED1
2472 * is Yellow (logical state) and LED2 is Green (physical state),
2473 *
2474 * Note: We try to match the Mellanox HCA LED behavior as best
2475 * we can. Green indicates physical link state is OK (something is
2476 * plugged in, and we can train).
2477 * Amber indicates the link is logically up (ACTIVE).
2478 * Mellanox further blinks the amber LED to indicate data packet
2479 * activity, but we have no hardware support for that, so it would
2480 * require waking up every 10-20 msecs and checking the counters
2481 * on the chip, and then turning the LED off if appropriate. That's
2482 * visible overhead, so not something we will do.
2483 */
2484 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2485 {
2486 struct qib_devdata *dd = ppd->dd;
2487 u64 extctl, ledblink = 0, val;
2488 unsigned long flags;
2489 int yel, grn;
2490
2491 /*
2492 * The diags use the LED to indicate diag info, so we leave
2493 * the external LED alone when the diags are running.
2494 */
2495 if (dd->diag_client)
2496 return;
2497
2498 /* Allow override of LED display for, e.g. Locating system in rack */
2499 if (ppd->led_override) {
2500 grn = (ppd->led_override & QIB_LED_PHYS);
2501 yel = (ppd->led_override & QIB_LED_LOG);
2502 } else if (on) {
2503 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2504 grn = qib_7322_phys_portstate(val) ==
2505 IB_PHYSPORTSTATE_LINKUP;
2506 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2507 } else {
2508 grn = 0;
2509 yel = 0;
2510 }
2511
2512 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2513 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2514 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2515 if (grn) {
2516 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2517 /*
2518 * Counts are in chip clock (4ns) periods.
2519 * This is 1/16 sec (66.6ms) on,
2520 * 3/16 sec (187.5 ms) off, with packets rcvd.
2521 */
2522 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2523 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2524 }
2525 if (yel)
2526 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2527 dd->cspec->extctrl = extctl;
2528 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2529 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2530
2531 if (ledblink) /* blink the LED on packet receive */
2532 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2533 }
2534
2535 /*
2536 * Disable MSIx interrupt if enabled, call generic MSIx code
2537 * to cleanup, and clear pending MSIx interrupts.
2538 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2539 */
2540 static void qib_7322_nomsix(struct qib_devdata *dd)
2541 {
2542 u64 intgranted;
2543 int n;
2544
2545 dd->cspec->main_int_mask = ~0ULL;
2546 n = dd->cspec->num_msix_entries;
2547 if (n) {
2548 int i;
2549
2550 dd->cspec->num_msix_entries = 0;
2551 for (i = 0; i < n; i++)
2552 free_irq(dd->cspec->msix_entries[i].vector,
2553 dd->cspec->msix_arg[i]);
2554 qib_nomsix(dd);
2555 }
2556 /* make sure no MSIx interrupts are left pending */
2557 intgranted = qib_read_kreg64(dd, kr_intgranted);
2558 if (intgranted)
2559 qib_write_kreg(dd, kr_intgranted, intgranted);
2560 }
2561
2562 static void qib_7322_free_irq(struct qib_devdata *dd)
2563 {
2564 if (dd->cspec->irq) {
2565 free_irq(dd->cspec->irq, dd);
2566 dd->cspec->irq = 0;
2567 }
2568 qib_7322_nomsix(dd);
2569 }
2570
2571 static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2572 {
2573 int i;
2574
2575 qib_7322_free_irq(dd);
2576 kfree(dd->cspec->cntrs);
2577 kfree(dd->cspec->sendchkenable);
2578 kfree(dd->cspec->sendgrhchk);
2579 kfree(dd->cspec->sendibchk);
2580 kfree(dd->cspec->msix_entries);
2581 kfree(dd->cspec->msix_arg);
2582 for (i = 0; i < dd->num_pports; i++) {
2583 unsigned long flags;
2584 u32 mask = QSFP_GPIO_MOD_PRS_N |
2585 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2586
2587 kfree(dd->pport[i].cpspec->portcntrs);
2588 if (dd->flags & QIB_HAS_QSFP) {
2589 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2590 dd->cspec->gpio_mask &= ~mask;
2591 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2592 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2593 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data);
2594 }
2595 if (dd->pport[i].ibport_data.smi_ah)
2596 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah);
2597 }
2598 }
2599
2600 /* handle SDMA interrupts */
2601 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2602 {
2603 struct qib_pportdata *ppd0 = &dd->pport[0];
2604 struct qib_pportdata *ppd1 = &dd->pport[1];
2605 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2606 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2607 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2608 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2609
2610 if (intr0)
2611 qib_sdma_intr(ppd0);
2612 if (intr1)
2613 qib_sdma_intr(ppd1);
2614
2615 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2616 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2617 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2618 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2619 }
2620
2621 /*
2622 * Set or clear the Send buffer available interrupt enable bit.
2623 */
2624 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2625 {
2626 unsigned long flags;
2627
2628 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2629 if (needint)
2630 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2631 else
2632 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2633 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2634 qib_write_kreg(dd, kr_scratch, 0ULL);
2635 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2636 }
2637
2638 /*
2639 * Somehow got an interrupt with reserved bits set in interrupt status.
2640 * Print a message so we know it happened, then clear them.
2641 * keep mainline interrupt handler cache-friendly
2642 */
2643 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2644 {
2645 u64 kills;
2646 char msg[128];
2647
2648 kills = istat & ~QIB_I_BITSEXTANT;
2649 qib_dev_err(dd, "Clearing reserved interrupt(s) 0x%016llx:"
2650 " %s\n", (unsigned long long) kills, msg);
2651 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2652 }
2653
2654 /* keep mainline interrupt handler cache-friendly */
2655 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2656 {
2657 u32 gpiostatus;
2658 int handled = 0;
2659 int pidx;
2660
2661 /*
2662 * Boards for this chip currently don't use GPIO interrupts,
2663 * so clear by writing GPIOstatus to GPIOclear, and complain
2664 * to developer. To avoid endless repeats, clear
2665 * the bits in the mask, since there is some kind of
2666 * programming error or chip problem.
2667 */
2668 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2669 /*
2670 * In theory, writing GPIOstatus to GPIOclear could
2671 * have a bad side-effect on some diagnostic that wanted
2672 * to poll for a status-change, but the various shadows
2673 * make that problematic at best. Diags will just suppress
2674 * all GPIO interrupts during such tests.
2675 */
2676 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2677 /*
2678 * Check for QSFP MOD_PRS changes
2679 * only works for single port if IB1 != pidx1
2680 */
2681 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2682 ++pidx) {
2683 struct qib_pportdata *ppd;
2684 struct qib_qsfp_data *qd;
2685 u32 mask;
2686 if (!dd->pport[pidx].link_speed_supported)
2687 continue;
2688 mask = QSFP_GPIO_MOD_PRS_N;
2689 ppd = dd->pport + pidx;
2690 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2691 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2692 u64 pins;
2693 qd = &ppd->cpspec->qsfp_data;
2694 gpiostatus &= ~mask;
2695 pins = qib_read_kreg64(dd, kr_extstatus);
2696 pins >>= SYM_LSB(EXTStatus, GPIOIn);
2697 if (!(pins & mask)) {
2698 ++handled;
2699 qd->t_insert = get_jiffies_64();
2700 queue_work(ib_wq, &qd->work);
2701 }
2702 }
2703 }
2704
2705 if (gpiostatus && !handled) {
2706 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
2707 u32 gpio_irq = mask & gpiostatus;
2708
2709 /*
2710 * Clear any troublemakers, and update chip from shadow
2711 */
2712 dd->cspec->gpio_mask &= ~gpio_irq;
2713 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2714 }
2715 }
2716
2717 /*
2718 * Handle errors and unusual events first, separate function
2719 * to improve cache hits for fast path interrupt handling.
2720 */
2721 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
2722 {
2723 if (istat & ~QIB_I_BITSEXTANT)
2724 unknown_7322_ibits(dd, istat);
2725 if (istat & QIB_I_GPIO)
2726 unknown_7322_gpio_intr(dd);
2727 if (istat & QIB_I_C_ERROR)
2728 handle_7322_errors(dd);
2729 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
2730 handle_7322_p_errors(dd->rcd[0]->ppd);
2731 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
2732 handle_7322_p_errors(dd->rcd[1]->ppd);
2733 }
2734
2735 /*
2736 * Dynamically adjust the rcv int timeout for a context based on incoming
2737 * packet rate.
2738 */
2739 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
2740 {
2741 struct qib_devdata *dd = rcd->dd;
2742 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
2743
2744 /*
2745 * Dynamically adjust idle timeout on chip
2746 * based on number of packets processed.
2747 */
2748 if (npkts < rcv_int_count && timeout > 2)
2749 timeout >>= 1;
2750 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
2751 timeout = min(timeout << 1, rcv_int_timeout);
2752 else
2753 return;
2754
2755 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
2756 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
2757 }
2758
2759 /*
2760 * This is the main interrupt handler.
2761 * It will normally only be used for low frequency interrupts but may
2762 * have to handle all interrupts if INTx is enabled or fewer than normal
2763 * MSIx interrupts were allocated.
2764 * This routine should ignore the interrupt bits for any of the
2765 * dedicated MSIx handlers.
2766 */
2767 static irqreturn_t qib_7322intr(int irq, void *data)
2768 {
2769 struct qib_devdata *dd = data;
2770 irqreturn_t ret;
2771 u64 istat;
2772 u64 ctxtrbits;
2773 u64 rmask;
2774 unsigned i;
2775 u32 npkts;
2776
2777 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
2778 /*
2779 * This return value is not great, but we do not want the
2780 * interrupt core code to remove our interrupt handler
2781 * because we don't appear to be handling an interrupt
2782 * during a chip reset.
2783 */
2784 ret = IRQ_HANDLED;
2785 goto bail;
2786 }
2787
2788 istat = qib_read_kreg64(dd, kr_intstatus);
2789
2790 if (unlikely(istat == ~0ULL)) {
2791 qib_bad_intrstatus(dd);
2792 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
2793 /* don't know if it was our interrupt or not */
2794 ret = IRQ_NONE;
2795 goto bail;
2796 }
2797
2798 istat &= dd->cspec->main_int_mask;
2799 if (unlikely(!istat)) {
2800 /* already handled, or shared and not us */
2801 ret = IRQ_NONE;
2802 goto bail;
2803 }
2804
2805 qib_stats.sps_ints++;
2806 if (dd->int_counter != (u32) -1)
2807 dd->int_counter++;
2808
2809 /* handle "errors" of various kinds first, device ahead of port */
2810 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
2811 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
2812 INT_MASK_P(Err, 1))))
2813 unlikely_7322_intr(dd, istat);
2814
2815 /*
2816 * Clear the interrupt bits we found set, relatively early, so we
2817 * "know" know the chip will have seen this by the time we process
2818 * the queue, and will re-interrupt if necessary. The processor
2819 * itself won't take the interrupt again until we return.
2820 */
2821 qib_write_kreg(dd, kr_intclear, istat);
2822
2823 /*
2824 * Handle kernel receive queues before checking for pio buffers
2825 * available since receives can overflow; piobuf waiters can afford
2826 * a few extra cycles, since they were waiting anyway.
2827 */
2828 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
2829 if (ctxtrbits) {
2830 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
2831 (1ULL << QIB_I_RCVURG_LSB);
2832 for (i = 0; i < dd->first_user_ctxt; i++) {
2833 if (ctxtrbits & rmask) {
2834 ctxtrbits &= ~rmask;
2835 if (dd->rcd[i]) {
2836 qib_kreceive(dd->rcd[i], NULL, &npkts);
2837 }
2838 }
2839 rmask <<= 1;
2840 }
2841 if (ctxtrbits) {
2842 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
2843 (ctxtrbits >> QIB_I_RCVURG_LSB);
2844 qib_handle_urcv(dd, ctxtrbits);
2845 }
2846 }
2847
2848 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
2849 sdma_7322_intr(dd, istat);
2850
2851 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2852 qib_ib_piobufavail(dd);
2853
2854 ret = IRQ_HANDLED;
2855 bail:
2856 return ret;
2857 }
2858
2859 /*
2860 * Dedicated receive packet available interrupt handler.
2861 */
2862 static irqreturn_t qib_7322pintr(int irq, void *data)
2863 {
2864 struct qib_ctxtdata *rcd = data;
2865 struct qib_devdata *dd = rcd->dd;
2866 u32 npkts;
2867
2868 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2869 /*
2870 * This return value is not great, but we do not want the
2871 * interrupt core code to remove our interrupt handler
2872 * because we don't appear to be handling an interrupt
2873 * during a chip reset.
2874 */
2875 return IRQ_HANDLED;
2876
2877 qib_stats.sps_ints++;
2878 if (dd->int_counter != (u32) -1)
2879 dd->int_counter++;
2880
2881 /* Clear the interrupt bit we expect to be set. */
2882 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
2883 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
2884
2885 qib_kreceive(rcd, NULL, &npkts);
2886
2887 return IRQ_HANDLED;
2888 }
2889
2890 /*
2891 * Dedicated Send buffer available interrupt handler.
2892 */
2893 static irqreturn_t qib_7322bufavail(int irq, void *data)
2894 {
2895 struct qib_devdata *dd = data;
2896
2897 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2898 /*
2899 * This return value is not great, but we do not want the
2900 * interrupt core code to remove our interrupt handler
2901 * because we don't appear to be handling an interrupt
2902 * during a chip reset.
2903 */
2904 return IRQ_HANDLED;
2905
2906 qib_stats.sps_ints++;
2907 if (dd->int_counter != (u32) -1)
2908 dd->int_counter++;
2909
2910 /* Clear the interrupt bit we expect to be set. */
2911 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
2912
2913 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
2914 if (dd->flags & QIB_INITTED)
2915 qib_ib_piobufavail(dd);
2916 else
2917 qib_wantpiobuf_7322_intr(dd, 0);
2918
2919 return IRQ_HANDLED;
2920 }
2921
2922 /*
2923 * Dedicated Send DMA interrupt handler.
2924 */
2925 static irqreturn_t sdma_intr(int irq, void *data)
2926 {
2927 struct qib_pportdata *ppd = data;
2928 struct qib_devdata *dd = ppd->dd;
2929
2930 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2931 /*
2932 * This return value is not great, but we do not want the
2933 * interrupt core code to remove our interrupt handler
2934 * because we don't appear to be handling an interrupt
2935 * during a chip reset.
2936 */
2937 return IRQ_HANDLED;
2938
2939 qib_stats.sps_ints++;
2940 if (dd->int_counter != (u32) -1)
2941 dd->int_counter++;
2942
2943 /* Clear the interrupt bit we expect to be set. */
2944 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2945 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
2946 qib_sdma_intr(ppd);
2947
2948 return IRQ_HANDLED;
2949 }
2950
2951 /*
2952 * Dedicated Send DMA idle interrupt handler.
2953 */
2954 static irqreturn_t sdma_idle_intr(int irq, void *data)
2955 {
2956 struct qib_pportdata *ppd = data;
2957 struct qib_devdata *dd = ppd->dd;
2958
2959 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2960 /*
2961 * This return value is not great, but we do not want the
2962 * interrupt core code to remove our interrupt handler
2963 * because we don't appear to be handling an interrupt
2964 * during a chip reset.
2965 */
2966 return IRQ_HANDLED;
2967
2968 qib_stats.sps_ints++;
2969 if (dd->int_counter != (u32) -1)
2970 dd->int_counter++;
2971
2972 /* Clear the interrupt bit we expect to be set. */
2973 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2974 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
2975 qib_sdma_intr(ppd);
2976
2977 return IRQ_HANDLED;
2978 }
2979
2980 /*
2981 * Dedicated Send DMA progress interrupt handler.
2982 */
2983 static irqreturn_t sdma_progress_intr(int irq, void *data)
2984 {
2985 struct qib_pportdata *ppd = data;
2986 struct qib_devdata *dd = ppd->dd;
2987
2988 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2989 /*
2990 * This return value is not great, but we do not want the
2991 * interrupt core code to remove our interrupt handler
2992 * because we don't appear to be handling an interrupt
2993 * during a chip reset.
2994 */
2995 return IRQ_HANDLED;
2996
2997 qib_stats.sps_ints++;
2998 if (dd->int_counter != (u32) -1)
2999 dd->int_counter++;
3000
3001 /* Clear the interrupt bit we expect to be set. */
3002 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3003 INT_MASK_P(SDmaProgress, 1) :
3004 INT_MASK_P(SDmaProgress, 0));
3005 qib_sdma_intr(ppd);
3006
3007 return IRQ_HANDLED;
3008 }
3009
3010 /*
3011 * Dedicated Send DMA cleanup interrupt handler.
3012 */
3013 static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3014 {
3015 struct qib_pportdata *ppd = data;
3016 struct qib_devdata *dd = ppd->dd;
3017
3018 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3019 /*
3020 * This return value is not great, but we do not want the
3021 * interrupt core code to remove our interrupt handler
3022 * because we don't appear to be handling an interrupt
3023 * during a chip reset.
3024 */
3025 return IRQ_HANDLED;
3026
3027 qib_stats.sps_ints++;
3028 if (dd->int_counter != (u32) -1)
3029 dd->int_counter++;
3030
3031 /* Clear the interrupt bit we expect to be set. */
3032 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3033 INT_MASK_PM(SDmaCleanupDone, 1) :
3034 INT_MASK_PM(SDmaCleanupDone, 0));
3035 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3036
3037 return IRQ_HANDLED;
3038 }
3039
3040 /*
3041 * Set up our chip-specific interrupt handler.
3042 * The interrupt type has already been setup, so
3043 * we just need to do the registration and error checking.
3044 * If we are using MSIx interrupts, we may fall back to
3045 * INTx later, if the interrupt handler doesn't get called
3046 * within 1/2 second (see verify_interrupt()).
3047 */
3048 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3049 {
3050 int ret, i, msixnum;
3051 u64 redirect[6];
3052 u64 mask;
3053
3054 if (!dd->num_pports)
3055 return;
3056
3057 if (clearpend) {
3058 /*
3059 * if not switching interrupt types, be sure interrupts are
3060 * disabled, and then clear anything pending at this point,
3061 * because we are starting clean.
3062 */
3063 qib_7322_set_intr_state(dd, 0);
3064
3065 /* clear the reset error, init error/hwerror mask */
3066 qib_7322_init_hwerrors(dd);
3067
3068 /* clear any interrupt bits that might be set */
3069 qib_write_kreg(dd, kr_intclear, ~0ULL);
3070
3071 /* make sure no pending MSIx intr, and clear diag reg */
3072 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3073 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3074 }
3075
3076 if (!dd->cspec->num_msix_entries) {
3077 /* Try to get INTx interrupt */
3078 try_intx:
3079 if (!dd->pcidev->irq) {
3080 qib_dev_err(dd, "irq is 0, BIOS error? "
3081 "Interrupts won't work\n");
3082 goto bail;
3083 }
3084 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3085 IRQF_SHARED, QIB_DRV_NAME, dd);
3086 if (ret) {
3087 qib_dev_err(dd, "Couldn't setup INTx "
3088 "interrupt (irq=%d): %d\n",
3089 dd->pcidev->irq, ret);
3090 goto bail;
3091 }
3092 dd->cspec->irq = dd->pcidev->irq;
3093 dd->cspec->main_int_mask = ~0ULL;
3094 goto bail;
3095 }
3096
3097 /* Try to get MSIx interrupts */
3098 memset(redirect, 0, sizeof redirect);
3099 mask = ~0ULL;
3100 msixnum = 0;
3101 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3102 irq_handler_t handler;
3103 const char *name;
3104 void *arg;
3105 u64 val;
3106 int lsb, reg, sh;
3107
3108 if (i < ARRAY_SIZE(irq_table)) {
3109 if (irq_table[i].port) {
3110 /* skip if for a non-configured port */
3111 if (irq_table[i].port > dd->num_pports)
3112 continue;
3113 arg = dd->pport + irq_table[i].port - 1;
3114 } else
3115 arg = dd;
3116 lsb = irq_table[i].lsb;
3117 handler = irq_table[i].handler;
3118 name = irq_table[i].name;
3119 } else {
3120 unsigned ctxt;
3121
3122 ctxt = i - ARRAY_SIZE(irq_table);
3123 /* per krcvq context receive interrupt */
3124 arg = dd->rcd[ctxt];
3125 if (!arg)
3126 continue;
3127 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3128 handler = qib_7322pintr;
3129 name = QIB_DRV_NAME " (kctx)";
3130 }
3131 ret = request_irq(dd->cspec->msix_entries[msixnum].vector,
3132 handler, 0, name, arg);
3133 if (ret) {
3134 /*
3135 * Shouldn't happen since the enable said we could
3136 * have as many as we are trying to setup here.
3137 */
3138 qib_dev_err(dd, "Couldn't setup MSIx "
3139 "interrupt (vec=%d, irq=%d): %d\n", msixnum,
3140 dd->cspec->msix_entries[msixnum].vector,
3141 ret);
3142 qib_7322_nomsix(dd);
3143 goto try_intx;
3144 }
3145 dd->cspec->msix_arg[msixnum] = arg;
3146 if (lsb >= 0) {
3147 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3148 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3149 SYM_LSB(IntRedirect0, vec1);
3150 mask &= ~(1ULL << lsb);
3151 redirect[reg] |= ((u64) msixnum) << sh;
3152 }
3153 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3154 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3155 msixnum++;
3156 }
3157 /* Initialize the vector mapping */
3158 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3159 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3160 dd->cspec->main_int_mask = mask;
3161 bail:;
3162 }
3163
3164 /**
3165 * qib_7322_boardname - fill in the board name and note features
3166 * @dd: the qlogic_ib device
3167 *
3168 * info will be based on the board revision register
3169 */
3170 static unsigned qib_7322_boardname(struct qib_devdata *dd)
3171 {
3172 /* Will need enumeration of board-types here */
3173 char *n;
3174 u32 boardid, namelen;
3175 unsigned features = DUAL_PORT_CAP;
3176
3177 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3178
3179 switch (boardid) {
3180 case 0:
3181 n = "InfiniPath_QLE7342_Emulation";
3182 break;
3183 case 1:
3184 n = "InfiniPath_QLE7340";
3185 dd->flags |= QIB_HAS_QSFP;
3186 features = PORT_SPD_CAP;
3187 break;
3188 case 2:
3189 n = "InfiniPath_QLE7342";
3190 dd->flags |= QIB_HAS_QSFP;
3191 break;
3192 case 3:
3193 n = "InfiniPath_QMI7342";
3194 break;
3195 case 4:
3196 n = "InfiniPath_Unsupported7342";
3197 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3198 features = 0;
3199 break;
3200 case BOARD_QMH7342:
3201 n = "InfiniPath_QMH7342";
3202 features = 0x24;
3203 break;
3204 case BOARD_QME7342:
3205 n = "InfiniPath_QME7342";
3206 break;
3207 case 8:
3208 n = "InfiniPath_QME7362";
3209 dd->flags |= QIB_HAS_QSFP;
3210 break;
3211 case 15:
3212 n = "InfiniPath_QLE7342_TEST";
3213 dd->flags |= QIB_HAS_QSFP;
3214 break;
3215 default:
3216 n = "InfiniPath_QLE73xy_UNKNOWN";
3217 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3218 break;
3219 }
3220 dd->board_atten = 1; /* index into txdds_Xdr */
3221
3222 namelen = strlen(n) + 1;
3223 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3224 if (!dd->boardname)
3225 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3226 else
3227 snprintf(dd->boardname, namelen, "%s", n);
3228
3229 snprintf(dd->boardversion, sizeof(dd->boardversion),
3230 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3231 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3232 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
3233 dd->majrev, dd->minrev,
3234 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
3235
3236 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
3237 qib_devinfo(dd->pcidev, "IB%u: Forced to single port mode"
3238 " by module parameter\n", dd->unit);
3239 features &= PORT_SPD_CAP;
3240 }
3241
3242 return features;
3243 }
3244
3245 /*
3246 * This routine sleeps, so it can only be called from user context, not
3247 * from interrupt context.
3248 */
3249 static int qib_do_7322_reset(struct qib_devdata *dd)
3250 {
3251 u64 val;
3252 u64 *msix_vecsave;
3253 int i, msix_entries, ret = 1;
3254 u16 cmdval;
3255 u8 int_line, clinesz;
3256 unsigned long flags;
3257
3258 /* Use dev_err so it shows up in logs, etc. */
3259 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3260
3261 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3262
3263 msix_entries = dd->cspec->num_msix_entries;
3264
3265 /* no interrupts till re-initted */
3266 qib_7322_set_intr_state(dd, 0);
3267
3268 if (msix_entries) {
3269 qib_7322_nomsix(dd);
3270 /* can be up to 512 bytes, too big for stack */
3271 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3272 sizeof(u64), GFP_KERNEL);
3273 if (!msix_vecsave)
3274 qib_dev_err(dd, "No mem to save MSIx data\n");
3275 } else
3276 msix_vecsave = NULL;
3277
3278 /*
3279 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3280 * info that is set up by the BIOS, so we have to save and restore
3281 * it ourselves. There is some risk something could change it,
3282 * after we save it, but since we have disabled the MSIx, it
3283 * shouldn't be touched...
3284 */
3285 for (i = 0; i < msix_entries; i++) {
3286 u64 vecaddr, vecdata;
3287 vecaddr = qib_read_kreg64(dd, 2 * i +
3288 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3289 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3290 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3291 if (msix_vecsave) {
3292 msix_vecsave[2 * i] = vecaddr;
3293 /* save it without the masked bit set */
3294 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3295 }
3296 }
3297
3298 dd->pport->cpspec->ibdeltainprog = 0;
3299 dd->pport->cpspec->ibsymdelta = 0;
3300 dd->pport->cpspec->iblnkerrdelta = 0;
3301 dd->pport->cpspec->ibmalfdelta = 0;
3302 dd->int_counter = 0; /* so we check interrupts work again */
3303
3304 /*
3305 * Keep chip from being accessed until we are ready. Use
3306 * writeq() directly, to allow the write even though QIB_PRESENT
3307 * isn't set.
3308 */
3309 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3310 dd->flags |= QIB_DOING_RESET;
3311 val = dd->control | QLOGIC_IB_C_RESET;
3312 writeq(val, &dd->kregbase[kr_control]);
3313
3314 for (i = 1; i <= 5; i++) {
3315 /*
3316 * Allow MBIST, etc. to complete; longer on each retry.
3317 * We sometimes get machine checks from bus timeout if no
3318 * response, so for now, make it *really* long.
3319 */
3320 msleep(1000 + (1 + i) * 3000);
3321
3322 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3323
3324 /*
3325 * Use readq directly, so we don't need to mark it as PRESENT
3326 * until we get a successful indication that all is well.
3327 */
3328 val = readq(&dd->kregbase[kr_revision]);
3329 if (val == dd->revision)
3330 break;
3331 if (i == 5) {
3332 qib_dev_err(dd, "Failed to initialize after reset, "
3333 "unusable\n");
3334 ret = 0;
3335 goto bail;
3336 }
3337 }
3338
3339 dd->flags |= QIB_PRESENT; /* it's back */
3340
3341 if (msix_entries) {
3342 /* restore the MSIx vector address and data if saved above */
3343 for (i = 0; i < msix_entries; i++) {
3344 dd->cspec->msix_entries[i].entry = i;
3345 if (!msix_vecsave || !msix_vecsave[2 * i])
3346 continue;
3347 qib_write_kreg(dd, 2 * i +
3348 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3349 msix_vecsave[2 * i]);
3350 qib_write_kreg(dd, 1 + 2 * i +
3351 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3352 msix_vecsave[1 + 2 * i]);
3353 }
3354 }
3355
3356 /* initialize the remaining registers. */
3357 for (i = 0; i < dd->num_pports; ++i)
3358 write_7322_init_portregs(&dd->pport[i]);
3359 write_7322_initregs(dd);
3360
3361 if (qib_pcie_params(dd, dd->lbus_width,
3362 &dd->cspec->num_msix_entries,
3363 dd->cspec->msix_entries))
3364 qib_dev_err(dd, "Reset failed to setup PCIe or interrupts; "
3365 "continuing anyway\n");
3366
3367 qib_setup_7322_interrupt(dd, 1);
3368
3369 for (i = 0; i < dd->num_pports; ++i) {
3370 struct qib_pportdata *ppd = &dd->pport[i];
3371
3372 spin_lock_irqsave(&ppd->lflags_lock, flags);
3373 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3374 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3375 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3376 }
3377
3378 bail:
3379 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */
3380 kfree(msix_vecsave);
3381 return ret;
3382 }
3383
3384 /**
3385 * qib_7322_put_tid - write a TID to the chip
3386 * @dd: the qlogic_ib device
3387 * @tidptr: pointer to the expected TID (in chip) to update
3388 * @tidtype: 0 for eager, 1 for expected
3389 * @pa: physical address of in memory buffer; tidinvalid if freeing
3390 */
3391 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3392 u32 type, unsigned long pa)
3393 {
3394 if (!(dd->flags & QIB_PRESENT))
3395 return;
3396 if (pa != dd->tidinvalid) {
3397 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3398
3399 /* paranoia checks */
3400 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3401 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3402 pa);
3403 return;
3404 }
3405 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
3406 qib_dev_err(dd, "Physical page address 0x%lx "
3407 "larger than supported\n", pa);
3408 return;
3409 }
3410
3411 if (type == RCVHQ_RCV_TYPE_EAGER)
3412 chippa |= dd->tidtemplate;
3413 else /* for now, always full 4KB page */
3414 chippa |= IBA7322_TID_SZ_4K;
3415 pa = chippa;
3416 }
3417 writeq(pa, tidptr);
3418 mmiowb();
3419 }
3420
3421 /**
3422 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3423 * @dd: the qlogic_ib device
3424 * @ctxt: the ctxt
3425 *
3426 * clear all TID entries for a ctxt, expected and eager.
3427 * Used from qib_close().
3428 */
3429 static void qib_7322_clear_tids(struct qib_devdata *dd,
3430 struct qib_ctxtdata *rcd)
3431 {
3432 u64 __iomem *tidbase;
3433 unsigned long tidinv;
3434 u32 ctxt;
3435 int i;
3436
3437 if (!dd->kregbase || !rcd)
3438 return;
3439
3440 ctxt = rcd->ctxt;
3441
3442 tidinv = dd->tidinvalid;
3443 tidbase = (u64 __iomem *)
3444 ((char __iomem *) dd->kregbase +
3445 dd->rcvtidbase +
3446 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3447
3448 for (i = 0; i < dd->rcvtidcnt; i++)
3449 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3450 tidinv);
3451
3452 tidbase = (u64 __iomem *)
3453 ((char __iomem *) dd->kregbase +
3454 dd->rcvegrbase +
3455 rcd->rcvegr_tid_base * sizeof(*tidbase));
3456
3457 for (i = 0; i < rcd->rcvegrcnt; i++)
3458 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3459 tidinv);
3460 }
3461
3462 /**
3463 * qib_7322_tidtemplate - setup constants for TID updates
3464 * @dd: the qlogic_ib device
3465 *
3466 * We setup stuff that we use a lot, to avoid calculating each time
3467 */
3468 static void qib_7322_tidtemplate(struct qib_devdata *dd)
3469 {
3470 /*
3471 * For now, we always allocate 4KB buffers (at init) so we can
3472 * receive max size packets. We may want a module parameter to
3473 * specify 2KB or 4KB and/or make it per port instead of per device
3474 * for those who want to reduce memory footprint. Note that the
3475 * rcvhdrentsize size must be large enough to hold the largest
3476 * IB header (currently 96 bytes) that we expect to handle (plus of
3477 * course the 2 dwords of RHF).
3478 */
3479 if (dd->rcvegrbufsize == 2048)
3480 dd->tidtemplate = IBA7322_TID_SZ_2K;
3481 else if (dd->rcvegrbufsize == 4096)
3482 dd->tidtemplate = IBA7322_TID_SZ_4K;
3483 dd->tidinvalid = 0;
3484 }
3485
3486 /**
3487 * qib_init_7322_get_base_info - set chip-specific flags for user code
3488 * @rcd: the qlogic_ib ctxt
3489 * @kbase: qib_base_info pointer
3490 *
3491 * We set the PCIE flag because the lower bandwidth on PCIe vs
3492 * HyperTransport can affect some user packet algorithims.
3493 */
3494
3495 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3496 struct qib_base_info *kinfo)
3497 {
3498 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3499 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3500 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3501 if (rcd->dd->cspec->r1)
3502 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3503 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3504 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3505
3506 return 0;
3507 }
3508
3509 static struct qib_message_header *
3510 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3511 {
3512 u32 offset = qib_hdrget_offset(rhf_addr);
3513
3514 return (struct qib_message_header *)
3515 (rhf_addr - dd->rhf_offset + offset);
3516 }
3517
3518 /*
3519 * Configure number of contexts.
3520 */
3521 static void qib_7322_config_ctxts(struct qib_devdata *dd)
3522 {
3523 unsigned long flags;
3524 u32 nchipctxts;
3525
3526 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3527 dd->cspec->numctxts = nchipctxts;
3528 if (qib_n_krcv_queues > 1 && dd->num_pports) {
3529 dd->first_user_ctxt = NUM_IB_PORTS +
3530 (qib_n_krcv_queues - 1) * dd->num_pports;
3531 if (dd->first_user_ctxt > nchipctxts)
3532 dd->first_user_ctxt = nchipctxts;
3533 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3534 } else {
3535 dd->first_user_ctxt = NUM_IB_PORTS;
3536 dd->n_krcv_queues = 1;
3537 }
3538
3539 if (!qib_cfgctxts) {
3540 int nctxts = dd->first_user_ctxt + num_online_cpus();
3541
3542 if (nctxts <= 6)
3543 dd->ctxtcnt = 6;
3544 else if (nctxts <= 10)
3545 dd->ctxtcnt = 10;
3546 else if (nctxts <= nchipctxts)
3547 dd->ctxtcnt = nchipctxts;
3548 } else if (qib_cfgctxts < dd->num_pports)
3549 dd->ctxtcnt = dd->num_pports;
3550 else if (qib_cfgctxts <= nchipctxts)
3551 dd->ctxtcnt = qib_cfgctxts;
3552 if (!dd->ctxtcnt) /* none of the above, set to max */
3553 dd->ctxtcnt = nchipctxts;
3554
3555 /*
3556 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3557 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3558 * Lock to be paranoid about later motion, etc.
3559 */
3560 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3561 if (dd->ctxtcnt > 10)
3562 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3563 else if (dd->ctxtcnt > 6)
3564 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3565 /* else configure for default 6 receive ctxts */
3566
3567 /* The XRC opcode is 5. */
3568 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3569
3570 /*
3571 * RcvCtrl *must* be written here so that the
3572 * chip understands how to change rcvegrcnt below.
3573 */
3574 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
3575 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3576
3577 /* kr_rcvegrcnt changes based on the number of contexts enabled */
3578 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3579 if (qib_rcvhdrcnt)
3580 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
3581 else
3582 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt,
3583 dd->num_pports > 1 ? 1024U : 2048U);
3584 }
3585
3586 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
3587 {
3588
3589 int lsb, ret = 0;
3590 u64 maskr; /* right-justified mask */
3591
3592 switch (which) {
3593
3594 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
3595 ret = ppd->link_width_enabled;
3596 goto done;
3597
3598 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
3599 ret = ppd->link_width_active;
3600 goto done;
3601
3602 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
3603 ret = ppd->link_speed_enabled;
3604 goto done;
3605
3606 case QIB_IB_CFG_SPD: /* Get current Link spd */
3607 ret = ppd->link_speed_active;
3608 goto done;
3609
3610 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
3611 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3612 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3613 break;
3614
3615 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
3616 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3617 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3618 break;
3619
3620 case QIB_IB_CFG_LINKLATENCY:
3621 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
3622 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
3623 goto done;
3624
3625 case QIB_IB_CFG_OP_VLS:
3626 ret = ppd->vls_operational;
3627 goto done;
3628
3629 case QIB_IB_CFG_VL_HIGH_CAP:
3630 ret = 16;
3631 goto done;
3632
3633 case QIB_IB_CFG_VL_LOW_CAP:
3634 ret = 16;
3635 goto done;
3636
3637 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3638 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3639 OverrunThreshold);
3640 goto done;
3641
3642 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3643 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3644 PhyerrThreshold);
3645 goto done;
3646
3647 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3648 /* will only take effect when the link state changes */
3649 ret = (ppd->cpspec->ibcctrl_a &
3650 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
3651 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
3652 goto done;
3653
3654 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
3655 lsb = IBA7322_IBC_HRTBT_LSB;
3656 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3657 break;
3658
3659 case QIB_IB_CFG_PMA_TICKS:
3660 /*
3661 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
3662 * Since the clock is always 250MHz, the value is 3, 1 or 0.
3663 */
3664 if (ppd->link_speed_active == QIB_IB_QDR)
3665 ret = 3;
3666 else if (ppd->link_speed_active == QIB_IB_DDR)
3667 ret = 1;
3668 else
3669 ret = 0;
3670 goto done;
3671
3672 default:
3673 ret = -EINVAL;
3674 goto done;
3675 }
3676 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
3677 done:
3678 return ret;
3679 }
3680
3681 /*
3682 * Below again cribbed liberally from older version. Do not lean
3683 * heavily on it.
3684 */
3685 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
3686 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
3687 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
3688
3689 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
3690 {
3691 struct qib_devdata *dd = ppd->dd;
3692 u64 maskr; /* right-justified mask */
3693 int lsb, ret = 0;
3694 u16 lcmd, licmd;
3695 unsigned long flags;
3696
3697 switch (which) {
3698 case QIB_IB_CFG_LIDLMC:
3699 /*
3700 * Set LID and LMC. Combined to avoid possible hazard
3701 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
3702 */
3703 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
3704 maskr = IBA7322_IBC_DLIDLMC_MASK;
3705 /*
3706 * For header-checking, the SLID in the packet will
3707 * be masked with SendIBSLMCMask, and compared
3708 * with SendIBSLIDAssignMask. Make sure we do not
3709 * set any bits not covered by the mask, or we get
3710 * false-positives.
3711 */
3712 qib_write_kreg_port(ppd, krp_sendslid,
3713 val & (val >> 16) & SendIBSLIDAssignMask);
3714 qib_write_kreg_port(ppd, krp_sendslidmask,
3715 (val >> 16) & SendIBSLMCMask);
3716 break;
3717
3718 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
3719 ppd->link_width_enabled = val;
3720 /* convert IB value to chip register value */
3721 if (val == IB_WIDTH_1X)
3722 val = 0;
3723 else if (val == IB_WIDTH_4X)
3724 val = 1;
3725 else
3726 val = 3;
3727 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
3728 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
3729 break;
3730
3731 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
3732 /*
3733 * As with width, only write the actual register if the
3734 * link is currently down, otherwise takes effect on next
3735 * link change. Since setting is being explicitly requested
3736 * (via MAD or sysfs), clear autoneg failure status if speed
3737 * autoneg is enabled.
3738 */
3739 ppd->link_speed_enabled = val;
3740 val <<= IBA7322_IBC_SPEED_LSB;
3741 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
3742 IBA7322_IBC_MAX_SPEED_MASK;
3743 if (val & (val - 1)) {
3744 /* Muliple speeds enabled */
3745 val |= IBA7322_IBC_IBTA_1_2_MASK |
3746 IBA7322_IBC_MAX_SPEED_MASK;
3747 spin_lock_irqsave(&ppd->lflags_lock, flags);
3748 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3749 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3750 } else if (val & IBA7322_IBC_SPEED_QDR)
3751 val |= IBA7322_IBC_IBTA_1_2_MASK;
3752 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
3753 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
3754 break;
3755
3756 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
3757 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3758 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3759 break;
3760
3761 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
3762 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3763 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3764 break;
3765
3766 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3767 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3768 OverrunThreshold);
3769 if (maskr != val) {
3770 ppd->cpspec->ibcctrl_a &=
3771 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
3772 ppd->cpspec->ibcctrl_a |= (u64) val <<
3773 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
3774 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3775 ppd->cpspec->ibcctrl_a);
3776 qib_write_kreg(dd, kr_scratch, 0ULL);
3777 }
3778 goto bail;
3779
3780 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3781 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3782 PhyerrThreshold);
3783 if (maskr != val) {
3784 ppd->cpspec->ibcctrl_a &=
3785 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
3786 ppd->cpspec->ibcctrl_a |= (u64) val <<
3787 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
3788 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3789 ppd->cpspec->ibcctrl_a);
3790 qib_write_kreg(dd, kr_scratch, 0ULL);
3791 }
3792 goto bail;
3793
3794 case QIB_IB_CFG_PKEYS: /* update pkeys */
3795 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
3796 ((u64) ppd->pkeys[2] << 32) |
3797 ((u64) ppd->pkeys[3] << 48);
3798 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
3799 goto bail;
3800
3801 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3802 /* will only take effect when the link state changes */
3803 if (val == IB_LINKINITCMD_POLL)
3804 ppd->cpspec->ibcctrl_a &=
3805 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3806 else /* SLEEP */
3807 ppd->cpspec->ibcctrl_a |=
3808 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3809 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
3810 qib_write_kreg(dd, kr_scratch, 0ULL);
3811 goto bail;
3812
3813 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
3814 /*
3815 * Update our housekeeping variables, and set IBC max
3816 * size, same as init code; max IBC is max we allow in
3817 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
3818 * Set even if it's unchanged, print debug message only
3819 * on changes.
3820 */
3821 val = (ppd->ibmaxlen >> 2) + 1;
3822 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
3823 ppd->cpspec->ibcctrl_a |= (u64)val <<
3824 SYM_LSB(IBCCtrlA_0, MaxPktLen);
3825 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3826 ppd->cpspec->ibcctrl_a);
3827 qib_write_kreg(dd, kr_scratch, 0ULL);
3828 goto bail;
3829
3830 case QIB_IB_CFG_LSTATE: /* set the IB link state */
3831 switch (val & 0xffff0000) {
3832 case IB_LINKCMD_DOWN:
3833 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
3834 ppd->cpspec->ibmalfusesnap = 1;
3835 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
3836 crp_errlink);
3837 if (!ppd->cpspec->ibdeltainprog &&
3838 qib_compat_ddr_negotiate) {
3839 ppd->cpspec->ibdeltainprog = 1;
3840 ppd->cpspec->ibsymsnap =
3841 read_7322_creg32_port(ppd,
3842 crp_ibsymbolerr);
3843 ppd->cpspec->iblnkerrsnap =
3844 read_7322_creg32_port(ppd,
3845 crp_iblinkerrrecov);
3846 }
3847 break;
3848
3849 case IB_LINKCMD_ARMED:
3850 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
3851 if (ppd->cpspec->ibmalfusesnap) {
3852 ppd->cpspec->ibmalfusesnap = 0;
3853 ppd->cpspec->ibmalfdelta +=
3854 read_7322_creg32_port(ppd,
3855 crp_errlink) -
3856 ppd->cpspec->ibmalfsnap;
3857 }
3858 break;
3859
3860 case IB_LINKCMD_ACTIVE:
3861 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
3862 break;
3863
3864 default:
3865 ret = -EINVAL;
3866 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
3867 goto bail;
3868 }
3869 switch (val & 0xffff) {
3870 case IB_LINKINITCMD_NOP:
3871 licmd = 0;
3872 break;
3873
3874 case IB_LINKINITCMD_POLL:
3875 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
3876 break;
3877
3878 case IB_LINKINITCMD_SLEEP:
3879 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
3880 break;
3881
3882 case IB_LINKINITCMD_DISABLE:
3883 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
3884 ppd->cpspec->chase_end = 0;
3885 /*
3886 * stop state chase counter and timer, if running.
3887 * wait forpending timer, but don't clear .data (ppd)!
3888 */
3889 if (ppd->cpspec->chase_timer.expires) {
3890 del_timer_sync(&ppd->cpspec->chase_timer);
3891 ppd->cpspec->chase_timer.expires = 0;
3892 }
3893 break;
3894
3895 default:
3896 ret = -EINVAL;
3897 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
3898 val & 0xffff);
3899 goto bail;
3900 }
3901 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
3902 goto bail;
3903
3904 case QIB_IB_CFG_OP_VLS:
3905 if (ppd->vls_operational != val) {
3906 ppd->vls_operational = val;
3907 set_vls(ppd);
3908 }
3909 goto bail;
3910
3911 case QIB_IB_CFG_VL_HIGH_LIMIT:
3912 qib_write_kreg_port(ppd, krp_highprio_limit, val);
3913 goto bail;
3914
3915 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
3916 if (val > 3) {
3917 ret = -EINVAL;
3918 goto bail;
3919 }
3920 lsb = IBA7322_IBC_HRTBT_LSB;
3921 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3922 break;
3923
3924 case QIB_IB_CFG_PORT:
3925 /* val is the port number of the switch we are connected to. */
3926 if (ppd->dd->cspec->r1) {
3927 cancel_delayed_work(&ppd->cpspec->ipg_work);
3928 ppd->cpspec->ipg_tries = 0;
3929 }
3930 goto bail;
3931
3932 default:
3933 ret = -EINVAL;
3934 goto bail;
3935 }
3936 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
3937 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
3938 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
3939 qib_write_kreg(dd, kr_scratch, 0);
3940 bail:
3941 return ret;
3942 }
3943
3944 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
3945 {
3946 int ret = 0;
3947 u64 val, ctrlb;
3948
3949 /* only IBC loopback, may add serdes and xgxs loopbacks later */
3950 if (!strncmp(what, "ibc", 3)) {
3951 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
3952 Loopback);
3953 val = 0; /* disable heart beat, so link will come up */
3954 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
3955 ppd->dd->unit, ppd->port);
3956 } else if (!strncmp(what, "off", 3)) {
3957 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
3958 Loopback);
3959 /* enable heart beat again */
3960 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
3961 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback "
3962 "(normal)\n", ppd->dd->unit, ppd->port);
3963 } else
3964 ret = -EINVAL;
3965 if (!ret) {
3966 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3967 ppd->cpspec->ibcctrl_a);
3968 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
3969 << IBA7322_IBC_HRTBT_LSB);
3970 ppd->cpspec->ibcctrl_b = ctrlb | val;
3971 qib_write_kreg_port(ppd, krp_ibcctrl_b,
3972 ppd->cpspec->ibcctrl_b);
3973 qib_write_kreg(ppd->dd, kr_scratch, 0);
3974 }
3975 return ret;
3976 }
3977
3978 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
3979 struct ib_vl_weight_elem *vl)
3980 {
3981 unsigned i;
3982
3983 for (i = 0; i < 16; i++, regno++, vl++) {
3984 u32 val = qib_read_kreg_port(ppd, regno);
3985
3986 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
3987 SYM_RMASK(LowPriority0_0, VirtualLane);
3988 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
3989 SYM_RMASK(LowPriority0_0, Weight);
3990 }
3991 }
3992
3993 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
3994 struct ib_vl_weight_elem *vl)
3995 {
3996 unsigned i;
3997
3998 for (i = 0; i < 16; i++, regno++, vl++) {
3999 u64 val;
4000
4001 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
4002 SYM_LSB(LowPriority0_0, VirtualLane)) |
4003 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
4004 SYM_LSB(LowPriority0_0, Weight));
4005 qib_write_kreg_port(ppd, regno, val);
4006 }
4007 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
4008 struct qib_devdata *dd = ppd->dd;
4009 unsigned long flags;
4010
4011 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4012 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4013 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4014 qib_write_kreg(dd, kr_scratch, 0);
4015 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4016 }
4017 }
4018
4019 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
4020 {
4021 switch (which) {
4022 case QIB_IB_TBL_VL_HIGH_ARB:
4023 get_vl_weights(ppd, krp_highprio_0, t);
4024 break;
4025
4026 case QIB_IB_TBL_VL_LOW_ARB:
4027 get_vl_weights(ppd, krp_lowprio_0, t);
4028 break;
4029
4030 default:
4031 return -EINVAL;
4032 }
4033 return 0;
4034 }
4035
4036 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4037 {
4038 switch (which) {
4039 case QIB_IB_TBL_VL_HIGH_ARB:
4040 set_vl_weights(ppd, krp_highprio_0, t);
4041 break;
4042
4043 case QIB_IB_TBL_VL_LOW_ARB:
4044 set_vl_weights(ppd, krp_lowprio_0, t);
4045 break;
4046
4047 default:
4048 return -EINVAL;
4049 }
4050 return 0;
4051 }
4052
4053 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
4054 u32 updegr, u32 egrhd, u32 npkts)
4055 {
4056 /*
4057 * Need to write timeout register before updating rcvhdrhead to ensure
4058 * that the timer is enabled on reception of a packet.
4059 */
4060 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT)
4061 adjust_rcv_timeout(rcd, npkts);
4062 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4063 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4064 if (updegr)
4065 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
4066 }
4067
4068 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4069 {
4070 u32 head, tail;
4071
4072 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4073 if (rcd->rcvhdrtail_kvaddr)
4074 tail = qib_get_rcvhdrtail(rcd);
4075 else
4076 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4077 return head == tail;
4078 }
4079
4080 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4081 QIB_RCVCTRL_CTXT_DIS | \
4082 QIB_RCVCTRL_TIDFLOW_ENB | \
4083 QIB_RCVCTRL_TIDFLOW_DIS | \
4084 QIB_RCVCTRL_TAILUPD_ENB | \
4085 QIB_RCVCTRL_TAILUPD_DIS | \
4086 QIB_RCVCTRL_INTRAVAIL_ENB | \
4087 QIB_RCVCTRL_INTRAVAIL_DIS | \
4088 QIB_RCVCTRL_BP_ENB | \
4089 QIB_RCVCTRL_BP_DIS)
4090
4091 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4092 QIB_RCVCTRL_CTXT_DIS | \
4093 QIB_RCVCTRL_PKEY_DIS | \
4094 QIB_RCVCTRL_PKEY_ENB)
4095
4096 /*
4097 * Modify the RCVCTRL register in chip-specific way. This
4098 * is a function because bit positions and (future) register
4099 * location is chip-specifc, but the needed operations are
4100 * generic. <op> is a bit-mask because we often want to
4101 * do multiple modifications.
4102 */
4103 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4104 int ctxt)
4105 {
4106 struct qib_devdata *dd = ppd->dd;
4107 struct qib_ctxtdata *rcd;
4108 u64 mask, val;
4109 unsigned long flags;
4110
4111 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4112
4113 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4114 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4115 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4116 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4117 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4118 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4119 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4120 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4121 if (op & QIB_RCVCTRL_PKEY_ENB)
4122 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4123 if (op & QIB_RCVCTRL_PKEY_DIS)
4124 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4125 if (ctxt < 0) {
4126 mask = (1ULL << dd->ctxtcnt) - 1;
4127 rcd = NULL;
4128 } else {
4129 mask = (1ULL << ctxt);
4130 rcd = dd->rcd[ctxt];
4131 }
4132 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4133 ppd->p_rcvctrl |=
4134 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4135 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4136 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */
4137 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4138 }
4139 /* Write these registers before the context is enabled. */
4140 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4141 rcd->rcvhdrqtailaddr_phys);
4142 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4143 rcd->rcvhdrq_phys);
4144 rcd->seq_cnt = 1;
4145 }
4146 if (op & QIB_RCVCTRL_CTXT_DIS)
4147 ppd->p_rcvctrl &=
4148 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4149 if (op & QIB_RCVCTRL_BP_ENB)
4150 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4151 if (op & QIB_RCVCTRL_BP_DIS)
4152 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4153 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4154 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4155 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4156 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4157 /*
4158 * Decide which registers to write depending on the ops enabled.
4159 * Special case is "flush" (no bits set at all)
4160 * which needs to write both.
4161 */
4162 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4163 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4164 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4165 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4166 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4167 /*
4168 * Init the context registers also; if we were
4169 * disabled, tail and head should both be zero
4170 * already from the enable, but since we don't
4171 * know, we have to do it explicitly.
4172 */
4173 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4174 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4175
4176 /* be sure enabling write seen; hd/tl should be 0 */
4177 (void) qib_read_kreg32(dd, kr_scratch);
4178 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4179 dd->rcd[ctxt]->head = val;
4180 /* If kctxt, interrupt on next receive. */
4181 if (ctxt < dd->first_user_ctxt)
4182 val |= dd->rhdrhead_intr_off;
4183 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4184 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4185 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4186 /* arm rcv interrupt */
4187 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4188 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4189 }
4190 if (op & QIB_RCVCTRL_CTXT_DIS) {
4191 unsigned f;
4192
4193 /* Now that the context is disabled, clear these registers. */
4194 if (ctxt >= 0) {
4195 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4196 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4197 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4198 qib_write_ureg(dd, ur_rcvflowtable + f,
4199 TIDFLOW_ERRBITS, ctxt);
4200 } else {
4201 unsigned i;
4202
4203 for (i = 0; i < dd->cfgctxts; i++) {
4204 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4205 i, 0);
4206 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4207 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4208 qib_write_ureg(dd, ur_rcvflowtable + f,
4209 TIDFLOW_ERRBITS, i);
4210 }
4211 }
4212 }
4213 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4214 }
4215
4216 /*
4217 * Modify the SENDCTRL register in chip-specific way. This
4218 * is a function where there are multiple such registers with
4219 * slightly different layouts.
4220 * The chip doesn't allow back-to-back sendctrl writes, so write
4221 * the scratch register after writing sendctrl.
4222 *
4223 * Which register is written depends on the operation.
4224 * Most operate on the common register, while
4225 * SEND_ENB and SEND_DIS operate on the per-port ones.
4226 * SEND_ENB is included in common because it can change SPCL_TRIG
4227 */
4228 #define SENDCTRL_COMMON_MODS (\
4229 QIB_SENDCTRL_CLEAR | \
4230 QIB_SENDCTRL_AVAIL_DIS | \
4231 QIB_SENDCTRL_AVAIL_ENB | \
4232 QIB_SENDCTRL_AVAIL_BLIP | \
4233 QIB_SENDCTRL_DISARM | \
4234 QIB_SENDCTRL_DISARM_ALL | \
4235 QIB_SENDCTRL_SEND_ENB)
4236
4237 #define SENDCTRL_PORT_MODS (\
4238 QIB_SENDCTRL_CLEAR | \
4239 QIB_SENDCTRL_SEND_ENB | \
4240 QIB_SENDCTRL_SEND_DIS | \
4241 QIB_SENDCTRL_FLUSH)
4242
4243 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4244 {
4245 struct qib_devdata *dd = ppd->dd;
4246 u64 tmp_dd_sendctrl;
4247 unsigned long flags;
4248
4249 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4250
4251 /* First the dd ones that are "sticky", saved in shadow */
4252 if (op & QIB_SENDCTRL_CLEAR)
4253 dd->sendctrl = 0;
4254 if (op & QIB_SENDCTRL_AVAIL_DIS)
4255 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4256 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4257 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4258 if (dd->flags & QIB_USE_SPCL_TRIG)
4259 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4260 }
4261
4262 /* Then the ppd ones that are "sticky", saved in shadow */
4263 if (op & QIB_SENDCTRL_SEND_DIS)
4264 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4265 else if (op & QIB_SENDCTRL_SEND_ENB)
4266 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4267
4268 if (op & QIB_SENDCTRL_DISARM_ALL) {
4269 u32 i, last;
4270
4271 tmp_dd_sendctrl = dd->sendctrl;
4272 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4273 /*
4274 * Disarm any buffers that are not yet launched,
4275 * disabling updates until done.
4276 */
4277 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4278 for (i = 0; i < last; i++) {
4279 qib_write_kreg(dd, kr_sendctrl,
4280 tmp_dd_sendctrl |
4281 SYM_MASK(SendCtrl, Disarm) | i);
4282 qib_write_kreg(dd, kr_scratch, 0);
4283 }
4284 }
4285
4286 if (op & QIB_SENDCTRL_FLUSH) {
4287 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4288
4289 /*
4290 * Now drain all the fifos. The Abort bit should never be
4291 * needed, so for now, at least, we don't use it.
4292 */
4293 tmp_ppd_sendctrl |=
4294 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4295 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4296 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4297 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4298 qib_write_kreg(dd, kr_scratch, 0);
4299 }
4300
4301 tmp_dd_sendctrl = dd->sendctrl;
4302
4303 if (op & QIB_SENDCTRL_DISARM)
4304 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4305 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4306 SYM_LSB(SendCtrl, DisarmSendBuf));
4307 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4308 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4309 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4310
4311 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4312 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4313 qib_write_kreg(dd, kr_scratch, 0);
4314 }
4315
4316 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4317 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4318 qib_write_kreg(dd, kr_scratch, 0);
4319 }
4320
4321 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4322 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4323 qib_write_kreg(dd, kr_scratch, 0);
4324 }
4325
4326 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4327
4328 if (op & QIB_SENDCTRL_FLUSH) {
4329 u32 v;
4330 /*
4331 * ensure writes have hit chip, then do a few
4332 * more reads, to allow DMA of pioavail registers
4333 * to occur, so in-memory copy is in sync with
4334 * the chip. Not always safe to sleep.
4335 */
4336 v = qib_read_kreg32(dd, kr_scratch);
4337 qib_write_kreg(dd, kr_scratch, v);
4338 v = qib_read_kreg32(dd, kr_scratch);
4339 qib_write_kreg(dd, kr_scratch, v);
4340 qib_read_kreg32(dd, kr_scratch);
4341 }
4342 }
4343
4344 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4345 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4346 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4347
4348 /**
4349 * qib_portcntr_7322 - read a per-port chip counter
4350 * @ppd: the qlogic_ib pport
4351 * @creg: the counter to read (not a chip offset)
4352 */
4353 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4354 {
4355 struct qib_devdata *dd = ppd->dd;
4356 u64 ret = 0ULL;
4357 u16 creg;
4358 /* 0xffff for unimplemented or synthesized counters */
4359 static const u32 xlator[] = {
4360 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4361 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4362 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4363 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4364 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4365 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4366 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4367 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4368 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4369 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4370 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4371 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4372 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */
4373 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4374 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4375 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4376 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4377 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4378 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4379 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4380 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4381 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4382 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4383 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4384 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4385 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4386 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4387 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4388 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4389 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4390 /*
4391 * the next 3 aren't really counters, but were implemented
4392 * as counters in older chips, so still get accessed as
4393 * though they were counters from this code.
4394 */
4395 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4396 [QIBPORTCNTR_PSSTART] = krp_psstart,
4397 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4398 /* pseudo-counter, summed for all ports */
4399 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4400 };
4401
4402 if (reg >= ARRAY_SIZE(xlator)) {
4403 qib_devinfo(ppd->dd->pcidev,
4404 "Unimplemented portcounter %u\n", reg);
4405 goto done;
4406 }
4407 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4408
4409 /* handle non-counters and special cases first */
4410 if (reg == QIBPORTCNTR_KHDROVFL) {
4411 int i;
4412
4413 /* sum over all kernel contexts (skip if mini_init) */
4414 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4415 struct qib_ctxtdata *rcd = dd->rcd[i];
4416
4417 if (!rcd || rcd->ppd != ppd)
4418 continue;
4419 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4420 }
4421 goto done;
4422 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4423 /*
4424 * Used as part of the synthesis of port_rcv_errors
4425 * in the verbs code for IBTA counters. Not needed for 7322,
4426 * because all the errors are already counted by other cntrs.
4427 */
4428 goto done;
4429 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4430 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4431 /* were counters in older chips, now per-port kernel regs */
4432 ret = qib_read_kreg_port(ppd, creg);
4433 goto done;
4434 }
4435
4436 /*
4437 * Only fast increment counters are 64 bits; use 32 bit reads to
4438 * avoid two independent reads when on Opteron.
4439 */
4440 if (xlator[reg] & _PORT_64BIT_FLAG)
4441 ret = read_7322_creg_port(ppd, creg);
4442 else
4443 ret = read_7322_creg32_port(ppd, creg);
4444 if (creg == crp_ibsymbolerr) {
4445 if (ppd->cpspec->ibdeltainprog)
4446 ret -= ret - ppd->cpspec->ibsymsnap;
4447 ret -= ppd->cpspec->ibsymdelta;
4448 } else if (creg == crp_iblinkerrrecov) {
4449 if (ppd->cpspec->ibdeltainprog)
4450 ret -= ret - ppd->cpspec->iblnkerrsnap;
4451 ret -= ppd->cpspec->iblnkerrdelta;
4452 } else if (creg == crp_errlink)
4453 ret -= ppd->cpspec->ibmalfdelta;
4454 else if (creg == crp_iblinkdown)
4455 ret += ppd->cpspec->iblnkdowndelta;
4456 done:
4457 return ret;
4458 }
4459
4460 /*
4461 * Device counter names (not port-specific), one line per stat,
4462 * single string. Used by utilities like ipathstats to print the stats
4463 * in a way which works for different versions of drivers, without changing
4464 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4465 * display by utility.
4466 * Non-error counters are first.
4467 * Start of "error" conters is indicated by a leading "E " on the first
4468 * "error" counter, and doesn't count in label length.
4469 * The EgrOvfl list needs to be last so we truncate them at the configured
4470 * context count for the device.
4471 * cntr7322indices contains the corresponding register indices.
4472 */
4473 static const char cntr7322names[] =
4474 "Interrupts\n"
4475 "HostBusStall\n"
4476 "E RxTIDFull\n"
4477 "RxTIDInvalid\n"
4478 "RxTIDFloDrop\n" /* 7322 only */
4479 "Ctxt0EgrOvfl\n"
4480 "Ctxt1EgrOvfl\n"
4481 "Ctxt2EgrOvfl\n"
4482 "Ctxt3EgrOvfl\n"
4483 "Ctxt4EgrOvfl\n"
4484 "Ctxt5EgrOvfl\n"
4485 "Ctxt6EgrOvfl\n"
4486 "Ctxt7EgrOvfl\n"
4487 "Ctxt8EgrOvfl\n"
4488 "Ctxt9EgrOvfl\n"
4489 "Ctx10EgrOvfl\n"
4490 "Ctx11EgrOvfl\n"
4491 "Ctx12EgrOvfl\n"
4492 "Ctx13EgrOvfl\n"
4493 "Ctx14EgrOvfl\n"
4494 "Ctx15EgrOvfl\n"
4495 "Ctx16EgrOvfl\n"
4496 "Ctx17EgrOvfl\n"
4497 ;
4498
4499 static const u32 cntr7322indices[] = {
4500 cr_lbint | _PORT_64BIT_FLAG,
4501 cr_lbstall | _PORT_64BIT_FLAG,
4502 cr_tidfull,
4503 cr_tidinvalid,
4504 cr_rxtidflowdrop,
4505 cr_base_egrovfl + 0,
4506 cr_base_egrovfl + 1,
4507 cr_base_egrovfl + 2,
4508 cr_base_egrovfl + 3,
4509 cr_base_egrovfl + 4,
4510 cr_base_egrovfl + 5,
4511 cr_base_egrovfl + 6,
4512 cr_base_egrovfl + 7,
4513 cr_base_egrovfl + 8,
4514 cr_base_egrovfl + 9,
4515 cr_base_egrovfl + 10,
4516 cr_base_egrovfl + 11,
4517 cr_base_egrovfl + 12,
4518 cr_base_egrovfl + 13,
4519 cr_base_egrovfl + 14,
4520 cr_base_egrovfl + 15,
4521 cr_base_egrovfl + 16,
4522 cr_base_egrovfl + 17,
4523 };
4524
4525 /*
4526 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4527 * portcntr7322indices is somewhat complicated by some registers needing
4528 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4529 */
4530 static const char portcntr7322names[] =
4531 "TxPkt\n"
4532 "TxFlowPkt\n"
4533 "TxWords\n"
4534 "RxPkt\n"
4535 "RxFlowPkt\n"
4536 "RxWords\n"
4537 "TxFlowStall\n"
4538 "TxDmaDesc\n" /* 7220 and 7322-only */
4539 "E RxDlidFltr\n" /* 7220 and 7322-only */
4540 "IBStatusChng\n"
4541 "IBLinkDown\n"
4542 "IBLnkRecov\n"
4543 "IBRxLinkErr\n"
4544 "IBSymbolErr\n"
4545 "RxLLIErr\n"
4546 "RxBadFormat\n"
4547 "RxBadLen\n"
4548 "RxBufOvrfl\n"
4549 "RxEBP\n"
4550 "RxFlowCtlErr\n"
4551 "RxICRCerr\n"
4552 "RxLPCRCerr\n"
4553 "RxVCRCerr\n"
4554 "RxInvalLen\n"
4555 "RxInvalPKey\n"
4556 "RxPktDropped\n"
4557 "TxBadLength\n"
4558 "TxDropped\n"
4559 "TxInvalLen\n"
4560 "TxUnderrun\n"
4561 "TxUnsupVL\n"
4562 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4563 "RxVL15Drop\n"
4564 "RxVlErr\n"
4565 "XcessBufOvfl\n"
4566 "RxQPBadCtxt\n" /* 7322-only from here down */
4567 "TXBadHeader\n"
4568 ;
4569
4570 static const u32 portcntr7322indices[] = {
4571 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
4572 crp_pktsendflow,
4573 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
4574 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
4575 crp_pktrcvflowctrl,
4576 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
4577 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
4578 crp_txsdmadesc | _PORT_64BIT_FLAG,
4579 crp_rxdlidfltr,
4580 crp_ibstatuschange,
4581 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
4582 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
4583 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
4584 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
4585 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
4586 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
4587 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
4588 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
4589 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
4590 crp_rcvflowctrlviol,
4591 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
4592 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
4593 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
4594 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
4595 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
4596 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
4597 crp_txminmaxlenerr,
4598 crp_txdroppedpkt,
4599 crp_txlenerr,
4600 crp_txunderrun,
4601 crp_txunsupvl,
4602 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
4603 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
4604 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
4605 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
4606 crp_rxqpinvalidctxt,
4607 crp_txhdrerr,
4608 };
4609
4610 /* do all the setup to make the counter reads efficient later */
4611 static void init_7322_cntrnames(struct qib_devdata *dd)
4612 {
4613 int i, j = 0;
4614 char *s;
4615
4616 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
4617 i++) {
4618 /* we always have at least one counter before the egrovfl */
4619 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
4620 j = 1;
4621 s = strchr(s + 1, '\n');
4622 if (s && j)
4623 j++;
4624 }
4625 dd->cspec->ncntrs = i;
4626 if (!s)
4627 /* full list; size is without terminating null */
4628 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
4629 else
4630 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
4631 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
4632 * sizeof(u64), GFP_KERNEL);
4633 if (!dd->cspec->cntrs)
4634 qib_dev_err(dd, "Failed allocation for counters\n");
4635
4636 for (i = 0, s = (char *)portcntr7322names; s; i++)
4637 s = strchr(s + 1, '\n');
4638 dd->cspec->nportcntrs = i - 1;
4639 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
4640 for (i = 0; i < dd->num_pports; ++i) {
4641 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
4642 * sizeof(u64), GFP_KERNEL);
4643 if (!dd->pport[i].cpspec->portcntrs)
4644 qib_dev_err(dd, "Failed allocation for"
4645 " portcounters\n");
4646 }
4647 }
4648
4649 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
4650 u64 **cntrp)
4651 {
4652 u32 ret;
4653
4654 if (namep) {
4655 ret = dd->cspec->cntrnamelen;
4656 if (pos >= ret)
4657 ret = 0; /* final read after getting everything */
4658 else
4659 *namep = (char *) cntr7322names;
4660 } else {
4661 u64 *cntr = dd->cspec->cntrs;
4662 int i;
4663
4664 ret = dd->cspec->ncntrs * sizeof(u64);
4665 if (!cntr || pos >= ret) {
4666 /* everything read, or couldn't get memory */
4667 ret = 0;
4668 goto done;
4669 }
4670 *cntrp = cntr;
4671 for (i = 0; i < dd->cspec->ncntrs; i++)
4672 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
4673 *cntr++ = read_7322_creg(dd,
4674 cntr7322indices[i] &
4675 _PORT_CNTR_IDXMASK);
4676 else
4677 *cntr++ = read_7322_creg32(dd,
4678 cntr7322indices[i]);
4679 }
4680 done:
4681 return ret;
4682 }
4683
4684 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
4685 char **namep, u64 **cntrp)
4686 {
4687 u32 ret;
4688
4689 if (namep) {
4690 ret = dd->cspec->portcntrnamelen;
4691 if (pos >= ret)
4692 ret = 0; /* final read after getting everything */
4693 else
4694 *namep = (char *)portcntr7322names;
4695 } else {
4696 struct qib_pportdata *ppd = &dd->pport[port];
4697 u64 *cntr = ppd->cpspec->portcntrs;
4698 int i;
4699
4700 ret = dd->cspec->nportcntrs * sizeof(u64);
4701 if (!cntr || pos >= ret) {
4702 /* everything read, or couldn't get memory */
4703 ret = 0;
4704 goto done;
4705 }
4706 *cntrp = cntr;
4707 for (i = 0; i < dd->cspec->nportcntrs; i++) {
4708 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
4709 *cntr++ = qib_portcntr_7322(ppd,
4710 portcntr7322indices[i] &
4711 _PORT_CNTR_IDXMASK);
4712 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
4713 *cntr++ = read_7322_creg_port(ppd,
4714 portcntr7322indices[i] &
4715 _PORT_CNTR_IDXMASK);
4716 else
4717 *cntr++ = read_7322_creg32_port(ppd,
4718 portcntr7322indices[i]);
4719 }
4720 }
4721 done:
4722 return ret;
4723 }
4724
4725 /**
4726 * qib_get_7322_faststats - get word counters from chip before they overflow
4727 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
4728 *
4729 * VESTIGIAL IBA7322 has no "small fast counters", so the only
4730 * real purpose of this function is to maintain the notion of
4731 * "active time", which in turn is only logged into the eeprom,
4732 * which we don;t have, yet, for 7322-based boards.
4733 *
4734 * called from add_timer
4735 */
4736 static void qib_get_7322_faststats(unsigned long opaque)
4737 {
4738 struct qib_devdata *dd = (struct qib_devdata *) opaque;
4739 struct qib_pportdata *ppd;
4740 unsigned long flags;
4741 u64 traffic_wds;
4742 int pidx;
4743
4744 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
4745 ppd = dd->pport + pidx;
4746
4747 /*
4748 * If port isn't enabled or not operational ports, or
4749 * diags is running (can cause memory diags to fail)
4750 * skip this port this time.
4751 */
4752 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
4753 || dd->diag_client)
4754 continue;
4755
4756 /*
4757 * Maintain an activity timer, based on traffic
4758 * exceeding a threshold, so we need to check the word-counts
4759 * even if they are 64-bit.
4760 */
4761 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
4762 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
4763 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
4764 traffic_wds -= ppd->dd->traffic_wds;
4765 ppd->dd->traffic_wds += traffic_wds;
4766 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
4767 atomic_add(ACTIVITY_TIMER, &ppd->dd->active_time);
4768 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
4769 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
4770 QIB_IB_QDR) &&
4771 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
4772 QIBL_LINKACTIVE)) &&
4773 ppd->cpspec->qdr_dfe_time &&
4774 time_after64(get_jiffies_64(), ppd->cpspec->qdr_dfe_time)) {
4775 ppd->cpspec->qdr_dfe_on = 0;
4776
4777 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
4778 ppd->dd->cspec->r1 ?
4779 QDR_STATIC_ADAPT_INIT_R1 :
4780 QDR_STATIC_ADAPT_INIT);
4781 force_h1(ppd);
4782 }
4783 }
4784 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
4785 }
4786
4787 /*
4788 * If we were using MSIx, try to fallback to INTx.
4789 */
4790 static int qib_7322_intr_fallback(struct qib_devdata *dd)
4791 {
4792 if (!dd->cspec->num_msix_entries)
4793 return 0; /* already using INTx */
4794
4795 qib_devinfo(dd->pcidev, "MSIx interrupt not detected,"
4796 " trying INTx interrupts\n");
4797 qib_7322_nomsix(dd);
4798 qib_enable_intx(dd->pcidev);
4799 qib_setup_7322_interrupt(dd, 0);
4800 return 1;
4801 }
4802
4803 /*
4804 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
4805 * than resetting the IBC or external link state, and useful in some
4806 * cases to cause some retraining. To do this right, we reset IBC
4807 * as well, then return to previous state (which may be still in reset)
4808 * NOTE: some callers of this "know" this writes the current value
4809 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
4810 * check all callers.
4811 */
4812 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
4813 {
4814 u64 val;
4815 struct qib_devdata *dd = ppd->dd;
4816 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
4817 SYM_MASK(IBPCSConfig_0, xcv_treset) |
4818 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
4819
4820 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
4821 qib_write_kreg(dd, kr_hwerrmask,
4822 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
4823 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4824 ppd->cpspec->ibcctrl_a &
4825 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
4826
4827 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
4828 qib_read_kreg32(dd, kr_scratch);
4829 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
4830 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4831 qib_write_kreg(dd, kr_scratch, 0ULL);
4832 qib_write_kreg(dd, kr_hwerrclear,
4833 SYM_MASK(HwErrClear, statusValidNoEopClear));
4834 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
4835 }
4836
4837 /*
4838 * This code for non-IBTA-compliant IB speed negotiation is only known to
4839 * work for the SDR to DDR transition, and only between an HCA and a switch
4840 * with recent firmware. It is based on observed heuristics, rather than
4841 * actual knowledge of the non-compliant speed negotiation.
4842 * It has a number of hard-coded fields, since the hope is to rewrite this
4843 * when a spec is available on how the negoation is intended to work.
4844 */
4845 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
4846 u32 dcnt, u32 *data)
4847 {
4848 int i;
4849 u64 pbc;
4850 u32 __iomem *piobuf;
4851 u32 pnum, control, len;
4852 struct qib_devdata *dd = ppd->dd;
4853
4854 i = 0;
4855 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
4856 control = qib_7322_setpbc_control(ppd, len, 0, 15);
4857 pbc = ((u64) control << 32) | len;
4858 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
4859 if (i++ > 15)
4860 return;
4861 udelay(2);
4862 }
4863 /* disable header check on this packet, since it can't be valid */
4864 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
4865 writeq(pbc, piobuf);
4866 qib_flush_wc();
4867 qib_pio_copy(piobuf + 2, hdr, 7);
4868 qib_pio_copy(piobuf + 9, data, dcnt);
4869 if (dd->flags & QIB_USE_SPCL_TRIG) {
4870 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
4871
4872 qib_flush_wc();
4873 __raw_writel(0xaebecede, piobuf + spcl_off);
4874 }
4875 qib_flush_wc();
4876 qib_sendbuf_done(dd, pnum);
4877 /* and re-enable hdr check */
4878 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
4879 }
4880
4881 /*
4882 * _start packet gets sent twice at start, _done gets sent twice at end
4883 */
4884 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
4885 {
4886 struct qib_devdata *dd = ppd->dd;
4887 static u32 swapped;
4888 u32 dw, i, hcnt, dcnt, *data;
4889 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
4890 static u32 madpayload_start[0x40] = {
4891 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4892 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4893 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
4894 };
4895 static u32 madpayload_done[0x40] = {
4896 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4897 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4898 0x40000001, 0x1388, 0x15e, /* rest 0's */
4899 };
4900
4901 dcnt = ARRAY_SIZE(madpayload_start);
4902 hcnt = ARRAY_SIZE(hdr);
4903 if (!swapped) {
4904 /* for maintainability, do it at runtime */
4905 for (i = 0; i < hcnt; i++) {
4906 dw = (__force u32) cpu_to_be32(hdr[i]);
4907 hdr[i] = dw;
4908 }
4909 for (i = 0; i < dcnt; i++) {
4910 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
4911 madpayload_start[i] = dw;
4912 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
4913 madpayload_done[i] = dw;
4914 }
4915 swapped = 1;
4916 }
4917
4918 data = which ? madpayload_done : madpayload_start;
4919
4920 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4921 qib_read_kreg64(dd, kr_scratch);
4922 udelay(2);
4923 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4924 qib_read_kreg64(dd, kr_scratch);
4925 udelay(2);
4926 }
4927
4928 /*
4929 * Do the absolute minimum to cause an IB speed change, and make it
4930 * ready, but don't actually trigger the change. The caller will
4931 * do that when ready (if link is in Polling training state, it will
4932 * happen immediately, otherwise when link next goes down)
4933 *
4934 * This routine should only be used as part of the DDR autonegotation
4935 * code for devices that are not compliant with IB 1.2 (or code that
4936 * fixes things up for same).
4937 *
4938 * When link has gone down, and autoneg enabled, or autoneg has
4939 * failed and we give up until next time we set both speeds, and
4940 * then we want IBTA enabled as well as "use max enabled speed.
4941 */
4942 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
4943 {
4944 u64 newctrlb;
4945 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
4946 IBA7322_IBC_IBTA_1_2_MASK |
4947 IBA7322_IBC_MAX_SPEED_MASK);
4948
4949 if (speed & (speed - 1)) /* multiple speeds */
4950 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
4951 IBA7322_IBC_IBTA_1_2_MASK |
4952 IBA7322_IBC_MAX_SPEED_MASK;
4953 else
4954 newctrlb |= speed == QIB_IB_QDR ?
4955 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
4956 ((speed == QIB_IB_DDR ?
4957 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
4958
4959 if (newctrlb == ppd->cpspec->ibcctrl_b)
4960 return;
4961
4962 ppd->cpspec->ibcctrl_b = newctrlb;
4963 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4964 qib_write_kreg(ppd->dd, kr_scratch, 0);
4965 }
4966
4967 /*
4968 * This routine is only used when we are not talking to another
4969 * IB 1.2-compliant device that we think can do DDR.
4970 * (This includes all existing switch chips as of Oct 2007.)
4971 * 1.2-compliant devices go directly to DDR prior to reaching INIT
4972 */
4973 static void try_7322_autoneg(struct qib_pportdata *ppd)
4974 {
4975 unsigned long flags;
4976
4977 spin_lock_irqsave(&ppd->lflags_lock, flags);
4978 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
4979 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
4980 qib_autoneg_7322_send(ppd, 0);
4981 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
4982 qib_7322_mini_pcs_reset(ppd);
4983 /* 2 msec is minimum length of a poll cycle */
4984 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
4985 msecs_to_jiffies(2));
4986 }
4987
4988 /*
4989 * Handle the empirically determined mechanism for auto-negotiation
4990 * of DDR speed with switches.
4991 */
4992 static void autoneg_7322_work(struct work_struct *work)
4993 {
4994 struct qib_pportdata *ppd;
4995 struct qib_devdata *dd;
4996 u64 startms;
4997 u32 i;
4998 unsigned long flags;
4999
5000 ppd = container_of(work, struct qib_chippport_specific,
5001 autoneg_work.work)->ppd;
5002 dd = ppd->dd;
5003
5004 startms = jiffies_to_msecs(jiffies);
5005
5006 /*
5007 * Busy wait for this first part, it should be at most a
5008 * few hundred usec, since we scheduled ourselves for 2msec.
5009 */
5010 for (i = 0; i < 25; i++) {
5011 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
5012 == IB_7322_LT_STATE_POLLQUIET) {
5013 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
5014 break;
5015 }
5016 udelay(100);
5017 }
5018
5019 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
5020 goto done; /* we got there early or told to stop */
5021
5022 /* we expect this to timeout */
5023 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5024 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5025 msecs_to_jiffies(90)))
5026 goto done;
5027 qib_7322_mini_pcs_reset(ppd);
5028
5029 /* we expect this to timeout */
5030 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5031 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5032 msecs_to_jiffies(1700)))
5033 goto done;
5034 qib_7322_mini_pcs_reset(ppd);
5035
5036 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5037
5038 /*
5039 * Wait up to 250 msec for link to train and get to INIT at DDR;
5040 * this should terminate early.
5041 */
5042 wait_event_timeout(ppd->cpspec->autoneg_wait,
5043 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5044 msecs_to_jiffies(250));
5045 done:
5046 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5047 spin_lock_irqsave(&ppd->lflags_lock, flags);
5048 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5049 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5050 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5051 ppd->cpspec->autoneg_tries = 0;
5052 }
5053 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5054 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5055 }
5056 }
5057
5058 /*
5059 * This routine is used to request IPG set in the QLogic switch.
5060 * Only called if r1.
5061 */
5062 static void try_7322_ipg(struct qib_pportdata *ppd)
5063 {
5064 struct qib_ibport *ibp = &ppd->ibport_data;
5065 struct ib_mad_send_buf *send_buf;
5066 struct ib_mad_agent *agent;
5067 struct ib_smp *smp;
5068 unsigned delay;
5069 int ret;
5070
5071 agent = ibp->send_agent;
5072 if (!agent)
5073 goto retry;
5074
5075 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
5076 IB_MGMT_MAD_DATA, GFP_ATOMIC);
5077 if (IS_ERR(send_buf))
5078 goto retry;
5079
5080 if (!ibp->smi_ah) {
5081 struct ib_ah_attr attr;
5082 struct ib_ah *ah;
5083
5084 memset(&attr, 0, sizeof attr);
5085 attr.dlid = be16_to_cpu(IB_LID_PERMISSIVE);
5086 attr.port_num = ppd->port;
5087 ah = ib_create_ah(ibp->qp0->ibqp.pd, &attr);
5088 if (IS_ERR(ah))
5089 ret = -EINVAL;
5090 else {
5091 send_buf->ah = ah;
5092 ibp->smi_ah = to_iah(ah);
5093 ret = 0;
5094 }
5095 } else {
5096 send_buf->ah = &ibp->smi_ah->ibah;
5097 ret = 0;
5098 }
5099
5100 smp = send_buf->mad;
5101 smp->base_version = IB_MGMT_BASE_VERSION;
5102 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5103 smp->class_version = 1;
5104 smp->method = IB_MGMT_METHOD_SEND;
5105 smp->hop_cnt = 1;
5106 smp->attr_id = QIB_VENDOR_IPG;
5107 smp->attr_mod = 0;
5108
5109 if (!ret)
5110 ret = ib_post_send_mad(send_buf, NULL);
5111 if (ret)
5112 ib_free_send_mad(send_buf);
5113 retry:
5114 delay = 2 << ppd->cpspec->ipg_tries;
5115 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work,
5116 msecs_to_jiffies(delay));
5117 }
5118
5119 /*
5120 * Timeout handler for setting IPG.
5121 * Only called if r1.
5122 */
5123 static void ipg_7322_work(struct work_struct *work)
5124 {
5125 struct qib_pportdata *ppd;
5126
5127 ppd = container_of(work, struct qib_chippport_specific,
5128 ipg_work.work)->ppd;
5129 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5130 && ++ppd->cpspec->ipg_tries <= 10)
5131 try_7322_ipg(ppd);
5132 }
5133
5134 static u32 qib_7322_iblink_state(u64 ibcs)
5135 {
5136 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5137
5138 switch (state) {
5139 case IB_7322_L_STATE_INIT:
5140 state = IB_PORT_INIT;
5141 break;
5142 case IB_7322_L_STATE_ARM:
5143 state = IB_PORT_ARMED;
5144 break;
5145 case IB_7322_L_STATE_ACTIVE:
5146 /* fall through */
5147 case IB_7322_L_STATE_ACT_DEFER:
5148 state = IB_PORT_ACTIVE;
5149 break;
5150 default: /* fall through */
5151 case IB_7322_L_STATE_DOWN:
5152 state = IB_PORT_DOWN;
5153 break;
5154 }
5155 return state;
5156 }
5157
5158 /* returns the IBTA port state, rather than the IBC link training state */
5159 static u8 qib_7322_phys_portstate(u64 ibcs)
5160 {
5161 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5162 return qib_7322_physportstate[state];
5163 }
5164
5165 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5166 {
5167 int ret = 0, symadj = 0;
5168 unsigned long flags;
5169 int mult;
5170
5171 spin_lock_irqsave(&ppd->lflags_lock, flags);
5172 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5173 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5174
5175 /* Update our picture of width and speed from chip */
5176 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5177 ppd->link_speed_active = QIB_IB_QDR;
5178 mult = 4;
5179 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5180 ppd->link_speed_active = QIB_IB_DDR;
5181 mult = 2;
5182 } else {
5183 ppd->link_speed_active = QIB_IB_SDR;
5184 mult = 1;
5185 }
5186 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5187 ppd->link_width_active = IB_WIDTH_4X;
5188 mult *= 4;
5189 } else
5190 ppd->link_width_active = IB_WIDTH_1X;
5191 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5192
5193 if (!ibup) {
5194 u64 clr;
5195
5196 /* Link went down. */
5197 /* do IPG MAD again after linkdown, even if last time failed */
5198 ppd->cpspec->ipg_tries = 0;
5199 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5200 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5201 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5202 if (clr)
5203 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5204 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5205 QIBL_IB_AUTONEG_INPROG)))
5206 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5207 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5208 /* unlock the Tx settings, speed may change */
5209 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5210 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5211 reset_tx_deemphasis_override));
5212 qib_cancel_sends(ppd);
5213 /* on link down, ensure sane pcs state */
5214 qib_7322_mini_pcs_reset(ppd);
5215 spin_lock_irqsave(&ppd->sdma_lock, flags);
5216 if (__qib_sdma_running(ppd))
5217 __qib_sdma_process_event(ppd,
5218 qib_sdma_event_e70_go_idle);
5219 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5220 }
5221 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5222 if (clr == ppd->cpspec->iblnkdownsnap)
5223 ppd->cpspec->iblnkdowndelta++;
5224 } else {
5225 if (qib_compat_ddr_negotiate &&
5226 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5227 QIBL_IB_AUTONEG_INPROG)) &&
5228 ppd->link_speed_active == QIB_IB_SDR &&
5229 (ppd->link_speed_enabled & QIB_IB_DDR)
5230 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5231 /* we are SDR, and auto-negotiation enabled */
5232 ++ppd->cpspec->autoneg_tries;
5233 if (!ppd->cpspec->ibdeltainprog) {
5234 ppd->cpspec->ibdeltainprog = 1;
5235 ppd->cpspec->ibsymdelta +=
5236 read_7322_creg32_port(ppd,
5237 crp_ibsymbolerr) -
5238 ppd->cpspec->ibsymsnap;
5239 ppd->cpspec->iblnkerrdelta +=
5240 read_7322_creg32_port(ppd,
5241 crp_iblinkerrrecov) -
5242 ppd->cpspec->iblnkerrsnap;
5243 }
5244 try_7322_autoneg(ppd);
5245 ret = 1; /* no other IB status change processing */
5246 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5247 ppd->link_speed_active == QIB_IB_SDR) {
5248 qib_autoneg_7322_send(ppd, 1);
5249 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5250 qib_7322_mini_pcs_reset(ppd);
5251 udelay(2);
5252 ret = 1; /* no other IB status change processing */
5253 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5254 (ppd->link_speed_active & QIB_IB_DDR)) {
5255 spin_lock_irqsave(&ppd->lflags_lock, flags);
5256 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5257 QIBL_IB_AUTONEG_FAILED);
5258 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5259 ppd->cpspec->autoneg_tries = 0;
5260 /* re-enable SDR, for next link down */
5261 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5262 wake_up(&ppd->cpspec->autoneg_wait);
5263 symadj = 1;
5264 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5265 /*
5266 * Clear autoneg failure flag, and do setup
5267 * so we'll try next time link goes down and
5268 * back to INIT (possibly connected to a
5269 * different device).
5270 */
5271 spin_lock_irqsave(&ppd->lflags_lock, flags);
5272 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5273 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5274 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5275 symadj = 1;
5276 }
5277 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5278 symadj = 1;
5279 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5280 try_7322_ipg(ppd);
5281 if (!ppd->cpspec->recovery_init)
5282 setup_7322_link_recovery(ppd, 0);
5283 ppd->cpspec->qdr_dfe_time = jiffies +
5284 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5285 }
5286 ppd->cpspec->ibmalfusesnap = 0;
5287 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5288 crp_errlink);
5289 }
5290 if (symadj) {
5291 ppd->cpspec->iblnkdownsnap =
5292 read_7322_creg32_port(ppd, crp_iblinkdown);
5293 if (ppd->cpspec->ibdeltainprog) {
5294 ppd->cpspec->ibdeltainprog = 0;
5295 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5296 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5297 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5298 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5299 }
5300 } else if (!ibup && qib_compat_ddr_negotiate &&
5301 !ppd->cpspec->ibdeltainprog &&
5302 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5303 ppd->cpspec->ibdeltainprog = 1;
5304 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5305 crp_ibsymbolerr);
5306 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5307 crp_iblinkerrrecov);
5308 }
5309
5310 if (!ret)
5311 qib_setup_7322_setextled(ppd, ibup);
5312 return ret;
5313 }
5314
5315 /*
5316 * Does read/modify/write to appropriate registers to
5317 * set output and direction bits selected by mask.
5318 * these are in their canonical postions (e.g. lsb of
5319 * dir will end up in D48 of extctrl on existing chips).
5320 * returns contents of GP Inputs.
5321 */
5322 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5323 {
5324 u64 read_val, new_out;
5325 unsigned long flags;
5326
5327 if (mask) {
5328 /* some bits being written, lock access to GPIO */
5329 dir &= mask;
5330 out &= mask;
5331 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5332 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5333 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5334 new_out = (dd->cspec->gpio_out & ~mask) | out;
5335
5336 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5337 qib_write_kreg(dd, kr_gpio_out, new_out);
5338 dd->cspec->gpio_out = new_out;
5339 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5340 }
5341 /*
5342 * It is unlikely that a read at this time would get valid
5343 * data on a pin whose direction line was set in the same
5344 * call to this function. We include the read here because
5345 * that allows us to potentially combine a change on one pin with
5346 * a read on another, and because the old code did something like
5347 * this.
5348 */
5349 read_val = qib_read_kreg64(dd, kr_extstatus);
5350 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5351 }
5352
5353 /* Enable writes to config EEPROM, if possible. Returns previous state */
5354 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5355 {
5356 int prev_wen;
5357 u32 mask;
5358
5359 mask = 1 << QIB_EEPROM_WEN_NUM;
5360 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5361 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5362
5363 return prev_wen & 1;
5364 }
5365
5366 /*
5367 * Read fundamental info we need to use the chip. These are
5368 * the registers that describe chip capabilities, and are
5369 * saved in shadow registers.
5370 */
5371 static void get_7322_chip_params(struct qib_devdata *dd)
5372 {
5373 u64 val;
5374 u32 piobufs;
5375 int mtu;
5376
5377 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5378
5379 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5380
5381 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5382 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5383 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5384 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5385 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5386
5387 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5388 dd->piobcnt2k = val & ~0U;
5389 dd->piobcnt4k = val >> 32;
5390 val = qib_read_kreg64(dd, kr_sendpiosize);
5391 dd->piosize2k = val & ~0U;
5392 dd->piosize4k = val >> 32;
5393
5394 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5395 if (mtu == -1)
5396 mtu = QIB_DEFAULT_MTU;
5397 dd->pport[0].ibmtu = (u32)mtu;
5398 dd->pport[1].ibmtu = (u32)mtu;
5399
5400 /* these may be adjusted in init_chip_wc_pat() */
5401 dd->pio2kbase = (u32 __iomem *)
5402 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5403 dd->pio4kbase = (u32 __iomem *)
5404 ((char __iomem *) dd->kregbase +
5405 (dd->piobufbase >> 32));
5406 /*
5407 * 4K buffers take 2 pages; we use roundup just to be
5408 * paranoid; we calculate it once here, rather than on
5409 * ever buf allocate
5410 */
5411 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5412
5413 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5414
5415 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5416 (sizeof(u64) * BITS_PER_BYTE / 2);
5417 }
5418
5419 /*
5420 * The chip base addresses in cspec and cpspec have to be set
5421 * after possible init_chip_wc_pat(), rather than in
5422 * get_7322_chip_params(), so split out as separate function
5423 */
5424 static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5425 {
5426 u32 cregbase;
5427 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5428
5429 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5430 (char __iomem *)dd->kregbase);
5431
5432 dd->egrtidbase = (u64 __iomem *)
5433 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5434
5435 /* port registers are defined as relative to base of chip */
5436 dd->pport[0].cpspec->kpregbase =
5437 (u64 __iomem *)((char __iomem *)dd->kregbase);
5438 dd->pport[1].cpspec->kpregbase =
5439 (u64 __iomem *)(dd->palign +
5440 (char __iomem *)dd->kregbase);
5441 dd->pport[0].cpspec->cpregbase =
5442 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5443 kr_counterregbase) + (char __iomem *)dd->kregbase);
5444 dd->pport[1].cpspec->cpregbase =
5445 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5446 kr_counterregbase) + (char __iomem *)dd->kregbase);
5447 }
5448
5449 /*
5450 * This is a fairly special-purpose observer, so we only support
5451 * the port-specific parts of SendCtrl
5452 */
5453
5454 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5455 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5456 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5457 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5458 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5459 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5460 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5461
5462 static int sendctrl_hook(struct qib_devdata *dd,
5463 const struct diag_observer *op, u32 offs,
5464 u64 *data, u64 mask, int only_32)
5465 {
5466 unsigned long flags;
5467 unsigned idx;
5468 unsigned pidx;
5469 struct qib_pportdata *ppd = NULL;
5470 u64 local_data, all_bits;
5471
5472 /*
5473 * The fixed correspondence between Physical ports and pports is
5474 * severed. We need to hunt for the ppd that corresponds
5475 * to the offset we got. And we have to do that without admitting
5476 * we know the stride, apparently.
5477 */
5478 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5479 u64 __iomem *psptr;
5480 u32 psoffs;
5481
5482 ppd = dd->pport + pidx;
5483 if (!ppd->cpspec->kpregbase)
5484 continue;
5485
5486 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5487 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5488 if (psoffs == offs)
5489 break;
5490 }
5491
5492 /* If pport is not being managed by driver, just avoid shadows. */
5493 if (pidx >= dd->num_pports)
5494 ppd = NULL;
5495
5496 /* In any case, "idx" is flat index in kreg space */
5497 idx = offs / sizeof(u64);
5498
5499 all_bits = ~0ULL;
5500 if (only_32)
5501 all_bits >>= 32;
5502
5503 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5504 if (!ppd || (mask & all_bits) != all_bits) {
5505 /*
5506 * At least some mask bits are zero, so we need
5507 * to read. The judgement call is whether from
5508 * reg or shadow. First-cut: read reg, and complain
5509 * if any bits which should be shadowed are different
5510 * from their shadowed value.
5511 */
5512 if (only_32)
5513 local_data = (u64)qib_read_kreg32(dd, idx);
5514 else
5515 local_data = qib_read_kreg64(dd, idx);
5516 *data = (local_data & ~mask) | (*data & mask);
5517 }
5518 if (mask) {
5519 /*
5520 * At least some mask bits are one, so we need
5521 * to write, but only shadow some bits.
5522 */
5523 u64 sval, tval; /* Shadowed, transient */
5524
5525 /*
5526 * New shadow val is bits we don't want to touch,
5527 * ORed with bits we do, that are intended for shadow.
5528 */
5529 if (ppd) {
5530 sval = ppd->p_sendctrl & ~mask;
5531 sval |= *data & SENDCTRL_SHADOWED & mask;
5532 ppd->p_sendctrl = sval;
5533 } else
5534 sval = *data & SENDCTRL_SHADOWED & mask;
5535 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5536 qib_write_kreg(dd, idx, tval);
5537 qib_write_kreg(dd, kr_scratch, 0Ull);
5538 }
5539 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5540 return only_32 ? 4 : 8;
5541 }
5542
5543 static const struct diag_observer sendctrl_0_observer = {
5544 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5545 KREG_IDX(SendCtrl_0) * sizeof(u64)
5546 };
5547
5548 static const struct diag_observer sendctrl_1_observer = {
5549 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5550 KREG_IDX(SendCtrl_1) * sizeof(u64)
5551 };
5552
5553 static ushort sdma_fetch_prio = 8;
5554 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5555 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5556
5557 /* Besides logging QSFP events, we set appropriate TxDDS values */
5558 static void init_txdds_table(struct qib_pportdata *ppd, int override);
5559
5560 static void qsfp_7322_event(struct work_struct *work)
5561 {
5562 struct qib_qsfp_data *qd;
5563 struct qib_pportdata *ppd;
5564 u64 pwrup;
5565 int ret;
5566 u32 le2;
5567
5568 qd = container_of(work, struct qib_qsfp_data, work);
5569 ppd = qd->ppd;
5570 pwrup = qd->t_insert + msecs_to_jiffies(QSFP_PWR_LAG_MSEC);
5571
5572 /*
5573 * Some QSFP's not only do not respond until the full power-up
5574 * time, but may behave badly if we try. So hold off responding
5575 * to insertion.
5576 */
5577 while (1) {
5578 u64 now = get_jiffies_64();
5579 if (time_after64(now, pwrup))
5580 break;
5581 msleep(20);
5582 }
5583 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
5584 /*
5585 * Need to change LE2 back to defaults if we couldn't
5586 * read the cable type (to handle cable swaps), so do this
5587 * even on failure to read cable information. We don't
5588 * get here for QME, so IS_QME check not needed here.
5589 */
5590 if (!ret && !ppd->dd->cspec->r1) {
5591 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech))
5592 le2 = LE2_QME;
5593 else if (qd->cache.atten[1] >= qib_long_atten &&
5594 QSFP_IS_CU(qd->cache.tech))
5595 le2 = LE2_5m;
5596 else
5597 le2 = LE2_DEFAULT;
5598 } else
5599 le2 = LE2_DEFAULT;
5600 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
5601 init_txdds_table(ppd, 0);
5602 }
5603
5604 /*
5605 * There is little we can do but complain to the user if QSFP
5606 * initialization fails.
5607 */
5608 static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
5609 {
5610 unsigned long flags;
5611 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
5612 struct qib_devdata *dd = ppd->dd;
5613 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
5614
5615 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
5616 qd->ppd = ppd;
5617 qib_qsfp_init(qd, qsfp_7322_event);
5618 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5619 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
5620 dd->cspec->gpio_mask |= mod_prs_bit;
5621 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5622 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
5623 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5624 }
5625
5626 /*
5627 * called at device initialization time, and also if the txselect
5628 * module parameter is changed. This is used for cables that don't
5629 * have valid QSFP EEPROMs (not present, or attenuation is zero).
5630 * We initialize to the default, then if there is a specific
5631 * unit,port match, we use that (and set it immediately, for the
5632 * current speed, if the link is at INIT or better).
5633 * String format is "default# unit#,port#=# ... u,p=#", separators must
5634 * be a SPACE character. A newline terminates. The u,p=# tuples may
5635 * optionally have "u,p=#,#", where the final # is the H1 value
5636 * The last specific match is used (actually, all are used, but last
5637 * one is the one that winds up set); if none at all, fall back on default.
5638 */
5639 static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
5640 {
5641 char *nxt, *str;
5642 u32 pidx, unit, port, deflt, h1;
5643 unsigned long val;
5644 int any = 0, seth1;
5645 int txdds_size;
5646
5647 str = txselect_list;
5648
5649 /* default number is validated in setup_txselect() */
5650 deflt = simple_strtoul(str, &nxt, 0);
5651 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5652 dd->pport[pidx].cpspec->no_eep = deflt;
5653
5654 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ;
5655 if (IS_QME(dd) || IS_QMH(dd))
5656 txdds_size += TXDDS_MFG_SZ;
5657
5658 while (*nxt && nxt[1]) {
5659 str = ++nxt;
5660 unit = simple_strtoul(str, &nxt, 0);
5661 if (nxt == str || !*nxt || *nxt != ',') {
5662 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5663 ;
5664 continue;
5665 }
5666 str = ++nxt;
5667 port = simple_strtoul(str, &nxt, 0);
5668 if (nxt == str || *nxt != '=') {
5669 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5670 ;
5671 continue;
5672 }
5673 str = ++nxt;
5674 val = simple_strtoul(str, &nxt, 0);
5675 if (nxt == str) {
5676 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5677 ;
5678 continue;
5679 }
5680 if (val >= txdds_size)
5681 continue;
5682 seth1 = 0;
5683 h1 = 0; /* gcc thinks it might be used uninitted */
5684 if (*nxt == ',' && nxt[1]) {
5685 str = ++nxt;
5686 h1 = (u32)simple_strtoul(str, &nxt, 0);
5687 if (nxt == str)
5688 while (*nxt && *nxt++ != ' ') /* skip */
5689 ;
5690 else
5691 seth1 = 1;
5692 }
5693 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
5694 ++pidx) {
5695 struct qib_pportdata *ppd = &dd->pport[pidx];
5696
5697 if (ppd->port != port || !ppd->link_speed_supported)
5698 continue;
5699 ppd->cpspec->no_eep = val;
5700 if (seth1)
5701 ppd->cpspec->h1_val = h1;
5702 /* now change the IBC and serdes, overriding generic */
5703 init_txdds_table(ppd, 1);
5704 /* Re-enable the physical state machine on mezz boards
5705 * now that the correct settings have been set. */
5706 if (IS_QMH(dd) || IS_QME(dd))
5707 qib_set_ib_7322_lstate(ppd, 0,
5708 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
5709 any++;
5710 }
5711 if (*nxt == '\n')
5712 break; /* done */
5713 }
5714 if (change && !any) {
5715 /* no specific setting, use the default.
5716 * Change the IBC and serdes, but since it's
5717 * general, don't override specific settings.
5718 */
5719 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5720 if (dd->pport[pidx].link_speed_supported)
5721 init_txdds_table(&dd->pport[pidx], 0);
5722 }
5723 }
5724
5725 /* handle the txselect parameter changing */
5726 static int setup_txselect(const char *str, struct kernel_param *kp)
5727 {
5728 struct qib_devdata *dd;
5729 unsigned long val;
5730 char *n;
5731 if (strlen(str) >= MAX_ATTEN_LEN) {
5732 printk(KERN_INFO QIB_DRV_NAME " txselect_values string "
5733 "too long\n");
5734 return -ENOSPC;
5735 }
5736 val = simple_strtoul(str, &n, 0);
5737 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
5738 TXDDS_MFG_SZ)) {
5739 printk(KERN_INFO QIB_DRV_NAME
5740 "txselect_values must start with a number < %d\n",
5741 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ);
5742 return -EINVAL;
5743 }
5744 strcpy(txselect_list, str);
5745
5746 list_for_each_entry(dd, &qib_dev_list, list)
5747 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
5748 set_no_qsfp_atten(dd, 1);
5749 return 0;
5750 }
5751
5752 /*
5753 * Write the final few registers that depend on some of the
5754 * init setup. Done late in init, just before bringing up
5755 * the serdes.
5756 */
5757 static int qib_late_7322_initreg(struct qib_devdata *dd)
5758 {
5759 int ret = 0, n;
5760 u64 val;
5761
5762 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
5763 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
5764 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
5765 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
5766 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
5767 if (val != dd->pioavailregs_phys) {
5768 qib_dev_err(dd, "Catastrophic software error, "
5769 "SendPIOAvailAddr written as %lx, "
5770 "read back as %llx\n",
5771 (unsigned long) dd->pioavailregs_phys,
5772 (unsigned long long) val);
5773 ret = -EINVAL;
5774 }
5775
5776 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
5777 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
5778 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
5779 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
5780
5781 qib_register_observer(dd, &sendctrl_0_observer);
5782 qib_register_observer(dd, &sendctrl_1_observer);
5783
5784 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
5785 qib_write_kreg(dd, kr_control, dd->control);
5786 /*
5787 * Set SendDmaFetchPriority and init Tx params, including
5788 * QSFP handler on boards that have QSFP.
5789 * First set our default attenuation entry for cables that
5790 * don't have valid attenuation.
5791 */
5792 set_no_qsfp_atten(dd, 0);
5793 for (n = 0; n < dd->num_pports; ++n) {
5794 struct qib_pportdata *ppd = dd->pport + n;
5795
5796 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
5797 sdma_fetch_prio & 0xf);
5798 /* Initialize qsfp if present on board. */
5799 if (dd->flags & QIB_HAS_QSFP)
5800 qib_init_7322_qsfp(ppd);
5801 }
5802 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
5803 qib_write_kreg(dd, kr_control, dd->control);
5804
5805 return ret;
5806 }
5807
5808 /* per IB port errors. */
5809 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
5810 MASK_ACROSS(8, 15))
5811 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
5812 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
5813 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
5814 MASK_ACROSS(0, 11))
5815
5816 /*
5817 * Write the initialization per-port registers that need to be done at
5818 * driver load and after reset completes (i.e., that aren't done as part
5819 * of other init procedures called from qib_init.c).
5820 * Some of these should be redundant on reset, but play safe.
5821 */
5822 static void write_7322_init_portregs(struct qib_pportdata *ppd)
5823 {
5824 u64 val;
5825 int i;
5826
5827 if (!ppd->link_speed_supported) {
5828 /* no buffer credits for this port */
5829 for (i = 1; i < 8; i++)
5830 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
5831 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
5832 qib_write_kreg(ppd->dd, kr_scratch, 0);
5833 return;
5834 }
5835
5836 /*
5837 * Set the number of supported virtual lanes in IBC,
5838 * for flow control packet handling on unsupported VLs
5839 */
5840 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
5841 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
5842 val |= (u64)(ppd->vls_supported - 1) <<
5843 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
5844 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
5845
5846 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
5847
5848 /* enable tx header checking */
5849 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
5850 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
5851 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
5852
5853 qib_write_kreg_port(ppd, krp_ncmodectrl,
5854 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
5855
5856 /*
5857 * Unconditionally clear the bufmask bits. If SDMA is
5858 * enabled, we'll set them appropriately later.
5859 */
5860 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
5861 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
5862 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
5863 if (ppd->dd->cspec->r1)
5864 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
5865 }
5866
5867 /*
5868 * Write the initialization per-device registers that need to be done at
5869 * driver load and after reset completes (i.e., that aren't done as part
5870 * of other init procedures called from qib_init.c). Also write per-port
5871 * registers that are affected by overall device config, such as QP mapping
5872 * Some of these should be redundant on reset, but play safe.
5873 */
5874 static void write_7322_initregs(struct qib_devdata *dd)
5875 {
5876 struct qib_pportdata *ppd;
5877 int i, pidx;
5878 u64 val;
5879
5880 /* Set Multicast QPs received by port 2 to map to context one. */
5881 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
5882
5883 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5884 unsigned n, regno;
5885 unsigned long flags;
5886
5887 if (dd->n_krcv_queues < 2 ||
5888 !dd->pport[pidx].link_speed_supported)
5889 continue;
5890
5891 ppd = &dd->pport[pidx];
5892
5893 /* be paranoid against later code motion, etc. */
5894 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
5895 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
5896 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
5897
5898 /* Initialize QP to context mapping */
5899 regno = krp_rcvqpmaptable;
5900 val = 0;
5901 if (dd->num_pports > 1)
5902 n = dd->first_user_ctxt / dd->num_pports;
5903 else
5904 n = dd->first_user_ctxt - 1;
5905 for (i = 0; i < 32; ) {
5906 unsigned ctxt;
5907
5908 if (dd->num_pports > 1)
5909 ctxt = (i % n) * dd->num_pports + pidx;
5910 else if (i % n)
5911 ctxt = (i % n) + 1;
5912 else
5913 ctxt = ppd->hw_pidx;
5914 val |= ctxt << (5 * (i % 6));
5915 i++;
5916 if (i % 6 == 0) {
5917 qib_write_kreg_port(ppd, regno, val);
5918 val = 0;
5919 regno++;
5920 }
5921 }
5922 qib_write_kreg_port(ppd, regno, val);
5923 }
5924
5925 /*
5926 * Setup up interrupt mitigation for kernel contexts, but
5927 * not user contexts (user contexts use interrupts when
5928 * stalled waiting for any packet, so want those interrupts
5929 * right away).
5930 */
5931 for (i = 0; i < dd->first_user_ctxt; i++) {
5932 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
5933 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
5934 }
5935
5936 /*
5937 * Initialize as (disabled) rcvflow tables. Application code
5938 * will setup each flow as it uses the flow.
5939 * Doesn't clear any of the error bits that might be set.
5940 */
5941 val = TIDFLOW_ERRBITS; /* these are W1C */
5942 for (i = 0; i < dd->cfgctxts; i++) {
5943 int flow;
5944 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
5945 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
5946 }
5947
5948 /*
5949 * dual cards init to dual port recovery, single port cards to
5950 * the one port. Dual port cards may later adjust to 1 port,
5951 * and then back to dual port if both ports are connected
5952 * */
5953 if (dd->num_pports)
5954 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
5955 }
5956
5957 static int qib_init_7322_variables(struct qib_devdata *dd)
5958 {
5959 struct qib_pportdata *ppd;
5960 unsigned features, pidx, sbufcnt;
5961 int ret, mtu;
5962 u32 sbufs, updthresh;
5963
5964 /* pport structs are contiguous, allocated after devdata */
5965 ppd = (struct qib_pportdata *)(dd + 1);
5966 dd->pport = ppd;
5967 ppd[0].dd = dd;
5968 ppd[1].dd = dd;
5969
5970 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
5971
5972 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
5973 ppd[1].cpspec = &ppd[0].cpspec[1];
5974 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */
5975 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */
5976
5977 spin_lock_init(&dd->cspec->rcvmod_lock);
5978 spin_lock_init(&dd->cspec->gpio_lock);
5979
5980 /* we haven't yet set QIB_PRESENT, so use read directly */
5981 dd->revision = readq(&dd->kregbase[kr_revision]);
5982
5983 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
5984 qib_dev_err(dd, "Revision register read failure, "
5985 "giving up initialization\n");
5986 ret = -ENODEV;
5987 goto bail;
5988 }
5989 dd->flags |= QIB_PRESENT; /* now register routines work */
5990
5991 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
5992 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
5993 dd->cspec->r1 = dd->minrev == 1;
5994
5995 get_7322_chip_params(dd);
5996 features = qib_7322_boardname(dd);
5997
5998 /* now that piobcnt2k and 4k set, we can allocate these */
5999 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
6000 NUM_VL15_BUFS + BITS_PER_LONG - 1;
6001 sbufcnt /= BITS_PER_LONG;
6002 dd->cspec->sendchkenable = kmalloc(sbufcnt *
6003 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
6004 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
6005 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
6006 dd->cspec->sendibchk = kmalloc(sbufcnt *
6007 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
6008 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6009 !dd->cspec->sendibchk) {
6010 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
6011 ret = -ENOMEM;
6012 goto bail;
6013 }
6014
6015 ppd = dd->pport;
6016
6017 /*
6018 * GPIO bits for TWSI data and clock,
6019 * used for serial EEPROM.
6020 */
6021 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
6022 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
6023 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
6024
6025 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
6026 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
6027 QIB_HAS_THRESH_UPDATE |
6028 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
6029 dd->flags |= qib_special_trigger ?
6030 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
6031
6032 /*
6033 * Setup initial values. These may change when PAT is enabled, but
6034 * we need these to do initial chip register accesses.
6035 */
6036 qib_7322_set_baseaddrs(dd);
6037
6038 mtu = ib_mtu_enum_to_int(qib_ibmtu);
6039 if (mtu == -1)
6040 mtu = QIB_DEFAULT_MTU;
6041
6042 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6043 /* all hwerrors become interrupts, unless special purposed */
6044 dd->cspec->hwerrmask = ~0ULL;
6045 /* link_recovery setup causes these errors, so ignore them,
6046 * other than clearing them when they occur */
6047 dd->cspec->hwerrmask &=
6048 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
6049 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
6050 HWE_MASK(LATriggered));
6051
6052 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6053 struct qib_chippport_specific *cp = ppd->cpspec;
6054 ppd->link_speed_supported = features & PORT_SPD_CAP;
6055 features >>= PORT_SPD_CAP_SHIFT;
6056 if (!ppd->link_speed_supported) {
6057 /* single port mode (7340, or configured) */
6058 dd->skip_kctxt_mask |= 1 << pidx;
6059 if (pidx == 0) {
6060 /* Make sure port is disabled. */
6061 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6062 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6063 ppd[0] = ppd[1];
6064 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6065 IBSerdesPClkNotDetectMask_0)
6066 | SYM_MASK(HwErrMask,
6067 SDmaMemReadErrMask_0));
6068 dd->cspec->int_enable_mask &= ~(
6069 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6070 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6071 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6072 SYM_MASK(IntMask, SDmaIntMask_0) |
6073 SYM_MASK(IntMask, ErrIntMask_0) |
6074 SYM_MASK(IntMask, SendDoneIntMask_0));
6075 } else {
6076 /* Make sure port is disabled. */
6077 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6078 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6079 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6080 IBSerdesPClkNotDetectMask_1)
6081 | SYM_MASK(HwErrMask,
6082 SDmaMemReadErrMask_1));
6083 dd->cspec->int_enable_mask &= ~(
6084 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6085 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6086 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6087 SYM_MASK(IntMask, SDmaIntMask_1) |
6088 SYM_MASK(IntMask, ErrIntMask_1) |
6089 SYM_MASK(IntMask, SendDoneIntMask_1));
6090 }
6091 continue;
6092 }
6093
6094 dd->num_pports++;
6095 qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6096
6097 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6098 ppd->link_width_enabled = IB_WIDTH_4X;
6099 ppd->link_speed_enabled = ppd->link_speed_supported;
6100 /*
6101 * Set the initial values to reasonable default, will be set
6102 * for real when link is up.
6103 */
6104 ppd->link_width_active = IB_WIDTH_4X;
6105 ppd->link_speed_active = QIB_IB_SDR;
6106 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6107 switch (qib_num_cfg_vls) {
6108 case 1:
6109 ppd->vls_supported = IB_VL_VL0;
6110 break;
6111 case 2:
6112 ppd->vls_supported = IB_VL_VL0_1;
6113 break;
6114 default:
6115 qib_devinfo(dd->pcidev,
6116 "Invalid num_vls %u, using 4 VLs\n",
6117 qib_num_cfg_vls);
6118 qib_num_cfg_vls = 4;
6119 /* fall through */
6120 case 4:
6121 ppd->vls_supported = IB_VL_VL0_3;
6122 break;
6123 case 8:
6124 if (mtu <= 2048)
6125 ppd->vls_supported = IB_VL_VL0_7;
6126 else {
6127 qib_devinfo(dd->pcidev,
6128 "Invalid num_vls %u for MTU %d "
6129 ", using 4 VLs\n",
6130 qib_num_cfg_vls, mtu);
6131 ppd->vls_supported = IB_VL_VL0_3;
6132 qib_num_cfg_vls = 4;
6133 }
6134 break;
6135 }
6136 ppd->vls_operational = ppd->vls_supported;
6137
6138 init_waitqueue_head(&cp->autoneg_wait);
6139 INIT_DELAYED_WORK(&cp->autoneg_work,
6140 autoneg_7322_work);
6141 if (ppd->dd->cspec->r1)
6142 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6143
6144 /*
6145 * For Mez and similar cards, no qsfp info, so do
6146 * the "cable info" setup here. Can be overridden
6147 * in adapter-specific routines.
6148 */
6149 if (!(dd->flags & QIB_HAS_QSFP)) {
6150 if (!IS_QMH(dd) && !IS_QME(dd))
6151 qib_devinfo(dd->pcidev, "IB%u:%u: "
6152 "Unknown mezzanine card type\n",
6153 dd->unit, ppd->port);
6154 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
6155 /*
6156 * Choose center value as default tx serdes setting
6157 * until changed through module parameter.
6158 */
6159 ppd->cpspec->no_eep = IS_QMH(dd) ?
6160 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
6161 } else
6162 cp->h1_val = H1_FORCE_VAL;
6163
6164 /* Avoid writes to chip for mini_init */
6165 if (!qib_mini_init)
6166 write_7322_init_portregs(ppd);
6167
6168 init_timer(&cp->chase_timer);
6169 cp->chase_timer.function = reenable_chase;
6170 cp->chase_timer.data = (unsigned long)ppd;
6171
6172 ppd++;
6173 }
6174
6175 dd->rcvhdrentsize = qib_rcvhdrentsize ?
6176 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
6177 dd->rcvhdrsize = qib_rcvhdrsize ?
6178 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
6179 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
6180
6181 /* we always allocate at least 2048 bytes for eager buffers */
6182 dd->rcvegrbufsize = max(mtu, 2048);
6183
6184 qib_7322_tidtemplate(dd);
6185
6186 /*
6187 * We can request a receive interrupt for 1 or
6188 * more packets from current offset.
6189 */
6190 dd->rhdrhead_intr_off =
6191 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6192
6193 /* setup the stats timer; the add_timer is done at end of init */
6194 init_timer(&dd->stats_timer);
6195 dd->stats_timer.function = qib_get_7322_faststats;
6196 dd->stats_timer.data = (unsigned long) dd;
6197
6198 dd->ureg_align = 0x10000; /* 64KB alignment */
6199
6200 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6201
6202 qib_7322_config_ctxts(dd);
6203 qib_set_ctxtcnt(dd);
6204
6205 if (qib_wc_pat) {
6206 resource_size_t vl15off;
6207 /*
6208 * We do not set WC on the VL15 buffers to avoid
6209 * a rare problem with unaligned writes from
6210 * interrupt-flushed store buffers, so we need
6211 * to map those separately here. We can't solve
6212 * this for the rarely used mtrr case.
6213 */
6214 ret = init_chip_wc_pat(dd, 0);
6215 if (ret)
6216 goto bail;
6217
6218 /* vl15 buffers start just after the 4k buffers */
6219 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6220 dd->piobcnt4k * dd->align4k;
6221 dd->piovl15base = ioremap_nocache(vl15off,
6222 NUM_VL15_BUFS * dd->align4k);
6223 if (!dd->piovl15base)
6224 goto bail;
6225 }
6226 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6227
6228 ret = 0;
6229 if (qib_mini_init)
6230 goto bail;
6231 if (!dd->num_pports) {
6232 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6233 goto bail; /* no error, so can still figure out why err */
6234 }
6235
6236 write_7322_initregs(dd);
6237 ret = qib_create_ctxts(dd);
6238 init_7322_cntrnames(dd);
6239
6240 updthresh = 8U; /* update threshold */
6241
6242 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6243 * reserve the update threshold amount for other kernel use, such
6244 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6245 * unless we aren't enabling SDMA, in which case we want to use
6246 * all the 4k bufs for the kernel.
6247 * if this was less than the update threshold, we could wait
6248 * a long time for an update. Coded this way because we
6249 * sometimes change the update threshold for various reasons,
6250 * and we want this to remain robust.
6251 */
6252 if (dd->flags & QIB_HAS_SEND_DMA) {
6253 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6254 sbufs = updthresh > 3 ? updthresh : 3;
6255 } else {
6256 dd->cspec->sdmabufcnt = 0;
6257 sbufs = dd->piobcnt4k;
6258 }
6259 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6260 dd->cspec->sdmabufcnt;
6261 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6262 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6263 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6264 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6265
6266 /*
6267 * If we have 16 user contexts, we will have 7 sbufs
6268 * per context, so reduce the update threshold to match. We
6269 * want to update before we actually run out, at low pbufs/ctxt
6270 * so give ourselves some margin.
6271 */
6272 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6273 updthresh = dd->pbufsctxt - 2;
6274 dd->cspec->updthresh_dflt = updthresh;
6275 dd->cspec->updthresh = updthresh;
6276
6277 /* before full enable, no interrupts, no locking needed */
6278 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6279 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6280 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6281
6282 dd->psxmitwait_supported = 1;
6283 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6284 bail:
6285 if (!dd->ctxtcnt)
6286 dd->ctxtcnt = 1; /* for other initialization code */
6287
6288 return ret;
6289 }
6290
6291 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6292 u32 *pbufnum)
6293 {
6294 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6295 struct qib_devdata *dd = ppd->dd;
6296
6297 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6298 if (pbc & PBC_7322_VL15_SEND) {
6299 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6300 last = first;
6301 } else {
6302 if ((plen + 1) > dd->piosize2kmax_dwords)
6303 first = dd->piobcnt2k;
6304 else
6305 first = 0;
6306 last = dd->cspec->lastbuf_for_pio;
6307 }
6308 return qib_getsendbuf_range(dd, pbufnum, first, last);
6309 }
6310
6311 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6312 u32 start)
6313 {
6314 qib_write_kreg_port(ppd, krp_psinterval, intv);
6315 qib_write_kreg_port(ppd, krp_psstart, start);
6316 }
6317
6318 /*
6319 * Must be called with sdma_lock held, or before init finished.
6320 */
6321 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6322 {
6323 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6324 }
6325
6326 static struct sdma_set_state_action sdma_7322_action_table[] = {
6327 [qib_sdma_state_s00_hw_down] = {
6328 .go_s99_running_tofalse = 1,
6329 .op_enable = 0,
6330 .op_intenable = 0,
6331 .op_halt = 0,
6332 .op_drain = 0,
6333 },
6334 [qib_sdma_state_s10_hw_start_up_wait] = {
6335 .op_enable = 0,
6336 .op_intenable = 1,
6337 .op_halt = 1,
6338 .op_drain = 0,
6339 },
6340 [qib_sdma_state_s20_idle] = {
6341 .op_enable = 1,
6342 .op_intenable = 1,
6343 .op_halt = 1,
6344 .op_drain = 0,
6345 },
6346 [qib_sdma_state_s30_sw_clean_up_wait] = {
6347 .op_enable = 0,
6348 .op_intenable = 1,
6349 .op_halt = 1,
6350 .op_drain = 0,
6351 },
6352 [qib_sdma_state_s40_hw_clean_up_wait] = {
6353 .op_enable = 1,
6354 .op_intenable = 1,
6355 .op_halt = 1,
6356 .op_drain = 0,
6357 },
6358 [qib_sdma_state_s50_hw_halt_wait] = {
6359 .op_enable = 1,
6360 .op_intenable = 1,
6361 .op_halt = 1,
6362 .op_drain = 1,
6363 },
6364 [qib_sdma_state_s99_running] = {
6365 .op_enable = 1,
6366 .op_intenable = 1,
6367 .op_halt = 0,
6368 .op_drain = 0,
6369 .go_s99_running_totrue = 1,
6370 },
6371 };
6372
6373 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6374 {
6375 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6376 }
6377
6378 static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6379 {
6380 struct qib_devdata *dd = ppd->dd;
6381 unsigned lastbuf, erstbuf;
6382 u64 senddmabufmask[3] = { 0 };
6383 int n, ret = 0;
6384
6385 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6386 qib_sdma_7322_setlengen(ppd);
6387 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
6388 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6389 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6390 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6391
6392 if (dd->num_pports)
6393 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6394 else
6395 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6396 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6397 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6398 dd->cspec->sdmabufcnt);
6399 lastbuf = erstbuf + n;
6400
6401 ppd->sdma_state.first_sendbuf = erstbuf;
6402 ppd->sdma_state.last_sendbuf = lastbuf;
6403 for (; erstbuf < lastbuf; ++erstbuf) {
6404 unsigned word = erstbuf / BITS_PER_LONG;
6405 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6406
6407 BUG_ON(word >= 3);
6408 senddmabufmask[word] |= 1ULL << bit;
6409 }
6410 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6411 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6412 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6413 return ret;
6414 }
6415
6416 /* sdma_lock must be held */
6417 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6418 {
6419 struct qib_devdata *dd = ppd->dd;
6420 int sane;
6421 int use_dmahead;
6422 u16 swhead;
6423 u16 swtail;
6424 u16 cnt;
6425 u16 hwhead;
6426
6427 use_dmahead = __qib_sdma_running(ppd) &&
6428 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6429 retry:
6430 hwhead = use_dmahead ?
6431 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6432 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6433
6434 swhead = ppd->sdma_descq_head;
6435 swtail = ppd->sdma_descq_tail;
6436 cnt = ppd->sdma_descq_cnt;
6437
6438 if (swhead < swtail)
6439 /* not wrapped */
6440 sane = (hwhead >= swhead) & (hwhead <= swtail);
6441 else if (swhead > swtail)
6442 /* wrapped around */
6443 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
6444 (hwhead <= swtail);
6445 else
6446 /* empty */
6447 sane = (hwhead == swhead);
6448
6449 if (unlikely(!sane)) {
6450 if (use_dmahead) {
6451 /* try one more time, directly from the register */
6452 use_dmahead = 0;
6453 goto retry;
6454 }
6455 /* proceed as if no progress */
6456 hwhead = swhead;
6457 }
6458
6459 return hwhead;
6460 }
6461
6462 static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
6463 {
6464 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
6465
6466 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
6467 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
6468 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
6469 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
6470 }
6471
6472 /*
6473 * Compute the amount of delay before sending the next packet if the
6474 * port's send rate differs from the static rate set for the QP.
6475 * The delay affects the next packet and the amount of the delay is
6476 * based on the length of the this packet.
6477 */
6478 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
6479 u8 srate, u8 vl)
6480 {
6481 u8 snd_mult = ppd->delay_mult;
6482 u8 rcv_mult = ib_rate_to_delay[srate];
6483 u32 ret;
6484
6485 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
6486
6487 /* Indicate VL15, else set the VL in the control word */
6488 if (vl == 15)
6489 ret |= PBC_7322_VL15_SEND_CTRL;
6490 else
6491 ret |= vl << PBC_VL_NUM_LSB;
6492 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
6493
6494 return ret;
6495 }
6496
6497 /*
6498 * Enable the per-port VL15 send buffers for use.
6499 * They follow the rest of the buffers, without a config parameter.
6500 * This was in initregs, but that is done before the shadow
6501 * is set up, and this has to be done after the shadow is
6502 * set up.
6503 */
6504 static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
6505 {
6506 unsigned vl15bufs;
6507
6508 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
6509 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
6510 TXCHK_CHG_TYPE_KERN, NULL);
6511 }
6512
6513 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
6514 {
6515 if (rcd->ctxt < NUM_IB_PORTS) {
6516 if (rcd->dd->num_pports > 1) {
6517 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
6518 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
6519 } else {
6520 rcd->rcvegrcnt = KCTXT0_EGRCNT;
6521 rcd->rcvegr_tid_base = 0;
6522 }
6523 } else {
6524 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
6525 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
6526 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
6527 }
6528 }
6529
6530 #define QTXSLEEPS 5000
6531 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
6532 u32 len, u32 which, struct qib_ctxtdata *rcd)
6533 {
6534 int i;
6535 const int last = start + len - 1;
6536 const int lastr = last / BITS_PER_LONG;
6537 u32 sleeps = 0;
6538 int wait = rcd != NULL;
6539 unsigned long flags;
6540
6541 while (wait) {
6542 unsigned long shadow;
6543 int cstart, previ = -1;
6544
6545 /*
6546 * when flipping from kernel to user, we can't change
6547 * the checking type if the buffer is allocated to the
6548 * driver. It's OK the other direction, because it's
6549 * from close, and we have just disarm'ed all the
6550 * buffers. All the kernel to kernel changes are also
6551 * OK.
6552 */
6553 for (cstart = start; cstart <= last; cstart++) {
6554 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6555 / BITS_PER_LONG;
6556 if (i != previ) {
6557 shadow = (unsigned long)
6558 le64_to_cpu(dd->pioavailregs_dma[i]);
6559 previ = i;
6560 }
6561 if (test_bit(((2 * cstart) +
6562 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6563 % BITS_PER_LONG, &shadow))
6564 break;
6565 }
6566
6567 if (cstart > last)
6568 break;
6569
6570 if (sleeps == QTXSLEEPS)
6571 break;
6572 /* make sure we see an updated copy next time around */
6573 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6574 sleeps++;
6575 msleep(20);
6576 }
6577
6578 switch (which) {
6579 case TXCHK_CHG_TYPE_DIS1:
6580 /*
6581 * disable checking on a range; used by diags; just
6582 * one buffer, but still written generically
6583 */
6584 for (i = start; i <= last; i++)
6585 clear_bit(i, dd->cspec->sendchkenable);
6586 break;
6587
6588 case TXCHK_CHG_TYPE_ENAB1:
6589 /*
6590 * (re)enable checking on a range; used by diags; just
6591 * one buffer, but still written generically; read
6592 * scratch to be sure buffer actually triggered, not
6593 * just flushed from processor.
6594 */
6595 qib_read_kreg32(dd, kr_scratch);
6596 for (i = start; i <= last; i++)
6597 set_bit(i, dd->cspec->sendchkenable);
6598 break;
6599
6600 case TXCHK_CHG_TYPE_KERN:
6601 /* usable by kernel */
6602 for (i = start; i <= last; i++) {
6603 set_bit(i, dd->cspec->sendibchk);
6604 clear_bit(i, dd->cspec->sendgrhchk);
6605 }
6606 spin_lock_irqsave(&dd->uctxt_lock, flags);
6607 /* see if we need to raise avail update threshold */
6608 for (i = dd->first_user_ctxt;
6609 dd->cspec->updthresh != dd->cspec->updthresh_dflt
6610 && i < dd->cfgctxts; i++)
6611 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
6612 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
6613 < dd->cspec->updthresh_dflt)
6614 break;
6615 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
6616 if (i == dd->cfgctxts) {
6617 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6618 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
6619 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6620 dd->sendctrl |= (dd->cspec->updthresh &
6621 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
6622 SYM_LSB(SendCtrl, AvailUpdThld);
6623 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6624 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6625 }
6626 break;
6627
6628 case TXCHK_CHG_TYPE_USER:
6629 /* for user process */
6630 for (i = start; i <= last; i++) {
6631 clear_bit(i, dd->cspec->sendibchk);
6632 set_bit(i, dd->cspec->sendgrhchk);
6633 }
6634 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6635 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
6636 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
6637 dd->cspec->updthresh = (rcd->piocnt /
6638 rcd->subctxt_cnt) - 1;
6639 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6640 dd->sendctrl |= (dd->cspec->updthresh &
6641 SYM_RMASK(SendCtrl, AvailUpdThld))
6642 << SYM_LSB(SendCtrl, AvailUpdThld);
6643 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6644 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6645 } else
6646 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6647 break;
6648
6649 default:
6650 break;
6651 }
6652
6653 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
6654 qib_write_kreg(dd, kr_sendcheckmask + i,
6655 dd->cspec->sendchkenable[i]);
6656
6657 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
6658 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
6659 dd->cspec->sendgrhchk[i]);
6660 qib_write_kreg(dd, kr_sendibpktmask + i,
6661 dd->cspec->sendibchk[i]);
6662 }
6663
6664 /*
6665 * Be sure whatever we did was seen by the chip and acted upon,
6666 * before we return. Mostly important for which >= 2.
6667 */
6668 qib_read_kreg32(dd, kr_scratch);
6669 }
6670
6671
6672 /* useful for trigger analyzers, etc. */
6673 static void writescratch(struct qib_devdata *dd, u32 val)
6674 {
6675 qib_write_kreg(dd, kr_scratch, val);
6676 }
6677
6678 /* Dummy for now, use chip regs soon */
6679 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
6680 {
6681 return -ENXIO;
6682 }
6683
6684 /**
6685 * qib_init_iba7322_funcs - set up the chip-specific function pointers
6686 * @dev: the pci_dev for qlogic_ib device
6687 * @ent: pci_device_id struct for this dev
6688 *
6689 * Also allocates, inits, and returns the devdata struct for this
6690 * device instance
6691 *
6692 * This is global, and is called directly at init to set up the
6693 * chip-specific function pointers for later use.
6694 */
6695 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
6696 const struct pci_device_id *ent)
6697 {
6698 struct qib_devdata *dd;
6699 int ret, i;
6700 u32 tabsize, actual_cnt = 0;
6701
6702 dd = qib_alloc_devdata(pdev,
6703 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
6704 sizeof(struct qib_chip_specific) +
6705 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
6706 if (IS_ERR(dd))
6707 goto bail;
6708
6709 dd->f_bringup_serdes = qib_7322_bringup_serdes;
6710 dd->f_cleanup = qib_setup_7322_cleanup;
6711 dd->f_clear_tids = qib_7322_clear_tids;
6712 dd->f_free_irq = qib_7322_free_irq;
6713 dd->f_get_base_info = qib_7322_get_base_info;
6714 dd->f_get_msgheader = qib_7322_get_msgheader;
6715 dd->f_getsendbuf = qib_7322_getsendbuf;
6716 dd->f_gpio_mod = gpio_7322_mod;
6717 dd->f_eeprom_wen = qib_7322_eeprom_wen;
6718 dd->f_hdrqempty = qib_7322_hdrqempty;
6719 dd->f_ib_updown = qib_7322_ib_updown;
6720 dd->f_init_ctxt = qib_7322_init_ctxt;
6721 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
6722 dd->f_intr_fallback = qib_7322_intr_fallback;
6723 dd->f_late_initreg = qib_late_7322_initreg;
6724 dd->f_setpbc_control = qib_7322_setpbc_control;
6725 dd->f_portcntr = qib_portcntr_7322;
6726 dd->f_put_tid = qib_7322_put_tid;
6727 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
6728 dd->f_rcvctrl = rcvctrl_7322_mod;
6729 dd->f_read_cntrs = qib_read_7322cntrs;
6730 dd->f_read_portcntrs = qib_read_7322portcntrs;
6731 dd->f_reset = qib_do_7322_reset;
6732 dd->f_init_sdma_regs = init_sdma_7322_regs;
6733 dd->f_sdma_busy = qib_sdma_7322_busy;
6734 dd->f_sdma_gethead = qib_sdma_7322_gethead;
6735 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
6736 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
6737 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
6738 dd->f_sendctrl = sendctrl_7322_mod;
6739 dd->f_set_armlaunch = qib_set_7322_armlaunch;
6740 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
6741 dd->f_iblink_state = qib_7322_iblink_state;
6742 dd->f_ibphys_portstate = qib_7322_phys_portstate;
6743 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
6744 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
6745 dd->f_set_ib_loopback = qib_7322_set_loopback;
6746 dd->f_get_ib_table = qib_7322_get_ib_table;
6747 dd->f_set_ib_table = qib_7322_set_ib_table;
6748 dd->f_set_intr_state = qib_7322_set_intr_state;
6749 dd->f_setextled = qib_setup_7322_setextled;
6750 dd->f_txchk_change = qib_7322_txchk_change;
6751 dd->f_update_usrhead = qib_update_7322_usrhead;
6752 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
6753 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
6754 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
6755 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
6756 dd->f_sdma_init_early = qib_7322_sdma_init_early;
6757 dd->f_writescratch = writescratch;
6758 dd->f_tempsense_rd = qib_7322_tempsense_rd;
6759 /*
6760 * Do remaining PCIe setup and save PCIe values in dd.
6761 * Any error printing is already done by the init code.
6762 * On return, we have the chip mapped, but chip registers
6763 * are not set up until start of qib_init_7322_variables.
6764 */
6765 ret = qib_pcie_ddinit(dd, pdev, ent);
6766 if (ret < 0)
6767 goto bail_free;
6768
6769 /* initialize chip-specific variables */
6770 ret = qib_init_7322_variables(dd);
6771 if (ret)
6772 goto bail_cleanup;
6773
6774 if (qib_mini_init || !dd->num_pports)
6775 goto bail;
6776
6777 /*
6778 * Determine number of vectors we want; depends on port count
6779 * and number of configured kernel receive queues actually used.
6780 * Should also depend on whether sdma is enabled or not, but
6781 * that's such a rare testing case it's not worth worrying about.
6782 */
6783 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
6784 for (i = 0; i < tabsize; i++)
6785 if ((i < ARRAY_SIZE(irq_table) &&
6786 irq_table[i].port <= dd->num_pports) ||
6787 (i >= ARRAY_SIZE(irq_table) &&
6788 dd->rcd[i - ARRAY_SIZE(irq_table)]))
6789 actual_cnt++;
6790 tabsize = actual_cnt;
6791 dd->cspec->msix_entries = kmalloc(tabsize *
6792 sizeof(struct msix_entry), GFP_KERNEL);
6793 dd->cspec->msix_arg = kmalloc(tabsize *
6794 sizeof(void *), GFP_KERNEL);
6795 if (!dd->cspec->msix_entries || !dd->cspec->msix_arg) {
6796 qib_dev_err(dd, "No memory for MSIx table\n");
6797 tabsize = 0;
6798 }
6799 for (i = 0; i < tabsize; i++)
6800 dd->cspec->msix_entries[i].entry = i;
6801
6802 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
6803 qib_dev_err(dd, "Failed to setup PCIe or interrupts; "
6804 "continuing anyway\n");
6805 /* may be less than we wanted, if not enough available */
6806 dd->cspec->num_msix_entries = tabsize;
6807
6808 /* setup interrupt handler */
6809 qib_setup_7322_interrupt(dd, 1);
6810
6811 /* clear diagctrl register, in case diags were running and crashed */
6812 qib_write_kreg(dd, kr_hwdiagctrl, 0);
6813
6814 goto bail;
6815
6816 bail_cleanup:
6817 qib_pcie_ddcleanup(dd);
6818 bail_free:
6819 qib_free_devdata(dd);
6820 dd = ERR_PTR(ret);
6821 bail:
6822 return dd;
6823 }
6824
6825 /*
6826 * Set the table entry at the specified index from the table specifed.
6827 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
6828 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
6829 * 'idx' below addresses the correct entry, while its 4 LSBs select the
6830 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
6831 */
6832 #define DDS_ENT_AMP_LSB 14
6833 #define DDS_ENT_MAIN_LSB 9
6834 #define DDS_ENT_POST_LSB 5
6835 #define DDS_ENT_PRE_XTRA_LSB 3
6836 #define DDS_ENT_PRE_LSB 0
6837
6838 /*
6839 * Set one entry in the TxDDS table for spec'd port
6840 * ridx picks one of the entries, while tp points
6841 * to the appropriate table entry.
6842 */
6843 static void set_txdds(struct qib_pportdata *ppd, int ridx,
6844 const struct txdds_ent *tp)
6845 {
6846 struct qib_devdata *dd = ppd->dd;
6847 u32 pack_ent;
6848 int regidx;
6849
6850 /* Get correct offset in chip-space, and in source table */
6851 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
6852 /*
6853 * We do not use qib_write_kreg_port() because it was intended
6854 * only for registers in the lower "port specific" pages.
6855 * So do index calculation by hand.
6856 */
6857 if (ppd->hw_pidx)
6858 regidx += (dd->palign / sizeof(u64));
6859
6860 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
6861 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
6862 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
6863 pack_ent |= tp->post << DDS_ENT_POST_LSB;
6864 qib_write_kreg(dd, regidx, pack_ent);
6865 /* Prevent back-to-back writes by hitting scratch */
6866 qib_write_kreg(ppd->dd, kr_scratch, 0);
6867 }
6868
6869 static const struct vendor_txdds_ent vendor_txdds[] = {
6870 { /* Amphenol 1m 30awg NoEq */
6871 { 0x41, 0x50, 0x48 }, "584470002 ",
6872 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
6873 },
6874 { /* Amphenol 3m 28awg NoEq */
6875 { 0x41, 0x50, 0x48 }, "584470004 ",
6876 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
6877 },
6878 { /* Finisar 3m OM2 Optical */
6879 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
6880 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
6881 },
6882 { /* Finisar 30m OM2 Optical */
6883 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
6884 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
6885 },
6886 { /* Finisar Default OM2 Optical */
6887 { 0x00, 0x90, 0x65 }, NULL,
6888 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
6889 },
6890 { /* Gore 1m 30awg NoEq */
6891 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
6892 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
6893 },
6894 { /* Gore 2m 30awg NoEq */
6895 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
6896 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
6897 },
6898 { /* Gore 1m 28awg NoEq */
6899 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
6900 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
6901 },
6902 { /* Gore 3m 28awg NoEq */
6903 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
6904 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
6905 },
6906 { /* Gore 5m 24awg Eq */
6907 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
6908 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
6909 },
6910 { /* Gore 7m 24awg Eq */
6911 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
6912 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
6913 },
6914 { /* Gore 5m 26awg Eq */
6915 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
6916 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
6917 },
6918 { /* Gore 7m 26awg Eq */
6919 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
6920 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
6921 },
6922 { /* Intersil 12m 24awg Active */
6923 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
6924 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
6925 },
6926 { /* Intersil 10m 28awg Active */
6927 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
6928 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
6929 },
6930 { /* Intersil 7m 30awg Active */
6931 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
6932 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
6933 },
6934 { /* Intersil 5m 32awg Active */
6935 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
6936 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
6937 },
6938 { /* Intersil Default Active */
6939 { 0x00, 0x30, 0xB4 }, NULL,
6940 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
6941 },
6942 { /* Luxtera 20m Active Optical */
6943 { 0x00, 0x25, 0x63 }, NULL,
6944 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
6945 },
6946 { /* Molex 1M Cu loopback */
6947 { 0x00, 0x09, 0x3A }, "74763-0025 ",
6948 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
6949 },
6950 { /* Molex 2m 28awg NoEq */
6951 { 0x00, 0x09, 0x3A }, "74757-2201 ",
6952 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
6953 },
6954 };
6955
6956 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
6957 /* amp, pre, main, post */
6958 { 2, 2, 15, 6 }, /* Loopback */
6959 { 0, 0, 0, 1 }, /* 2 dB */
6960 { 0, 0, 0, 2 }, /* 3 dB */
6961 { 0, 0, 0, 3 }, /* 4 dB */
6962 { 0, 0, 0, 4 }, /* 5 dB */
6963 { 0, 0, 0, 5 }, /* 6 dB */
6964 { 0, 0, 0, 6 }, /* 7 dB */
6965 { 0, 0, 0, 7 }, /* 8 dB */
6966 { 0, 0, 0, 8 }, /* 9 dB */
6967 { 0, 0, 0, 9 }, /* 10 dB */
6968 { 0, 0, 0, 10 }, /* 11 dB */
6969 { 0, 0, 0, 11 }, /* 12 dB */
6970 { 0, 0, 0, 12 }, /* 13 dB */
6971 { 0, 0, 0, 13 }, /* 14 dB */
6972 { 0, 0, 0, 14 }, /* 15 dB */
6973 { 0, 0, 0, 15 }, /* 16 dB */
6974 };
6975
6976 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
6977 /* amp, pre, main, post */
6978 { 2, 2, 15, 6 }, /* Loopback */
6979 { 0, 0, 0, 8 }, /* 2 dB */
6980 { 0, 0, 0, 8 }, /* 3 dB */
6981 { 0, 0, 0, 9 }, /* 4 dB */
6982 { 0, 0, 0, 9 }, /* 5 dB */
6983 { 0, 0, 0, 10 }, /* 6 dB */
6984 { 0, 0, 0, 10 }, /* 7 dB */
6985 { 0, 0, 0, 11 }, /* 8 dB */
6986 { 0, 0, 0, 11 }, /* 9 dB */
6987 { 0, 0, 0, 12 }, /* 10 dB */
6988 { 0, 0, 0, 12 }, /* 11 dB */
6989 { 0, 0, 0, 13 }, /* 12 dB */
6990 { 0, 0, 0, 13 }, /* 13 dB */
6991 { 0, 0, 0, 14 }, /* 14 dB */
6992 { 0, 0, 0, 14 }, /* 15 dB */
6993 { 0, 0, 0, 15 }, /* 16 dB */
6994 };
6995
6996 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
6997 /* amp, pre, main, post */
6998 { 2, 2, 15, 6 }, /* Loopback */
6999 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
7000 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
7001 { 0, 1, 0, 11 }, /* 4 dB */
7002 { 0, 1, 0, 13 }, /* 5 dB */
7003 { 0, 1, 0, 15 }, /* 6 dB */
7004 { 0, 1, 3, 15 }, /* 7 dB */
7005 { 0, 1, 7, 15 }, /* 8 dB */
7006 { 0, 1, 7, 15 }, /* 9 dB */
7007 { 0, 1, 8, 15 }, /* 10 dB */
7008 { 0, 1, 9, 15 }, /* 11 dB */
7009 { 0, 1, 10, 15 }, /* 12 dB */
7010 { 0, 2, 6, 15 }, /* 13 dB */
7011 { 0, 2, 7, 15 }, /* 14 dB */
7012 { 0, 2, 8, 15 }, /* 15 dB */
7013 { 0, 2, 9, 15 }, /* 16 dB */
7014 };
7015
7016 /*
7017 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
7018 * These are mostly used for mez cards going through connectors
7019 * and backplane traces, but can be used to add other "unusual"
7020 * table values as well.
7021 */
7022 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
7023 /* amp, pre, main, post */
7024 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7025 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7026 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7027 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7028 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7029 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7030 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7031 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7032 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7033 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7034 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7035 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
7036 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
7037 };
7038
7039 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
7040 /* amp, pre, main, post */
7041 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7042 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7043 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7044 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7045 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7046 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7047 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7048 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7049 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7050 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7051 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7052 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
7053 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
7054 };
7055
7056 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7057 /* amp, pre, main, post */
7058 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7059 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7060 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7061 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7062 { 0, 1, 12, 10 }, /* QME7342 backplane setting */
7063 { 0, 1, 12, 11 }, /* QME7342 backplane setting */
7064 { 0, 1, 12, 12 }, /* QME7342 backplane setting */
7065 { 0, 1, 12, 14 }, /* QME7342 backplane setting */
7066 { 0, 1, 12, 6 }, /* QME7342 backplane setting */
7067 { 0, 1, 12, 7 }, /* QME7342 backplane setting */
7068 { 0, 1, 12, 8 }, /* QME7342 backplane setting */
7069 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
7070 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
7071 };
7072
7073 static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = {
7074 /* amp, pre, main, post */
7075 { 0, 0, 0, 0 }, /* QME7342 mfg settings */
7076 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */
7077 };
7078
7079 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7080 unsigned atten)
7081 {
7082 /*
7083 * The attenuation table starts at 2dB for entry 1,
7084 * with entry 0 being the loopback entry.
7085 */
7086 if (atten <= 2)
7087 atten = 1;
7088 else if (atten > TXDDS_TABLE_SZ)
7089 atten = TXDDS_TABLE_SZ - 1;
7090 else
7091 atten--;
7092 return txdds + atten;
7093 }
7094
7095 /*
7096 * if override is set, the module parameter txselect has a value
7097 * for this specific port, so use it, rather than our normal mechanism.
7098 */
7099 static void find_best_ent(struct qib_pportdata *ppd,
7100 const struct txdds_ent **sdr_dds,
7101 const struct txdds_ent **ddr_dds,
7102 const struct txdds_ent **qdr_dds, int override)
7103 {
7104 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7105 int idx;
7106
7107 /* Search table of known cables */
7108 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7109 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7110
7111 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7112 (!v->partnum ||
7113 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7114 *sdr_dds = &v->sdr;
7115 *ddr_dds = &v->ddr;
7116 *qdr_dds = &v->qdr;
7117 return;
7118 }
7119 }
7120
7121 /* Lookup serdes setting by cable type and attenuation */
7122 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7123 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7124 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7125 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7126 return;
7127 }
7128
7129 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7130 qd->atten[1])) {
7131 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7132 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7133 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7134 return;
7135 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
7136 /*
7137 * If we have no (or incomplete) data from the cable
7138 * EEPROM, or no QSFP, or override is set, use the
7139 * module parameter value to index into the attentuation
7140 * table.
7141 */
7142 idx = ppd->cpspec->no_eep;
7143 *sdr_dds = &txdds_sdr[idx];
7144 *ddr_dds = &txdds_ddr[idx];
7145 *qdr_dds = &txdds_qdr[idx];
7146 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7147 /* similar to above, but index into the "extra" table. */
7148 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7149 *sdr_dds = &txdds_extra_sdr[idx];
7150 *ddr_dds = &txdds_extra_ddr[idx];
7151 *qdr_dds = &txdds_extra_qdr[idx];
7152 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) &&
7153 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
7154 TXDDS_MFG_SZ)) {
7155 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
7156 printk(KERN_INFO QIB_DRV_NAME
7157 " IB%u:%u use idx %u into txdds_mfg\n",
7158 ppd->dd->unit, ppd->port, idx);
7159 *sdr_dds = &txdds_extra_mfg[idx];
7160 *ddr_dds = &txdds_extra_mfg[idx];
7161 *qdr_dds = &txdds_extra_mfg[idx];
7162 } else {
7163 /* this shouldn't happen, it's range checked */
7164 *sdr_dds = txdds_sdr + qib_long_atten;
7165 *ddr_dds = txdds_ddr + qib_long_atten;
7166 *qdr_dds = txdds_qdr + qib_long_atten;
7167 }
7168 }
7169
7170 static void init_txdds_table(struct qib_pportdata *ppd, int override)
7171 {
7172 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7173 struct txdds_ent *dds;
7174 int idx;
7175 int single_ent = 0;
7176
7177 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7178
7179 /* for mez cards or override, use the selected value for all entries */
7180 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
7181 single_ent = 1;
7182
7183 /* Fill in the first entry with the best entry found. */
7184 set_txdds(ppd, 0, sdr_dds);
7185 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7186 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
7187 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7188 QIBL_LINKACTIVE)) {
7189 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7190 QIB_IB_QDR ? qdr_dds :
7191 (ppd->link_speed_active ==
7192 QIB_IB_DDR ? ddr_dds : sdr_dds));
7193 write_tx_serdes_param(ppd, dds);
7194 }
7195
7196 /* Fill in the remaining entries with the default table values. */
7197 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7198 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7199 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7200 single_ent ? ddr_dds : txdds_ddr + idx);
7201 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7202 single_ent ? qdr_dds : txdds_qdr + idx);
7203 }
7204 }
7205
7206 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7207 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7208 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7209 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7210 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7211 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7212 #define AHB_TRANS_TRIES 10
7213
7214 /*
7215 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7216 * 5=subsystem which is why most calls have "chan + chan >> 1"
7217 * for the channel argument.
7218 */
7219 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7220 u32 data, u32 mask)
7221 {
7222 u32 rd_data, wr_data, sz_mask;
7223 u64 trans, acc, prev_acc;
7224 u32 ret = 0xBAD0BAD;
7225 int tries;
7226
7227 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7228 /* From this point on, make sure we return access */
7229 acc = (quad << 1) | 1;
7230 qib_write_kreg(dd, KR_AHB_ACC, acc);
7231
7232 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7233 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7234 if (trans & AHB_TRANS_RDY)
7235 break;
7236 }
7237 if (tries >= AHB_TRANS_TRIES) {
7238 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7239 goto bail;
7240 }
7241
7242 /* If mask is not all 1s, we need to read, but different SerDes
7243 * entities have different sizes
7244 */
7245 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7246 wr_data = data & mask & sz_mask;
7247 if ((~mask & sz_mask) != 0) {
7248 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7249 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7250
7251 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7252 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7253 if (trans & AHB_TRANS_RDY)
7254 break;
7255 }
7256 if (tries >= AHB_TRANS_TRIES) {
7257 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7258 AHB_TRANS_TRIES);
7259 goto bail;
7260 }
7261 /* Re-read in case host split reads and read data first */
7262 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7263 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7264 wr_data |= (rd_data & ~mask & sz_mask);
7265 }
7266
7267 /* If mask is not zero, we need to write. */
7268 if (mask & sz_mask) {
7269 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7270 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7271 trans |= AHB_WR;
7272 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7273
7274 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7275 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7276 if (trans & AHB_TRANS_RDY)
7277 break;
7278 }
7279 if (tries >= AHB_TRANS_TRIES) {
7280 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7281 AHB_TRANS_TRIES);
7282 goto bail;
7283 }
7284 }
7285 ret = wr_data;
7286 bail:
7287 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7288 return ret;
7289 }
7290
7291 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7292 unsigned mask)
7293 {
7294 struct qib_devdata *dd = ppd->dd;
7295 int chan;
7296 u32 rbc;
7297
7298 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7299 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7300 data, mask);
7301 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7302 addr, 0, 0);
7303 }
7304 }
7305
7306 static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
7307 {
7308 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
7309 u8 state = SYM_FIELD(data, IBSerdesCtrl_0, RXLOSEN);
7310
7311 if (enable && !state) {
7312 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS on\n",
7313 ppd->dd->unit, ppd->port);
7314 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7315 } else if (!enable && state) {
7316 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS off\n",
7317 ppd->dd->unit, ppd->port);
7318 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7319 }
7320 qib_write_kreg_port(ppd, krp_serdesctrl, data);
7321 }
7322
7323 static int serdes_7322_init(struct qib_pportdata *ppd)
7324 {
7325 int ret = 0;
7326 if (ppd->dd->cspec->r1)
7327 ret = serdes_7322_init_old(ppd);
7328 else
7329 ret = serdes_7322_init_new(ppd);
7330 return ret;
7331 }
7332
7333 static int serdes_7322_init_old(struct qib_pportdata *ppd)
7334 {
7335 u32 le_val;
7336
7337 /*
7338 * Initialize the Tx DDS tables. Also done every QSFP event,
7339 * for adapters with QSFP
7340 */
7341 init_txdds_table(ppd, 0);
7342
7343 /* ensure no tx overrides from earlier driver loads */
7344 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7345 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7346 reset_tx_deemphasis_override));
7347
7348 /* Patch some SerDes defaults to "Better for IB" */
7349 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7350 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7351
7352 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7353 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7354 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7355 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7356
7357 /* May be overridden in qsfp_7322_event */
7358 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7359 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7360
7361 /* enable LE1 adaptation for all but QME, which is disabled */
7362 le_val = IS_QME(ppd->dd) ? 0 : 1;
7363 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7364
7365 /* Clear cmode-override, may be set from older driver */
7366 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7367
7368 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7369 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7370
7371 /* setup LoS params; these are subsystem, so chan == 5 */
7372 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7373 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7374 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7375 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7376 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7377
7378 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7379 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7380 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7381 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7382 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7383
7384 /* LoS filter select enabled */
7385 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7386
7387 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7388 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7389 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7390 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7391
7392 serdes_7322_los_enable(ppd, 1);
7393
7394 /* rxbistena; set 0 to avoid effects of it switch later */
7395 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7396
7397 /* Configure 4 DFE taps, and only they adapt */
7398 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7399
7400 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7401 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7402 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7403
7404 /*
7405 * Set receive adaptation mode. SDR and DDR adaptation are
7406 * always on, and QDR is initially enabled; later disabled.
7407 */
7408 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7409 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7410 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7411 ppd->dd->cspec->r1 ?
7412 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7413 ppd->cpspec->qdr_dfe_on = 1;
7414
7415 /* FLoop LOS gate: PPM filter enabled */
7416 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7417
7418 /* rx offset center enabled */
7419 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
7420
7421 if (!ppd->dd->cspec->r1) {
7422 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
7423 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
7424 }
7425
7426 /* Set the frequency loop bandwidth to 15 */
7427 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
7428
7429 return 0;
7430 }
7431
7432 static int serdes_7322_init_new(struct qib_pportdata *ppd)
7433 {
7434 u64 tstart;
7435 u32 le_val, rxcaldone;
7436 int chan, chan_done = (1 << SERDES_CHANS) - 1;
7437
7438 /*
7439 * Initialize the Tx DDS tables. Also done every QSFP event,
7440 * for adapters with QSFP
7441 */
7442 init_txdds_table(ppd, 0);
7443
7444 /* Clear cmode-override, may be set from older driver */
7445 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7446
7447 /* ensure no tx overrides from earlier driver loads */
7448 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7449 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7450 reset_tx_deemphasis_override));
7451
7452 /* START OF LSI SUGGESTED SERDES BRINGUP */
7453 /* Reset - Calibration Setup */
7454 /* Stop DFE adaptaion */
7455 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
7456 /* Disable LE1 */
7457 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
7458 /* Disable autoadapt for LE1 */
7459 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
7460 /* Disable LE2 */
7461 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
7462 /* Disable VGA */
7463 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7464 /* Disable AFE Offset Cancel */
7465 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
7466 /* Disable Timing Loop */
7467 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
7468 /* Disable Frequency Loop */
7469 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
7470 /* Disable Baseline Wander Correction */
7471 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
7472 /* Disable RX Calibration */
7473 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7474 /* Disable RX Offset Calibration */
7475 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
7476 /* Select BB CDR */
7477 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
7478 /* CDR Step Size */
7479 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
7480 /* Enable phase Calibration */
7481 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
7482 /* DFE Bandwidth [2:14-12] */
7483 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
7484 /* DFE Config (4 taps only) */
7485 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
7486 /* Gain Loop Bandwidth */
7487 if (!ppd->dd->cspec->r1) {
7488 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
7489 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
7490 } else {
7491 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
7492 }
7493 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */
7494 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */
7495 /* Data Rate Select [5:7-6] (leave as default) */
7496 /* RX Parallel Word Width [3:10-8] (leave as default) */
7497
7498 /* RX REST */
7499 /* Single- or Multi-channel reset */
7500 /* RX Analog reset */
7501 /* RX Digital reset */
7502 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
7503 msleep(20);
7504 /* RX Analog reset */
7505 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
7506 msleep(20);
7507 /* RX Digital reset */
7508 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
7509 msleep(20);
7510
7511 /* setup LoS params; these are subsystem, so chan == 5 */
7512 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7513 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7514 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7515 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7516 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7517
7518 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7519 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7520 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7521 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7522 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7523
7524 /* LoS filter select enabled */
7525 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7526
7527 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7528 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7529 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7530 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7531
7532 /* Turn on LOS on initial SERDES init */
7533 serdes_7322_los_enable(ppd, 1);
7534 /* FLoop LOS gate: PPM filter enabled */
7535 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7536
7537 /* RX LATCH CALIBRATION */
7538 /* Enable Eyefinder Phase Calibration latch */
7539 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
7540 /* Enable RX Offset Calibration latch */
7541 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
7542 msleep(20);
7543 /* Start Calibration */
7544 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
7545 tstart = get_jiffies_64();
7546 while (chan_done &&
7547 !time_after64(get_jiffies_64(),
7548 tstart + msecs_to_jiffies(500))) {
7549 msleep(20);
7550 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7551 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7552 (chan + (chan >> 1)),
7553 25, 0, 0);
7554 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
7555 (~chan_done & (1 << chan)) == 0)
7556 chan_done &= ~(1 << chan);
7557 }
7558 }
7559 if (chan_done) {
7560 printk(KERN_INFO QIB_DRV_NAME
7561 " Serdes %d calibration not done after .5 sec: 0x%x\n",
7562 IBSD(ppd->hw_pidx), chan_done);
7563 } else {
7564 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7565 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7566 (chan + (chan >> 1)),
7567 25, 0, 0);
7568 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
7569 printk(KERN_INFO QIB_DRV_NAME
7570 " Serdes %d chan %d calibration "
7571 "failed\n", IBSD(ppd->hw_pidx), chan);
7572 }
7573 }
7574
7575 /* Turn off Calibration */
7576 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7577 msleep(20);
7578
7579 /* BRING RX UP */
7580 /* Set LE2 value (May be overridden in qsfp_7322_event) */
7581 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7582 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7583 /* Set LE2 Loop bandwidth */
7584 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
7585 /* Enable LE2 */
7586 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
7587 msleep(20);
7588 /* Enable H0 only */
7589 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
7590 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7591 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7592 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7593 /* Enable VGA */
7594 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7595 msleep(20);
7596 /* Set Frequency Loop Bandwidth */
7597 ibsd_wr_allchans(ppd, 2, (7 << 5), BMASK(8, 5));
7598 /* Enable Frequency Loop */
7599 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
7600 /* Set Timing Loop Bandwidth */
7601 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7602 /* Enable Timing Loop */
7603 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
7604 msleep(50);
7605 /* Enable DFE
7606 * Set receive adaptation mode. SDR and DDR adaptation are
7607 * always on, and QDR is initially enabled; later disabled.
7608 */
7609 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7610 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7611 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7612 ppd->dd->cspec->r1 ?
7613 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7614 ppd->cpspec->qdr_dfe_on = 1;
7615 /* Disable LE1 */
7616 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
7617 /* Disable auto adapt for LE1 */
7618 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
7619 msleep(20);
7620 /* Enable AFE Offset Cancel */
7621 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
7622 /* Enable Baseline Wander Correction */
7623 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
7624 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7625 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7626 /* VGA output common mode */
7627 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
7628
7629 return 0;
7630 }
7631
7632 /* start adjust QMH serdes parameters */
7633
7634 static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
7635 {
7636 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7637 9, code << 9, 0x3f << 9);
7638 }
7639
7640 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
7641 int enable, u32 tapenable)
7642 {
7643 if (enable)
7644 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7645 1, 3 << 10, 0x1f << 10);
7646 else
7647 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7648 1, 0, 0x1f << 10);
7649 }
7650
7651 /* Set clock to 1, 0, 1, 0 */
7652 static void clock_man(struct qib_pportdata *ppd, int chan)
7653 {
7654 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7655 4, 0x4000, 0x4000);
7656 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7657 4, 0, 0x4000);
7658 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7659 4, 0x4000, 0x4000);
7660 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7661 4, 0, 0x4000);
7662 }
7663
7664 /*
7665 * write the current Tx serdes pre,post,main,amp settings into the serdes.
7666 * The caller must pass the settings appropriate for the current speed,
7667 * or not care if they are correct for the current speed.
7668 */
7669 static void write_tx_serdes_param(struct qib_pportdata *ppd,
7670 struct txdds_ent *txdds)
7671 {
7672 u64 deemph;
7673
7674 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
7675 /* field names for amp, main, post, pre, respectively */
7676 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
7677 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
7678 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
7679 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
7680
7681 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7682 tx_override_deemphasis_select);
7683 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7684 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7685 txampcntl_d2a);
7686 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7687 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7688 txc0_ena);
7689 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7690 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7691 txcp1_ena);
7692 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7693 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7694 txcn1_ena);
7695 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
7696 }
7697
7698 /*
7699 * Set the parameters for mez cards on link bounce, so they are
7700 * always exactly what was requested. Similar logic to init_txdds
7701 * but does just the serdes.
7702 */
7703 static void adj_tx_serdes(struct qib_pportdata *ppd)
7704 {
7705 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7706 struct txdds_ent *dds;
7707
7708 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
7709 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
7710 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
7711 ddr_dds : sdr_dds));
7712 write_tx_serdes_param(ppd, dds);
7713 }
7714
7715 /* set QDR forced value for H1, if needed */
7716 static void force_h1(struct qib_pportdata *ppd)
7717 {
7718 int chan;
7719
7720 ppd->cpspec->qdr_reforce = 0;
7721 if (!ppd->dd->cspec->r1)
7722 return;
7723
7724 for (chan = 0; chan < SERDES_CHANS; chan++) {
7725 set_man_mode_h1(ppd, chan, 1, 0);
7726 set_man_code(ppd, chan, ppd->cpspec->h1_val);
7727 clock_man(ppd, chan);
7728 set_man_mode_h1(ppd, chan, 0, 0);
7729 }
7730 }
7731
7732 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
7733 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
7734
7735 #define R_OPCODE_LSB 3
7736 #define R_OP_NOP 0
7737 #define R_OP_SHIFT 2
7738 #define R_OP_UPDATE 3
7739 #define R_TDI_LSB 2
7740 #define R_TDO_LSB 1
7741 #define R_RDY 1
7742
7743 static int qib_r_grab(struct qib_devdata *dd)
7744 {
7745 u64 val;
7746 val = SJA_EN;
7747 qib_write_kreg(dd, kr_r_access, val);
7748 qib_read_kreg32(dd, kr_scratch);
7749 return 0;
7750 }
7751
7752 /* qib_r_wait_for_rdy() not only waits for the ready bit, it
7753 * returns the current state of R_TDO
7754 */
7755 static int qib_r_wait_for_rdy(struct qib_devdata *dd)
7756 {
7757 u64 val;
7758 int timeout;
7759 for (timeout = 0; timeout < 100 ; ++timeout) {
7760 val = qib_read_kreg32(dd, kr_r_access);
7761 if (val & R_RDY)
7762 return (val >> R_TDO_LSB) & 1;
7763 }
7764 return -1;
7765 }
7766
7767 static int qib_r_shift(struct qib_devdata *dd, int bisten,
7768 int len, u8 *inp, u8 *outp)
7769 {
7770 u64 valbase, val;
7771 int ret, pos;
7772
7773 valbase = SJA_EN | (bisten << BISTEN_LSB) |
7774 (R_OP_SHIFT << R_OPCODE_LSB);
7775 ret = qib_r_wait_for_rdy(dd);
7776 if (ret < 0)
7777 goto bail;
7778 for (pos = 0; pos < len; ++pos) {
7779 val = valbase;
7780 if (outp) {
7781 outp[pos >> 3] &= ~(1 << (pos & 7));
7782 outp[pos >> 3] |= (ret << (pos & 7));
7783 }
7784 if (inp) {
7785 int tdi = inp[pos >> 3] >> (pos & 7);
7786 val |= ((tdi & 1) << R_TDI_LSB);
7787 }
7788 qib_write_kreg(dd, kr_r_access, val);
7789 qib_read_kreg32(dd, kr_scratch);
7790 ret = qib_r_wait_for_rdy(dd);
7791 if (ret < 0)
7792 break;
7793 }
7794 /* Restore to NOP between operations. */
7795 val = SJA_EN | (bisten << BISTEN_LSB);
7796 qib_write_kreg(dd, kr_r_access, val);
7797 qib_read_kreg32(dd, kr_scratch);
7798 ret = qib_r_wait_for_rdy(dd);
7799
7800 if (ret >= 0)
7801 ret = pos;
7802 bail:
7803 return ret;
7804 }
7805
7806 static int qib_r_update(struct qib_devdata *dd, int bisten)
7807 {
7808 u64 val;
7809 int ret;
7810
7811 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
7812 ret = qib_r_wait_for_rdy(dd);
7813 if (ret >= 0) {
7814 qib_write_kreg(dd, kr_r_access, val);
7815 qib_read_kreg32(dd, kr_scratch);
7816 }
7817 return ret;
7818 }
7819
7820 #define BISTEN_PORT_SEL 15
7821 #define LEN_PORT_SEL 625
7822 #define BISTEN_AT 17
7823 #define LEN_AT 156
7824 #define BISTEN_ETM 16
7825 #define LEN_ETM 632
7826
7827 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
7828
7829 /* these are common for all IB port use cases. */
7830 static u8 reset_at[BIT2BYTE(LEN_AT)] = {
7831 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7832 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7833 };
7834 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
7835 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7836 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7837 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
7838 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
7839 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
7840 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
7841 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7842 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
7843 };
7844 static u8 at[BIT2BYTE(LEN_AT)] = {
7845 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
7846 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7847 };
7848
7849 /* used for IB1 or IB2, only one in use */
7850 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
7851 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7852 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7853 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7854 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
7855 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7856 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
7857 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
7858 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
7859 };
7860
7861 /* used when both IB1 and IB2 are in use */
7862 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
7863 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7864 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
7865 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7866 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
7867 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
7868 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
7869 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
7870 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
7871 };
7872
7873 /* used when only IB1 is in use */
7874 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
7875 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7876 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7877 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7878 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7879 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7880 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7881 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7882 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7883 };
7884
7885 /* used when only IB2 is in use */
7886 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
7887 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
7888 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
7889 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7890 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7891 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
7892 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7893 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7894 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
7895 };
7896
7897 /* used when both IB1 and IB2 are in use */
7898 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
7899 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7900 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7901 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7902 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7903 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7904 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
7905 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7906 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7907 };
7908
7909 /*
7910 * Do setup to properly handle IB link recovery; if port is zero, we
7911 * are initializing to cover both ports; otherwise we are initializing
7912 * to cover a single port card, or the port has reached INIT and we may
7913 * need to switch coverage types.
7914 */
7915 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
7916 {
7917 u8 *portsel, *etm;
7918 struct qib_devdata *dd = ppd->dd;
7919
7920 if (!ppd->dd->cspec->r1)
7921 return;
7922 if (!both) {
7923 dd->cspec->recovery_ports_initted++;
7924 ppd->cpspec->recovery_init = 1;
7925 }
7926 if (!both && dd->cspec->recovery_ports_initted == 1) {
7927 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
7928 etm = atetm_1port;
7929 } else {
7930 portsel = portsel_2port;
7931 etm = atetm_2port;
7932 }
7933
7934 if (qib_r_grab(dd) < 0 ||
7935 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
7936 qib_r_update(dd, BISTEN_ETM) < 0 ||
7937 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
7938 qib_r_update(dd, BISTEN_AT) < 0 ||
7939 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
7940 portsel, NULL) < 0 ||
7941 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
7942 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
7943 qib_r_update(dd, BISTEN_AT) < 0 ||
7944 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
7945 qib_r_update(dd, BISTEN_ETM) < 0)
7946 qib_dev_err(dd, "Failed IB link recovery setup\n");
7947 }
7948
7949 static void check_7322_rxe_status(struct qib_pportdata *ppd)
7950 {
7951 struct qib_devdata *dd = ppd->dd;
7952 u64 fmask;
7953
7954 if (dd->cspec->recovery_ports_initted != 1)
7955 return; /* rest doesn't apply to dualport */
7956 qib_write_kreg(dd, kr_control, dd->control |
7957 SYM_MASK(Control, FreezeMode));
7958 (void)qib_read_kreg64(dd, kr_scratch);
7959 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
7960 fmask = qib_read_kreg64(dd, kr_act_fmask);
7961 if (!fmask) {
7962 /*
7963 * require a powercycle before we'll work again, and make
7964 * sure we get no more interrupts, and don't turn off
7965 * freeze.
7966 */
7967 ppd->dd->cspec->stay_in_freeze = 1;
7968 qib_7322_set_intr_state(ppd->dd, 0);
7969 qib_write_kreg(dd, kr_fmask, 0ULL);
7970 qib_dev_err(dd, "HCA unusable until powercycled\n");
7971 return; /* eventually reset */
7972 }
7973
7974 qib_write_kreg(ppd->dd, kr_hwerrclear,
7975 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
7976
7977 /* don't do the full clear_freeze(), not needed for this */
7978 qib_write_kreg(dd, kr_control, dd->control);
7979 qib_read_kreg32(dd, kr_scratch);
7980 /* take IBC out of reset */
7981 if (ppd->link_speed_supported) {
7982 ppd->cpspec->ibcctrl_a &=
7983 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
7984 qib_write_kreg_port(ppd, krp_ibcctrl_a,
7985 ppd->cpspec->ibcctrl_a);
7986 qib_read_kreg32(dd, kr_scratch);
7987 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
7988 qib_set_ib_7322_lstate(ppd, 0,
7989 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
7990 }
7991 }
Linux kernel - Deliverables
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