2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * This file contains all of the code that is specific to the
35 * InfiniPath 7322 chip
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
42 #include <linux/jiffies.h>
43 #include <rdma/ib_verbs.h>
44 #include <rdma/ib_smi.h>
47 #include "qib_7322_regs.h"
52 static void qib_setup_7322_setextled(struct qib_pportdata
*, u32
);
53 static void qib_7322_handle_hwerrors(struct qib_devdata
*, char *, size_t);
54 static void sendctrl_7322_mod(struct qib_pportdata
*ppd
, u32 op
);
55 static irqreturn_t
qib_7322intr(int irq
, void *data
);
56 static irqreturn_t
qib_7322bufavail(int irq
, void *data
);
57 static irqreturn_t
sdma_intr(int irq
, void *data
);
58 static irqreturn_t
sdma_idle_intr(int irq
, void *data
);
59 static irqreturn_t
sdma_progress_intr(int irq
, void *data
);
60 static irqreturn_t
sdma_cleanup_intr(int irq
, void *data
);
61 static void qib_7322_txchk_change(struct qib_devdata
*, u32
, u32
, u32
,
62 struct qib_ctxtdata
*rcd
);
63 static u8
qib_7322_phys_portstate(u64
);
64 static u32
qib_7322_iblink_state(u64
);
65 static void qib_set_ib_7322_lstate(struct qib_pportdata
*ppd
, u16 linkcmd
,
67 static void force_h1(struct qib_pportdata
*);
68 static void adj_tx_serdes(struct qib_pportdata
*);
69 static u32
qib_7322_setpbc_control(struct qib_pportdata
*, u32
, u8
, u8
);
70 static void qib_7322_mini_pcs_reset(struct qib_pportdata
*);
72 static u32
ahb_mod(struct qib_devdata
*, int, int, int, u32
, u32
);
73 static void ibsd_wr_allchans(struct qib_pportdata
*, int, unsigned, unsigned);
74 static void serdes_7322_los_enable(struct qib_pportdata
*, int);
75 static int serdes_7322_init_old(struct qib_pportdata
*);
76 static int serdes_7322_init_new(struct qib_pportdata
*);
78 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
80 /* LE2 serdes values for different cases */
85 /* Below is special-purpose, so only really works for the IB SerDes blocks. */
86 #define IBSD(hw_pidx) (hw_pidx + 2)
88 /* these are variables for documentation and experimentation purposes */
89 static const unsigned rcv_int_timeout
= 375;
90 static const unsigned rcv_int_count
= 16;
91 static const unsigned sdma_idle_cnt
= 64;
93 /* Time to stop altering Rx Equalization parameters, after link up. */
94 #define RXEQ_DISABLE_MSECS 2500
97 * Number of VLs we are configured to use (to allow for more
98 * credits per vl, etc.)
100 ushort qib_num_cfg_vls
= 2;
101 module_param_named(num_vls
, qib_num_cfg_vls
, ushort
, S_IRUGO
);
102 MODULE_PARM_DESC(num_vls
, "Set number of Virtual Lanes to use (1-8)");
104 static ushort qib_chase
= 1;
105 module_param_named(chase
, qib_chase
, ushort
, S_IRUGO
);
106 MODULE_PARM_DESC(chase
, "Enable state chase handling");
108 static ushort qib_long_atten
= 10; /* 10 dB ~= 5m length */
109 module_param_named(long_attenuation
, qib_long_atten
, ushort
, S_IRUGO
);
110 MODULE_PARM_DESC(long_attenuation
, \
111 "attenuation cutoff (dB) for long copper cable setup");
113 static ushort qib_singleport
;
114 module_param_named(singleport
, qib_singleport
, ushort
, S_IRUGO
);
115 MODULE_PARM_DESC(singleport
, "Use only IB port 1; more per-port buffer space");
118 * Receive header queue sizes
120 static unsigned qib_rcvhdrcnt
;
121 module_param_named(rcvhdrcnt
, qib_rcvhdrcnt
, uint
, S_IRUGO
);
122 MODULE_PARM_DESC(rcvhdrcnt
, "receive header count");
124 static unsigned qib_rcvhdrsize
;
125 module_param_named(rcvhdrsize
, qib_rcvhdrsize
, uint
, S_IRUGO
);
126 MODULE_PARM_DESC(rcvhdrsize
, "receive header size in 32-bit words");
128 static unsigned qib_rcvhdrentsize
;
129 module_param_named(rcvhdrentsize
, qib_rcvhdrentsize
, uint
, S_IRUGO
);
130 MODULE_PARM_DESC(rcvhdrentsize
, "receive header entry size in 32-bit words");
132 #define MAX_ATTEN_LEN 64 /* plenty for any real system */
133 /* for read back, default index is ~5m copper cable */
134 static char txselect_list
[MAX_ATTEN_LEN
] = "10";
135 static struct kparam_string kp_txselect
= {
136 .string
= txselect_list
,
137 .maxlen
= MAX_ATTEN_LEN
139 static int setup_txselect(const char *, struct kernel_param
*);
140 module_param_call(txselect
, setup_txselect
, param_get_string
,
141 &kp_txselect
, S_IWUSR
| S_IRUGO
);
142 MODULE_PARM_DESC(txselect
, \
143 "Tx serdes indices (for no QSFP or invalid QSFP data)");
145 #define BOARD_QME7342 5
146 #define BOARD_QMH7342 6
147 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
149 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
152 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
154 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
156 #define MASK_ACROSS(lsb, msb) \
157 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
159 #define SYM_RMASK(regname, fldname) ((u64) \
160 QIB_7322_##regname##_##fldname##_RMASK)
162 #define SYM_MASK(regname, fldname) ((u64) \
163 QIB_7322_##regname##_##fldname##_RMASK << \
164 QIB_7322_##regname##_##fldname##_LSB)
166 #define SYM_FIELD(value, regname, fldname) ((u64) \
167 (((value) >> SYM_LSB(regname, fldname)) & \
168 SYM_RMASK(regname, fldname)))
170 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
171 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
172 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
174 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
175 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
176 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
177 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
178 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
179 /* Below because most, but not all, fields of IntMask have that full suffix */
180 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
183 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
186 * the size bits give us 2^N, in KB units. 0 marks as invalid,
187 * and 7 is reserved. We currently use only 2KB and 4KB
189 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
190 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
191 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
192 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
194 #define SendIBSLIDAssignMask \
195 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
196 #define SendIBSLMCMask \
197 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
199 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
200 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
201 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
202 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
203 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
204 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
206 #define _QIB_GPIO_SDA_NUM 1
207 #define _QIB_GPIO_SCL_NUM 0
208 #define QIB_EEPROM_WEN_NUM 14
209 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
211 /* HW counter clock is at 4nsec */
212 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
214 /* full speed IB port 1 only */
215 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
216 #define PORT_SPD_CAP_SHIFT 3
218 /* full speed featuremask, both ports */
219 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
222 * This file contains almost all the chip-specific register information and
223 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
226 /* Use defines to tie machine-generated names to lower-case names */
227 #define kr_contextcnt KREG_IDX(ContextCnt)
228 #define kr_control KREG_IDX(Control)
229 #define kr_counterregbase KREG_IDX(CntrRegBase)
230 #define kr_errclear KREG_IDX(ErrClear)
231 #define kr_errmask KREG_IDX(ErrMask)
232 #define kr_errstatus KREG_IDX(ErrStatus)
233 #define kr_extctrl KREG_IDX(EXTCtrl)
234 #define kr_extstatus KREG_IDX(EXTStatus)
235 #define kr_gpio_clear KREG_IDX(GPIOClear)
236 #define kr_gpio_mask KREG_IDX(GPIOMask)
237 #define kr_gpio_out KREG_IDX(GPIOOut)
238 #define kr_gpio_status KREG_IDX(GPIOStatus)
239 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
240 #define kr_debugportval KREG_IDX(DebugPortValueReg)
241 #define kr_fmask KREG_IDX(feature_mask)
242 #define kr_act_fmask KREG_IDX(active_feature_mask)
243 #define kr_hwerrclear KREG_IDX(HwErrClear)
244 #define kr_hwerrmask KREG_IDX(HwErrMask)
245 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
246 #define kr_intclear KREG_IDX(IntClear)
247 #define kr_intmask KREG_IDX(IntMask)
248 #define kr_intredirect KREG_IDX(IntRedirect0)
249 #define kr_intstatus KREG_IDX(IntStatus)
250 #define kr_pagealign KREG_IDX(PageAlign)
251 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
252 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
253 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
254 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
255 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
256 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
257 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
258 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
259 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
260 #define kr_revision KREG_IDX(Revision)
261 #define kr_scratch KREG_IDX(Scratch)
262 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
263 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
264 #define kr_sendctrl KREG_IDX(SendCtrl)
265 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
266 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
267 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
268 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
269 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
270 #define kr_sendpiosize KREG_IDX(SendBufSize)
271 #define kr_sendregbase KREG_IDX(SendRegBase)
272 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
273 #define kr_userregbase KREG_IDX(UserRegBase)
274 #define kr_intgranted KREG_IDX(Int_Granted)
275 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
276 #define kr_intblocked KREG_IDX(IntBlocked)
277 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
280 * per-port kernel registers. Access only with qib_read_kreg_port()
281 * or qib_write_kreg_port()
283 #define krp_errclear KREG_IBPORT_IDX(ErrClear)
284 #define krp_errmask KREG_IBPORT_IDX(ErrMask)
285 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
286 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
287 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
288 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
289 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
290 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
291 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
292 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
293 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
294 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
295 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
296 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
297 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
298 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
299 #define krp_psinterval KREG_IBPORT_IDX(PSInterval)
300 #define krp_psstart KREG_IBPORT_IDX(PSStart)
301 #define krp_psstat KREG_IBPORT_IDX(PSStat)
302 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
303 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
304 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
305 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
306 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
307 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
308 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
309 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
310 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
311 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
312 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
313 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
314 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
315 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
316 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
317 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
318 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
319 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
320 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
321 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
322 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
323 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
324 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
325 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
326 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
327 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
328 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
329 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
330 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
331 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
332 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
335 * Per-context kernel registers. Access only with qib_read_kreg_ctxt()
336 * or qib_write_kreg_ctxt()
338 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
339 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
342 * TID Flow table, per context. Reduces
343 * number of hdrq updates to one per flow (or on errors).
344 * context 0 and 1 share same memory, but have distinct
345 * addresses. Since for now, we never use expected sends
346 * on kernel contexts, we don't worry about that (we initialize
347 * those entries for ctxt 0/1 on driver load twice, for example).
349 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
350 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
352 /* these are the error bits in the tid flows, and are W1C */
353 #define TIDFLOW_ERRBITS ( \
354 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
355 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
356 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
357 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
359 /* Most (not all) Counters are per-IBport.
360 * Requires LBIntCnt is at offset 0 in the group
362 #define CREG_IDX(regname) \
363 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
365 #define crp_badformat CREG_IDX(RxVersionErrCnt)
366 #define crp_err_rlen CREG_IDX(RxLenErrCnt)
367 #define crp_erricrc CREG_IDX(RxICRCErrCnt)
368 #define crp_errlink CREG_IDX(RxLinkMalformCnt)
369 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
370 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
371 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
372 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
373 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
374 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
375 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
376 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
377 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
378 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
379 #define crp_pktrcv CREG_IDX(RxDataPktCnt)
380 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
381 #define crp_pktsend CREG_IDX(TxDataPktCnt)
382 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
383 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
384 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
385 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
386 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
387 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
388 #define crp_rcvebp CREG_IDX(RxEBPCnt)
389 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
390 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
391 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
392 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
393 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
394 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
395 #define crp_rxvlerr CREG_IDX(RxVlErrCnt)
396 #define crp_sendstall CREG_IDX(TxFlowStallCnt)
397 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
398 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
399 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
400 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
401 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
402 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
403 #define crp_txunderrun CREG_IDX(TxUnderrunCnt)
404 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
405 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
406 #define crp_wordrcv CREG_IDX(RxDwordCnt)
407 #define crp_wordsend CREG_IDX(TxDwordCnt)
408 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
410 /* these are the (few) counters that are not port-specific */
411 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
412 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
413 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
414 #define cr_lbint CREG_DEVIDX(LBIntCnt)
415 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
416 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
417 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
418 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
419 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
421 /* no chip register for # of IB ports supported, so define */
422 #define NUM_IB_PORTS 2
424 /* 1 VL15 buffer per hardware IB port, no register for this, so define */
425 #define NUM_VL15_BUFS NUM_IB_PORTS
428 * context 0 and 1 are special, and there is no chip register that
429 * defines this value, so we have to define it here.
430 * These are all allocated to either 0 or 1 for single port
431 * hardware configuration, otherwise each gets half
433 #define KCTXT0_EGRCNT 2048
435 /* values for vl and port fields in PBC, 7322-specific */
436 #define PBC_PORT_SEL_LSB 26
437 #define PBC_PORT_SEL_RMASK 1
438 #define PBC_VL_NUM_LSB 27
439 #define PBC_VL_NUM_RMASK 7
440 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
441 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
443 static u8 ib_rate_to_delay
[IB_RATE_120_GBPS
+ 1] = {
444 [IB_RATE_2_5_GBPS
] = 16,
445 [IB_RATE_5_GBPS
] = 8,
446 [IB_RATE_10_GBPS
] = 4,
447 [IB_RATE_20_GBPS
] = 2,
448 [IB_RATE_30_GBPS
] = 2,
449 [IB_RATE_40_GBPS
] = 1
452 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
453 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
455 /* link training states, from IBC */
456 #define IB_7322_LT_STATE_DISABLED 0x00
457 #define IB_7322_LT_STATE_LINKUP 0x01
458 #define IB_7322_LT_STATE_POLLACTIVE 0x02
459 #define IB_7322_LT_STATE_POLLQUIET 0x03
460 #define IB_7322_LT_STATE_SLEEPDELAY 0x04
461 #define IB_7322_LT_STATE_SLEEPQUIET 0x05
462 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
463 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09
464 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a
465 #define IB_7322_LT_STATE_CFGIDLE 0x0b
466 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
467 #define IB_7322_LT_STATE_TXREVLANES 0x0d
468 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
469 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f
470 #define IB_7322_LT_STATE_CFGENH 0x10
471 #define IB_7322_LT_STATE_CFGTEST 0x11
473 /* link state machine states from IBC */
474 #define IB_7322_L_STATE_DOWN 0x0
475 #define IB_7322_L_STATE_INIT 0x1
476 #define IB_7322_L_STATE_ARM 0x2
477 #define IB_7322_L_STATE_ACTIVE 0x3
478 #define IB_7322_L_STATE_ACT_DEFER 0x4
480 static const u8 qib_7322_physportstate
[0x20] = {
481 [IB_7322_LT_STATE_DISABLED
] = IB_PHYSPORTSTATE_DISABLED
,
482 [IB_7322_LT_STATE_LINKUP
] = IB_PHYSPORTSTATE_LINKUP
,
483 [IB_7322_LT_STATE_POLLACTIVE
] = IB_PHYSPORTSTATE_POLL
,
484 [IB_7322_LT_STATE_POLLQUIET
] = IB_PHYSPORTSTATE_POLL
,
485 [IB_7322_LT_STATE_SLEEPDELAY
] = IB_PHYSPORTSTATE_SLEEP
,
486 [IB_7322_LT_STATE_SLEEPQUIET
] = IB_PHYSPORTSTATE_SLEEP
,
487 [IB_7322_LT_STATE_CFGDEBOUNCE
] = IB_PHYSPORTSTATE_CFG_TRAIN
,
488 [IB_7322_LT_STATE_CFGRCVFCFG
] =
489 IB_PHYSPORTSTATE_CFG_TRAIN
,
490 [IB_7322_LT_STATE_CFGWAITRMT
] =
491 IB_PHYSPORTSTATE_CFG_TRAIN
,
492 [IB_7322_LT_STATE_CFGIDLE
] = IB_PHYSPORTSTATE_CFG_IDLE
,
493 [IB_7322_LT_STATE_RECOVERRETRAIN
] =
494 IB_PHYSPORTSTATE_LINK_ERR_RECOVER
,
495 [IB_7322_LT_STATE_RECOVERWAITRMT
] =
496 IB_PHYSPORTSTATE_LINK_ERR_RECOVER
,
497 [IB_7322_LT_STATE_RECOVERIDLE
] =
498 IB_PHYSPORTSTATE_LINK_ERR_RECOVER
,
499 [IB_7322_LT_STATE_CFGENH
] = IB_PHYSPORTSTATE_CFG_ENH
,
500 [IB_7322_LT_STATE_CFGTEST
] = IB_PHYSPORTSTATE_CFG_TRAIN
,
501 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN
,
502 [0x13] = IB_PHYSPORTSTATE_CFG_WAIT_ENH
,
503 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN
,
504 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN
,
505 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN
,
506 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
509 struct qib_chip_specific
{
510 u64 __iomem
*cregbase
;
512 spinlock_t rcvmod_lock
; /* protect rcvctrl shadow changes */
513 spinlock_t gpio_lock
; /* RMW of shadows/regs for ExtCtrl and GPIO */
514 u64 main_int_mask
; /* clear bits which have dedicated handlers */
515 u64 int_enable_mask
; /* for per port interrupts in single port mode */
518 u64 gpio_out
; /* shadow of kr_gpio_out, for rmw ops */
519 u64 gpio_mask
; /* shadow the gpio mask register */
520 u64 extctrl
; /* shadow the gpio output enable, etc... */
527 u32 updthresh
; /* current AvailUpdThld */
528 u32 updthresh_dflt
; /* default AvailUpdThld */
531 u32 num_msix_entries
;
535 u32 recovery_ports_initted
;
536 struct msix_entry
*msix_entries
;
538 unsigned long *sendchkenable
;
539 unsigned long *sendgrhchk
;
540 unsigned long *sendibchk
;
541 u32 rcvavail_timeout
[18];
542 char emsgbuf
[128]; /* for device error interrupt msg buffer */
545 /* Table of entries in "human readable" form Tx Emphasis. */
553 struct vendor_txdds_ent
{
554 u8 oui
[QSFP_VOUI_LEN
];
556 struct txdds_ent sdr
;
557 struct txdds_ent ddr
;
558 struct txdds_ent qdr
;
561 static void write_tx_serdes_param(struct qib_pportdata
*, struct txdds_ent
*);
563 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
564 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */
565 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */
566 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
568 #define H1_FORCE_VAL 8
569 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
570 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
572 /* The static and dynamic registers are paired, and the pairs indexed by spd */
573 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
576 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
577 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
578 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
579 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
580 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
582 struct qib_chippport_specific
{
583 u64 __iomem
*kpregbase
;
584 u64 __iomem
*cpregbase
;
586 struct qib_pportdata
*ppd
;
587 wait_queue_head_t autoneg_wait
;
588 struct delayed_work autoneg_work
;
589 struct delayed_work ipg_work
;
590 struct timer_list chase_timer
;
592 * these 5 fields are used to establish deltas for IB symbol
593 * errors and linkrecovery errors. They can be reported on
594 * some chips during link negotiation prior to INIT, and with
595 * DDR when faking DDR negotiations with non-IBTA switches.
596 * The chip counters are adjusted at driver unload if there is
608 u64 ibcctrl_a
; /* krp_ibcctrl_a shadow */
609 u64 ibcctrl_b
; /* krp_ibcctrl_b shadow */
617 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
618 * entry zero is unused, to simplify indexing
621 u8 no_eep
; /* txselect table index to use if no qsfp info */
624 struct qib_qsfp_data qsfp_data
;
625 char epmsgbuf
[192]; /* for port error interrupt msg buffer */
630 irq_handler_t handler
;
632 int port
; /* 0 if not port-specific, else port # */
634 { QIB_DRV_NAME
, qib_7322intr
, -1, 0 },
635 { QIB_DRV_NAME
" (buf avail)", qib_7322bufavail
,
636 SYM_LSB(IntStatus
, SendBufAvail
), 0 },
637 { QIB_DRV_NAME
" (sdma 0)", sdma_intr
,
638 SYM_LSB(IntStatus
, SDmaInt_0
), 1 },
639 { QIB_DRV_NAME
" (sdma 1)", sdma_intr
,
640 SYM_LSB(IntStatus
, SDmaInt_1
), 2 },
641 { QIB_DRV_NAME
" (sdmaI 0)", sdma_idle_intr
,
642 SYM_LSB(IntStatus
, SDmaIdleInt_0
), 1 },
643 { QIB_DRV_NAME
" (sdmaI 1)", sdma_idle_intr
,
644 SYM_LSB(IntStatus
, SDmaIdleInt_1
), 2 },
645 { QIB_DRV_NAME
" (sdmaP 0)", sdma_progress_intr
,
646 SYM_LSB(IntStatus
, SDmaProgressInt_0
), 1 },
647 { QIB_DRV_NAME
" (sdmaP 1)", sdma_progress_intr
,
648 SYM_LSB(IntStatus
, SDmaProgressInt_1
), 2 },
649 { QIB_DRV_NAME
" (sdmaC 0)", sdma_cleanup_intr
,
650 SYM_LSB(IntStatus
, SDmaCleanupDone_0
), 1 },
651 { QIB_DRV_NAME
" (sdmaC 1)", sdma_cleanup_intr
,
652 SYM_LSB(IntStatus
, SDmaCleanupDone_1
), 2 },
656 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
657 /* cycle through TS1/TS2 till OK */
658 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
659 /* wait for TS1, then go on */
660 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
661 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
663 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
664 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
665 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
667 #define BLOB_7322_IBCHG 0x101
669 static inline void qib_write_kreg(const struct qib_devdata
*dd
,
670 const u32 regno
, u64 value
);
671 static inline u32
qib_read_kreg32(const struct qib_devdata
*, const u32
);
672 static void write_7322_initregs(struct qib_devdata
*);
673 static void write_7322_init_portregs(struct qib_pportdata
*);
674 static void setup_7322_link_recovery(struct qib_pportdata
*, u32
);
675 static void check_7322_rxe_status(struct qib_pportdata
*);
676 static u32 __iomem
*qib_7322_getsendbuf(struct qib_pportdata
*, u64
, u32
*);
679 * qib_read_ureg32 - read 32-bit virtualized per-context register
681 * @regno: register number
682 * @ctxt: context number
684 * Return the contents of a register that is virtualized to be per context.
685 * Returns -1 on errors (not distinguishable from valid contents at
686 * runtime; we may add a separate error variable at some point).
688 static inline u32
qib_read_ureg32(const struct qib_devdata
*dd
,
689 enum qib_ureg regno
, int ctxt
)
691 if (!dd
->kregbase
|| !(dd
->flags
& QIB_PRESENT
))
693 return readl(regno
+ (u64 __iomem
*)(
694 (dd
->ureg_align
* ctxt
) + (dd
->userbase
?
695 (char __iomem
*)dd
->userbase
:
696 (char __iomem
*)dd
->kregbase
+ dd
->uregbase
)));
700 * qib_read_ureg - read virtualized per-context register
702 * @regno: register number
703 * @ctxt: context number
705 * Return the contents of a register that is virtualized to be per context.
706 * Returns -1 on errors (not distinguishable from valid contents at
707 * runtime; we may add a separate error variable at some point).
709 static inline u64
qib_read_ureg(const struct qib_devdata
*dd
,
710 enum qib_ureg regno
, int ctxt
)
713 if (!dd
->kregbase
|| !(dd
->flags
& QIB_PRESENT
))
715 return readq(regno
+ (u64 __iomem
*)(
716 (dd
->ureg_align
* ctxt
) + (dd
->userbase
?
717 (char __iomem
*)dd
->userbase
:
718 (char __iomem
*)dd
->kregbase
+ dd
->uregbase
)));
722 * qib_write_ureg - write virtualized per-context register
724 * @regno: register number
728 * Write the contents of a register that is virtualized to be per context.
730 static inline void qib_write_ureg(const struct qib_devdata
*dd
,
731 enum qib_ureg regno
, u64 value
, int ctxt
)
735 ubase
= (u64 __iomem
*)
736 ((char __iomem
*) dd
->userbase
+
737 dd
->ureg_align
* ctxt
);
739 ubase
= (u64 __iomem
*)
741 (char __iomem
*) dd
->kregbase
+
742 dd
->ureg_align
* ctxt
);
744 if (dd
->kregbase
&& (dd
->flags
& QIB_PRESENT
))
745 writeq(value
, &ubase
[regno
]);
748 static inline u32
qib_read_kreg32(const struct qib_devdata
*dd
,
751 if (!dd
->kregbase
|| !(dd
->flags
& QIB_PRESENT
))
753 return readl((u32 __iomem
*) &dd
->kregbase
[regno
]);
756 static inline u64
qib_read_kreg64(const struct qib_devdata
*dd
,
759 if (!dd
->kregbase
|| !(dd
->flags
& QIB_PRESENT
))
761 return readq(&dd
->kregbase
[regno
]);
764 static inline void qib_write_kreg(const struct qib_devdata
*dd
,
765 const u32 regno
, u64 value
)
767 if (dd
->kregbase
&& (dd
->flags
& QIB_PRESENT
))
768 writeq(value
, &dd
->kregbase
[regno
]);
772 * not many sanity checks for the port-specific kernel register routines,
773 * since they are only used when it's known to be safe.
775 static inline u64
qib_read_kreg_port(const struct qib_pportdata
*ppd
,
778 if (!ppd
->cpspec
->kpregbase
|| !(ppd
->dd
->flags
& QIB_PRESENT
))
780 return readq(&ppd
->cpspec
->kpregbase
[regno
]);
783 static inline void qib_write_kreg_port(const struct qib_pportdata
*ppd
,
784 const u16 regno
, u64 value
)
786 if (ppd
->cpspec
&& ppd
->dd
&& ppd
->cpspec
->kpregbase
&&
787 (ppd
->dd
->flags
& QIB_PRESENT
))
788 writeq(value
, &ppd
->cpspec
->kpregbase
[regno
]);
792 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
793 * @dd: the qlogic_ib device
794 * @regno: the register number to write
795 * @ctxt: the context containing the register
796 * @value: the value to write
798 static inline void qib_write_kreg_ctxt(const struct qib_devdata
*dd
,
799 const u16 regno
, unsigned ctxt
,
802 qib_write_kreg(dd
, regno
+ ctxt
, value
);
805 static inline u64
read_7322_creg(const struct qib_devdata
*dd
, u16 regno
)
807 if (!dd
->cspec
->cregbase
|| !(dd
->flags
& QIB_PRESENT
))
809 return readq(&dd
->cspec
->cregbase
[regno
]);
814 static inline u32
read_7322_creg32(const struct qib_devdata
*dd
, u16 regno
)
816 if (!dd
->cspec
->cregbase
|| !(dd
->flags
& QIB_PRESENT
))
818 return readl(&dd
->cspec
->cregbase
[regno
]);
823 static inline void write_7322_creg_port(const struct qib_pportdata
*ppd
,
824 u16 regno
, u64 value
)
826 if (ppd
->cpspec
&& ppd
->cpspec
->cpregbase
&&
827 (ppd
->dd
->flags
& QIB_PRESENT
))
828 writeq(value
, &ppd
->cpspec
->cpregbase
[regno
]);
831 static inline u64
read_7322_creg_port(const struct qib_pportdata
*ppd
,
834 if (!ppd
->cpspec
|| !ppd
->cpspec
->cpregbase
||
835 !(ppd
->dd
->flags
& QIB_PRESENT
))
837 return readq(&ppd
->cpspec
->cpregbase
[regno
]);
840 static inline u32
read_7322_creg32_port(const struct qib_pportdata
*ppd
,
843 if (!ppd
->cpspec
|| !ppd
->cpspec
->cpregbase
||
844 !(ppd
->dd
->flags
& QIB_PRESENT
))
846 return readl(&ppd
->cpspec
->cpregbase
[regno
]);
849 /* bits in Control register */
850 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
851 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
853 /* bits in general interrupt regs */
854 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
855 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
856 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
857 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
858 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
859 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
860 #define QIB_I_C_ERROR INT_MASK(Err)
862 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
863 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
864 #define QIB_I_GPIO INT_MASK(AssertGPIO)
865 #define QIB_I_P_SDMAINT(pidx) \
866 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
867 INT_MASK_P(SDmaProgress, pidx) | \
868 INT_MASK_PM(SDmaCleanupDone, pidx))
870 /* Interrupt bits that are "per port" */
871 #define QIB_I_P_BITSEXTANT(pidx) \
872 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
873 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
874 INT_MASK_P(SDmaProgress, pidx) | \
875 INT_MASK_PM(SDmaCleanupDone, pidx))
877 /* Interrupt bits that are common to a device */
878 /* currently unused: QIB_I_SPIOSENT */
879 #define QIB_I_C_BITSEXTANT \
880 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
882 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
884 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
885 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
888 * Error bits that are "per port".
890 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
891 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
892 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
893 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
894 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
895 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
896 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
897 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
898 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
899 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
900 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
901 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
902 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
903 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
904 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
905 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
906 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
907 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
908 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
909 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
910 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
911 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
912 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
913 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
914 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
915 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
916 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
917 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
919 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
920 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
921 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
922 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
923 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
924 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
925 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
926 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
927 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
928 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
929 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
931 /* Error bits that are common to a device */
932 #define QIB_E_RESET ERR_MASK(ResetNegated)
933 #define QIB_E_HARDWARE ERR_MASK(HardwareErr)
934 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
938 * Per chip (rather than per-port) errors. Most either do
939 * nothing but trigger a print (because they self-recover, or
940 * always occur in tandem with other errors that handle the
941 * issue), or because they indicate errors with no recovery,
942 * but we want to know that they happened.
944 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
945 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
946 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
947 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
948 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
949 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
950 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
951 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
953 /* SDMA chip errors (not per port)
954 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
955 * the SDMAHALT error immediately, so we just print the dup error via the
956 * E_AUTO mechanism. This is true of most of the per-port fatal errors
957 * as well, but since this is port-independent, by definition, it's
958 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
959 * packet send errors, and so are handled in the same manner as other
962 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
963 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
964 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
967 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
968 * it is used to print "common" packet errors.
970 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
971 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
972 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
973 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
976 /* Error Bits that Packet-related (Receive, per-port) */
977 #define QIB_E_P_RPKTERRS (\
978 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
979 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
980 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
981 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
982 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
983 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
986 * Error bits that are Send-related (per port)
987 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
988 * All of these potentially need to have a buffer disarmed
990 #define QIB_E_P_SPKTERRS (\
991 QIB_E_P_SUNEXP_PKTNUM |\
992 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
993 QIB_E_P_SMAXPKTLEN |\
994 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
995 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
996 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
998 #define QIB_E_SPKTERRS ( \
999 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1000 ERR_MASK_N(SendUnsupportedVLErr) | \
1001 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1003 #define QIB_E_P_SDMAERRS ( \
1004 QIB_E_P_SDMAHALT | \
1005 QIB_E_P_SDMADESCADDRMISALIGN | \
1006 QIB_E_P_SDMAUNEXPDATA | \
1007 QIB_E_P_SDMAMISSINGDW | \
1008 QIB_E_P_SDMADWEN | \
1009 QIB_E_P_SDMARPYTAG | \
1010 QIB_E_P_SDMA1STDESC | \
1011 QIB_E_P_SDMABASE | \
1012 QIB_E_P_SDMATAILOUTOFBOUND | \
1013 QIB_E_P_SDMAOUTOFBOUND | \
1014 QIB_E_P_SDMAGENMISMATCH)
1017 * This sets some bits more than once, but makes it more obvious which
1018 * bits are not handled under other categories, and the repeat definition
1021 #define QIB_E_P_BITSEXTANT ( \
1022 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1023 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1024 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1025 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1029 * These are errors that can occur when the link
1030 * changes state while a packet is being sent or received. This doesn't
1031 * cover things like EBP or VCRC that can be the result of a sending
1032 * having the link change state, so we receive a "known bad" packet.
1033 * All of these are "per port", so renamed:
1035 #define QIB_E_P_LINK_PKTERRS (\
1036 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1037 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1038 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1042 * This sets some bits more than once, but makes it more obvious which
1043 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1044 * and the repeat definition is not a problem.
1046 #define QIB_E_C_BITSEXTANT (\
1047 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1048 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1049 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1051 /* Likewise Neuter E_SPKT_ERRS_IGNORE */
1052 #define E_SPKT_ERRS_IGNORE 0
1054 #define QIB_EXTS_MEMBIST_DISABLED \
1055 SYM_MASK(EXTStatus, MemBISTDisabled)
1056 #define QIB_EXTS_MEMBIST_ENDTEST \
1057 SYM_MASK(EXTStatus, MemBISTEndTest)
1059 #define QIB_E_SPIOARMLAUNCH \
1060 ERR_MASK(SendArmLaunchErr)
1062 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1063 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1066 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1067 * and also if forced QDR (only QDR enabled). It's enabled for the
1068 * forced QDR case so that scrambling will be enabled by the TS3
1069 * exchange, when supported by both sides of the link.
1071 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1072 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1073 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1074 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1075 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1076 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1077 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1078 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1080 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1081 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1083 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1084 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1085 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1087 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1088 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1089 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1090 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1091 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1092 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1093 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1095 #define IBA7322_REDIRECT_VEC_PER_REG 12
1097 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1098 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1099 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1100 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1101 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1103 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1105 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1107 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1108 fldname##Mask##_##port), .msg = #fldname }
1109 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs
[] = {
1110 HWE_AUTO_P(IBSerdesPClkNotDetect
, 1),
1111 HWE_AUTO_P(IBSerdesPClkNotDetect
, 0),
1112 HWE_AUTO(PCIESerdesPClkNotDetect
),
1113 HWE_AUTO(PowerOnBISTFailed
),
1114 HWE_AUTO(TempsenseTholdReached
),
1115 HWE_AUTO(MemoryErr
),
1116 HWE_AUTO(PCIeBusParityErr
),
1117 HWE_AUTO(PcieCplTimeout
),
1118 HWE_AUTO(PciePoisonedTLP
),
1119 HWE_AUTO_P(SDmaMemReadErr
, 1),
1120 HWE_AUTO_P(SDmaMemReadErr
, 0),
1121 HWE_AUTO_P(IBCBusFromSPCParityErr
, 1),
1122 HWE_AUTO_P(IBCBusToSPCParityErr
, 1),
1123 HWE_AUTO_P(IBCBusFromSPCParityErr
, 0),
1124 HWE_AUTO(statusValidNoEop
),
1125 HWE_AUTO(LATriggered
),
1129 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1131 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1133 static const struct qib_hwerror_msgs qib_7322error_msgs
[] = {
1134 E_AUTO(ResetNegated
),
1135 E_AUTO(HardwareErr
),
1136 E_AUTO(InvalidAddrErr
),
1137 E_AUTO(SDmaVL15Err
),
1138 E_AUTO(SBufVL15MisUseErr
),
1139 E_AUTO(InvalidEEPCmd
),
1140 E_AUTO(RcvContextShareErr
),
1141 E_AUTO(SendVLMismatchErr
),
1142 E_AUTO(SendArmLaunchErr
),
1143 E_AUTO(SendSpecialTriggerErr
),
1144 E_AUTO(SDmaWrongPortErr
),
1145 E_AUTO(SDmaBufMaskDuplicateErr
),
1146 E_AUTO(RcvHdrFullErr
),
1147 E_AUTO(RcvEgrFullErr
),
1151 static const struct qib_hwerror_msgs qib_7322p_error_msgs
[] = {
1152 E_P_AUTO(IBStatusChanged
),
1153 E_P_AUTO(SHeadersErr
),
1154 E_P_AUTO(VL15BufMisuseErr
),
1156 * SDmaHaltErr is not really an error, make it clearer;
1158 {.mask
= SYM_MASK(ErrMask_0
, SDmaHaltErrMask
), .msg
= "SDmaHalted"},
1159 E_P_AUTO(SDmaDescAddrMisalignErr
),
1160 E_P_AUTO(SDmaUnexpDataErr
),
1161 E_P_AUTO(SDmaMissingDwErr
),
1162 E_P_AUTO(SDmaDwEnErr
),
1163 E_P_AUTO(SDmaRpyTagErr
),
1164 E_P_AUTO(SDma1stDescErr
),
1165 E_P_AUTO(SDmaBaseErr
),
1166 E_P_AUTO(SDmaTailOutOfBoundErr
),
1167 E_P_AUTO(SDmaOutOfBoundErr
),
1168 E_P_AUTO(SDmaGenMismatchErr
),
1169 E_P_AUTO(SendBufMisuseErr
),
1170 E_P_AUTO(SendUnsupportedVLErr
),
1171 E_P_AUTO(SendUnexpectedPktNumErr
),
1172 E_P_AUTO(SendDroppedDataPktErr
),
1173 E_P_AUTO(SendDroppedSmpPktErr
),
1174 E_P_AUTO(SendPktLenErr
),
1175 E_P_AUTO(SendUnderRunErr
),
1176 E_P_AUTO(SendMaxPktLenErr
),
1177 E_P_AUTO(SendMinPktLenErr
),
1178 E_P_AUTO(RcvIBLostLinkErr
),
1179 E_P_AUTO(RcvHdrErr
),
1180 E_P_AUTO(RcvHdrLenErr
),
1181 E_P_AUTO(RcvBadTidErr
),
1182 E_P_AUTO(RcvBadVersionErr
),
1183 E_P_AUTO(RcvIBFlowErr
),
1184 E_P_AUTO(RcvEBPErr
),
1185 E_P_AUTO(RcvUnsupportedVLErr
),
1186 E_P_AUTO(RcvUnexpectedCharErr
),
1187 E_P_AUTO(RcvShortPktLenErr
),
1188 E_P_AUTO(RcvLongPktLenErr
),
1189 E_P_AUTO(RcvMaxPktLenErr
),
1190 E_P_AUTO(RcvMinPktLenErr
),
1191 E_P_AUTO(RcvICRCErr
),
1192 E_P_AUTO(RcvVCRCErr
),
1193 E_P_AUTO(RcvFormatErr
),
1198 * Below generates "auto-message" for interrupts not specific to any port or
1201 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1203 /* Below generates "auto-message" for interrupts specific to a port */
1204 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1205 SYM_LSB(IntMask, fldname##Mask##_0), \
1206 SYM_LSB(IntMask, fldname##Mask##_1)), \
1207 .msg = #fldname "_P" }
1208 /* For some reason, the SerDesTrimDone bits are reversed */
1209 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1210 SYM_LSB(IntMask, fldname##Mask##_1), \
1211 SYM_LSB(IntMask, fldname##Mask##_0)), \
1212 .msg = #fldname "_P" }
1214 * Below generates "auto-message" for interrupts specific to a context,
1215 * with ctxt-number appended
1217 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1218 SYM_LSB(IntMask, fldname##0IntMask), \
1219 SYM_LSB(IntMask, fldname##17IntMask)), \
1220 .msg = #fldname "_C"}
1222 static const struct qib_hwerror_msgs qib_7322_intr_msgs
[] = {
1223 INTR_AUTO_P(SDmaInt
),
1224 INTR_AUTO_P(SDmaProgressInt
),
1225 INTR_AUTO_P(SDmaIdleInt
),
1226 INTR_AUTO_P(SDmaCleanupDone
),
1227 INTR_AUTO_C(RcvUrg
),
1228 INTR_AUTO_P(ErrInt
),
1229 INTR_AUTO(ErrInt
), /* non-port-specific errs */
1230 INTR_AUTO(AssertGPIOInt
),
1231 INTR_AUTO_P(SendDoneInt
),
1232 INTR_AUTO(SendBufAvailInt
),
1233 INTR_AUTO_C(RcvAvail
),
1237 #define TXSYMPTOM_AUTO_P(fldname) \
1238 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), .msg = #fldname }
1239 static const struct qib_hwerror_msgs hdrchk_msgs
[] = {
1240 TXSYMPTOM_AUTO_P(NonKeyPacket
),
1241 TXSYMPTOM_AUTO_P(GRHFail
),
1242 TXSYMPTOM_AUTO_P(PkeyFail
),
1243 TXSYMPTOM_AUTO_P(QPFail
),
1244 TXSYMPTOM_AUTO_P(SLIDFail
),
1245 TXSYMPTOM_AUTO_P(RawIPV6
),
1246 TXSYMPTOM_AUTO_P(PacketTooSmall
),
1250 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1253 * Called when we might have an error that is specific to a particular
1254 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1255 * because we don't need to force the update of pioavail
1257 static void qib_disarm_7322_senderrbufs(struct qib_pportdata
*ppd
)
1259 struct qib_devdata
*dd
= ppd
->dd
;
1262 u32 piobcnt
= dd
->piobcnt2k
+ dd
->piobcnt4k
+ NUM_VL15_BUFS
;
1263 u32 regcnt
= (piobcnt
+ BITS_PER_LONG
- 1) / BITS_PER_LONG
;
1264 unsigned long sbuf
[4];
1267 * It's possible that sendbuffererror could have bits set; might
1268 * have already done this as a result of hardware error handling.
1271 for (i
= 0; i
< regcnt
; ++i
) {
1272 sbuf
[i
] = qib_read_kreg64(dd
, kr_sendbuffererror
+ i
);
1275 qib_write_kreg(dd
, kr_sendbuffererror
+ i
, sbuf
[i
]);
1280 qib_disarm_piobufs_set(dd
, sbuf
, piobcnt
);
1283 /* No txe_recover yet, if ever */
1285 /* No decode__errors yet */
1286 static void err_decode(char *msg
, size_t len
, u64 errs
,
1287 const struct qib_hwerror_msgs
*msp
)
1290 int took
, multi
, n
= 0;
1292 while (msp
&& msp
->mask
) {
1293 multi
= (msp
->mask
& (msp
->mask
- 1));
1294 while (errs
& msp
->mask
) {
1295 these
= (errs
& msp
->mask
);
1296 lmask
= (these
& (these
- 1)) ^ these
;
1299 /* separate the strings */
1303 took
= scnprintf(msg
, len
, "%s", msp
->msg
);
1309 /* More than one bit this mask */
1312 while (lmask
& msp
->mask
) {
1316 took
= scnprintf(msg
, len
, "_%d", idx
);
1323 /* If some bits are left, show in hex. */
1325 snprintf(msg
, len
, "%sMORE:%llX", n
? "," : "",
1326 (unsigned long long) errs
);
1329 /* only called if r1 set */
1330 static void flush_fifo(struct qib_pportdata
*ppd
)
1332 struct qib_devdata
*dd
= ppd
->dd
;
1333 u32 __iomem
*piobuf
;
1337 const unsigned hdrwords
= 7;
1338 static struct qib_ib_header ibhdr
= {
1339 .lrh
[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH
),
1340 .lrh
[1] = IB_LID_PERMISSIVE
,
1341 .lrh
[2] = cpu_to_be16(hdrwords
+ SIZE_OF_CRC
),
1342 .lrh
[3] = IB_LID_PERMISSIVE
,
1343 .u
.oth
.bth
[0] = cpu_to_be32(
1344 (IB_OPCODE_UD_SEND_ONLY
<< 24) | QIB_DEFAULT_P_KEY
),
1345 .u
.oth
.bth
[1] = cpu_to_be32(0),
1346 .u
.oth
.bth
[2] = cpu_to_be32(0),
1347 .u
.oth
.u
.ud
.deth
[0] = cpu_to_be32(0),
1348 .u
.oth
.u
.ud
.deth
[1] = cpu_to_be32(0),
1352 * Send a dummy VL15 packet to flush the launch FIFO.
1353 * This will not actually be sent since the TxeBypassIbc bit is set.
1355 pbc
= PBC_7322_VL15_SEND
|
1356 (((u64
)ppd
->hw_pidx
) << (PBC_PORT_SEL_LSB
+ 32)) |
1357 (hdrwords
+ SIZE_OF_CRC
);
1358 piobuf
= qib_7322_getsendbuf(ppd
, pbc
, &bufn
);
1361 writeq(pbc
, piobuf
);
1362 hdr
= (u32
*) &ibhdr
;
1363 if (dd
->flags
& QIB_PIO_FLUSH_WC
) {
1365 qib_pio_copy(piobuf
+ 2, hdr
, hdrwords
- 1);
1367 __raw_writel(hdr
[hdrwords
- 1], piobuf
+ hdrwords
+ 1);
1370 qib_pio_copy(piobuf
+ 2, hdr
, hdrwords
);
1371 qib_sendbuf_done(dd
, bufn
);
1375 * This is called with interrupts disabled and sdma_lock held.
1377 static void qib_7322_sdma_sendctrl(struct qib_pportdata
*ppd
, unsigned op
)
1379 struct qib_devdata
*dd
= ppd
->dd
;
1380 u64 set_sendctrl
= 0;
1381 u64 clr_sendctrl
= 0;
1383 if (op
& QIB_SDMA_SENDCTRL_OP_ENABLE
)
1384 set_sendctrl
|= SYM_MASK(SendCtrl_0
, SDmaEnable
);
1386 clr_sendctrl
|= SYM_MASK(SendCtrl_0
, SDmaEnable
);
1388 if (op
& QIB_SDMA_SENDCTRL_OP_INTENABLE
)
1389 set_sendctrl
|= SYM_MASK(SendCtrl_0
, SDmaIntEnable
);
1391 clr_sendctrl
|= SYM_MASK(SendCtrl_0
, SDmaIntEnable
);
1393 if (op
& QIB_SDMA_SENDCTRL_OP_HALT
)
1394 set_sendctrl
|= SYM_MASK(SendCtrl_0
, SDmaHalt
);
1396 clr_sendctrl
|= SYM_MASK(SendCtrl_0
, SDmaHalt
);
1398 if (op
& QIB_SDMA_SENDCTRL_OP_DRAIN
)
1399 set_sendctrl
|= SYM_MASK(SendCtrl_0
, TxeBypassIbc
) |
1400 SYM_MASK(SendCtrl_0
, TxeAbortIbc
) |
1401 SYM_MASK(SendCtrl_0
, TxeDrainRmFifo
);
1403 clr_sendctrl
|= SYM_MASK(SendCtrl_0
, TxeBypassIbc
) |
1404 SYM_MASK(SendCtrl_0
, TxeAbortIbc
) |
1405 SYM_MASK(SendCtrl_0
, TxeDrainRmFifo
);
1407 spin_lock(&dd
->sendctrl_lock
);
1409 /* If we are draining everything, block sends first */
1410 if (op
& QIB_SDMA_SENDCTRL_OP_DRAIN
) {
1411 ppd
->p_sendctrl
&= ~SYM_MASK(SendCtrl_0
, SendEnable
);
1412 qib_write_kreg_port(ppd
, krp_sendctrl
, ppd
->p_sendctrl
);
1413 qib_write_kreg(dd
, kr_scratch
, 0);
1416 ppd
->p_sendctrl
|= set_sendctrl
;
1417 ppd
->p_sendctrl
&= ~clr_sendctrl
;
1419 if (op
& QIB_SDMA_SENDCTRL_OP_CLEANUP
)
1420 qib_write_kreg_port(ppd
, krp_sendctrl
,
1422 SYM_MASK(SendCtrl_0
, SDmaCleanup
));
1424 qib_write_kreg_port(ppd
, krp_sendctrl
, ppd
->p_sendctrl
);
1425 qib_write_kreg(dd
, kr_scratch
, 0);
1427 if (op
& QIB_SDMA_SENDCTRL_OP_DRAIN
) {
1428 ppd
->p_sendctrl
|= SYM_MASK(SendCtrl_0
, SendEnable
);
1429 qib_write_kreg_port(ppd
, krp_sendctrl
, ppd
->p_sendctrl
);
1430 qib_write_kreg(dd
, kr_scratch
, 0);
1433 spin_unlock(&dd
->sendctrl_lock
);
1435 if ((op
& QIB_SDMA_SENDCTRL_OP_DRAIN
) && ppd
->dd
->cspec
->r1
)
1439 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata
*ppd
)
1441 __qib_sdma_process_event(ppd
, qib_sdma_event_e50_hw_cleaned
);
1444 static void qib_sdma_7322_setlengen(struct qib_pportdata
*ppd
)
1447 * Set SendDmaLenGen and clear and set
1448 * the MSB of the generation count to enable generation checking
1449 * and load the internal generation counter.
1451 qib_write_kreg_port(ppd
, krp_senddmalengen
, ppd
->sdma_descq_cnt
);
1452 qib_write_kreg_port(ppd
, krp_senddmalengen
,
1453 ppd
->sdma_descq_cnt
|
1454 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB
));
1458 * Must be called with sdma_lock held, or before init finished.
1460 static void qib_sdma_update_7322_tail(struct qib_pportdata
*ppd
, u16 tail
)
1462 /* Commit writes to memory and advance the tail on the chip */
1464 ppd
->sdma_descq_tail
= tail
;
1465 qib_write_kreg_port(ppd
, krp_senddmatail
, tail
);
1469 * This is called with interrupts disabled and sdma_lock held.
1471 static void qib_7322_sdma_hw_start_up(struct qib_pportdata
*ppd
)
1475 * The hardware doesn't require this but we do it so that verbs
1476 * and user applications don't wait for link active to send stale
1479 sendctrl_7322_mod(ppd
, QIB_SENDCTRL_FLUSH
);
1481 qib_sdma_7322_setlengen(ppd
);
1482 qib_sdma_update_7322_tail(ppd
, 0); /* Set SendDmaTail */
1483 ppd
->sdma_head_dma
[0] = 0;
1484 qib_7322_sdma_sendctrl(ppd
,
1485 ppd
->sdma_state
.current_op
| QIB_SDMA_SENDCTRL_OP_CLEANUP
);
1488 #define DISABLES_SDMA ( \
1489 QIB_E_P_SDMAHALT | \
1490 QIB_E_P_SDMADESCADDRMISALIGN | \
1491 QIB_E_P_SDMAMISSINGDW | \
1492 QIB_E_P_SDMADWEN | \
1493 QIB_E_P_SDMARPYTAG | \
1494 QIB_E_P_SDMA1STDESC | \
1495 QIB_E_P_SDMABASE | \
1496 QIB_E_P_SDMATAILOUTOFBOUND | \
1497 QIB_E_P_SDMAOUTOFBOUND | \
1498 QIB_E_P_SDMAGENMISMATCH)
1500 static void sdma_7322_p_errors(struct qib_pportdata
*ppd
, u64 errs
)
1502 unsigned long flags
;
1503 struct qib_devdata
*dd
= ppd
->dd
;
1505 errs
&= QIB_E_P_SDMAERRS
;
1507 if (errs
& QIB_E_P_SDMAUNEXPDATA
)
1508 qib_dev_err(dd
, "IB%u:%u SDmaUnexpData\n", dd
->unit
,
1511 spin_lock_irqsave(&ppd
->sdma_lock
, flags
);
1513 switch (ppd
->sdma_state
.current_state
) {
1514 case qib_sdma_state_s00_hw_down
:
1517 case qib_sdma_state_s10_hw_start_up_wait
:
1518 if (errs
& QIB_E_P_SDMAHALT
)
1519 __qib_sdma_process_event(ppd
,
1520 qib_sdma_event_e20_hw_started
);
1523 case qib_sdma_state_s20_idle
:
1526 case qib_sdma_state_s30_sw_clean_up_wait
:
1529 case qib_sdma_state_s40_hw_clean_up_wait
:
1530 if (errs
& QIB_E_P_SDMAHALT
)
1531 __qib_sdma_process_event(ppd
,
1532 qib_sdma_event_e50_hw_cleaned
);
1535 case qib_sdma_state_s50_hw_halt_wait
:
1536 if (errs
& QIB_E_P_SDMAHALT
)
1537 __qib_sdma_process_event(ppd
,
1538 qib_sdma_event_e60_hw_halted
);
1541 case qib_sdma_state_s99_running
:
1542 __qib_sdma_process_event(ppd
, qib_sdma_event_e7322_err_halted
);
1543 __qib_sdma_process_event(ppd
, qib_sdma_event_e60_hw_halted
);
1547 spin_unlock_irqrestore(&ppd
->sdma_lock
, flags
);
1551 * handle per-device errors (not per-port errors)
1553 static noinline
void handle_7322_errors(struct qib_devdata
*dd
)
1561 qib_stats
.sps_errints
++;
1562 errs
= qib_read_kreg64(dd
, kr_errstatus
);
1564 qib_devinfo(dd
->pcidev
, "device error interrupt, "
1565 "but no error bits set!\n");
1569 /* don't report errors that are masked */
1570 errs
&= dd
->cspec
->errormask
;
1571 msg
= dd
->cspec
->emsgbuf
;
1573 /* do these first, they are most important */
1574 if (errs
& QIB_E_HARDWARE
) {
1576 qib_7322_handle_hwerrors(dd
, msg
, sizeof dd
->cspec
->emsgbuf
);
1578 for (log_idx
= 0; log_idx
< QIB_EEP_LOG_CNT
; ++log_idx
)
1579 if (errs
& dd
->eep_st_masks
[log_idx
].errs_to_log
)
1580 qib_inc_eeprom_err(dd
, log_idx
, 1);
1582 if (errs
& QIB_E_SPKTERRS
) {
1583 qib_disarm_7322_senderrbufs(dd
->pport
);
1584 qib_stats
.sps_txerrs
++;
1585 } else if (errs
& QIB_E_INVALIDADDR
)
1586 qib_stats
.sps_txerrs
++;
1587 else if (errs
& QIB_E_ARMLAUNCH
) {
1588 qib_stats
.sps_txerrs
++;
1589 qib_disarm_7322_senderrbufs(dd
->pport
);
1591 qib_write_kreg(dd
, kr_errclear
, errs
);
1594 * The ones we mask off are handled specially below
1595 * or above. Also mask SDMADISABLED by default as it
1598 mask
= QIB_E_HARDWARE
;
1601 err_decode(msg
, sizeof dd
->cspec
->emsgbuf
, errs
& ~mask
,
1602 qib_7322error_msgs
);
1605 * Getting reset is a tragedy for all ports. Mark the device
1606 * _and_ the ports as "offline" in way meaningful to each.
1608 if (errs
& QIB_E_RESET
) {
1611 qib_dev_err(dd
, "Got reset, requires re-init "
1612 "(unload and reload driver)\n");
1613 dd
->flags
&= ~QIB_INITTED
; /* needs re-init */
1614 /* mark as having had error */
1615 *dd
->devstatusp
|= QIB_STATUS_HWERROR
;
1616 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
)
1617 if (dd
->pport
[pidx
].link_speed_supported
)
1618 *dd
->pport
[pidx
].statusp
&= ~QIB_STATUS_IB_CONF
;
1622 qib_dev_err(dd
, "%s error\n", msg
);
1625 * If there were hdrq or egrfull errors, wake up any processes
1626 * waiting in poll. We used to try to check which contexts had
1627 * the overflow, but given the cost of that and the chip reads
1628 * to support it, it's better to just wake everybody up if we
1629 * get an overflow; waiters can poll again if it's not them.
1631 if (errs
& (ERR_MASK(RcvEgrFullErr
) | ERR_MASK(RcvHdrFullErr
))) {
1632 qib_handle_urcv(dd
, ~0U);
1633 if (errs
& ERR_MASK(RcvEgrFullErr
))
1634 qib_stats
.sps_buffull
++;
1636 qib_stats
.sps_hdrfull
++;
1643 static void reenable_chase(unsigned long opaque
)
1645 struct qib_pportdata
*ppd
= (struct qib_pportdata
*)opaque
;
1647 ppd
->cpspec
->chase_timer
.expires
= 0;
1648 qib_set_ib_7322_lstate(ppd
, QLOGIC_IB_IBCC_LINKCMD_DOWN
,
1649 QLOGIC_IB_IBCC_LINKINITCMD_POLL
);
1652 static void disable_chase(struct qib_pportdata
*ppd
, u64 tnow
, u8 ibclt
)
1654 ppd
->cpspec
->chase_end
= 0;
1659 qib_set_ib_7322_lstate(ppd
, QLOGIC_IB_IBCC_LINKCMD_DOWN
,
1660 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE
);
1661 ppd
->cpspec
->chase_timer
.expires
= jiffies
+ QIB_CHASE_DIS_TIME
;
1662 add_timer(&ppd
->cpspec
->chase_timer
);
1665 static void handle_serdes_issues(struct qib_pportdata
*ppd
, u64 ibcst
)
1670 ibclt
= (u8
)SYM_FIELD(ibcst
, IBCStatusA_0
, LinkTrainingState
);
1673 * Detect and handle the state chase issue, where we can
1674 * get stuck if we are unlucky on timing on both sides of
1675 * the link. If we are, we disable, set a timer, and
1679 case IB_7322_LT_STATE_CFGRCVFCFG
:
1680 case IB_7322_LT_STATE_CFGWAITRMT
:
1681 case IB_7322_LT_STATE_TXREVLANES
:
1682 case IB_7322_LT_STATE_CFGENH
:
1683 tnow
= get_jiffies_64();
1684 if (ppd
->cpspec
->chase_end
&&
1685 time_after64(tnow
, ppd
->cpspec
->chase_end
))
1686 disable_chase(ppd
, tnow
, ibclt
);
1687 else if (!ppd
->cpspec
->chase_end
)
1688 ppd
->cpspec
->chase_end
= tnow
+ QIB_CHASE_TIME
;
1691 ppd
->cpspec
->chase_end
= 0;
1695 if (ibclt
== IB_7322_LT_STATE_CFGTEST
&&
1696 (ibcst
& SYM_MASK(IBCStatusA_0
, LinkSpeedQDR
))) {
1698 ppd
->cpspec
->qdr_reforce
= 1;
1699 if (!ppd
->dd
->cspec
->r1
)
1700 serdes_7322_los_enable(ppd
, 0);
1701 } else if (ppd
->cpspec
->qdr_reforce
&&
1702 (ibcst
& SYM_MASK(IBCStatusA_0
, LinkSpeedQDR
)) &&
1703 (ibclt
== IB_7322_LT_STATE_CFGENH
||
1704 ibclt
== IB_7322_LT_STATE_CFGIDLE
||
1705 ibclt
== IB_7322_LT_STATE_LINKUP
))
1708 if ((IS_QMH(ppd
->dd
) || IS_QME(ppd
->dd
)) &&
1709 ppd
->link_speed_enabled
== QIB_IB_QDR
&&
1710 (ibclt
== IB_7322_LT_STATE_CFGTEST
||
1711 ibclt
== IB_7322_LT_STATE_CFGENH
||
1712 (ibclt
>= IB_7322_LT_STATE_POLLACTIVE
&&
1713 ibclt
<= IB_7322_LT_STATE_SLEEPQUIET
)))
1716 if (ibclt
!= IB_7322_LT_STATE_LINKUP
) {
1717 u8 ltstate
= qib_7322_phys_portstate(ibcst
);
1718 u8 pibclt
= (u8
)SYM_FIELD(ppd
->lastibcstat
, IBCStatusA_0
,
1720 if (!ppd
->dd
->cspec
->r1
&&
1721 pibclt
== IB_7322_LT_STATE_LINKUP
&&
1722 ltstate
!= IB_PHYSPORTSTATE_LINK_ERR_RECOVER
&&
1723 ltstate
!= IB_PHYSPORTSTATE_RECOVERY_RETRAIN
&&
1724 ltstate
!= IB_PHYSPORTSTATE_RECOVERY_WAITRMT
&&
1725 ltstate
!= IB_PHYSPORTSTATE_RECOVERY_IDLE
)
1726 /* If the link went down (but no into recovery,
1727 * turn LOS back on */
1728 serdes_7322_los_enable(ppd
, 1);
1729 if (!ppd
->cpspec
->qdr_dfe_on
&&
1730 ibclt
<= IB_7322_LT_STATE_SLEEPQUIET
) {
1731 ppd
->cpspec
->qdr_dfe_on
= 1;
1732 ppd
->cpspec
->qdr_dfe_time
= 0;
1733 /* On link down, reenable QDR adaptation */
1734 qib_write_kreg_port(ppd
, krp_static_adapt_dis(2),
1735 ppd
->dd
->cspec
->r1
?
1736 QDR_STATIC_ADAPT_DOWN_R1
:
1737 QDR_STATIC_ADAPT_DOWN
);
1738 printk(KERN_INFO QIB_DRV_NAME
1739 " IB%u:%u re-enabled QDR adaptation "
1740 "ibclt %x\n", ppd
->dd
->unit
, ppd
->port
, ibclt
);
1745 static int qib_7322_set_ib_cfg(struct qib_pportdata
*, int, u32
);
1748 * This is per-pport error handling.
1749 * will likely get it's own MSIx interrupt (one for each port,
1750 * although just a single handler).
1752 static noinline
void handle_7322_p_errors(struct qib_pportdata
*ppd
)
1755 u64 ignore_this_time
= 0, iserr
= 0, errs
, fmask
;
1756 struct qib_devdata
*dd
= ppd
->dd
;
1758 /* do this as soon as possible */
1759 fmask
= qib_read_kreg64(dd
, kr_act_fmask
);
1761 check_7322_rxe_status(ppd
);
1763 errs
= qib_read_kreg_port(ppd
, krp_errstatus
);
1765 qib_devinfo(dd
->pcidev
,
1766 "Port%d error interrupt, but no error bits set!\n",
1769 errs
&= ~QIB_E_P_IBSTATUSCHANGED
;
1773 msg
= ppd
->cpspec
->epmsgbuf
;
1776 if (errs
& ~QIB_E_P_BITSEXTANT
) {
1777 err_decode(msg
, sizeof ppd
->cpspec
->epmsgbuf
,
1778 errs
& ~QIB_E_P_BITSEXTANT
, qib_7322p_error_msgs
);
1780 snprintf(msg
, sizeof ppd
->cpspec
->epmsgbuf
,
1782 qib_dev_porterr(dd
, ppd
->port
, "error interrupt with unknown"
1783 " errors 0x%016Lx set (and %s)\n",
1784 (errs
& ~QIB_E_P_BITSEXTANT
), msg
);
1788 if (errs
& QIB_E_P_SHDR
) {
1791 /* determine cause, then write to clear */
1792 symptom
= qib_read_kreg_port(ppd
, krp_sendhdrsymptom
);
1793 qib_write_kreg_port(ppd
, krp_sendhdrsymptom
, 0);
1794 err_decode(msg
, sizeof ppd
->cpspec
->epmsgbuf
, symptom
,
1797 /* senderrbuf cleared in SPKTERRS below */
1800 if (errs
& QIB_E_P_SPKTERRS
) {
1801 if ((errs
& QIB_E_P_LINK_PKTERRS
) &&
1802 !(ppd
->lflags
& QIBL_LINKACTIVE
)) {
1804 * This can happen when trying to bring the link
1805 * up, but the IB link changes state at the "wrong"
1806 * time. The IB logic then complains that the packet
1807 * isn't valid. We don't want to confuse people, so
1808 * we just don't print them, except at debug
1810 err_decode(msg
, sizeof ppd
->cpspec
->epmsgbuf
,
1811 (errs
& QIB_E_P_LINK_PKTERRS
),
1812 qib_7322p_error_msgs
);
1814 ignore_this_time
= errs
& QIB_E_P_LINK_PKTERRS
;
1816 qib_disarm_7322_senderrbufs(ppd
);
1817 } else if ((errs
& QIB_E_P_LINK_PKTERRS
) &&
1818 !(ppd
->lflags
& QIBL_LINKACTIVE
)) {
1820 * This can happen when SMA is trying to bring the link
1821 * up, but the IB link changes state at the "wrong" time.
1822 * The IB logic then complains that the packet isn't
1823 * valid. We don't want to confuse people, so we just
1824 * don't print them, except at debug
1826 err_decode(msg
, sizeof ppd
->cpspec
->epmsgbuf
, errs
,
1827 qib_7322p_error_msgs
);
1828 ignore_this_time
= errs
& QIB_E_P_LINK_PKTERRS
;
1832 qib_write_kreg_port(ppd
, krp_errclear
, errs
);
1834 errs
&= ~ignore_this_time
;
1838 if (errs
& QIB_E_P_RPKTERRS
)
1839 qib_stats
.sps_rcverrs
++;
1840 if (errs
& QIB_E_P_SPKTERRS
)
1841 qib_stats
.sps_txerrs
++;
1843 iserr
= errs
& ~(QIB_E_P_RPKTERRS
| QIB_E_P_PKTERRS
);
1845 if (errs
& QIB_E_P_SDMAERRS
)
1846 sdma_7322_p_errors(ppd
, errs
);
1848 if (errs
& QIB_E_P_IBSTATUSCHANGED
) {
1852 ibcs
= qib_read_kreg_port(ppd
, krp_ibcstatus_a
);
1853 ltstate
= qib_7322_phys_portstate(ibcs
);
1855 if (!(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
))
1856 handle_serdes_issues(ppd
, ibcs
);
1857 if (!(ppd
->cpspec
->ibcctrl_a
&
1858 SYM_MASK(IBCCtrlA_0
, IBStatIntReductionEn
))) {
1860 * We got our interrupt, so init code should be
1861 * happy and not try alternatives. Now squelch
1862 * other "chatter" from link-negotiation (pre Init)
1864 ppd
->cpspec
->ibcctrl_a
|=
1865 SYM_MASK(IBCCtrlA_0
, IBStatIntReductionEn
);
1866 qib_write_kreg_port(ppd
, krp_ibcctrl_a
,
1867 ppd
->cpspec
->ibcctrl_a
);
1870 /* Update our picture of width and speed from chip */
1871 ppd
->link_width_active
=
1872 (ibcs
& SYM_MASK(IBCStatusA_0
, LinkWidthActive
)) ?
1873 IB_WIDTH_4X
: IB_WIDTH_1X
;
1874 ppd
->link_speed_active
= (ibcs
& SYM_MASK(IBCStatusA_0
,
1875 LinkSpeedQDR
)) ? QIB_IB_QDR
: (ibcs
&
1876 SYM_MASK(IBCStatusA_0
, LinkSpeedActive
)) ?
1877 QIB_IB_DDR
: QIB_IB_SDR
;
1879 if ((ppd
->lflags
& QIBL_IB_LINK_DISABLED
) && ltstate
!=
1880 IB_PHYSPORTSTATE_DISABLED
)
1881 qib_set_ib_7322_lstate(ppd
, 0,
1882 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE
);
1885 * Since going into a recovery state causes the link
1886 * state to go down and since recovery is transitory,
1887 * it is better if we "miss" ever seeing the link
1888 * training state go into recovery (i.e., ignore this
1889 * transition for link state special handling purposes)
1890 * without updating lastibcstat.
1892 if (ltstate
!= IB_PHYSPORTSTATE_LINK_ERR_RECOVER
&&
1893 ltstate
!= IB_PHYSPORTSTATE_RECOVERY_RETRAIN
&&
1894 ltstate
!= IB_PHYSPORTSTATE_RECOVERY_WAITRMT
&&
1895 ltstate
!= IB_PHYSPORTSTATE_RECOVERY_IDLE
)
1896 qib_handle_e_ibstatuschanged(ppd
, ibcs
);
1899 qib_dev_porterr(dd
, ppd
->port
, "%s error\n", msg
);
1901 if (ppd
->state_wanted
& ppd
->lflags
)
1902 wake_up_interruptible(&ppd
->state_wait
);
1907 /* enable/disable chip from delivering interrupts */
1908 static void qib_7322_set_intr_state(struct qib_devdata
*dd
, u32 enable
)
1911 if (dd
->flags
& QIB_BADINTR
)
1913 qib_write_kreg(dd
, kr_intmask
, dd
->cspec
->int_enable_mask
);
1914 /* cause any pending enabled interrupts to be re-delivered */
1915 qib_write_kreg(dd
, kr_intclear
, 0ULL);
1916 if (dd
->cspec
->num_msix_entries
) {
1917 /* and same for MSIx */
1918 u64 val
= qib_read_kreg64(dd
, kr_intgranted
);
1920 qib_write_kreg(dd
, kr_intgranted
, val
);
1923 qib_write_kreg(dd
, kr_intmask
, 0ULL);
1927 * Try to cleanup as much as possible for anything that might have gone
1928 * wrong while in freeze mode, such as pio buffers being written by user
1929 * processes (causing armlaunch), send errors due to going into freeze mode,
1930 * etc., and try to avoid causing extra interrupts while doing so.
1931 * Forcibly update the in-memory pioavail register copies after cleanup
1932 * because the chip won't do it while in freeze mode (the register values
1933 * themselves are kept correct).
1934 * Make sure that we don't lose any important interrupts by using the chip
1935 * feature that says that writing 0 to a bit in *clear that is set in
1936 * *status will cause an interrupt to be generated again (if allowed by
1938 * This is in chip-specific code because of all of the register accesses,
1939 * even though the details are similar on most chips.
1941 static void qib_7322_clear_freeze(struct qib_devdata
*dd
)
1945 /* disable error interrupts, to avoid confusion */
1946 qib_write_kreg(dd
, kr_errmask
, 0ULL);
1948 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
)
1949 if (dd
->pport
[pidx
].link_speed_supported
)
1950 qib_write_kreg_port(dd
->pport
+ pidx
, krp_errmask
,
1953 /* also disable interrupts; errormask is sometimes overwriten */
1954 qib_7322_set_intr_state(dd
, 0);
1956 /* clear the freeze, and be sure chip saw it */
1957 qib_write_kreg(dd
, kr_control
, dd
->control
);
1958 qib_read_kreg32(dd
, kr_scratch
);
1961 * Force new interrupt if any hwerr, error or interrupt bits are
1962 * still set, and clear "safe" send packet errors related to freeze
1963 * and cancelling sends. Re-enable error interrupts before possible
1964 * force of re-interrupt on pending interrupts.
1966 qib_write_kreg(dd
, kr_hwerrclear
, 0ULL);
1967 qib_write_kreg(dd
, kr_errclear
, E_SPKT_ERRS_IGNORE
);
1968 qib_write_kreg(dd
, kr_errmask
, dd
->cspec
->errormask
);
1969 /* We need to purge per-port errs and reset mask, too */
1970 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
1971 if (!dd
->pport
[pidx
].link_speed_supported
)
1973 qib_write_kreg_port(dd
->pport
+ pidx
, krp_errclear
, ~0Ull);
1974 qib_write_kreg_port(dd
->pport
+ pidx
, krp_errmask
, ~0Ull);
1976 qib_7322_set_intr_state(dd
, 1);
1979 /* no error handling to speak of */
1981 * qib_7322_handle_hwerrors - display hardware errors.
1982 * @dd: the qlogic_ib device
1983 * @msg: the output buffer
1984 * @msgl: the size of the output buffer
1986 * Use same msg buffer as regular errors to avoid excessive stack
1987 * use. Most hardware errors are catastrophic, but for right now,
1988 * we'll print them and continue. We reuse the same message buffer as
1989 * qib_handle_errors() to avoid excessive stack usage.
1991 static void qib_7322_handle_hwerrors(struct qib_devdata
*dd
, char *msg
,
1998 hwerrs
= qib_read_kreg64(dd
, kr_hwerrstatus
);
2001 if (hwerrs
== ~0ULL) {
2002 qib_dev_err(dd
, "Read of hardware error status failed "
2003 "(all bits set); ignoring\n");
2006 qib_stats
.sps_hwerrs
++;
2008 /* Always clear the error status register, except BIST fail */
2009 qib_write_kreg(dd
, kr_hwerrclear
, hwerrs
&
2010 ~HWE_MASK(PowerOnBISTFailed
));
2012 hwerrs
&= dd
->cspec
->hwerrmask
;
2014 /* no EEPROM logging, yet */
2017 qib_devinfo(dd
->pcidev
, "Hardware error: hwerr=0x%llx "
2018 "(cleared)\n", (unsigned long long) hwerrs
);
2020 ctrl
= qib_read_kreg32(dd
, kr_control
);
2021 if ((ctrl
& SYM_MASK(Control
, FreezeMode
)) && !dd
->diag_client
) {
2023 * No recovery yet...
2025 if ((hwerrs
& ~HWE_MASK(LATriggered
)) ||
2026 dd
->cspec
->stay_in_freeze
) {
2028 * If any set that we aren't ignoring only make the
2029 * complaint once, in case it's stuck or recurring,
2030 * and we get here multiple times
2031 * Force link down, so switch knows, and
2032 * LEDs are turned off.
2034 if (dd
->flags
& QIB_INITTED
)
2037 qib_7322_clear_freeze(dd
);
2040 if (hwerrs
& HWE_MASK(PowerOnBISTFailed
)) {
2042 strlcpy(msg
, "[Memory BIST test failed, "
2043 "InfiniPath hardware unusable]", msgl
);
2044 /* ignore from now on, so disable until driver reloaded */
2045 dd
->cspec
->hwerrmask
&= ~HWE_MASK(PowerOnBISTFailed
);
2046 qib_write_kreg(dd
, kr_hwerrmask
, dd
->cspec
->hwerrmask
);
2049 err_decode(msg
, msgl
, hwerrs
, qib_7322_hwerror_msgs
);
2051 /* Ignore esoteric PLL failures et al. */
2053 qib_dev_err(dd
, "%s hardware error\n", msg
);
2055 if (isfatal
&& !dd
->diag_client
) {
2056 qib_dev_err(dd
, "Fatal Hardware Error, no longer"
2057 " usable, SN %.16s\n", dd
->serial
);
2059 * for /sys status file and user programs to print; if no
2060 * trailing brace is copied, we'll know it was truncated.
2063 snprintf(dd
->freezemsg
, dd
->freezelen
,
2065 qib_disable_after_error(dd
);
2071 * qib_7322_init_hwerrors - enable hardware errors
2072 * @dd: the qlogic_ib device
2074 * now that we have finished initializing everything that might reasonably
2075 * cause a hardware error, and cleared those errors bits as they occur,
2076 * we can enable hardware errors in the mask (potentially enabling
2077 * freeze mode), and enable hardware errors as errors (along with
2078 * everything else) in errormask
2080 static void qib_7322_init_hwerrors(struct qib_devdata
*dd
)
2085 extsval
= qib_read_kreg64(dd
, kr_extstatus
);
2086 if (!(extsval
& (QIB_EXTS_MEMBIST_DISABLED
|
2087 QIB_EXTS_MEMBIST_ENDTEST
)))
2088 qib_dev_err(dd
, "MemBIST did not complete!\n");
2090 /* never clear BIST failure, so reported on each driver load */
2091 qib_write_kreg(dd
, kr_hwerrclear
, ~HWE_MASK(PowerOnBISTFailed
));
2092 qib_write_kreg(dd
, kr_hwerrmask
, dd
->cspec
->hwerrmask
);
2095 qib_write_kreg(dd
, kr_errclear
, ~0ULL);
2096 /* enable errors that are masked, at least this first time. */
2097 qib_write_kreg(dd
, kr_errmask
, ~0ULL);
2098 dd
->cspec
->errormask
= qib_read_kreg64(dd
, kr_errmask
);
2099 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
)
2100 if (dd
->pport
[pidx
].link_speed_supported
)
2101 qib_write_kreg_port(dd
->pport
+ pidx
, krp_errmask
,
2106 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2107 * on chips that are count-based, rather than trigger-based. There is no
2108 * reference counting, but that's also fine, given the intended use.
2109 * Only chip-specific because it's all register accesses
2111 static void qib_set_7322_armlaunch(struct qib_devdata
*dd
, u32 enable
)
2114 qib_write_kreg(dd
, kr_errclear
, QIB_E_SPIOARMLAUNCH
);
2115 dd
->cspec
->errormask
|= QIB_E_SPIOARMLAUNCH
;
2117 dd
->cspec
->errormask
&= ~QIB_E_SPIOARMLAUNCH
;
2118 qib_write_kreg(dd
, kr_errmask
, dd
->cspec
->errormask
);
2122 * Formerly took parameter <which> in pre-shifted,
2123 * pre-merged form with LinkCmd and LinkInitCmd
2124 * together, and assuming the zero was NOP.
2126 static void qib_set_ib_7322_lstate(struct qib_pportdata
*ppd
, u16 linkcmd
,
2130 struct qib_devdata
*dd
= ppd
->dd
;
2131 unsigned long flags
;
2133 if (linitcmd
== QLOGIC_IB_IBCC_LINKINITCMD_DISABLE
) {
2135 * If we are told to disable, note that so link-recovery
2136 * code does not attempt to bring us back up.
2137 * Also reset everything that we can, so we start
2138 * completely clean when re-enabled (before we
2139 * actually issue the disable to the IBC)
2141 qib_7322_mini_pcs_reset(ppd
);
2142 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
2143 ppd
->lflags
|= QIBL_IB_LINK_DISABLED
;
2144 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
2145 } else if (linitcmd
|| linkcmd
== QLOGIC_IB_IBCC_LINKCMD_DOWN
) {
2147 * Any other linkinitcmd will lead to LINKDOWN and then
2148 * to INIT (if all is well), so clear flag to let
2149 * link-recovery code attempt to bring us back up.
2151 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
2152 ppd
->lflags
&= ~QIBL_IB_LINK_DISABLED
;
2153 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
2155 * Clear status change interrupt reduction so the
2156 * new state is seen.
2158 ppd
->cpspec
->ibcctrl_a
&=
2159 ~SYM_MASK(IBCCtrlA_0
, IBStatIntReductionEn
);
2162 mod_wd
= (linkcmd
<< IBA7322_IBCC_LINKCMD_SHIFT
) |
2163 (linitcmd
<< QLOGIC_IB_IBCC_LINKINITCMD_SHIFT
);
2165 qib_write_kreg_port(ppd
, krp_ibcctrl_a
, ppd
->cpspec
->ibcctrl_a
|
2167 /* write to chip to prevent back-to-back writes of ibc reg */
2168 qib_write_kreg(dd
, kr_scratch
, 0);
2173 * The total RCV buffer memory is 64KB, used for both ports, and is
2174 * in units of 64 bytes (same as IB flow control credit unit).
2175 * The consumedVL unit in the same registers are in 32 byte units!
2176 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2177 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2178 * in krp_rxcreditvl15, rather than 10.
2180 #define RCV_BUF_UNITSZ 64
2181 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2183 static void set_vls(struct qib_pportdata
*ppd
)
2185 int i
, numvls
, totcred
, cred_vl
, vl0extra
;
2186 struct qib_devdata
*dd
= ppd
->dd
;
2189 numvls
= qib_num_vls(ppd
->vls_operational
);
2192 * Set up per-VL credits. Below is kluge based on these assumptions:
2193 * 1) port is disabled at the time early_init is called.
2194 * 2) give VL15 17 credits, for two max-plausible packets.
2195 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2197 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2198 totcred
= NUM_RCV_BUF_UNITS(dd
);
2199 cred_vl
= (2 * 288 + RCV_BUF_UNITSZ
- 1) / RCV_BUF_UNITSZ
;
2201 qib_write_kreg_port(ppd
, krp_rxcreditvl15
, (u64
) cred_vl
);
2202 cred_vl
= totcred
/ numvls
;
2203 vl0extra
= totcred
- cred_vl
* numvls
;
2204 qib_write_kreg_port(ppd
, krp_rxcreditvl0
, cred_vl
+ vl0extra
);
2205 for (i
= 1; i
< numvls
; i
++)
2206 qib_write_kreg_port(ppd
, krp_rxcreditvl0
+ i
, cred_vl
);
2207 for (; i
< 8; i
++) /* no buffer space for other VLs */
2208 qib_write_kreg_port(ppd
, krp_rxcreditvl0
+ i
, 0);
2210 /* Notify IBC that credits need to be recalculated */
2211 val
= qib_read_kreg_port(ppd
, krp_ibsdtestiftx
);
2212 val
|= SYM_MASK(IB_SDTEST_IF_TX_0
, CREDIT_CHANGE
);
2213 qib_write_kreg_port(ppd
, krp_ibsdtestiftx
, val
);
2214 qib_write_kreg(dd
, kr_scratch
, 0ULL);
2215 val
&= ~SYM_MASK(IB_SDTEST_IF_TX_0
, CREDIT_CHANGE
);
2216 qib_write_kreg_port(ppd
, krp_ibsdtestiftx
, val
);
2218 for (i
= 0; i
< numvls
; i
++)
2219 val
= qib_read_kreg_port(ppd
, krp_rxcreditvl0
+ i
);
2220 val
= qib_read_kreg_port(ppd
, krp_rxcreditvl15
);
2222 /* Change the number of operational VLs */
2223 ppd
->cpspec
->ibcctrl_a
= (ppd
->cpspec
->ibcctrl_a
&
2224 ~SYM_MASK(IBCCtrlA_0
, NumVLane
)) |
2225 ((u64
)(numvls
- 1) << SYM_LSB(IBCCtrlA_0
, NumVLane
));
2226 qib_write_kreg_port(ppd
, krp_ibcctrl_a
, ppd
->cpspec
->ibcctrl_a
);
2227 qib_write_kreg(dd
, kr_scratch
, 0ULL);
2231 * The code that deals with actual SerDes is in serdes_7322_init().
2232 * Compared to the code for iba7220, it is minimal.
2234 static int serdes_7322_init(struct qib_pportdata
*ppd
);
2237 * qib_7322_bringup_serdes - bring up the serdes
2238 * @ppd: physical port on the qlogic_ib device
2240 static int qib_7322_bringup_serdes(struct qib_pportdata
*ppd
)
2242 struct qib_devdata
*dd
= ppd
->dd
;
2244 unsigned long flags
;
2248 * SerDes model not in Pd, but still need to
2249 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2252 /* Put IBC in reset, sends disabled (should be in reset already) */
2253 ppd
->cpspec
->ibcctrl_a
&= ~SYM_MASK(IBCCtrlA_0
, IBLinkEn
);
2254 qib_write_kreg_port(ppd
, krp_ibcctrl_a
, ppd
->cpspec
->ibcctrl_a
);
2255 qib_write_kreg(dd
, kr_scratch
, 0ULL);
2257 if (qib_compat_ddr_negotiate
) {
2258 ppd
->cpspec
->ibdeltainprog
= 1;
2259 ppd
->cpspec
->ibsymsnap
= read_7322_creg32_port(ppd
,
2261 ppd
->cpspec
->iblnkerrsnap
= read_7322_creg32_port(ppd
,
2262 crp_iblinkerrrecov
);
2265 /* flowcontrolwatermark is in units of KBytes */
2266 ibc
= 0x5ULL
<< SYM_LSB(IBCCtrlA_0
, FlowCtrlWaterMark
);
2268 * Flow control is sent this often, even if no changes in
2269 * buffer space occur. Units are 128ns for this chip.
2272 ibc
|= 24ULL << SYM_LSB(IBCCtrlA_0
, FlowCtrlPeriod
);
2273 /* max error tolerance */
2274 ibc
|= 0xfULL
<< SYM_LSB(IBCCtrlA_0
, PhyerrThreshold
);
2275 /* IB credit flow control. */
2276 ibc
|= 0xfULL
<< SYM_LSB(IBCCtrlA_0
, OverrunThreshold
);
2278 * set initial max size pkt IBC will send, including ICRC; it's the
2279 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2281 ibc
|= ((u64
)(ppd
->ibmaxlen
>> 2) + 1) <<
2282 SYM_LSB(IBCCtrlA_0
, MaxPktLen
);
2283 ppd
->cpspec
->ibcctrl_a
= ibc
; /* without linkcmd or linkinitcmd! */
2285 /* initially come up waiting for TS1, without sending anything. */
2286 val
= ppd
->cpspec
->ibcctrl_a
| (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE
<<
2287 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT
);
2290 * Reset the PCS interface to the serdes (and also ibc, which is still
2291 * in reset from above). Writes new value of ibcctrl_a as last step.
2293 qib_7322_mini_pcs_reset(ppd
);
2294 qib_write_kreg(dd
, kr_scratch
, 0ULL);
2296 if (!ppd
->cpspec
->ibcctrl_b
) {
2297 unsigned lse
= ppd
->link_speed_enabled
;
2300 * Not on re-init after reset, establish shadow
2301 * and force initial config.
2303 ppd
->cpspec
->ibcctrl_b
= qib_read_kreg_port(ppd
,
2305 ppd
->cpspec
->ibcctrl_b
&= ~(IBA7322_IBC_SPEED_QDR
|
2306 IBA7322_IBC_SPEED_DDR
|
2307 IBA7322_IBC_SPEED_SDR
|
2308 IBA7322_IBC_WIDTH_AUTONEG
|
2309 SYM_MASK(IBCCtrlB_0
, IB_LANE_REV_SUPPORTED
));
2310 if (lse
& (lse
- 1)) /* Muliple speeds enabled */
2311 ppd
->cpspec
->ibcctrl_b
|=
2312 (lse
<< IBA7322_IBC_SPEED_LSB
) |
2313 IBA7322_IBC_IBTA_1_2_MASK
|
2314 IBA7322_IBC_MAX_SPEED_MASK
;
2316 ppd
->cpspec
->ibcctrl_b
|= (lse
== QIB_IB_QDR
) ?
2317 IBA7322_IBC_SPEED_QDR
|
2318 IBA7322_IBC_IBTA_1_2_MASK
:
2319 (lse
== QIB_IB_DDR
) ?
2320 IBA7322_IBC_SPEED_DDR
:
2321 IBA7322_IBC_SPEED_SDR
;
2322 if ((ppd
->link_width_enabled
& (IB_WIDTH_1X
| IB_WIDTH_4X
)) ==
2323 (IB_WIDTH_1X
| IB_WIDTH_4X
))
2324 ppd
->cpspec
->ibcctrl_b
|= IBA7322_IBC_WIDTH_AUTONEG
;
2326 ppd
->cpspec
->ibcctrl_b
|=
2327 ppd
->link_width_enabled
== IB_WIDTH_4X
?
2328 IBA7322_IBC_WIDTH_4X_ONLY
:
2329 IBA7322_IBC_WIDTH_1X_ONLY
;
2331 /* always enable these on driver reload, not sticky */
2332 ppd
->cpspec
->ibcctrl_b
|= (IBA7322_IBC_RXPOL_MASK
|
2333 IBA7322_IBC_HRTBT_MASK
);
2335 qib_write_kreg_port(ppd
, krp_ibcctrl_b
, ppd
->cpspec
->ibcctrl_b
);
2337 /* setup so we have more time at CFGTEST to change H1 */
2338 val
= qib_read_kreg_port(ppd
, krp_ibcctrl_c
);
2339 val
&= ~SYM_MASK(IBCCtrlC_0
, IB_FRONT_PORCH
);
2340 val
|= 0xfULL
<< SYM_LSB(IBCCtrlC_0
, IB_FRONT_PORCH
);
2341 qib_write_kreg_port(ppd
, krp_ibcctrl_c
, val
);
2343 serdes_7322_init(ppd
);
2345 guid
= be64_to_cpu(ppd
->guid
);
2348 guid
= be64_to_cpu(dd
->base_guid
) + ppd
->port
- 1;
2349 ppd
->guid
= cpu_to_be64(guid
);
2352 qib_write_kreg_port(ppd
, krp_hrtbt_guid
, guid
);
2353 /* write to chip to prevent back-to-back writes of ibc reg */
2354 qib_write_kreg(dd
, kr_scratch
, 0);
2357 ppd
->cpspec
->ibcctrl_a
|= SYM_MASK(IBCCtrlA_0
, IBLinkEn
);
2360 /* be paranoid against later code motion, etc. */
2361 spin_lock_irqsave(&dd
->cspec
->rcvmod_lock
, flags
);
2362 ppd
->p_rcvctrl
|= SYM_MASK(RcvCtrl_0
, RcvIBPortEnable
);
2363 qib_write_kreg_port(ppd
, krp_rcvctrl
, ppd
->p_rcvctrl
);
2364 spin_unlock_irqrestore(&dd
->cspec
->rcvmod_lock
, flags
);
2366 /* Hold the link state machine for mezz boards */
2367 if (IS_QMH(dd
) || IS_QME(dd
))
2368 qib_set_ib_7322_lstate(ppd
, 0,
2369 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE
);
2371 /* Also enable IBSTATUSCHG interrupt. */
2372 val
= qib_read_kreg_port(ppd
, krp_errmask
);
2373 qib_write_kreg_port(ppd
, krp_errmask
,
2374 val
| ERR_MASK_N(IBStatusChanged
));
2376 /* Always zero until we start messing with SerDes for real */
2381 * qib_7322_quiet_serdes - set serdes to txidle
2382 * @dd: the qlogic_ib device
2383 * Called when driver is being unloaded
2385 static void qib_7322_mini_quiet_serdes(struct qib_pportdata
*ppd
)
2388 unsigned long flags
;
2390 qib_set_ib_7322_lstate(ppd
, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE
);
2392 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
2393 ppd
->lflags
&= ~QIBL_IB_AUTONEG_INPROG
;
2394 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
2395 wake_up(&ppd
->cpspec
->autoneg_wait
);
2396 cancel_delayed_work_sync(&ppd
->cpspec
->autoneg_work
);
2397 if (ppd
->dd
->cspec
->r1
)
2398 cancel_delayed_work_sync(&ppd
->cpspec
->ipg_work
);
2400 ppd
->cpspec
->chase_end
= 0;
2401 if (ppd
->cpspec
->chase_timer
.data
) /* if initted */
2402 del_timer_sync(&ppd
->cpspec
->chase_timer
);
2405 * Despite the name, actually disables IBC as well. Do it when
2406 * we are as sure as possible that no more packets can be
2407 * received, following the down and the PCS reset.
2408 * The actual disabling happens in qib_7322_mini_pci_reset(),
2409 * along with the PCS being reset.
2411 ppd
->cpspec
->ibcctrl_a
&= ~SYM_MASK(IBCCtrlA_0
, IBLinkEn
);
2412 qib_7322_mini_pcs_reset(ppd
);
2415 * Update the adjusted counters so the adjustment persists
2416 * across driver reload.
2418 if (ppd
->cpspec
->ibsymdelta
|| ppd
->cpspec
->iblnkerrdelta
||
2419 ppd
->cpspec
->ibdeltainprog
|| ppd
->cpspec
->iblnkdowndelta
) {
2420 struct qib_devdata
*dd
= ppd
->dd
;
2423 /* enable counter writes */
2424 diagc
= qib_read_kreg64(dd
, kr_hwdiagctrl
);
2425 qib_write_kreg(dd
, kr_hwdiagctrl
,
2426 diagc
| SYM_MASK(HwDiagCtrl
, CounterWrEnable
));
2428 if (ppd
->cpspec
->ibsymdelta
|| ppd
->cpspec
->ibdeltainprog
) {
2429 val
= read_7322_creg32_port(ppd
, crp_ibsymbolerr
);
2430 if (ppd
->cpspec
->ibdeltainprog
)
2431 val
-= val
- ppd
->cpspec
->ibsymsnap
;
2432 val
-= ppd
->cpspec
->ibsymdelta
;
2433 write_7322_creg_port(ppd
, crp_ibsymbolerr
, val
);
2435 if (ppd
->cpspec
->iblnkerrdelta
|| ppd
->cpspec
->ibdeltainprog
) {
2436 val
= read_7322_creg32_port(ppd
, crp_iblinkerrrecov
);
2437 if (ppd
->cpspec
->ibdeltainprog
)
2438 val
-= val
- ppd
->cpspec
->iblnkerrsnap
;
2439 val
-= ppd
->cpspec
->iblnkerrdelta
;
2440 write_7322_creg_port(ppd
, crp_iblinkerrrecov
, val
);
2442 if (ppd
->cpspec
->iblnkdowndelta
) {
2443 val
= read_7322_creg32_port(ppd
, crp_iblinkdown
);
2444 val
+= ppd
->cpspec
->iblnkdowndelta
;
2445 write_7322_creg_port(ppd
, crp_iblinkdown
, val
);
2448 * No need to save ibmalfdelta since IB perfcounters
2449 * are cleared on driver reload.
2452 /* and disable counter writes */
2453 qib_write_kreg(dd
, kr_hwdiagctrl
, diagc
);
2458 * qib_setup_7322_setextled - set the state of the two external LEDs
2459 * @ppd: physical port on the qlogic_ib device
2460 * @on: whether the link is up or not
2462 * The exact combo of LEDs if on is true is determined by looking
2465 * These LEDs indicate the physical and logical state of IB link.
2466 * For this chip (at least with recommended board pinouts), LED1
2467 * is Yellow (logical state) and LED2 is Green (physical state),
2469 * Note: We try to match the Mellanox HCA LED behavior as best
2470 * we can. Green indicates physical link state is OK (something is
2471 * plugged in, and we can train).
2472 * Amber indicates the link is logically up (ACTIVE).
2473 * Mellanox further blinks the amber LED to indicate data packet
2474 * activity, but we have no hardware support for that, so it would
2475 * require waking up every 10-20 msecs and checking the counters
2476 * on the chip, and then turning the LED off if appropriate. That's
2477 * visible overhead, so not something we will do.
2479 static void qib_setup_7322_setextled(struct qib_pportdata
*ppd
, u32 on
)
2481 struct qib_devdata
*dd
= ppd
->dd
;
2482 u64 extctl
, ledblink
= 0, val
;
2483 unsigned long flags
;
2487 * The diags use the LED to indicate diag info, so we leave
2488 * the external LED alone when the diags are running.
2490 if (dd
->diag_client
)
2493 /* Allow override of LED display for, e.g. Locating system in rack */
2494 if (ppd
->led_override
) {
2495 grn
= (ppd
->led_override
& QIB_LED_PHYS
);
2496 yel
= (ppd
->led_override
& QIB_LED_LOG
);
2498 val
= qib_read_kreg_port(ppd
, krp_ibcstatus_a
);
2499 grn
= qib_7322_phys_portstate(val
) ==
2500 IB_PHYSPORTSTATE_LINKUP
;
2501 yel
= qib_7322_iblink_state(val
) == IB_PORT_ACTIVE
;
2507 spin_lock_irqsave(&dd
->cspec
->gpio_lock
, flags
);
2508 extctl
= dd
->cspec
->extctrl
& (ppd
->port
== 1 ?
2509 ~ExtLED_IB1_MASK
: ~ExtLED_IB2_MASK
);
2511 extctl
|= ppd
->port
== 1 ? ExtLED_IB1_GRN
: ExtLED_IB2_GRN
;
2513 * Counts are in chip clock (4ns) periods.
2514 * This is 1/16 sec (66.6ms) on,
2515 * 3/16 sec (187.5 ms) off, with packets rcvd.
2517 ledblink
= ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT
) |
2518 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT
);
2521 extctl
|= ppd
->port
== 1 ? ExtLED_IB1_YEL
: ExtLED_IB2_YEL
;
2522 dd
->cspec
->extctrl
= extctl
;
2523 qib_write_kreg(dd
, kr_extctrl
, dd
->cspec
->extctrl
);
2524 spin_unlock_irqrestore(&dd
->cspec
->gpio_lock
, flags
);
2526 if (ledblink
) /* blink the LED on packet receive */
2527 qib_write_kreg_port(ppd
, krp_rcvpktledcnt
, ledblink
);
2531 * Disable MSIx interrupt if enabled, call generic MSIx code
2532 * to cleanup, and clear pending MSIx interrupts.
2533 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2535 static void qib_7322_nomsix(struct qib_devdata
*dd
)
2540 dd
->cspec
->main_int_mask
= ~0ULL;
2541 n
= dd
->cspec
->num_msix_entries
;
2545 dd
->cspec
->num_msix_entries
= 0;
2546 for (i
= 0; i
< n
; i
++)
2547 free_irq(dd
->cspec
->msix_entries
[i
].vector
,
2548 dd
->cspec
->msix_arg
[i
]);
2551 /* make sure no MSIx interrupts are left pending */
2552 intgranted
= qib_read_kreg64(dd
, kr_intgranted
);
2554 qib_write_kreg(dd
, kr_intgranted
, intgranted
);
2557 static void qib_7322_free_irq(struct qib_devdata
*dd
)
2559 if (dd
->cspec
->irq
) {
2560 free_irq(dd
->cspec
->irq
, dd
);
2563 qib_7322_nomsix(dd
);
2566 static void qib_setup_7322_cleanup(struct qib_devdata
*dd
)
2570 qib_7322_free_irq(dd
);
2571 kfree(dd
->cspec
->cntrs
);
2572 kfree(dd
->cspec
->sendchkenable
);
2573 kfree(dd
->cspec
->sendgrhchk
);
2574 kfree(dd
->cspec
->sendibchk
);
2575 kfree(dd
->cspec
->msix_entries
);
2576 kfree(dd
->cspec
->msix_arg
);
2577 for (i
= 0; i
< dd
->num_pports
; i
++) {
2578 unsigned long flags
;
2579 u32 mask
= QSFP_GPIO_MOD_PRS_N
|
2580 (QSFP_GPIO_MOD_PRS_N
<< QSFP_GPIO_PORT2_SHIFT
);
2582 kfree(dd
->pport
[i
].cpspec
->portcntrs
);
2583 if (dd
->flags
& QIB_HAS_QSFP
) {
2584 spin_lock_irqsave(&dd
->cspec
->gpio_lock
, flags
);
2585 dd
->cspec
->gpio_mask
&= ~mask
;
2586 qib_write_kreg(dd
, kr_gpio_mask
, dd
->cspec
->gpio_mask
);
2587 spin_unlock_irqrestore(&dd
->cspec
->gpio_lock
, flags
);
2588 qib_qsfp_deinit(&dd
->pport
[i
].cpspec
->qsfp_data
);
2590 if (dd
->pport
[i
].ibport_data
.smi_ah
)
2591 ib_destroy_ah(&dd
->pport
[i
].ibport_data
.smi_ah
->ibah
);
2595 /* handle SDMA interrupts */
2596 static void sdma_7322_intr(struct qib_devdata
*dd
, u64 istat
)
2598 struct qib_pportdata
*ppd0
= &dd
->pport
[0];
2599 struct qib_pportdata
*ppd1
= &dd
->pport
[1];
2600 u64 intr0
= istat
& (INT_MASK_P(SDma
, 0) |
2601 INT_MASK_P(SDmaIdle
, 0) | INT_MASK_P(SDmaProgress
, 0));
2602 u64 intr1
= istat
& (INT_MASK_P(SDma
, 1) |
2603 INT_MASK_P(SDmaIdle
, 1) | INT_MASK_P(SDmaProgress
, 1));
2606 qib_sdma_intr(ppd0
);
2608 qib_sdma_intr(ppd1
);
2610 if (istat
& INT_MASK_PM(SDmaCleanupDone
, 0))
2611 qib_sdma_process_event(ppd0
, qib_sdma_event_e20_hw_started
);
2612 if (istat
& INT_MASK_PM(SDmaCleanupDone
, 1))
2613 qib_sdma_process_event(ppd1
, qib_sdma_event_e20_hw_started
);
2617 * Set or clear the Send buffer available interrupt enable bit.
2619 static void qib_wantpiobuf_7322_intr(struct qib_devdata
*dd
, u32 needint
)
2621 unsigned long flags
;
2623 spin_lock_irqsave(&dd
->sendctrl_lock
, flags
);
2625 dd
->sendctrl
|= SYM_MASK(SendCtrl
, SendIntBufAvail
);
2627 dd
->sendctrl
&= ~SYM_MASK(SendCtrl
, SendIntBufAvail
);
2628 qib_write_kreg(dd
, kr_sendctrl
, dd
->sendctrl
);
2629 qib_write_kreg(dd
, kr_scratch
, 0ULL);
2630 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
2634 * Somehow got an interrupt with reserved bits set in interrupt status.
2635 * Print a message so we know it happened, then clear them.
2636 * keep mainline interrupt handler cache-friendly
2638 static noinline
void unknown_7322_ibits(struct qib_devdata
*dd
, u64 istat
)
2643 kills
= istat
& ~QIB_I_BITSEXTANT
;
2644 qib_dev_err(dd
, "Clearing reserved interrupt(s) 0x%016llx:"
2645 " %s\n", (unsigned long long) kills
, msg
);
2646 qib_write_kreg(dd
, kr_intmask
, (dd
->cspec
->int_enable_mask
& ~kills
));
2649 /* keep mainline interrupt handler cache-friendly */
2650 static noinline
void unknown_7322_gpio_intr(struct qib_devdata
*dd
)
2657 * Boards for this chip currently don't use GPIO interrupts,
2658 * so clear by writing GPIOstatus to GPIOclear, and complain
2659 * to developer. To avoid endless repeats, clear
2660 * the bits in the mask, since there is some kind of
2661 * programming error or chip problem.
2663 gpiostatus
= qib_read_kreg32(dd
, kr_gpio_status
);
2665 * In theory, writing GPIOstatus to GPIOclear could
2666 * have a bad side-effect on some diagnostic that wanted
2667 * to poll for a status-change, but the various shadows
2668 * make that problematic at best. Diags will just suppress
2669 * all GPIO interrupts during such tests.
2671 qib_write_kreg(dd
, kr_gpio_clear
, gpiostatus
);
2673 * Check for QSFP MOD_PRS changes
2674 * only works for single port if IB1 != pidx1
2676 for (pidx
= 0; pidx
< dd
->num_pports
&& (dd
->flags
& QIB_HAS_QSFP
);
2678 struct qib_pportdata
*ppd
;
2679 struct qib_qsfp_data
*qd
;
2681 if (!dd
->pport
[pidx
].link_speed_supported
)
2683 mask
= QSFP_GPIO_MOD_PRS_N
;
2684 ppd
= dd
->pport
+ pidx
;
2685 mask
<<= (QSFP_GPIO_PORT2_SHIFT
* ppd
->hw_pidx
);
2686 if (gpiostatus
& dd
->cspec
->gpio_mask
& mask
) {
2688 qd
= &ppd
->cpspec
->qsfp_data
;
2689 gpiostatus
&= ~mask
;
2690 pins
= qib_read_kreg64(dd
, kr_extstatus
);
2691 pins
>>= SYM_LSB(EXTStatus
, GPIOIn
);
2692 if (!(pins
& mask
)) {
2694 qd
->t_insert
= get_jiffies_64();
2695 queue_work(ib_wq
, &qd
->work
);
2700 if (gpiostatus
&& !handled
) {
2701 const u32 mask
= qib_read_kreg32(dd
, kr_gpio_mask
);
2702 u32 gpio_irq
= mask
& gpiostatus
;
2705 * Clear any troublemakers, and update chip from shadow
2707 dd
->cspec
->gpio_mask
&= ~gpio_irq
;
2708 qib_write_kreg(dd
, kr_gpio_mask
, dd
->cspec
->gpio_mask
);
2713 * Handle errors and unusual events first, separate function
2714 * to improve cache hits for fast path interrupt handling.
2716 static noinline
void unlikely_7322_intr(struct qib_devdata
*dd
, u64 istat
)
2718 if (istat
& ~QIB_I_BITSEXTANT
)
2719 unknown_7322_ibits(dd
, istat
);
2720 if (istat
& QIB_I_GPIO
)
2721 unknown_7322_gpio_intr(dd
);
2722 if (istat
& QIB_I_C_ERROR
)
2723 handle_7322_errors(dd
);
2724 if (istat
& INT_MASK_P(Err
, 0) && dd
->rcd
[0])
2725 handle_7322_p_errors(dd
->rcd
[0]->ppd
);
2726 if (istat
& INT_MASK_P(Err
, 1) && dd
->rcd
[1])
2727 handle_7322_p_errors(dd
->rcd
[1]->ppd
);
2731 * Dynamically adjust the rcv int timeout for a context based on incoming
2734 static void adjust_rcv_timeout(struct qib_ctxtdata
*rcd
, int npkts
)
2736 struct qib_devdata
*dd
= rcd
->dd
;
2737 u32 timeout
= dd
->cspec
->rcvavail_timeout
[rcd
->ctxt
];
2740 * Dynamically adjust idle timeout on chip
2741 * based on number of packets processed.
2743 if (npkts
< rcv_int_count
&& timeout
> 2)
2745 else if (npkts
>= rcv_int_count
&& timeout
< rcv_int_timeout
)
2746 timeout
= min(timeout
<< 1, rcv_int_timeout
);
2750 dd
->cspec
->rcvavail_timeout
[rcd
->ctxt
] = timeout
;
2751 qib_write_kreg(dd
, kr_rcvavailtimeout
+ rcd
->ctxt
, timeout
);
2755 * This is the main interrupt handler.
2756 * It will normally only be used for low frequency interrupts but may
2757 * have to handle all interrupts if INTx is enabled or fewer than normal
2758 * MSIx interrupts were allocated.
2759 * This routine should ignore the interrupt bits for any of the
2760 * dedicated MSIx handlers.
2762 static irqreturn_t
qib_7322intr(int irq
, void *data
)
2764 struct qib_devdata
*dd
= data
;
2772 if ((dd
->flags
& (QIB_PRESENT
| QIB_BADINTR
)) != QIB_PRESENT
) {
2774 * This return value is not great, but we do not want the
2775 * interrupt core code to remove our interrupt handler
2776 * because we don't appear to be handling an interrupt
2777 * during a chip reset.
2783 istat
= qib_read_kreg64(dd
, kr_intstatus
);
2785 if (unlikely(istat
== ~0ULL)) {
2786 qib_bad_intrstatus(dd
);
2787 qib_dev_err(dd
, "Interrupt status all f's, skipping\n");
2788 /* don't know if it was our interrupt or not */
2793 istat
&= dd
->cspec
->main_int_mask
;
2794 if (unlikely(!istat
)) {
2795 /* already handled, or shared and not us */
2800 qib_stats
.sps_ints
++;
2801 if (dd
->int_counter
!= (u32
) -1)
2804 /* handle "errors" of various kinds first, device ahead of port */
2805 if (unlikely(istat
& (~QIB_I_BITSEXTANT
| QIB_I_GPIO
|
2806 QIB_I_C_ERROR
| INT_MASK_P(Err
, 0) |
2807 INT_MASK_P(Err
, 1))))
2808 unlikely_7322_intr(dd
, istat
);
2811 * Clear the interrupt bits we found set, relatively early, so we
2812 * "know" know the chip will have seen this by the time we process
2813 * the queue, and will re-interrupt if necessary. The processor
2814 * itself won't take the interrupt again until we return.
2816 qib_write_kreg(dd
, kr_intclear
, istat
);
2819 * Handle kernel receive queues before checking for pio buffers
2820 * available since receives can overflow; piobuf waiters can afford
2821 * a few extra cycles, since they were waiting anyway.
2823 ctxtrbits
= istat
& (QIB_I_RCVAVAIL_MASK
| QIB_I_RCVURG_MASK
);
2825 rmask
= (1ULL << QIB_I_RCVAVAIL_LSB
) |
2826 (1ULL << QIB_I_RCVURG_LSB
);
2827 for (i
= 0; i
< dd
->first_user_ctxt
; i
++) {
2828 if (ctxtrbits
& rmask
) {
2829 ctxtrbits
&= ~rmask
;
2831 qib_kreceive(dd
->rcd
[i
], NULL
, &npkts
);
2837 ctxtrbits
= (ctxtrbits
>> QIB_I_RCVAVAIL_LSB
) |
2838 (ctxtrbits
>> QIB_I_RCVURG_LSB
);
2839 qib_handle_urcv(dd
, ctxtrbits
);
2843 if (istat
& (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
2844 sdma_7322_intr(dd
, istat
);
2846 if ((istat
& QIB_I_SPIOBUFAVAIL
) && (dd
->flags
& QIB_INITTED
))
2847 qib_ib_piobufavail(dd
);
2855 * Dedicated receive packet available interrupt handler.
2857 static irqreturn_t
qib_7322pintr(int irq
, void *data
)
2859 struct qib_ctxtdata
*rcd
= data
;
2860 struct qib_devdata
*dd
= rcd
->dd
;
2863 if ((dd
->flags
& (QIB_PRESENT
| QIB_BADINTR
)) != QIB_PRESENT
)
2865 * This return value is not great, but we do not want the
2866 * interrupt core code to remove our interrupt handler
2867 * because we don't appear to be handling an interrupt
2868 * during a chip reset.
2872 qib_stats
.sps_ints
++;
2873 if (dd
->int_counter
!= (u32
) -1)
2876 /* Clear the interrupt bit we expect to be set. */
2877 qib_write_kreg(dd
, kr_intclear
, ((1ULL << QIB_I_RCVAVAIL_LSB
) |
2878 (1ULL << QIB_I_RCVURG_LSB
)) << rcd
->ctxt
);
2880 qib_kreceive(rcd
, NULL
, &npkts
);
2886 * Dedicated Send buffer available interrupt handler.
2888 static irqreturn_t
qib_7322bufavail(int irq
, void *data
)
2890 struct qib_devdata
*dd
= data
;
2892 if ((dd
->flags
& (QIB_PRESENT
| QIB_BADINTR
)) != QIB_PRESENT
)
2894 * This return value is not great, but we do not want the
2895 * interrupt core code to remove our interrupt handler
2896 * because we don't appear to be handling an interrupt
2897 * during a chip reset.
2901 qib_stats
.sps_ints
++;
2902 if (dd
->int_counter
!= (u32
) -1)
2905 /* Clear the interrupt bit we expect to be set. */
2906 qib_write_kreg(dd
, kr_intclear
, QIB_I_SPIOBUFAVAIL
);
2908 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
2909 if (dd
->flags
& QIB_INITTED
)
2910 qib_ib_piobufavail(dd
);
2912 qib_wantpiobuf_7322_intr(dd
, 0);
2918 * Dedicated Send DMA interrupt handler.
2920 static irqreturn_t
sdma_intr(int irq
, void *data
)
2922 struct qib_pportdata
*ppd
= data
;
2923 struct qib_devdata
*dd
= ppd
->dd
;
2925 if ((dd
->flags
& (QIB_PRESENT
| QIB_BADINTR
)) != QIB_PRESENT
)
2927 * This return value is not great, but we do not want the
2928 * interrupt core code to remove our interrupt handler
2929 * because we don't appear to be handling an interrupt
2930 * during a chip reset.
2934 qib_stats
.sps_ints
++;
2935 if (dd
->int_counter
!= (u32
) -1)
2938 /* Clear the interrupt bit we expect to be set. */
2939 qib_write_kreg(dd
, kr_intclear
, ppd
->hw_pidx
?
2940 INT_MASK_P(SDma
, 1) : INT_MASK_P(SDma
, 0));
2947 * Dedicated Send DMA idle interrupt handler.
2949 static irqreturn_t
sdma_idle_intr(int irq
, void *data
)
2951 struct qib_pportdata
*ppd
= data
;
2952 struct qib_devdata
*dd
= ppd
->dd
;
2954 if ((dd
->flags
& (QIB_PRESENT
| QIB_BADINTR
)) != QIB_PRESENT
)
2956 * This return value is not great, but we do not want the
2957 * interrupt core code to remove our interrupt handler
2958 * because we don't appear to be handling an interrupt
2959 * during a chip reset.
2963 qib_stats
.sps_ints
++;
2964 if (dd
->int_counter
!= (u32
) -1)
2967 /* Clear the interrupt bit we expect to be set. */
2968 qib_write_kreg(dd
, kr_intclear
, ppd
->hw_pidx
?
2969 INT_MASK_P(SDmaIdle
, 1) : INT_MASK_P(SDmaIdle
, 0));
2976 * Dedicated Send DMA progress interrupt handler.
2978 static irqreturn_t
sdma_progress_intr(int irq
, void *data
)
2980 struct qib_pportdata
*ppd
= data
;
2981 struct qib_devdata
*dd
= ppd
->dd
;
2983 if ((dd
->flags
& (QIB_PRESENT
| QIB_BADINTR
)) != QIB_PRESENT
)
2985 * This return value is not great, but we do not want the
2986 * interrupt core code to remove our interrupt handler
2987 * because we don't appear to be handling an interrupt
2988 * during a chip reset.
2992 qib_stats
.sps_ints
++;
2993 if (dd
->int_counter
!= (u32
) -1)
2996 /* Clear the interrupt bit we expect to be set. */
2997 qib_write_kreg(dd
, kr_intclear
, ppd
->hw_pidx
?
2998 INT_MASK_P(SDmaProgress
, 1) :
2999 INT_MASK_P(SDmaProgress
, 0));
3006 * Dedicated Send DMA cleanup interrupt handler.
3008 static irqreturn_t
sdma_cleanup_intr(int irq
, void *data
)
3010 struct qib_pportdata
*ppd
= data
;
3011 struct qib_devdata
*dd
= ppd
->dd
;
3013 if ((dd
->flags
& (QIB_PRESENT
| QIB_BADINTR
)) != QIB_PRESENT
)
3015 * This return value is not great, but we do not want the
3016 * interrupt core code to remove our interrupt handler
3017 * because we don't appear to be handling an interrupt
3018 * during a chip reset.
3022 qib_stats
.sps_ints
++;
3023 if (dd
->int_counter
!= (u32
) -1)
3026 /* Clear the interrupt bit we expect to be set. */
3027 qib_write_kreg(dd
, kr_intclear
, ppd
->hw_pidx
?
3028 INT_MASK_PM(SDmaCleanupDone
, 1) :
3029 INT_MASK_PM(SDmaCleanupDone
, 0));
3030 qib_sdma_process_event(ppd
, qib_sdma_event_e20_hw_started
);
3036 * Set up our chip-specific interrupt handler.
3037 * The interrupt type has already been setup, so
3038 * we just need to do the registration and error checking.
3039 * If we are using MSIx interrupts, we may fall back to
3040 * INTx later, if the interrupt handler doesn't get called
3041 * within 1/2 second (see verify_interrupt()).
3043 static void qib_setup_7322_interrupt(struct qib_devdata
*dd
, int clearpend
)
3045 int ret
, i
, msixnum
;
3049 if (!dd
->num_pports
)
3054 * if not switching interrupt types, be sure interrupts are
3055 * disabled, and then clear anything pending at this point,
3056 * because we are starting clean.
3058 qib_7322_set_intr_state(dd
, 0);
3060 /* clear the reset error, init error/hwerror mask */
3061 qib_7322_init_hwerrors(dd
);
3063 /* clear any interrupt bits that might be set */
3064 qib_write_kreg(dd
, kr_intclear
, ~0ULL);
3066 /* make sure no pending MSIx intr, and clear diag reg */
3067 qib_write_kreg(dd
, kr_intgranted
, ~0ULL);
3068 qib_write_kreg(dd
, kr_vecclr_wo_int
, ~0ULL);
3071 if (!dd
->cspec
->num_msix_entries
) {
3072 /* Try to get INTx interrupt */
3074 if (!dd
->pcidev
->irq
) {
3075 qib_dev_err(dd
, "irq is 0, BIOS error? "
3076 "Interrupts won't work\n");
3079 ret
= request_irq(dd
->pcidev
->irq
, qib_7322intr
,
3080 IRQF_SHARED
, QIB_DRV_NAME
, dd
);
3082 qib_dev_err(dd
, "Couldn't setup INTx "
3083 "interrupt (irq=%d): %d\n",
3084 dd
->pcidev
->irq
, ret
);
3087 dd
->cspec
->irq
= dd
->pcidev
->irq
;
3088 dd
->cspec
->main_int_mask
= ~0ULL;
3092 /* Try to get MSIx interrupts */
3093 memset(redirect
, 0, sizeof redirect
);
3096 for (i
= 0; msixnum
< dd
->cspec
->num_msix_entries
; i
++) {
3097 irq_handler_t handler
;
3103 if (i
< ARRAY_SIZE(irq_table
)) {
3104 if (irq_table
[i
].port
) {
3105 /* skip if for a non-configured port */
3106 if (irq_table
[i
].port
> dd
->num_pports
)
3108 arg
= dd
->pport
+ irq_table
[i
].port
- 1;
3111 lsb
= irq_table
[i
].lsb
;
3112 handler
= irq_table
[i
].handler
;
3113 name
= irq_table
[i
].name
;
3117 ctxt
= i
- ARRAY_SIZE(irq_table
);
3118 /* per krcvq context receive interrupt */
3119 arg
= dd
->rcd
[ctxt
];
3122 lsb
= QIB_I_RCVAVAIL_LSB
+ ctxt
;
3123 handler
= qib_7322pintr
;
3124 name
= QIB_DRV_NAME
" (kctx)";
3126 ret
= request_irq(dd
->cspec
->msix_entries
[msixnum
].vector
,
3127 handler
, 0, name
, arg
);
3130 * Shouldn't happen since the enable said we could
3131 * have as many as we are trying to setup here.
3133 qib_dev_err(dd
, "Couldn't setup MSIx "
3134 "interrupt (vec=%d, irq=%d): %d\n", msixnum
,
3135 dd
->cspec
->msix_entries
[msixnum
].vector
,
3137 qib_7322_nomsix(dd
);
3140 dd
->cspec
->msix_arg
[msixnum
] = arg
;
3142 reg
= lsb
/ IBA7322_REDIRECT_VEC_PER_REG
;
3143 sh
= (lsb
% IBA7322_REDIRECT_VEC_PER_REG
) *
3144 SYM_LSB(IntRedirect0
, vec1
);
3145 mask
&= ~(1ULL << lsb
);
3146 redirect
[reg
] |= ((u64
) msixnum
) << sh
;
3148 val
= qib_read_kreg64(dd
, 2 * msixnum
+ 1 +
3149 (QIB_7322_MsixTable_OFFS
/ sizeof(u64
)));
3152 /* Initialize the vector mapping */
3153 for (i
= 0; i
< ARRAY_SIZE(redirect
); i
++)
3154 qib_write_kreg(dd
, kr_intredirect
+ i
, redirect
[i
]);
3155 dd
->cspec
->main_int_mask
= mask
;
3160 * qib_7322_boardname - fill in the board name and note features
3161 * @dd: the qlogic_ib device
3163 * info will be based on the board revision register
3165 static unsigned qib_7322_boardname(struct qib_devdata
*dd
)
3167 /* Will need enumeration of board-types here */
3169 u32 boardid
, namelen
;
3170 unsigned features
= DUAL_PORT_CAP
;
3172 boardid
= SYM_FIELD(dd
->revision
, Revision
, BoardID
);
3176 n
= "InfiniPath_QLE7342_Emulation";
3179 n
= "InfiniPath_QLE7340";
3180 dd
->flags
|= QIB_HAS_QSFP
;
3181 features
= PORT_SPD_CAP
;
3184 n
= "InfiniPath_QLE7342";
3185 dd
->flags
|= QIB_HAS_QSFP
;
3188 n
= "InfiniPath_QMI7342";
3191 n
= "InfiniPath_Unsupported7342";
3192 qib_dev_err(dd
, "Unsupported version of QMH7342\n");
3196 n
= "InfiniPath_QMH7342";
3200 n
= "InfiniPath_QME7342";
3203 n
= "InfiniPath_QME7362";
3204 dd
->flags
|= QIB_HAS_QSFP
;
3207 n
= "InfiniPath_QLE7342_TEST";
3208 dd
->flags
|= QIB_HAS_QSFP
;
3211 n
= "InfiniPath_QLE73xy_UNKNOWN";
3212 qib_dev_err(dd
, "Unknown 7322 board type %u\n", boardid
);
3215 dd
->board_atten
= 1; /* index into txdds_Xdr */
3217 namelen
= strlen(n
) + 1;
3218 dd
->boardname
= kmalloc(namelen
, GFP_KERNEL
);
3220 qib_dev_err(dd
, "Failed allocation for board name: %s\n", n
);
3222 snprintf(dd
->boardname
, namelen
, "%s", n
);
3224 snprintf(dd
->boardversion
, sizeof(dd
->boardversion
),
3225 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3226 QIB_CHIP_VERS_MAJ
, QIB_CHIP_VERS_MIN
, dd
->boardname
,
3227 (unsigned)SYM_FIELD(dd
->revision
, Revision_R
, Arch
),
3228 dd
->majrev
, dd
->minrev
,
3229 (unsigned)SYM_FIELD(dd
->revision
, Revision_R
, SW
));
3231 if (qib_singleport
&& (features
>> PORT_SPD_CAP_SHIFT
) & PORT_SPD_CAP
) {
3232 qib_devinfo(dd
->pcidev
, "IB%u: Forced to single port mode"
3233 " by module parameter\n", dd
->unit
);
3234 features
&= PORT_SPD_CAP
;
3241 * This routine sleeps, so it can only be called from user context, not
3242 * from interrupt context.
3244 static int qib_do_7322_reset(struct qib_devdata
*dd
)
3248 int i
, msix_entries
, ret
= 1;
3250 u8 int_line
, clinesz
;
3251 unsigned long flags
;
3253 /* Use dev_err so it shows up in logs, etc. */
3254 qib_dev_err(dd
, "Resetting InfiniPath unit %u\n", dd
->unit
);
3256 qib_pcie_getcmd(dd
, &cmdval
, &int_line
, &clinesz
);
3258 msix_entries
= dd
->cspec
->num_msix_entries
;
3260 /* no interrupts till re-initted */
3261 qib_7322_set_intr_state(dd
, 0);
3264 qib_7322_nomsix(dd
);
3265 /* can be up to 512 bytes, too big for stack */
3266 msix_vecsave
= kmalloc(2 * dd
->cspec
->num_msix_entries
*
3267 sizeof(u64
), GFP_KERNEL
);
3269 qib_dev_err(dd
, "No mem to save MSIx data\n");
3271 msix_vecsave
= NULL
;
3274 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3275 * info that is set up by the BIOS, so we have to save and restore
3276 * it ourselves. There is some risk something could change it,
3277 * after we save it, but since we have disabled the MSIx, it
3278 * shouldn't be touched...
3280 for (i
= 0; i
< msix_entries
; i
++) {
3281 u64 vecaddr
, vecdata
;
3282 vecaddr
= qib_read_kreg64(dd
, 2 * i
+
3283 (QIB_7322_MsixTable_OFFS
/ sizeof(u64
)));
3284 vecdata
= qib_read_kreg64(dd
, 1 + 2 * i
+
3285 (QIB_7322_MsixTable_OFFS
/ sizeof(u64
)));
3287 msix_vecsave
[2 * i
] = vecaddr
;
3288 /* save it without the masked bit set */
3289 msix_vecsave
[1 + 2 * i
] = vecdata
& ~0x100000000ULL
;
3293 dd
->pport
->cpspec
->ibdeltainprog
= 0;
3294 dd
->pport
->cpspec
->ibsymdelta
= 0;
3295 dd
->pport
->cpspec
->iblnkerrdelta
= 0;
3296 dd
->pport
->cpspec
->ibmalfdelta
= 0;
3297 dd
->int_counter
= 0; /* so we check interrupts work again */
3300 * Keep chip from being accessed until we are ready. Use
3301 * writeq() directly, to allow the write even though QIB_PRESENT
3304 dd
->flags
&= ~(QIB_INITTED
| QIB_PRESENT
| QIB_BADINTR
);
3305 dd
->flags
|= QIB_DOING_RESET
;
3306 val
= dd
->control
| QLOGIC_IB_C_RESET
;
3307 writeq(val
, &dd
->kregbase
[kr_control
]);
3309 for (i
= 1; i
<= 5; i
++) {
3311 * Allow MBIST, etc. to complete; longer on each retry.
3312 * We sometimes get machine checks from bus timeout if no
3313 * response, so for now, make it *really* long.
3315 msleep(1000 + (1 + i
) * 3000);
3317 qib_pcie_reenable(dd
, cmdval
, int_line
, clinesz
);
3320 * Use readq directly, so we don't need to mark it as PRESENT
3321 * until we get a successful indication that all is well.
3323 val
= readq(&dd
->kregbase
[kr_revision
]);
3324 if (val
== dd
->revision
)
3327 qib_dev_err(dd
, "Failed to initialize after reset, "
3334 dd
->flags
|= QIB_PRESENT
; /* it's back */
3337 /* restore the MSIx vector address and data if saved above */
3338 for (i
= 0; i
< msix_entries
; i
++) {
3339 dd
->cspec
->msix_entries
[i
].entry
= i
;
3340 if (!msix_vecsave
|| !msix_vecsave
[2 * i
])
3342 qib_write_kreg(dd
, 2 * i
+
3343 (QIB_7322_MsixTable_OFFS
/ sizeof(u64
)),
3344 msix_vecsave
[2 * i
]);
3345 qib_write_kreg(dd
, 1 + 2 * i
+
3346 (QIB_7322_MsixTable_OFFS
/ sizeof(u64
)),
3347 msix_vecsave
[1 + 2 * i
]);
3351 /* initialize the remaining registers. */
3352 for (i
= 0; i
< dd
->num_pports
; ++i
)
3353 write_7322_init_portregs(&dd
->pport
[i
]);
3354 write_7322_initregs(dd
);
3356 if (qib_pcie_params(dd
, dd
->lbus_width
,
3357 &dd
->cspec
->num_msix_entries
,
3358 dd
->cspec
->msix_entries
))
3359 qib_dev_err(dd
, "Reset failed to setup PCIe or interrupts; "
3360 "continuing anyway\n");
3362 qib_setup_7322_interrupt(dd
, 1);
3364 for (i
= 0; i
< dd
->num_pports
; ++i
) {
3365 struct qib_pportdata
*ppd
= &dd
->pport
[i
];
3367 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
3368 ppd
->lflags
|= QIBL_IB_FORCE_NOTIFY
;
3369 ppd
->lflags
&= ~QIBL_IB_AUTONEG_FAILED
;
3370 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
3374 dd
->flags
&= ~QIB_DOING_RESET
; /* OK or not, no longer resetting */
3375 kfree(msix_vecsave
);
3380 * qib_7322_put_tid - write a TID to the chip
3381 * @dd: the qlogic_ib device
3382 * @tidptr: pointer to the expected TID (in chip) to update
3383 * @tidtype: 0 for eager, 1 for expected
3384 * @pa: physical address of in memory buffer; tidinvalid if freeing
3386 static void qib_7322_put_tid(struct qib_devdata
*dd
, u64 __iomem
*tidptr
,
3387 u32 type
, unsigned long pa
)
3389 if (!(dd
->flags
& QIB_PRESENT
))
3391 if (pa
!= dd
->tidinvalid
) {
3392 u64 chippa
= pa
>> IBA7322_TID_PA_SHIFT
;
3394 /* paranoia checks */
3395 if (pa
!= (chippa
<< IBA7322_TID_PA_SHIFT
)) {
3396 qib_dev_err(dd
, "Physaddr %lx not 2KB aligned!\n",
3400 if (chippa
>= (1UL << IBA7322_TID_SZ_SHIFT
)) {
3401 qib_dev_err(dd
, "Physical page address 0x%lx "
3402 "larger than supported\n", pa
);
3406 if (type
== RCVHQ_RCV_TYPE_EAGER
)
3407 chippa
|= dd
->tidtemplate
;
3408 else /* for now, always full 4KB page */
3409 chippa
|= IBA7322_TID_SZ_4K
;
3417 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3418 * @dd: the qlogic_ib device
3421 * clear all TID entries for a ctxt, expected and eager.
3422 * Used from qib_close().
3424 static void qib_7322_clear_tids(struct qib_devdata
*dd
,
3425 struct qib_ctxtdata
*rcd
)
3427 u64 __iomem
*tidbase
;
3428 unsigned long tidinv
;
3432 if (!dd
->kregbase
|| !rcd
)
3437 tidinv
= dd
->tidinvalid
;
3438 tidbase
= (u64 __iomem
*)
3439 ((char __iomem
*) dd
->kregbase
+
3441 ctxt
* dd
->rcvtidcnt
* sizeof(*tidbase
));
3443 for (i
= 0; i
< dd
->rcvtidcnt
; i
++)
3444 qib_7322_put_tid(dd
, &tidbase
[i
], RCVHQ_RCV_TYPE_EXPECTED
,
3447 tidbase
= (u64 __iomem
*)
3448 ((char __iomem
*) dd
->kregbase
+
3450 rcd
->rcvegr_tid_base
* sizeof(*tidbase
));
3452 for (i
= 0; i
< rcd
->rcvegrcnt
; i
++)
3453 qib_7322_put_tid(dd
, &tidbase
[i
], RCVHQ_RCV_TYPE_EAGER
,
3458 * qib_7322_tidtemplate - setup constants for TID updates
3459 * @dd: the qlogic_ib device
3461 * We setup stuff that we use a lot, to avoid calculating each time
3463 static void qib_7322_tidtemplate(struct qib_devdata
*dd
)
3466 * For now, we always allocate 4KB buffers (at init) so we can
3467 * receive max size packets. We may want a module parameter to
3468 * specify 2KB or 4KB and/or make it per port instead of per device
3469 * for those who want to reduce memory footprint. Note that the
3470 * rcvhdrentsize size must be large enough to hold the largest
3471 * IB header (currently 96 bytes) that we expect to handle (plus of
3472 * course the 2 dwords of RHF).
3474 if (dd
->rcvegrbufsize
== 2048)
3475 dd
->tidtemplate
= IBA7322_TID_SZ_2K
;
3476 else if (dd
->rcvegrbufsize
== 4096)
3477 dd
->tidtemplate
= IBA7322_TID_SZ_4K
;
3482 * qib_init_7322_get_base_info - set chip-specific flags for user code
3483 * @rcd: the qlogic_ib ctxt
3484 * @kbase: qib_base_info pointer
3486 * We set the PCIE flag because the lower bandwidth on PCIe vs
3487 * HyperTransport can affect some user packet algorithims.
3490 static int qib_7322_get_base_info(struct qib_ctxtdata
*rcd
,
3491 struct qib_base_info
*kinfo
)
3493 kinfo
->spi_runtime_flags
|= QIB_RUNTIME_CTXT_MSB_IN_QP
|
3494 QIB_RUNTIME_PCIE
| QIB_RUNTIME_NODMA_RTAIL
|
3495 QIB_RUNTIME_HDRSUPP
| QIB_RUNTIME_SDMA
;
3496 if (rcd
->dd
->cspec
->r1
)
3497 kinfo
->spi_runtime_flags
|= QIB_RUNTIME_RCHK
;
3498 if (rcd
->dd
->flags
& QIB_USE_SPCL_TRIG
)
3499 kinfo
->spi_runtime_flags
|= QIB_RUNTIME_SPECIAL_TRIGGER
;
3504 static struct qib_message_header
*
3505 qib_7322_get_msgheader(struct qib_devdata
*dd
, __le32
*rhf_addr
)
3507 u32 offset
= qib_hdrget_offset(rhf_addr
);
3509 return (struct qib_message_header
*)
3510 (rhf_addr
- dd
->rhf_offset
+ offset
);
3514 * Configure number of contexts.
3516 static void qib_7322_config_ctxts(struct qib_devdata
*dd
)
3518 unsigned long flags
;
3521 nchipctxts
= qib_read_kreg32(dd
, kr_contextcnt
);
3522 dd
->cspec
->numctxts
= nchipctxts
;
3523 if (qib_n_krcv_queues
> 1 && dd
->num_pports
) {
3524 dd
->first_user_ctxt
= NUM_IB_PORTS
+
3525 (qib_n_krcv_queues
- 1) * dd
->num_pports
;
3526 if (dd
->first_user_ctxt
> nchipctxts
)
3527 dd
->first_user_ctxt
= nchipctxts
;
3528 dd
->n_krcv_queues
= dd
->first_user_ctxt
/ dd
->num_pports
;
3530 dd
->first_user_ctxt
= NUM_IB_PORTS
;
3531 dd
->n_krcv_queues
= 1;
3534 if (!qib_cfgctxts
) {
3535 int nctxts
= dd
->first_user_ctxt
+ num_online_cpus();
3539 else if (nctxts
<= 10)
3541 else if (nctxts
<= nchipctxts
)
3542 dd
->ctxtcnt
= nchipctxts
;
3543 } else if (qib_cfgctxts
< dd
->num_pports
)
3544 dd
->ctxtcnt
= dd
->num_pports
;
3545 else if (qib_cfgctxts
<= nchipctxts
)
3546 dd
->ctxtcnt
= qib_cfgctxts
;
3547 if (!dd
->ctxtcnt
) /* none of the above, set to max */
3548 dd
->ctxtcnt
= nchipctxts
;
3551 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3552 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3553 * Lock to be paranoid about later motion, etc.
3555 spin_lock_irqsave(&dd
->cspec
->rcvmod_lock
, flags
);
3556 if (dd
->ctxtcnt
> 10)
3557 dd
->rcvctrl
|= 2ULL << SYM_LSB(RcvCtrl
, ContextCfg
);
3558 else if (dd
->ctxtcnt
> 6)
3559 dd
->rcvctrl
|= 1ULL << SYM_LSB(RcvCtrl
, ContextCfg
);
3560 /* else configure for default 6 receive ctxts */
3562 /* The XRC opcode is 5. */
3563 dd
->rcvctrl
|= 5ULL << SYM_LSB(RcvCtrl
, XrcTypeCode
);
3566 * RcvCtrl *must* be written here so that the
3567 * chip understands how to change rcvegrcnt below.
3569 qib_write_kreg(dd
, kr_rcvctrl
, dd
->rcvctrl
);
3570 spin_unlock_irqrestore(&dd
->cspec
->rcvmod_lock
, flags
);
3572 /* kr_rcvegrcnt changes based on the number of contexts enabled */
3573 dd
->cspec
->rcvegrcnt
= qib_read_kreg32(dd
, kr_rcvegrcnt
);
3575 dd
->rcvhdrcnt
= max(dd
->cspec
->rcvegrcnt
, qib_rcvhdrcnt
);
3577 dd
->rcvhdrcnt
= max(dd
->cspec
->rcvegrcnt
,
3578 dd
->num_pports
> 1 ? 1024U : 2048U);
3581 static int qib_7322_get_ib_cfg(struct qib_pportdata
*ppd
, int which
)
3585 u64 maskr
; /* right-justified mask */
3589 case QIB_IB_CFG_LWID_ENB
: /* Get allowed Link-width */
3590 ret
= ppd
->link_width_enabled
;
3593 case QIB_IB_CFG_LWID
: /* Get currently active Link-width */
3594 ret
= ppd
->link_width_active
;
3597 case QIB_IB_CFG_SPD_ENB
: /* Get allowed Link speeds */
3598 ret
= ppd
->link_speed_enabled
;
3601 case QIB_IB_CFG_SPD
: /* Get current Link spd */
3602 ret
= ppd
->link_speed_active
;
3605 case QIB_IB_CFG_RXPOL_ENB
: /* Get Auto-RX-polarity enable */
3606 lsb
= SYM_LSB(IBCCtrlB_0
, IB_POLARITY_REV_SUPP
);
3607 maskr
= SYM_RMASK(IBCCtrlB_0
, IB_POLARITY_REV_SUPP
);
3610 case QIB_IB_CFG_LREV_ENB
: /* Get Auto-Lane-reversal enable */
3611 lsb
= SYM_LSB(IBCCtrlB_0
, IB_LANE_REV_SUPPORTED
);
3612 maskr
= SYM_RMASK(IBCCtrlB_0
, IB_LANE_REV_SUPPORTED
);
3615 case QIB_IB_CFG_LINKLATENCY
:
3616 ret
= qib_read_kreg_port(ppd
, krp_ibcstatus_b
) &
3617 SYM_MASK(IBCStatusB_0
, LinkRoundTripLatency
);
3620 case QIB_IB_CFG_OP_VLS
:
3621 ret
= ppd
->vls_operational
;
3624 case QIB_IB_CFG_VL_HIGH_CAP
:
3628 case QIB_IB_CFG_VL_LOW_CAP
:
3632 case QIB_IB_CFG_OVERRUN_THRESH
: /* IB overrun threshold */
3633 ret
= SYM_FIELD(ppd
->cpspec
->ibcctrl_a
, IBCCtrlA_0
,
3637 case QIB_IB_CFG_PHYERR_THRESH
: /* IB PHY error threshold */
3638 ret
= SYM_FIELD(ppd
->cpspec
->ibcctrl_a
, IBCCtrlA_0
,
3642 case QIB_IB_CFG_LINKDEFAULT
: /* IB link default (sleep/poll) */
3643 /* will only take effect when the link state changes */
3644 ret
= (ppd
->cpspec
->ibcctrl_a
&
3645 SYM_MASK(IBCCtrlA_0
, LinkDownDefaultState
)) ?
3646 IB_LINKINITCMD_SLEEP
: IB_LINKINITCMD_POLL
;
3649 case QIB_IB_CFG_HRTBT
: /* Get Heartbeat off/enable/auto */
3650 lsb
= IBA7322_IBC_HRTBT_LSB
;
3651 maskr
= IBA7322_IBC_HRTBT_RMASK
; /* OR of AUTO and ENB */
3654 case QIB_IB_CFG_PMA_TICKS
:
3656 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
3657 * Since the clock is always 250MHz, the value is 3, 1 or 0.
3659 if (ppd
->link_speed_active
== QIB_IB_QDR
)
3661 else if (ppd
->link_speed_active
== QIB_IB_DDR
)
3671 ret
= (int)((ppd
->cpspec
->ibcctrl_b
>> lsb
) & maskr
);
3677 * Below again cribbed liberally from older version. Do not lean
3680 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
3681 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
3682 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
3684 static int qib_7322_set_ib_cfg(struct qib_pportdata
*ppd
, int which
, u32 val
)
3686 struct qib_devdata
*dd
= ppd
->dd
;
3687 u64 maskr
; /* right-justified mask */
3690 unsigned long flags
;
3693 case QIB_IB_CFG_LIDLMC
:
3695 * Set LID and LMC. Combined to avoid possible hazard
3696 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
3698 lsb
= IBA7322_IBC_DLIDLMC_SHIFT
;
3699 maskr
= IBA7322_IBC_DLIDLMC_MASK
;
3701 * For header-checking, the SLID in the packet will
3702 * be masked with SendIBSLMCMask, and compared
3703 * with SendIBSLIDAssignMask. Make sure we do not
3704 * set any bits not covered by the mask, or we get
3707 qib_write_kreg_port(ppd
, krp_sendslid
,
3708 val
& (val
>> 16) & SendIBSLIDAssignMask
);
3709 qib_write_kreg_port(ppd
, krp_sendslidmask
,
3710 (val
>> 16) & SendIBSLMCMask
);
3713 case QIB_IB_CFG_LWID_ENB
: /* set allowed Link-width */
3714 ppd
->link_width_enabled
= val
;
3715 /* convert IB value to chip register value */
3716 if (val
== IB_WIDTH_1X
)
3718 else if (val
== IB_WIDTH_4X
)
3722 maskr
= SYM_RMASK(IBCCtrlB_0
, IB_NUM_CHANNELS
);
3723 lsb
= SYM_LSB(IBCCtrlB_0
, IB_NUM_CHANNELS
);
3726 case QIB_IB_CFG_SPD_ENB
: /* set allowed Link speeds */
3728 * As with width, only write the actual register if the
3729 * link is currently down, otherwise takes effect on next
3730 * link change. Since setting is being explicitly requested
3731 * (via MAD or sysfs), clear autoneg failure status if speed
3732 * autoneg is enabled.
3734 ppd
->link_speed_enabled
= val
;
3735 val
<<= IBA7322_IBC_SPEED_LSB
;
3736 maskr
= IBA7322_IBC_SPEED_MASK
| IBA7322_IBC_IBTA_1_2_MASK
|
3737 IBA7322_IBC_MAX_SPEED_MASK
;
3738 if (val
& (val
- 1)) {
3739 /* Muliple speeds enabled */
3740 val
|= IBA7322_IBC_IBTA_1_2_MASK
|
3741 IBA7322_IBC_MAX_SPEED_MASK
;
3742 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
3743 ppd
->lflags
&= ~QIBL_IB_AUTONEG_FAILED
;
3744 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
3745 } else if (val
& IBA7322_IBC_SPEED_QDR
)
3746 val
|= IBA7322_IBC_IBTA_1_2_MASK
;
3747 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
3748 lsb
= SYM_LSB(IBCCtrlB_0
, IB_ENHANCED_MODE
);
3751 case QIB_IB_CFG_RXPOL_ENB
: /* set Auto-RX-polarity enable */
3752 lsb
= SYM_LSB(IBCCtrlB_0
, IB_POLARITY_REV_SUPP
);
3753 maskr
= SYM_RMASK(IBCCtrlB_0
, IB_POLARITY_REV_SUPP
);
3756 case QIB_IB_CFG_LREV_ENB
: /* set Auto-Lane-reversal enable */
3757 lsb
= SYM_LSB(IBCCtrlB_0
, IB_LANE_REV_SUPPORTED
);
3758 maskr
= SYM_RMASK(IBCCtrlB_0
, IB_LANE_REV_SUPPORTED
);
3761 case QIB_IB_CFG_OVERRUN_THRESH
: /* IB overrun threshold */
3762 maskr
= SYM_FIELD(ppd
->cpspec
->ibcctrl_a
, IBCCtrlA_0
,
3765 ppd
->cpspec
->ibcctrl_a
&=
3766 ~SYM_MASK(IBCCtrlA_0
, OverrunThreshold
);
3767 ppd
->cpspec
->ibcctrl_a
|= (u64
) val
<<
3768 SYM_LSB(IBCCtrlA_0
, OverrunThreshold
);
3769 qib_write_kreg_port(ppd
, krp_ibcctrl_a
,
3770 ppd
->cpspec
->ibcctrl_a
);
3771 qib_write_kreg(dd
, kr_scratch
, 0ULL);
3775 case QIB_IB_CFG_PHYERR_THRESH
: /* IB PHY error threshold */
3776 maskr
= SYM_FIELD(ppd
->cpspec
->ibcctrl_a
, IBCCtrlA_0
,
3779 ppd
->cpspec
->ibcctrl_a
&=
3780 ~SYM_MASK(IBCCtrlA_0
, PhyerrThreshold
);
3781 ppd
->cpspec
->ibcctrl_a
|= (u64
) val
<<
3782 SYM_LSB(IBCCtrlA_0
, PhyerrThreshold
);
3783 qib_write_kreg_port(ppd
, krp_ibcctrl_a
,
3784 ppd
->cpspec
->ibcctrl_a
);
3785 qib_write_kreg(dd
, kr_scratch
, 0ULL);
3789 case QIB_IB_CFG_PKEYS
: /* update pkeys */
3790 maskr
= (u64
) ppd
->pkeys
[0] | ((u64
) ppd
->pkeys
[1] << 16) |
3791 ((u64
) ppd
->pkeys
[2] << 32) |
3792 ((u64
) ppd
->pkeys
[3] << 48);
3793 qib_write_kreg_port(ppd
, krp_partitionkey
, maskr
);
3796 case QIB_IB_CFG_LINKDEFAULT
: /* IB link default (sleep/poll) */
3797 /* will only take effect when the link state changes */
3798 if (val
== IB_LINKINITCMD_POLL
)
3799 ppd
->cpspec
->ibcctrl_a
&=
3800 ~SYM_MASK(IBCCtrlA_0
, LinkDownDefaultState
);
3802 ppd
->cpspec
->ibcctrl_a
|=
3803 SYM_MASK(IBCCtrlA_0
, LinkDownDefaultState
);
3804 qib_write_kreg_port(ppd
, krp_ibcctrl_a
, ppd
->cpspec
->ibcctrl_a
);
3805 qib_write_kreg(dd
, kr_scratch
, 0ULL);
3808 case QIB_IB_CFG_MTU
: /* update the MTU in IBC */
3810 * Update our housekeeping variables, and set IBC max
3811 * size, same as init code; max IBC is max we allow in
3812 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
3813 * Set even if it's unchanged, print debug message only
3816 val
= (ppd
->ibmaxlen
>> 2) + 1;
3817 ppd
->cpspec
->ibcctrl_a
&= ~SYM_MASK(IBCCtrlA_0
, MaxPktLen
);
3818 ppd
->cpspec
->ibcctrl_a
|= (u64
)val
<<
3819 SYM_LSB(IBCCtrlA_0
, MaxPktLen
);
3820 qib_write_kreg_port(ppd
, krp_ibcctrl_a
,
3821 ppd
->cpspec
->ibcctrl_a
);
3822 qib_write_kreg(dd
, kr_scratch
, 0ULL);
3825 case QIB_IB_CFG_LSTATE
: /* set the IB link state */
3826 switch (val
& 0xffff0000) {
3827 case IB_LINKCMD_DOWN
:
3828 lcmd
= QLOGIC_IB_IBCC_LINKCMD_DOWN
;
3829 ppd
->cpspec
->ibmalfusesnap
= 1;
3830 ppd
->cpspec
->ibmalfsnap
= read_7322_creg32_port(ppd
,
3832 if (!ppd
->cpspec
->ibdeltainprog
&&
3833 qib_compat_ddr_negotiate
) {
3834 ppd
->cpspec
->ibdeltainprog
= 1;
3835 ppd
->cpspec
->ibsymsnap
=
3836 read_7322_creg32_port(ppd
,
3838 ppd
->cpspec
->iblnkerrsnap
=
3839 read_7322_creg32_port(ppd
,
3840 crp_iblinkerrrecov
);
3844 case IB_LINKCMD_ARMED
:
3845 lcmd
= QLOGIC_IB_IBCC_LINKCMD_ARMED
;
3846 if (ppd
->cpspec
->ibmalfusesnap
) {
3847 ppd
->cpspec
->ibmalfusesnap
= 0;
3848 ppd
->cpspec
->ibmalfdelta
+=
3849 read_7322_creg32_port(ppd
,
3851 ppd
->cpspec
->ibmalfsnap
;
3855 case IB_LINKCMD_ACTIVE
:
3856 lcmd
= QLOGIC_IB_IBCC_LINKCMD_ACTIVE
;
3861 qib_dev_err(dd
, "bad linkcmd req 0x%x\n", val
>> 16);
3864 switch (val
& 0xffff) {
3865 case IB_LINKINITCMD_NOP
:
3869 case IB_LINKINITCMD_POLL
:
3870 licmd
= QLOGIC_IB_IBCC_LINKINITCMD_POLL
;
3873 case IB_LINKINITCMD_SLEEP
:
3874 licmd
= QLOGIC_IB_IBCC_LINKINITCMD_SLEEP
;
3877 case IB_LINKINITCMD_DISABLE
:
3878 licmd
= QLOGIC_IB_IBCC_LINKINITCMD_DISABLE
;
3879 ppd
->cpspec
->chase_end
= 0;
3881 * stop state chase counter and timer, if running.
3882 * wait forpending timer, but don't clear .data (ppd)!
3884 if (ppd
->cpspec
->chase_timer
.expires
) {
3885 del_timer_sync(&ppd
->cpspec
->chase_timer
);
3886 ppd
->cpspec
->chase_timer
.expires
= 0;
3892 qib_dev_err(dd
, "bad linkinitcmd req 0x%x\n",
3896 qib_set_ib_7322_lstate(ppd
, lcmd
, licmd
);
3899 case QIB_IB_CFG_OP_VLS
:
3900 if (ppd
->vls_operational
!= val
) {
3901 ppd
->vls_operational
= val
;
3906 case QIB_IB_CFG_VL_HIGH_LIMIT
:
3907 qib_write_kreg_port(ppd
, krp_highprio_limit
, val
);
3910 case QIB_IB_CFG_HRTBT
: /* set Heartbeat off/enable/auto */
3915 lsb
= IBA7322_IBC_HRTBT_LSB
;
3916 maskr
= IBA7322_IBC_HRTBT_RMASK
; /* OR of AUTO and ENB */
3919 case QIB_IB_CFG_PORT
:
3920 /* val is the port number of the switch we are connected to. */
3921 if (ppd
->dd
->cspec
->r1
) {
3922 cancel_delayed_work(&ppd
->cpspec
->ipg_work
);
3923 ppd
->cpspec
->ipg_tries
= 0;
3931 ppd
->cpspec
->ibcctrl_b
&= ~(maskr
<< lsb
);
3932 ppd
->cpspec
->ibcctrl_b
|= (((u64
) val
& maskr
) << lsb
);
3933 qib_write_kreg_port(ppd
, krp_ibcctrl_b
, ppd
->cpspec
->ibcctrl_b
);
3934 qib_write_kreg(dd
, kr_scratch
, 0);
3939 static int qib_7322_set_loopback(struct qib_pportdata
*ppd
, const char *what
)
3944 /* only IBC loopback, may add serdes and xgxs loopbacks later */
3945 if (!strncmp(what
, "ibc", 3)) {
3946 ppd
->cpspec
->ibcctrl_a
|= SYM_MASK(IBCCtrlA_0
,
3948 val
= 0; /* disable heart beat, so link will come up */
3949 qib_devinfo(ppd
->dd
->pcidev
, "Enabling IB%u:%u IBC loopback\n",
3950 ppd
->dd
->unit
, ppd
->port
);
3951 } else if (!strncmp(what
, "off", 3)) {
3952 ppd
->cpspec
->ibcctrl_a
&= ~SYM_MASK(IBCCtrlA_0
,
3954 /* enable heart beat again */
3955 val
= IBA7322_IBC_HRTBT_RMASK
<< IBA7322_IBC_HRTBT_LSB
;
3956 qib_devinfo(ppd
->dd
->pcidev
, "Disabling IB%u:%u IBC loopback "
3957 "(normal)\n", ppd
->dd
->unit
, ppd
->port
);
3961 qib_write_kreg_port(ppd
, krp_ibcctrl_a
,
3962 ppd
->cpspec
->ibcctrl_a
);
3963 ctrlb
= ppd
->cpspec
->ibcctrl_b
& ~(IBA7322_IBC_HRTBT_MASK
3964 << IBA7322_IBC_HRTBT_LSB
);
3965 ppd
->cpspec
->ibcctrl_b
= ctrlb
| val
;
3966 qib_write_kreg_port(ppd
, krp_ibcctrl_b
,
3967 ppd
->cpspec
->ibcctrl_b
);
3968 qib_write_kreg(ppd
->dd
, kr_scratch
, 0);
3973 static void get_vl_weights(struct qib_pportdata
*ppd
, unsigned regno
,
3974 struct ib_vl_weight_elem
*vl
)
3978 for (i
= 0; i
< 16; i
++, regno
++, vl
++) {
3979 u32 val
= qib_read_kreg_port(ppd
, regno
);
3981 vl
->vl
= (val
>> SYM_LSB(LowPriority0_0
, VirtualLane
)) &
3982 SYM_RMASK(LowPriority0_0
, VirtualLane
);
3983 vl
->weight
= (val
>> SYM_LSB(LowPriority0_0
, Weight
)) &
3984 SYM_RMASK(LowPriority0_0
, Weight
);
3988 static void set_vl_weights(struct qib_pportdata
*ppd
, unsigned regno
,
3989 struct ib_vl_weight_elem
*vl
)
3993 for (i
= 0; i
< 16; i
++, regno
++, vl
++) {
3996 val
= ((vl
->vl
& SYM_RMASK(LowPriority0_0
, VirtualLane
)) <<
3997 SYM_LSB(LowPriority0_0
, VirtualLane
)) |
3998 ((vl
->weight
& SYM_RMASK(LowPriority0_0
, Weight
)) <<
3999 SYM_LSB(LowPriority0_0
, Weight
));
4000 qib_write_kreg_port(ppd
, regno
, val
);
4002 if (!(ppd
->p_sendctrl
& SYM_MASK(SendCtrl_0
, IBVLArbiterEn
))) {
4003 struct qib_devdata
*dd
= ppd
->dd
;
4004 unsigned long flags
;
4006 spin_lock_irqsave(&dd
->sendctrl_lock
, flags
);
4007 ppd
->p_sendctrl
|= SYM_MASK(SendCtrl_0
, IBVLArbiterEn
);
4008 qib_write_kreg_port(ppd
, krp_sendctrl
, ppd
->p_sendctrl
);
4009 qib_write_kreg(dd
, kr_scratch
, 0);
4010 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
4014 static int qib_7322_get_ib_table(struct qib_pportdata
*ppd
, int which
, void *t
)
4017 case QIB_IB_TBL_VL_HIGH_ARB
:
4018 get_vl_weights(ppd
, krp_highprio_0
, t
);
4021 case QIB_IB_TBL_VL_LOW_ARB
:
4022 get_vl_weights(ppd
, krp_lowprio_0
, t
);
4031 static int qib_7322_set_ib_table(struct qib_pportdata
*ppd
, int which
, void *t
)
4034 case QIB_IB_TBL_VL_HIGH_ARB
:
4035 set_vl_weights(ppd
, krp_highprio_0
, t
);
4038 case QIB_IB_TBL_VL_LOW_ARB
:
4039 set_vl_weights(ppd
, krp_lowprio_0
, t
);
4048 static void qib_update_7322_usrhead(struct qib_ctxtdata
*rcd
, u64 hd
,
4049 u32 updegr
, u32 egrhd
, u32 npkts
)
4052 * Need to write timeout register before updating rcvhdrhead to ensure
4053 * that the timer is enabled on reception of a packet.
4055 if (hd
>> IBA7322_HDRHEAD_PKTINT_SHIFT
)
4056 adjust_rcv_timeout(rcd
, npkts
);
4057 qib_write_ureg(rcd
->dd
, ur_rcvhdrhead
, hd
, rcd
->ctxt
);
4058 qib_write_ureg(rcd
->dd
, ur_rcvhdrhead
, hd
, rcd
->ctxt
);
4060 qib_write_ureg(rcd
->dd
, ur_rcvegrindexhead
, egrhd
, rcd
->ctxt
);
4063 static u32
qib_7322_hdrqempty(struct qib_ctxtdata
*rcd
)
4067 head
= qib_read_ureg32(rcd
->dd
, ur_rcvhdrhead
, rcd
->ctxt
);
4068 if (rcd
->rcvhdrtail_kvaddr
)
4069 tail
= qib_get_rcvhdrtail(rcd
);
4071 tail
= qib_read_ureg32(rcd
->dd
, ur_rcvhdrtail
, rcd
->ctxt
);
4072 return head
== tail
;
4075 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4076 QIB_RCVCTRL_CTXT_DIS | \
4077 QIB_RCVCTRL_TIDFLOW_ENB | \
4078 QIB_RCVCTRL_TIDFLOW_DIS | \
4079 QIB_RCVCTRL_TAILUPD_ENB | \
4080 QIB_RCVCTRL_TAILUPD_DIS | \
4081 QIB_RCVCTRL_INTRAVAIL_ENB | \
4082 QIB_RCVCTRL_INTRAVAIL_DIS | \
4083 QIB_RCVCTRL_BP_ENB | \
4086 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4087 QIB_RCVCTRL_CTXT_DIS | \
4088 QIB_RCVCTRL_PKEY_DIS | \
4089 QIB_RCVCTRL_PKEY_ENB)
4092 * Modify the RCVCTRL register in chip-specific way. This
4093 * is a function because bit positions and (future) register
4094 * location is chip-specifc, but the needed operations are
4095 * generic. <op> is a bit-mask because we often want to
4096 * do multiple modifications.
4098 static void rcvctrl_7322_mod(struct qib_pportdata
*ppd
, unsigned int op
,
4101 struct qib_devdata
*dd
= ppd
->dd
;
4102 struct qib_ctxtdata
*rcd
;
4104 unsigned long flags
;
4106 spin_lock_irqsave(&dd
->cspec
->rcvmod_lock
, flags
);
4108 if (op
& QIB_RCVCTRL_TIDFLOW_ENB
)
4109 dd
->rcvctrl
|= SYM_MASK(RcvCtrl
, TidFlowEnable
);
4110 if (op
& QIB_RCVCTRL_TIDFLOW_DIS
)
4111 dd
->rcvctrl
&= ~SYM_MASK(RcvCtrl
, TidFlowEnable
);
4112 if (op
& QIB_RCVCTRL_TAILUPD_ENB
)
4113 dd
->rcvctrl
|= SYM_MASK(RcvCtrl
, TailUpd
);
4114 if (op
& QIB_RCVCTRL_TAILUPD_DIS
)
4115 dd
->rcvctrl
&= ~SYM_MASK(RcvCtrl
, TailUpd
);
4116 if (op
& QIB_RCVCTRL_PKEY_ENB
)
4117 ppd
->p_rcvctrl
&= ~SYM_MASK(RcvCtrl_0
, RcvPartitionKeyDisable
);
4118 if (op
& QIB_RCVCTRL_PKEY_DIS
)
4119 ppd
->p_rcvctrl
|= SYM_MASK(RcvCtrl_0
, RcvPartitionKeyDisable
);
4121 mask
= (1ULL << dd
->ctxtcnt
) - 1;
4124 mask
= (1ULL << ctxt
);
4125 rcd
= dd
->rcd
[ctxt
];
4127 if ((op
& QIB_RCVCTRL_CTXT_ENB
) && rcd
) {
4129 (mask
<< SYM_LSB(RcvCtrl_0
, ContextEnableKernel
));
4130 if (!(dd
->flags
& QIB_NODMA_RTAIL
)) {
4131 op
|= QIB_RCVCTRL_TAILUPD_ENB
; /* need reg write */
4132 dd
->rcvctrl
|= SYM_MASK(RcvCtrl
, TailUpd
);
4134 /* Write these registers before the context is enabled. */
4135 qib_write_kreg_ctxt(dd
, krc_rcvhdrtailaddr
, ctxt
,
4136 rcd
->rcvhdrqtailaddr_phys
);
4137 qib_write_kreg_ctxt(dd
, krc_rcvhdraddr
, ctxt
,
4141 if (op
& QIB_RCVCTRL_CTXT_DIS
)
4143 ~(mask
<< SYM_LSB(RcvCtrl_0
, ContextEnableKernel
));
4144 if (op
& QIB_RCVCTRL_BP_ENB
)
4145 dd
->rcvctrl
|= mask
<< SYM_LSB(RcvCtrl
, dontDropRHQFull
);
4146 if (op
& QIB_RCVCTRL_BP_DIS
)
4147 dd
->rcvctrl
&= ~(mask
<< SYM_LSB(RcvCtrl
, dontDropRHQFull
));
4148 if (op
& QIB_RCVCTRL_INTRAVAIL_ENB
)
4149 dd
->rcvctrl
|= (mask
<< SYM_LSB(RcvCtrl
, IntrAvail
));
4150 if (op
& QIB_RCVCTRL_INTRAVAIL_DIS
)
4151 dd
->rcvctrl
&= ~(mask
<< SYM_LSB(RcvCtrl
, IntrAvail
));
4153 * Decide which registers to write depending on the ops enabled.
4154 * Special case is "flush" (no bits set at all)
4155 * which needs to write both.
4157 if (op
== 0 || (op
& RCVCTRL_COMMON_MODS
))
4158 qib_write_kreg(dd
, kr_rcvctrl
, dd
->rcvctrl
);
4159 if (op
== 0 || (op
& RCVCTRL_PORT_MODS
))
4160 qib_write_kreg_port(ppd
, krp_rcvctrl
, ppd
->p_rcvctrl
);
4161 if ((op
& QIB_RCVCTRL_CTXT_ENB
) && dd
->rcd
[ctxt
]) {
4163 * Init the context registers also; if we were
4164 * disabled, tail and head should both be zero
4165 * already from the enable, but since we don't
4166 * know, we have to do it explicitly.
4168 val
= qib_read_ureg32(dd
, ur_rcvegrindextail
, ctxt
);
4169 qib_write_ureg(dd
, ur_rcvegrindexhead
, val
, ctxt
);
4171 /* be sure enabling write seen; hd/tl should be 0 */
4172 (void) qib_read_kreg32(dd
, kr_scratch
);
4173 val
= qib_read_ureg32(dd
, ur_rcvhdrtail
, ctxt
);
4174 dd
->rcd
[ctxt
]->head
= val
;
4175 /* If kctxt, interrupt on next receive. */
4176 if (ctxt
< dd
->first_user_ctxt
)
4177 val
|= dd
->rhdrhead_intr_off
;
4178 qib_write_ureg(dd
, ur_rcvhdrhead
, val
, ctxt
);
4179 } else if ((op
& QIB_RCVCTRL_INTRAVAIL_ENB
) &&
4180 dd
->rcd
[ctxt
] && dd
->rhdrhead_intr_off
) {
4181 /* arm rcv interrupt */
4182 val
= dd
->rcd
[ctxt
]->head
| dd
->rhdrhead_intr_off
;
4183 qib_write_ureg(dd
, ur_rcvhdrhead
, val
, ctxt
);
4185 if (op
& QIB_RCVCTRL_CTXT_DIS
) {
4188 /* Now that the context is disabled, clear these registers. */
4190 qib_write_kreg_ctxt(dd
, krc_rcvhdrtailaddr
, ctxt
, 0);
4191 qib_write_kreg_ctxt(dd
, krc_rcvhdraddr
, ctxt
, 0);
4192 for (f
= 0; f
< NUM_TIDFLOWS_CTXT
; f
++)
4193 qib_write_ureg(dd
, ur_rcvflowtable
+ f
,
4194 TIDFLOW_ERRBITS
, ctxt
);
4198 for (i
= 0; i
< dd
->cfgctxts
; i
++) {
4199 qib_write_kreg_ctxt(dd
, krc_rcvhdrtailaddr
,
4201 qib_write_kreg_ctxt(dd
, krc_rcvhdraddr
, i
, 0);
4202 for (f
= 0; f
< NUM_TIDFLOWS_CTXT
; f
++)
4203 qib_write_ureg(dd
, ur_rcvflowtable
+ f
,
4204 TIDFLOW_ERRBITS
, i
);
4208 spin_unlock_irqrestore(&dd
->cspec
->rcvmod_lock
, flags
);
4212 * Modify the SENDCTRL register in chip-specific way. This
4213 * is a function where there are multiple such registers with
4214 * slightly different layouts.
4215 * The chip doesn't allow back-to-back sendctrl writes, so write
4216 * the scratch register after writing sendctrl.
4218 * Which register is written depends on the operation.
4219 * Most operate on the common register, while
4220 * SEND_ENB and SEND_DIS operate on the per-port ones.
4221 * SEND_ENB is included in common because it can change SPCL_TRIG
4223 #define SENDCTRL_COMMON_MODS (\
4224 QIB_SENDCTRL_CLEAR | \
4225 QIB_SENDCTRL_AVAIL_DIS | \
4226 QIB_SENDCTRL_AVAIL_ENB | \
4227 QIB_SENDCTRL_AVAIL_BLIP | \
4228 QIB_SENDCTRL_DISARM | \
4229 QIB_SENDCTRL_DISARM_ALL | \
4230 QIB_SENDCTRL_SEND_ENB)
4232 #define SENDCTRL_PORT_MODS (\
4233 QIB_SENDCTRL_CLEAR | \
4234 QIB_SENDCTRL_SEND_ENB | \
4235 QIB_SENDCTRL_SEND_DIS | \
4238 static void sendctrl_7322_mod(struct qib_pportdata
*ppd
, u32 op
)
4240 struct qib_devdata
*dd
= ppd
->dd
;
4241 u64 tmp_dd_sendctrl
;
4242 unsigned long flags
;
4244 spin_lock_irqsave(&dd
->sendctrl_lock
, flags
);
4246 /* First the dd ones that are "sticky", saved in shadow */
4247 if (op
& QIB_SENDCTRL_CLEAR
)
4249 if (op
& QIB_SENDCTRL_AVAIL_DIS
)
4250 dd
->sendctrl
&= ~SYM_MASK(SendCtrl
, SendBufAvailUpd
);
4251 else if (op
& QIB_SENDCTRL_AVAIL_ENB
) {
4252 dd
->sendctrl
|= SYM_MASK(SendCtrl
, SendBufAvailUpd
);
4253 if (dd
->flags
& QIB_USE_SPCL_TRIG
)
4254 dd
->sendctrl
|= SYM_MASK(SendCtrl
, SpecialTriggerEn
);
4257 /* Then the ppd ones that are "sticky", saved in shadow */
4258 if (op
& QIB_SENDCTRL_SEND_DIS
)
4259 ppd
->p_sendctrl
&= ~SYM_MASK(SendCtrl_0
, SendEnable
);
4260 else if (op
& QIB_SENDCTRL_SEND_ENB
)
4261 ppd
->p_sendctrl
|= SYM_MASK(SendCtrl_0
, SendEnable
);
4263 if (op
& QIB_SENDCTRL_DISARM_ALL
) {
4266 tmp_dd_sendctrl
= dd
->sendctrl
;
4267 last
= dd
->piobcnt2k
+ dd
->piobcnt4k
+ NUM_VL15_BUFS
;
4269 * Disarm any buffers that are not yet launched,
4270 * disabling updates until done.
4272 tmp_dd_sendctrl
&= ~SYM_MASK(SendCtrl
, SendBufAvailUpd
);
4273 for (i
= 0; i
< last
; i
++) {
4274 qib_write_kreg(dd
, kr_sendctrl
,
4276 SYM_MASK(SendCtrl
, Disarm
) | i
);
4277 qib_write_kreg(dd
, kr_scratch
, 0);
4281 if (op
& QIB_SENDCTRL_FLUSH
) {
4282 u64 tmp_ppd_sendctrl
= ppd
->p_sendctrl
;
4285 * Now drain all the fifos. The Abort bit should never be
4286 * needed, so for now, at least, we don't use it.
4289 SYM_MASK(SendCtrl_0
, TxeDrainRmFifo
) |
4290 SYM_MASK(SendCtrl_0
, TxeDrainLaFifo
) |
4291 SYM_MASK(SendCtrl_0
, TxeBypassIbc
);
4292 qib_write_kreg_port(ppd
, krp_sendctrl
, tmp_ppd_sendctrl
);
4293 qib_write_kreg(dd
, kr_scratch
, 0);
4296 tmp_dd_sendctrl
= dd
->sendctrl
;
4298 if (op
& QIB_SENDCTRL_DISARM
)
4299 tmp_dd_sendctrl
|= SYM_MASK(SendCtrl
, Disarm
) |
4300 ((op
& QIB_7322_SendCtrl_DisarmSendBuf_RMASK
) <<
4301 SYM_LSB(SendCtrl
, DisarmSendBuf
));
4302 if ((op
& QIB_SENDCTRL_AVAIL_BLIP
) &&
4303 (dd
->sendctrl
& SYM_MASK(SendCtrl
, SendBufAvailUpd
)))
4304 tmp_dd_sendctrl
&= ~SYM_MASK(SendCtrl
, SendBufAvailUpd
);
4306 if (op
== 0 || (op
& SENDCTRL_COMMON_MODS
)) {
4307 qib_write_kreg(dd
, kr_sendctrl
, tmp_dd_sendctrl
);
4308 qib_write_kreg(dd
, kr_scratch
, 0);
4311 if (op
== 0 || (op
& SENDCTRL_PORT_MODS
)) {
4312 qib_write_kreg_port(ppd
, krp_sendctrl
, ppd
->p_sendctrl
);
4313 qib_write_kreg(dd
, kr_scratch
, 0);
4316 if (op
& QIB_SENDCTRL_AVAIL_BLIP
) {
4317 qib_write_kreg(dd
, kr_sendctrl
, dd
->sendctrl
);
4318 qib_write_kreg(dd
, kr_scratch
, 0);
4321 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
4323 if (op
& QIB_SENDCTRL_FLUSH
) {
4326 * ensure writes have hit chip, then do a few
4327 * more reads, to allow DMA of pioavail registers
4328 * to occur, so in-memory copy is in sync with
4329 * the chip. Not always safe to sleep.
4331 v
= qib_read_kreg32(dd
, kr_scratch
);
4332 qib_write_kreg(dd
, kr_scratch
, v
);
4333 v
= qib_read_kreg32(dd
, kr_scratch
);
4334 qib_write_kreg(dd
, kr_scratch
, v
);
4335 qib_read_kreg32(dd
, kr_scratch
);
4339 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4340 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4341 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4344 * qib_portcntr_7322 - read a per-port chip counter
4345 * @ppd: the qlogic_ib pport
4346 * @creg: the counter to read (not a chip offset)
4348 static u64
qib_portcntr_7322(struct qib_pportdata
*ppd
, u32 reg
)
4350 struct qib_devdata
*dd
= ppd
->dd
;
4353 /* 0xffff for unimplemented or synthesized counters */
4354 static const u32 xlator
[] = {
4355 [QIBPORTCNTR_PKTSEND
] = crp_pktsend
| _PORT_64BIT_FLAG
,
4356 [QIBPORTCNTR_WORDSEND
] = crp_wordsend
| _PORT_64BIT_FLAG
,
4357 [QIBPORTCNTR_PSXMITDATA
] = crp_psxmitdatacount
,
4358 [QIBPORTCNTR_PSXMITPKTS
] = crp_psxmitpktscount
,
4359 [QIBPORTCNTR_PSXMITWAIT
] = crp_psxmitwaitcount
,
4360 [QIBPORTCNTR_SENDSTALL
] = crp_sendstall
,
4361 [QIBPORTCNTR_PKTRCV
] = crp_pktrcv
| _PORT_64BIT_FLAG
,
4362 [QIBPORTCNTR_PSRCVDATA
] = crp_psrcvdatacount
,
4363 [QIBPORTCNTR_PSRCVPKTS
] = crp_psrcvpktscount
,
4364 [QIBPORTCNTR_RCVEBP
] = crp_rcvebp
,
4365 [QIBPORTCNTR_RCVOVFL
] = crp_rcvovfl
,
4366 [QIBPORTCNTR_WORDRCV
] = crp_wordrcv
| _PORT_64BIT_FLAG
,
4367 [QIBPORTCNTR_RXDROPPKT
] = 0xffff, /* not needed for 7322 */
4368 [QIBPORTCNTR_RXLOCALPHYERR
] = crp_rxotherlocalphyerr
,
4369 [QIBPORTCNTR_RXVLERR
] = crp_rxvlerr
,
4370 [QIBPORTCNTR_ERRICRC
] = crp_erricrc
,
4371 [QIBPORTCNTR_ERRVCRC
] = crp_errvcrc
,
4372 [QIBPORTCNTR_ERRLPCRC
] = crp_errlpcrc
,
4373 [QIBPORTCNTR_BADFORMAT
] = crp_badformat
,
4374 [QIBPORTCNTR_ERR_RLEN
] = crp_err_rlen
,
4375 [QIBPORTCNTR_IBSYMBOLERR
] = crp_ibsymbolerr
,
4376 [QIBPORTCNTR_INVALIDRLEN
] = crp_invalidrlen
,
4377 [QIBPORTCNTR_UNSUPVL
] = crp_txunsupvl
,
4378 [QIBPORTCNTR_EXCESSBUFOVFL
] = crp_excessbufferovfl
,
4379 [QIBPORTCNTR_ERRLINK
] = crp_errlink
,
4380 [QIBPORTCNTR_IBLINKDOWN
] = crp_iblinkdown
,
4381 [QIBPORTCNTR_IBLINKERRRECOV
] = crp_iblinkerrrecov
,
4382 [QIBPORTCNTR_LLI
] = crp_locallinkintegrityerr
,
4383 [QIBPORTCNTR_VL15PKTDROP
] = crp_vl15droppedpkt
,
4384 [QIBPORTCNTR_ERRPKEY
] = crp_errpkey
,
4386 * the next 3 aren't really counters, but were implemented
4387 * as counters in older chips, so still get accessed as
4388 * though they were counters from this code.
4390 [QIBPORTCNTR_PSINTERVAL
] = krp_psinterval
,
4391 [QIBPORTCNTR_PSSTART
] = krp_psstart
,
4392 [QIBPORTCNTR_PSSTAT
] = krp_psstat
,
4393 /* pseudo-counter, summed for all ports */
4394 [QIBPORTCNTR_KHDROVFL
] = 0xffff,
4397 if (reg
>= ARRAY_SIZE(xlator
)) {
4398 qib_devinfo(ppd
->dd
->pcidev
,
4399 "Unimplemented portcounter %u\n", reg
);
4402 creg
= xlator
[reg
] & _PORT_CNTR_IDXMASK
;
4404 /* handle non-counters and special cases first */
4405 if (reg
== QIBPORTCNTR_KHDROVFL
) {
4408 /* sum over all kernel contexts (skip if mini_init) */
4409 for (i
= 0; dd
->rcd
&& i
< dd
->first_user_ctxt
; i
++) {
4410 struct qib_ctxtdata
*rcd
= dd
->rcd
[i
];
4412 if (!rcd
|| rcd
->ppd
!= ppd
)
4414 ret
+= read_7322_creg32(dd
, cr_base_egrovfl
+ i
);
4417 } else if (reg
== QIBPORTCNTR_RXDROPPKT
) {
4419 * Used as part of the synthesis of port_rcv_errors
4420 * in the verbs code for IBTA counters. Not needed for 7322,
4421 * because all the errors are already counted by other cntrs.
4424 } else if (reg
== QIBPORTCNTR_PSINTERVAL
||
4425 reg
== QIBPORTCNTR_PSSTART
|| reg
== QIBPORTCNTR_PSSTAT
) {
4426 /* were counters in older chips, now per-port kernel regs */
4427 ret
= qib_read_kreg_port(ppd
, creg
);
4432 * Only fast increment counters are 64 bits; use 32 bit reads to
4433 * avoid two independent reads when on Opteron.
4435 if (xlator
[reg
] & _PORT_64BIT_FLAG
)
4436 ret
= read_7322_creg_port(ppd
, creg
);
4438 ret
= read_7322_creg32_port(ppd
, creg
);
4439 if (creg
== crp_ibsymbolerr
) {
4440 if (ppd
->cpspec
->ibdeltainprog
)
4441 ret
-= ret
- ppd
->cpspec
->ibsymsnap
;
4442 ret
-= ppd
->cpspec
->ibsymdelta
;
4443 } else if (creg
== crp_iblinkerrrecov
) {
4444 if (ppd
->cpspec
->ibdeltainprog
)
4445 ret
-= ret
- ppd
->cpspec
->iblnkerrsnap
;
4446 ret
-= ppd
->cpspec
->iblnkerrdelta
;
4447 } else if (creg
== crp_errlink
)
4448 ret
-= ppd
->cpspec
->ibmalfdelta
;
4449 else if (creg
== crp_iblinkdown
)
4450 ret
+= ppd
->cpspec
->iblnkdowndelta
;
4456 * Device counter names (not port-specific), one line per stat,
4457 * single string. Used by utilities like ipathstats to print the stats
4458 * in a way which works for different versions of drivers, without changing
4459 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4460 * display by utility.
4461 * Non-error counters are first.
4462 * Start of "error" conters is indicated by a leading "E " on the first
4463 * "error" counter, and doesn't count in label length.
4464 * The EgrOvfl list needs to be last so we truncate them at the configured
4465 * context count for the device.
4466 * cntr7322indices contains the corresponding register indices.
4468 static const char cntr7322names
[] =
4473 "RxTIDFloDrop\n" /* 7322 only */
4494 static const u32 cntr7322indices
[] = {
4495 cr_lbint
| _PORT_64BIT_FLAG
,
4496 cr_lbstall
| _PORT_64BIT_FLAG
,
4500 cr_base_egrovfl
+ 0,
4501 cr_base_egrovfl
+ 1,
4502 cr_base_egrovfl
+ 2,
4503 cr_base_egrovfl
+ 3,
4504 cr_base_egrovfl
+ 4,
4505 cr_base_egrovfl
+ 5,
4506 cr_base_egrovfl
+ 6,
4507 cr_base_egrovfl
+ 7,
4508 cr_base_egrovfl
+ 8,
4509 cr_base_egrovfl
+ 9,
4510 cr_base_egrovfl
+ 10,
4511 cr_base_egrovfl
+ 11,
4512 cr_base_egrovfl
+ 12,
4513 cr_base_egrovfl
+ 13,
4514 cr_base_egrovfl
+ 14,
4515 cr_base_egrovfl
+ 15,
4516 cr_base_egrovfl
+ 16,
4517 cr_base_egrovfl
+ 17,
4521 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4522 * portcntr7322indices is somewhat complicated by some registers needing
4523 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4525 static const char portcntr7322names
[] =
4533 "TxDmaDesc\n" /* 7220 and 7322-only */
4534 "E RxDlidFltr\n" /* 7220 and 7322-only */
4557 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4561 "RxQPBadCtxt\n" /* 7322-only from here down */
4565 static const u32 portcntr7322indices
[] = {
4566 QIBPORTCNTR_PKTSEND
| _PORT_VIRT_FLAG
,
4568 QIBPORTCNTR_WORDSEND
| _PORT_VIRT_FLAG
,
4569 QIBPORTCNTR_PKTRCV
| _PORT_VIRT_FLAG
,
4571 QIBPORTCNTR_WORDRCV
| _PORT_VIRT_FLAG
,
4572 QIBPORTCNTR_SENDSTALL
| _PORT_VIRT_FLAG
,
4573 crp_txsdmadesc
| _PORT_64BIT_FLAG
,
4576 QIBPORTCNTR_IBLINKDOWN
| _PORT_VIRT_FLAG
,
4577 QIBPORTCNTR_IBLINKERRRECOV
| _PORT_VIRT_FLAG
,
4578 QIBPORTCNTR_ERRLINK
| _PORT_VIRT_FLAG
,
4579 QIBPORTCNTR_IBSYMBOLERR
| _PORT_VIRT_FLAG
,
4580 QIBPORTCNTR_LLI
| _PORT_VIRT_FLAG
,
4581 QIBPORTCNTR_BADFORMAT
| _PORT_VIRT_FLAG
,
4582 QIBPORTCNTR_ERR_RLEN
| _PORT_VIRT_FLAG
,
4583 QIBPORTCNTR_RCVOVFL
| _PORT_VIRT_FLAG
,
4584 QIBPORTCNTR_RCVEBP
| _PORT_VIRT_FLAG
,
4585 crp_rcvflowctrlviol
,
4586 QIBPORTCNTR_ERRICRC
| _PORT_VIRT_FLAG
,
4587 QIBPORTCNTR_ERRLPCRC
| _PORT_VIRT_FLAG
,
4588 QIBPORTCNTR_ERRVCRC
| _PORT_VIRT_FLAG
,
4589 QIBPORTCNTR_INVALIDRLEN
| _PORT_VIRT_FLAG
,
4590 QIBPORTCNTR_ERRPKEY
| _PORT_VIRT_FLAG
,
4591 QIBPORTCNTR_RXDROPPKT
| _PORT_VIRT_FLAG
,
4597 QIBPORTCNTR_RXLOCALPHYERR
| _PORT_VIRT_FLAG
,
4598 QIBPORTCNTR_VL15PKTDROP
| _PORT_VIRT_FLAG
,
4599 QIBPORTCNTR_RXVLERR
| _PORT_VIRT_FLAG
,
4600 QIBPORTCNTR_EXCESSBUFOVFL
| _PORT_VIRT_FLAG
,
4601 crp_rxqpinvalidctxt
,
4605 /* do all the setup to make the counter reads efficient later */
4606 static void init_7322_cntrnames(struct qib_devdata
*dd
)
4611 for (i
= 0, s
= (char *)cntr7322names
; s
&& j
<= dd
->cfgctxts
;
4613 /* we always have at least one counter before the egrovfl */
4614 if (!j
&& !strncmp("Ctxt0EgrOvfl", s
+ 1, 12))
4616 s
= strchr(s
+ 1, '\n');
4620 dd
->cspec
->ncntrs
= i
;
4622 /* full list; size is without terminating null */
4623 dd
->cspec
->cntrnamelen
= sizeof(cntr7322names
) - 1;
4625 dd
->cspec
->cntrnamelen
= 1 + s
- cntr7322names
;
4626 dd
->cspec
->cntrs
= kmalloc(dd
->cspec
->ncntrs
4627 * sizeof(u64
), GFP_KERNEL
);
4628 if (!dd
->cspec
->cntrs
)
4629 qib_dev_err(dd
, "Failed allocation for counters\n");
4631 for (i
= 0, s
= (char *)portcntr7322names
; s
; i
++)
4632 s
= strchr(s
+ 1, '\n');
4633 dd
->cspec
->nportcntrs
= i
- 1;
4634 dd
->cspec
->portcntrnamelen
= sizeof(portcntr7322names
) - 1;
4635 for (i
= 0; i
< dd
->num_pports
; ++i
) {
4636 dd
->pport
[i
].cpspec
->portcntrs
= kmalloc(dd
->cspec
->nportcntrs
4637 * sizeof(u64
), GFP_KERNEL
);
4638 if (!dd
->pport
[i
].cpspec
->portcntrs
)
4639 qib_dev_err(dd
, "Failed allocation for"
4644 static u32
qib_read_7322cntrs(struct qib_devdata
*dd
, loff_t pos
, char **namep
,
4650 ret
= dd
->cspec
->cntrnamelen
;
4652 ret
= 0; /* final read after getting everything */
4654 *namep
= (char *) cntr7322names
;
4656 u64
*cntr
= dd
->cspec
->cntrs
;
4659 ret
= dd
->cspec
->ncntrs
* sizeof(u64
);
4660 if (!cntr
|| pos
>= ret
) {
4661 /* everything read, or couldn't get memory */
4666 for (i
= 0; i
< dd
->cspec
->ncntrs
; i
++)
4667 if (cntr7322indices
[i
] & _PORT_64BIT_FLAG
)
4668 *cntr
++ = read_7322_creg(dd
,
4669 cntr7322indices
[i
] &
4670 _PORT_CNTR_IDXMASK
);
4672 *cntr
++ = read_7322_creg32(dd
,
4673 cntr7322indices
[i
]);
4679 static u32
qib_read_7322portcntrs(struct qib_devdata
*dd
, loff_t pos
, u32 port
,
4680 char **namep
, u64
**cntrp
)
4685 ret
= dd
->cspec
->portcntrnamelen
;
4687 ret
= 0; /* final read after getting everything */
4689 *namep
= (char *)portcntr7322names
;
4691 struct qib_pportdata
*ppd
= &dd
->pport
[port
];
4692 u64
*cntr
= ppd
->cpspec
->portcntrs
;
4695 ret
= dd
->cspec
->nportcntrs
* sizeof(u64
);
4696 if (!cntr
|| pos
>= ret
) {
4697 /* everything read, or couldn't get memory */
4702 for (i
= 0; i
< dd
->cspec
->nportcntrs
; i
++) {
4703 if (portcntr7322indices
[i
] & _PORT_VIRT_FLAG
)
4704 *cntr
++ = qib_portcntr_7322(ppd
,
4705 portcntr7322indices
[i
] &
4706 _PORT_CNTR_IDXMASK
);
4707 else if (portcntr7322indices
[i
] & _PORT_64BIT_FLAG
)
4708 *cntr
++ = read_7322_creg_port(ppd
,
4709 portcntr7322indices
[i
] &
4710 _PORT_CNTR_IDXMASK
);
4712 *cntr
++ = read_7322_creg32_port(ppd
,
4713 portcntr7322indices
[i
]);
4721 * qib_get_7322_faststats - get word counters from chip before they overflow
4722 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
4724 * VESTIGIAL IBA7322 has no "small fast counters", so the only
4725 * real purpose of this function is to maintain the notion of
4726 * "active time", which in turn is only logged into the eeprom,
4727 * which we don;t have, yet, for 7322-based boards.
4729 * called from add_timer
4731 static void qib_get_7322_faststats(unsigned long opaque
)
4733 struct qib_devdata
*dd
= (struct qib_devdata
*) opaque
;
4734 struct qib_pportdata
*ppd
;
4735 unsigned long flags
;
4739 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
4740 ppd
= dd
->pport
+ pidx
;
4743 * If port isn't enabled or not operational ports, or
4744 * diags is running (can cause memory diags to fail)
4745 * skip this port this time.
4747 if (!ppd
->link_speed_supported
|| !(dd
->flags
& QIB_INITTED
)
4752 * Maintain an activity timer, based on traffic
4753 * exceeding a threshold, so we need to check the word-counts
4754 * even if they are 64-bit.
4756 traffic_wds
= qib_portcntr_7322(ppd
, QIBPORTCNTR_WORDRCV
) +
4757 qib_portcntr_7322(ppd
, QIBPORTCNTR_WORDSEND
);
4758 spin_lock_irqsave(&ppd
->dd
->eep_st_lock
, flags
);
4759 traffic_wds
-= ppd
->dd
->traffic_wds
;
4760 ppd
->dd
->traffic_wds
+= traffic_wds
;
4761 if (traffic_wds
>= QIB_TRAFFIC_ACTIVE_THRESHOLD
)
4762 atomic_add(ACTIVITY_TIMER
, &ppd
->dd
->active_time
);
4763 spin_unlock_irqrestore(&ppd
->dd
->eep_st_lock
, flags
);
4764 if (ppd
->cpspec
->qdr_dfe_on
&& (ppd
->link_speed_active
&
4766 (ppd
->lflags
& (QIBL_LINKINIT
| QIBL_LINKARMED
|
4767 QIBL_LINKACTIVE
)) &&
4768 ppd
->cpspec
->qdr_dfe_time
&&
4769 time_after64(get_jiffies_64(), ppd
->cpspec
->qdr_dfe_time
)) {
4770 ppd
->cpspec
->qdr_dfe_on
= 0;
4772 qib_write_kreg_port(ppd
, krp_static_adapt_dis(2),
4773 ppd
->dd
->cspec
->r1
?
4774 QDR_STATIC_ADAPT_INIT_R1
:
4775 QDR_STATIC_ADAPT_INIT
);
4779 mod_timer(&dd
->stats_timer
, jiffies
+ HZ
* ACTIVITY_TIMER
);
4783 * If we were using MSIx, try to fallback to INTx.
4785 static int qib_7322_intr_fallback(struct qib_devdata
*dd
)
4787 if (!dd
->cspec
->num_msix_entries
)
4788 return 0; /* already using INTx */
4790 qib_devinfo(dd
->pcidev
, "MSIx interrupt not detected,"
4791 " trying INTx interrupts\n");
4792 qib_7322_nomsix(dd
);
4793 qib_enable_intx(dd
->pcidev
);
4794 qib_setup_7322_interrupt(dd
, 0);
4799 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
4800 * than resetting the IBC or external link state, and useful in some
4801 * cases to cause some retraining. To do this right, we reset IBC
4802 * as well, then return to previous state (which may be still in reset)
4803 * NOTE: some callers of this "know" this writes the current value
4804 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
4805 * check all callers.
4807 static void qib_7322_mini_pcs_reset(struct qib_pportdata
*ppd
)
4810 struct qib_devdata
*dd
= ppd
->dd
;
4811 const u64 reset_bits
= SYM_MASK(IBPCSConfig_0
, xcv_rreset
) |
4812 SYM_MASK(IBPCSConfig_0
, xcv_treset
) |
4813 SYM_MASK(IBPCSConfig_0
, tx_rx_reset
);
4815 val
= qib_read_kreg_port(ppd
, krp_ib_pcsconfig
);
4816 qib_write_kreg(dd
, kr_hwerrmask
,
4817 dd
->cspec
->hwerrmask
& ~HWE_MASK(statusValidNoEop
));
4818 qib_write_kreg_port(ppd
, krp_ibcctrl_a
,
4819 ppd
->cpspec
->ibcctrl_a
&
4820 ~SYM_MASK(IBCCtrlA_0
, IBLinkEn
));
4822 qib_write_kreg_port(ppd
, krp_ib_pcsconfig
, val
| reset_bits
);
4823 qib_read_kreg32(dd
, kr_scratch
);
4824 qib_write_kreg_port(ppd
, krp_ib_pcsconfig
, val
& ~reset_bits
);
4825 qib_write_kreg_port(ppd
, krp_ibcctrl_a
, ppd
->cpspec
->ibcctrl_a
);
4826 qib_write_kreg(dd
, kr_scratch
, 0ULL);
4827 qib_write_kreg(dd
, kr_hwerrclear
,
4828 SYM_MASK(HwErrClear
, statusValidNoEopClear
));
4829 qib_write_kreg(dd
, kr_hwerrmask
, dd
->cspec
->hwerrmask
);
4833 * This code for non-IBTA-compliant IB speed negotiation is only known to
4834 * work for the SDR to DDR transition, and only between an HCA and a switch
4835 * with recent firmware. It is based on observed heuristics, rather than
4836 * actual knowledge of the non-compliant speed negotiation.
4837 * It has a number of hard-coded fields, since the hope is to rewrite this
4838 * when a spec is available on how the negoation is intended to work.
4840 static void autoneg_7322_sendpkt(struct qib_pportdata
*ppd
, u32
*hdr
,
4841 u32 dcnt
, u32
*data
)
4845 u32 __iomem
*piobuf
;
4846 u32 pnum
, control
, len
;
4847 struct qib_devdata
*dd
= ppd
->dd
;
4850 len
= 7 + dcnt
+ 1; /* 7 dword header, dword data, icrc */
4851 control
= qib_7322_setpbc_control(ppd
, len
, 0, 15);
4852 pbc
= ((u64
) control
<< 32) | len
;
4853 while (!(piobuf
= qib_7322_getsendbuf(ppd
, pbc
, &pnum
))) {
4858 /* disable header check on this packet, since it can't be valid */
4859 dd
->f_txchk_change(dd
, pnum
, 1, TXCHK_CHG_TYPE_DIS1
, NULL
);
4860 writeq(pbc
, piobuf
);
4862 qib_pio_copy(piobuf
+ 2, hdr
, 7);
4863 qib_pio_copy(piobuf
+ 9, data
, dcnt
);
4864 if (dd
->flags
& QIB_USE_SPCL_TRIG
) {
4865 u32 spcl_off
= (pnum
>= dd
->piobcnt2k
) ? 2047 : 1023;
4868 __raw_writel(0xaebecede, piobuf
+ spcl_off
);
4871 qib_sendbuf_done(dd
, pnum
);
4872 /* and re-enable hdr check */
4873 dd
->f_txchk_change(dd
, pnum
, 1, TXCHK_CHG_TYPE_ENAB1
, NULL
);
4877 * _start packet gets sent twice at start, _done gets sent twice at end
4879 static void qib_autoneg_7322_send(struct qib_pportdata
*ppd
, int which
)
4881 struct qib_devdata
*dd
= ppd
->dd
;
4883 u32 dw
, i
, hcnt
, dcnt
, *data
;
4884 static u32 hdr
[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
4885 static u32 madpayload_start
[0x40] = {
4886 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4887 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4888 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
4890 static u32 madpayload_done
[0x40] = {
4891 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4892 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4893 0x40000001, 0x1388, 0x15e, /* rest 0's */
4896 dcnt
= ARRAY_SIZE(madpayload_start
);
4897 hcnt
= ARRAY_SIZE(hdr
);
4899 /* for maintainability, do it at runtime */
4900 for (i
= 0; i
< hcnt
; i
++) {
4901 dw
= (__force u32
) cpu_to_be32(hdr
[i
]);
4904 for (i
= 0; i
< dcnt
; i
++) {
4905 dw
= (__force u32
) cpu_to_be32(madpayload_start
[i
]);
4906 madpayload_start
[i
] = dw
;
4907 dw
= (__force u32
) cpu_to_be32(madpayload_done
[i
]);
4908 madpayload_done
[i
] = dw
;
4913 data
= which
? madpayload_done
: madpayload_start
;
4915 autoneg_7322_sendpkt(ppd
, hdr
, dcnt
, data
);
4916 qib_read_kreg64(dd
, kr_scratch
);
4918 autoneg_7322_sendpkt(ppd
, hdr
, dcnt
, data
);
4919 qib_read_kreg64(dd
, kr_scratch
);
4924 * Do the absolute minimum to cause an IB speed change, and make it
4925 * ready, but don't actually trigger the change. The caller will
4926 * do that when ready (if link is in Polling training state, it will
4927 * happen immediately, otherwise when link next goes down)
4929 * This routine should only be used as part of the DDR autonegotation
4930 * code for devices that are not compliant with IB 1.2 (or code that
4931 * fixes things up for same).
4933 * When link has gone down, and autoneg enabled, or autoneg has
4934 * failed and we give up until next time we set both speeds, and
4935 * then we want IBTA enabled as well as "use max enabled speed.
4937 static void set_7322_ibspeed_fast(struct qib_pportdata
*ppd
, u32 speed
)
4940 newctrlb
= ppd
->cpspec
->ibcctrl_b
& ~(IBA7322_IBC_SPEED_MASK
|
4941 IBA7322_IBC_IBTA_1_2_MASK
|
4942 IBA7322_IBC_MAX_SPEED_MASK
);
4944 if (speed
& (speed
- 1)) /* multiple speeds */
4945 newctrlb
|= (speed
<< IBA7322_IBC_SPEED_LSB
) |
4946 IBA7322_IBC_IBTA_1_2_MASK
|
4947 IBA7322_IBC_MAX_SPEED_MASK
;
4949 newctrlb
|= speed
== QIB_IB_QDR
?
4950 IBA7322_IBC_SPEED_QDR
| IBA7322_IBC_IBTA_1_2_MASK
:
4951 ((speed
== QIB_IB_DDR
?
4952 IBA7322_IBC_SPEED_DDR
: IBA7322_IBC_SPEED_SDR
));
4954 if (newctrlb
== ppd
->cpspec
->ibcctrl_b
)
4957 ppd
->cpspec
->ibcctrl_b
= newctrlb
;
4958 qib_write_kreg_port(ppd
, krp_ibcctrl_b
, ppd
->cpspec
->ibcctrl_b
);
4959 qib_write_kreg(ppd
->dd
, kr_scratch
, 0);
4963 * This routine is only used when we are not talking to another
4964 * IB 1.2-compliant device that we think can do DDR.
4965 * (This includes all existing switch chips as of Oct 2007.)
4966 * 1.2-compliant devices go directly to DDR prior to reaching INIT
4968 static void try_7322_autoneg(struct qib_pportdata
*ppd
)
4970 unsigned long flags
;
4972 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
4973 ppd
->lflags
|= QIBL_IB_AUTONEG_INPROG
;
4974 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
4975 qib_autoneg_7322_send(ppd
, 0);
4976 set_7322_ibspeed_fast(ppd
, QIB_IB_DDR
);
4977 qib_7322_mini_pcs_reset(ppd
);
4978 /* 2 msec is minimum length of a poll cycle */
4979 queue_delayed_work(ib_wq
, &ppd
->cpspec
->autoneg_work
,
4980 msecs_to_jiffies(2));
4984 * Handle the empirically determined mechanism for auto-negotiation
4985 * of DDR speed with switches.
4987 static void autoneg_7322_work(struct work_struct
*work
)
4989 struct qib_pportdata
*ppd
;
4990 struct qib_devdata
*dd
;
4993 unsigned long flags
;
4995 ppd
= container_of(work
, struct qib_chippport_specific
,
4996 autoneg_work
.work
)->ppd
;
4999 startms
= jiffies_to_msecs(jiffies
);
5002 * Busy wait for this first part, it should be at most a
5003 * few hundred usec, since we scheduled ourselves for 2msec.
5005 for (i
= 0; i
< 25; i
++) {
5006 if (SYM_FIELD(ppd
->lastibcstat
, IBCStatusA_0
, LinkState
)
5007 == IB_7322_LT_STATE_POLLQUIET
) {
5008 qib_set_linkstate(ppd
, QIB_IB_LINKDOWN_DISABLE
);
5014 if (!(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
))
5015 goto done
; /* we got there early or told to stop */
5017 /* we expect this to timeout */
5018 if (wait_event_timeout(ppd
->cpspec
->autoneg_wait
,
5019 !(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
),
5020 msecs_to_jiffies(90)))
5022 qib_7322_mini_pcs_reset(ppd
);
5024 /* we expect this to timeout */
5025 if (wait_event_timeout(ppd
->cpspec
->autoneg_wait
,
5026 !(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
),
5027 msecs_to_jiffies(1700)))
5029 qib_7322_mini_pcs_reset(ppd
);
5031 set_7322_ibspeed_fast(ppd
, QIB_IB_SDR
);
5034 * Wait up to 250 msec for link to train and get to INIT at DDR;
5035 * this should terminate early.
5037 wait_event_timeout(ppd
->cpspec
->autoneg_wait
,
5038 !(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
),
5039 msecs_to_jiffies(250));
5041 if (ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
) {
5042 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
5043 ppd
->lflags
&= ~QIBL_IB_AUTONEG_INPROG
;
5044 if (ppd
->cpspec
->autoneg_tries
== AUTONEG_TRIES
) {
5045 ppd
->lflags
|= QIBL_IB_AUTONEG_FAILED
;
5046 ppd
->cpspec
->autoneg_tries
= 0;
5048 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
5049 set_7322_ibspeed_fast(ppd
, ppd
->link_speed_enabled
);
5054 * This routine is used to request IPG set in the QLogic switch.
5055 * Only called if r1.
5057 static void try_7322_ipg(struct qib_pportdata
*ppd
)
5059 struct qib_ibport
*ibp
= &ppd
->ibport_data
;
5060 struct ib_mad_send_buf
*send_buf
;
5061 struct ib_mad_agent
*agent
;
5066 agent
= ibp
->send_agent
;
5070 send_buf
= ib_create_send_mad(agent
, 0, 0, 0, IB_MGMT_MAD_HDR
,
5071 IB_MGMT_MAD_DATA
, GFP_ATOMIC
);
5072 if (IS_ERR(send_buf
))
5076 struct ib_ah_attr attr
;
5079 memset(&attr
, 0, sizeof attr
);
5080 attr
.dlid
= be16_to_cpu(IB_LID_PERMISSIVE
);
5081 attr
.port_num
= ppd
->port
;
5082 ah
= ib_create_ah(ibp
->qp0
->ibqp
.pd
, &attr
);
5087 ibp
->smi_ah
= to_iah(ah
);
5091 send_buf
->ah
= &ibp
->smi_ah
->ibah
;
5095 smp
= send_buf
->mad
;
5096 smp
->base_version
= IB_MGMT_BASE_VERSION
;
5097 smp
->mgmt_class
= IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE
;
5098 smp
->class_version
= 1;
5099 smp
->method
= IB_MGMT_METHOD_SEND
;
5101 smp
->attr_id
= QIB_VENDOR_IPG
;
5105 ret
= ib_post_send_mad(send_buf
, NULL
);
5107 ib_free_send_mad(send_buf
);
5109 delay
= 2 << ppd
->cpspec
->ipg_tries
;
5110 queue_delayed_work(ib_wq
, &ppd
->cpspec
->ipg_work
,
5111 msecs_to_jiffies(delay
));
5115 * Timeout handler for setting IPG.
5116 * Only called if r1.
5118 static void ipg_7322_work(struct work_struct
*work
)
5120 struct qib_pportdata
*ppd
;
5122 ppd
= container_of(work
, struct qib_chippport_specific
,
5123 ipg_work
.work
)->ppd
;
5124 if ((ppd
->lflags
& (QIBL_LINKINIT
| QIBL_LINKARMED
| QIBL_LINKACTIVE
))
5125 && ++ppd
->cpspec
->ipg_tries
<= 10)
5129 static u32
qib_7322_iblink_state(u64 ibcs
)
5131 u32 state
= (u32
)SYM_FIELD(ibcs
, IBCStatusA_0
, LinkState
);
5134 case IB_7322_L_STATE_INIT
:
5135 state
= IB_PORT_INIT
;
5137 case IB_7322_L_STATE_ARM
:
5138 state
= IB_PORT_ARMED
;
5140 case IB_7322_L_STATE_ACTIVE
:
5142 case IB_7322_L_STATE_ACT_DEFER
:
5143 state
= IB_PORT_ACTIVE
;
5145 default: /* fall through */
5146 case IB_7322_L_STATE_DOWN
:
5147 state
= IB_PORT_DOWN
;
5153 /* returns the IBTA port state, rather than the IBC link training state */
5154 static u8
qib_7322_phys_portstate(u64 ibcs
)
5156 u8 state
= (u8
)SYM_FIELD(ibcs
, IBCStatusA_0
, LinkTrainingState
);
5157 return qib_7322_physportstate
[state
];
5160 static int qib_7322_ib_updown(struct qib_pportdata
*ppd
, int ibup
, u64 ibcs
)
5162 int ret
= 0, symadj
= 0;
5163 unsigned long flags
;
5166 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
5167 ppd
->lflags
&= ~QIBL_IB_FORCE_NOTIFY
;
5168 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
5170 /* Update our picture of width and speed from chip */
5171 if (ibcs
& SYM_MASK(IBCStatusA_0
, LinkSpeedQDR
)) {
5172 ppd
->link_speed_active
= QIB_IB_QDR
;
5174 } else if (ibcs
& SYM_MASK(IBCStatusA_0
, LinkSpeedActive
)) {
5175 ppd
->link_speed_active
= QIB_IB_DDR
;
5178 ppd
->link_speed_active
= QIB_IB_SDR
;
5181 if (ibcs
& SYM_MASK(IBCStatusA_0
, LinkWidthActive
)) {
5182 ppd
->link_width_active
= IB_WIDTH_4X
;
5185 ppd
->link_width_active
= IB_WIDTH_1X
;
5186 ppd
->delay_mult
= ib_rate_to_delay
[mult_to_ib_rate(mult
)];
5191 /* Link went down. */
5192 /* do IPG MAD again after linkdown, even if last time failed */
5193 ppd
->cpspec
->ipg_tries
= 0;
5194 clr
= qib_read_kreg_port(ppd
, krp_ibcstatus_b
) &
5195 (SYM_MASK(IBCStatusB_0
, heartbeat_timed_out
) |
5196 SYM_MASK(IBCStatusB_0
, heartbeat_crosstalk
));
5198 qib_write_kreg_port(ppd
, krp_ibcstatus_b
, clr
);
5199 if (!(ppd
->lflags
& (QIBL_IB_AUTONEG_FAILED
|
5200 QIBL_IB_AUTONEG_INPROG
)))
5201 set_7322_ibspeed_fast(ppd
, ppd
->link_speed_enabled
);
5202 if (!(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
)) {
5203 /* unlock the Tx settings, speed may change */
5204 qib_write_kreg_port(ppd
, krp_tx_deemph_override
,
5205 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0
,
5206 reset_tx_deemphasis_override
));
5207 qib_cancel_sends(ppd
);
5208 /* on link down, ensure sane pcs state */
5209 qib_7322_mini_pcs_reset(ppd
);
5210 spin_lock_irqsave(&ppd
->sdma_lock
, flags
);
5211 if (__qib_sdma_running(ppd
))
5212 __qib_sdma_process_event(ppd
,
5213 qib_sdma_event_e70_go_idle
);
5214 spin_unlock_irqrestore(&ppd
->sdma_lock
, flags
);
5216 clr
= read_7322_creg32_port(ppd
, crp_iblinkdown
);
5217 if (clr
== ppd
->cpspec
->iblnkdownsnap
)
5218 ppd
->cpspec
->iblnkdowndelta
++;
5220 if (qib_compat_ddr_negotiate
&&
5221 !(ppd
->lflags
& (QIBL_IB_AUTONEG_FAILED
|
5222 QIBL_IB_AUTONEG_INPROG
)) &&
5223 ppd
->link_speed_active
== QIB_IB_SDR
&&
5224 (ppd
->link_speed_enabled
& QIB_IB_DDR
)
5225 && ppd
->cpspec
->autoneg_tries
< AUTONEG_TRIES
) {
5226 /* we are SDR, and auto-negotiation enabled */
5227 ++ppd
->cpspec
->autoneg_tries
;
5228 if (!ppd
->cpspec
->ibdeltainprog
) {
5229 ppd
->cpspec
->ibdeltainprog
= 1;
5230 ppd
->cpspec
->ibsymdelta
+=
5231 read_7322_creg32_port(ppd
,
5233 ppd
->cpspec
->ibsymsnap
;
5234 ppd
->cpspec
->iblnkerrdelta
+=
5235 read_7322_creg32_port(ppd
,
5236 crp_iblinkerrrecov
) -
5237 ppd
->cpspec
->iblnkerrsnap
;
5239 try_7322_autoneg(ppd
);
5240 ret
= 1; /* no other IB status change processing */
5241 } else if ((ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
) &&
5242 ppd
->link_speed_active
== QIB_IB_SDR
) {
5243 qib_autoneg_7322_send(ppd
, 1);
5244 set_7322_ibspeed_fast(ppd
, QIB_IB_DDR
);
5245 qib_7322_mini_pcs_reset(ppd
);
5247 ret
= 1; /* no other IB status change processing */
5248 } else if ((ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
) &&
5249 (ppd
->link_speed_active
& QIB_IB_DDR
)) {
5250 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
5251 ppd
->lflags
&= ~(QIBL_IB_AUTONEG_INPROG
|
5252 QIBL_IB_AUTONEG_FAILED
);
5253 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
5254 ppd
->cpspec
->autoneg_tries
= 0;
5255 /* re-enable SDR, for next link down */
5256 set_7322_ibspeed_fast(ppd
, ppd
->link_speed_enabled
);
5257 wake_up(&ppd
->cpspec
->autoneg_wait
);
5259 } else if (ppd
->lflags
& QIBL_IB_AUTONEG_FAILED
) {
5261 * Clear autoneg failure flag, and do setup
5262 * so we'll try next time link goes down and
5263 * back to INIT (possibly connected to a
5264 * different device).
5266 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
5267 ppd
->lflags
&= ~QIBL_IB_AUTONEG_FAILED
;
5268 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
5269 ppd
->cpspec
->ibcctrl_b
|= IBA7322_IBC_IBTA_1_2_MASK
;
5272 if (!(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
)) {
5274 if (ppd
->dd
->cspec
->r1
&& ppd
->cpspec
->ipg_tries
<= 10)
5276 if (!ppd
->cpspec
->recovery_init
)
5277 setup_7322_link_recovery(ppd
, 0);
5278 ppd
->cpspec
->qdr_dfe_time
= jiffies
+
5279 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY
);
5281 ppd
->cpspec
->ibmalfusesnap
= 0;
5282 ppd
->cpspec
->ibmalfsnap
= read_7322_creg32_port(ppd
,
5286 ppd
->cpspec
->iblnkdownsnap
=
5287 read_7322_creg32_port(ppd
, crp_iblinkdown
);
5288 if (ppd
->cpspec
->ibdeltainprog
) {
5289 ppd
->cpspec
->ibdeltainprog
= 0;
5290 ppd
->cpspec
->ibsymdelta
+= read_7322_creg32_port(ppd
,
5291 crp_ibsymbolerr
) - ppd
->cpspec
->ibsymsnap
;
5292 ppd
->cpspec
->iblnkerrdelta
+= read_7322_creg32_port(ppd
,
5293 crp_iblinkerrrecov
) - ppd
->cpspec
->iblnkerrsnap
;
5295 } else if (!ibup
&& qib_compat_ddr_negotiate
&&
5296 !ppd
->cpspec
->ibdeltainprog
&&
5297 !(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
)) {
5298 ppd
->cpspec
->ibdeltainprog
= 1;
5299 ppd
->cpspec
->ibsymsnap
= read_7322_creg32_port(ppd
,
5301 ppd
->cpspec
->iblnkerrsnap
= read_7322_creg32_port(ppd
,
5302 crp_iblinkerrrecov
);
5306 qib_setup_7322_setextled(ppd
, ibup
);
5311 * Does read/modify/write to appropriate registers to
5312 * set output and direction bits selected by mask.
5313 * these are in their canonical postions (e.g. lsb of
5314 * dir will end up in D48 of extctrl on existing chips).
5315 * returns contents of GP Inputs.
5317 static int gpio_7322_mod(struct qib_devdata
*dd
, u32 out
, u32 dir
, u32 mask
)
5319 u64 read_val
, new_out
;
5320 unsigned long flags
;
5323 /* some bits being written, lock access to GPIO */
5326 spin_lock_irqsave(&dd
->cspec
->gpio_lock
, flags
);
5327 dd
->cspec
->extctrl
&= ~((u64
)mask
<< SYM_LSB(EXTCtrl
, GPIOOe
));
5328 dd
->cspec
->extctrl
|= ((u64
) dir
<< SYM_LSB(EXTCtrl
, GPIOOe
));
5329 new_out
= (dd
->cspec
->gpio_out
& ~mask
) | out
;
5331 qib_write_kreg(dd
, kr_extctrl
, dd
->cspec
->extctrl
);
5332 qib_write_kreg(dd
, kr_gpio_out
, new_out
);
5333 dd
->cspec
->gpio_out
= new_out
;
5334 spin_unlock_irqrestore(&dd
->cspec
->gpio_lock
, flags
);
5337 * It is unlikely that a read at this time would get valid
5338 * data on a pin whose direction line was set in the same
5339 * call to this function. We include the read here because
5340 * that allows us to potentially combine a change on one pin with
5341 * a read on another, and because the old code did something like
5344 read_val
= qib_read_kreg64(dd
, kr_extstatus
);
5345 return SYM_FIELD(read_val
, EXTStatus
, GPIOIn
);
5348 /* Enable writes to config EEPROM, if possible. Returns previous state */
5349 static int qib_7322_eeprom_wen(struct qib_devdata
*dd
, int wen
)
5354 mask
= 1 << QIB_EEPROM_WEN_NUM
;
5355 prev_wen
= ~gpio_7322_mod(dd
, 0, 0, 0) >> QIB_EEPROM_WEN_NUM
;
5356 gpio_7322_mod(dd
, wen
? 0 : mask
, mask
, mask
);
5358 return prev_wen
& 1;
5362 * Read fundamental info we need to use the chip. These are
5363 * the registers that describe chip capabilities, and are
5364 * saved in shadow registers.
5366 static void get_7322_chip_params(struct qib_devdata
*dd
)
5372 dd
->palign
= qib_read_kreg32(dd
, kr_pagealign
);
5374 dd
->uregbase
= qib_read_kreg32(dd
, kr_userregbase
);
5376 dd
->rcvtidcnt
= qib_read_kreg32(dd
, kr_rcvtidcnt
);
5377 dd
->rcvtidbase
= qib_read_kreg32(dd
, kr_rcvtidbase
);
5378 dd
->rcvegrbase
= qib_read_kreg32(dd
, kr_rcvegrbase
);
5379 dd
->piobufbase
= qib_read_kreg64(dd
, kr_sendpiobufbase
);
5380 dd
->pio2k_bufbase
= dd
->piobufbase
& 0xffffffff;
5382 val
= qib_read_kreg64(dd
, kr_sendpiobufcnt
);
5383 dd
->piobcnt2k
= val
& ~0U;
5384 dd
->piobcnt4k
= val
>> 32;
5385 val
= qib_read_kreg64(dd
, kr_sendpiosize
);
5386 dd
->piosize2k
= val
& ~0U;
5387 dd
->piosize4k
= val
>> 32;
5389 mtu
= ib_mtu_enum_to_int(qib_ibmtu
);
5391 mtu
= QIB_DEFAULT_MTU
;
5392 dd
->pport
[0].ibmtu
= (u32
)mtu
;
5393 dd
->pport
[1].ibmtu
= (u32
)mtu
;
5395 /* these may be adjusted in init_chip_wc_pat() */
5396 dd
->pio2kbase
= (u32 __iomem
*)
5397 ((char __iomem
*) dd
->kregbase
+ dd
->pio2k_bufbase
);
5398 dd
->pio4kbase
= (u32 __iomem
*)
5399 ((char __iomem
*) dd
->kregbase
+
5400 (dd
->piobufbase
>> 32));
5402 * 4K buffers take 2 pages; we use roundup just to be
5403 * paranoid; we calculate it once here, rather than on
5406 dd
->align4k
= ALIGN(dd
->piosize4k
, dd
->palign
);
5408 piobufs
= dd
->piobcnt4k
+ dd
->piobcnt2k
+ NUM_VL15_BUFS
;
5410 dd
->pioavregs
= ALIGN(piobufs
, sizeof(u64
) * BITS_PER_BYTE
/ 2) /
5411 (sizeof(u64
) * BITS_PER_BYTE
/ 2);
5415 * The chip base addresses in cspec and cpspec have to be set
5416 * after possible init_chip_wc_pat(), rather than in
5417 * get_7322_chip_params(), so split out as separate function
5419 static void qib_7322_set_baseaddrs(struct qib_devdata
*dd
)
5422 cregbase
= qib_read_kreg32(dd
, kr_counterregbase
);
5424 dd
->cspec
->cregbase
= (u64 __iomem
*)(cregbase
+
5425 (char __iomem
*)dd
->kregbase
);
5427 dd
->egrtidbase
= (u64 __iomem
*)
5428 ((char __iomem
*) dd
->kregbase
+ dd
->rcvegrbase
);
5430 /* port registers are defined as relative to base of chip */
5431 dd
->pport
[0].cpspec
->kpregbase
=
5432 (u64 __iomem
*)((char __iomem
*)dd
->kregbase
);
5433 dd
->pport
[1].cpspec
->kpregbase
=
5434 (u64 __iomem
*)(dd
->palign
+
5435 (char __iomem
*)dd
->kregbase
);
5436 dd
->pport
[0].cpspec
->cpregbase
=
5437 (u64 __iomem
*)(qib_read_kreg_port(&dd
->pport
[0],
5438 kr_counterregbase
) + (char __iomem
*)dd
->kregbase
);
5439 dd
->pport
[1].cpspec
->cpregbase
=
5440 (u64 __iomem
*)(qib_read_kreg_port(&dd
->pport
[1],
5441 kr_counterregbase
) + (char __iomem
*)dd
->kregbase
);
5445 * This is a fairly special-purpose observer, so we only support
5446 * the port-specific parts of SendCtrl
5449 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5450 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5451 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5452 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5453 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5454 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5455 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5457 static int sendctrl_hook(struct qib_devdata
*dd
,
5458 const struct diag_observer
*op
, u32 offs
,
5459 u64
*data
, u64 mask
, int only_32
)
5461 unsigned long flags
;
5464 struct qib_pportdata
*ppd
= NULL
;
5465 u64 local_data
, all_bits
;
5468 * The fixed correspondence between Physical ports and pports is
5469 * severed. We need to hunt for the ppd that corresponds
5470 * to the offset we got. And we have to do that without admitting
5471 * we know the stride, apparently.
5473 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
5477 ppd
= dd
->pport
+ pidx
;
5478 if (!ppd
->cpspec
->kpregbase
)
5481 psptr
= ppd
->cpspec
->kpregbase
+ krp_sendctrl
;
5482 psoffs
= (u32
) (psptr
- dd
->kregbase
) * sizeof(*psptr
);
5487 /* If pport is not being managed by driver, just avoid shadows. */
5488 if (pidx
>= dd
->num_pports
)
5491 /* In any case, "idx" is flat index in kreg space */
5492 idx
= offs
/ sizeof(u64
);
5498 spin_lock_irqsave(&dd
->sendctrl_lock
, flags
);
5499 if (!ppd
|| (mask
& all_bits
) != all_bits
) {
5501 * At least some mask bits are zero, so we need
5502 * to read. The judgement call is whether from
5503 * reg or shadow. First-cut: read reg, and complain
5504 * if any bits which should be shadowed are different
5505 * from their shadowed value.
5508 local_data
= (u64
)qib_read_kreg32(dd
, idx
);
5510 local_data
= qib_read_kreg64(dd
, idx
);
5511 *data
= (local_data
& ~mask
) | (*data
& mask
);
5515 * At least some mask bits are one, so we need
5516 * to write, but only shadow some bits.
5518 u64 sval
, tval
; /* Shadowed, transient */
5521 * New shadow val is bits we don't want to touch,
5522 * ORed with bits we do, that are intended for shadow.
5525 sval
= ppd
->p_sendctrl
& ~mask
;
5526 sval
|= *data
& SENDCTRL_SHADOWED
& mask
;
5527 ppd
->p_sendctrl
= sval
;
5529 sval
= *data
& SENDCTRL_SHADOWED
& mask
;
5530 tval
= sval
| (*data
& ~SENDCTRL_SHADOWED
& mask
);
5531 qib_write_kreg(dd
, idx
, tval
);
5532 qib_write_kreg(dd
, kr_scratch
, 0Ull);
5534 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
5535 return only_32
? 4 : 8;
5538 static const struct diag_observer sendctrl_0_observer
= {
5539 sendctrl_hook
, KREG_IDX(SendCtrl_0
) * sizeof(u64
),
5540 KREG_IDX(SendCtrl_0
) * sizeof(u64
)
5543 static const struct diag_observer sendctrl_1_observer
= {
5544 sendctrl_hook
, KREG_IDX(SendCtrl_1
) * sizeof(u64
),
5545 KREG_IDX(SendCtrl_1
) * sizeof(u64
)
5548 static ushort sdma_fetch_prio
= 8;
5549 module_param_named(sdma_fetch_prio
, sdma_fetch_prio
, ushort
, S_IRUGO
);
5550 MODULE_PARM_DESC(sdma_fetch_prio
, "SDMA descriptor fetch priority");
5552 /* Besides logging QSFP events, we set appropriate TxDDS values */
5553 static void init_txdds_table(struct qib_pportdata
*ppd
, int override
);
5555 static void qsfp_7322_event(struct work_struct
*work
)
5557 struct qib_qsfp_data
*qd
;
5558 struct qib_pportdata
*ppd
;
5563 qd
= container_of(work
, struct qib_qsfp_data
, work
);
5565 pwrup
= qd
->t_insert
+ msecs_to_jiffies(QSFP_PWR_LAG_MSEC
);
5568 * Some QSFP's not only do not respond until the full power-up
5569 * time, but may behave badly if we try. So hold off responding
5573 u64 now
= get_jiffies_64();
5574 if (time_after64(now
, pwrup
))
5578 ret
= qib_refresh_qsfp_cache(ppd
, &qd
->cache
);
5580 * Need to change LE2 back to defaults if we couldn't
5581 * read the cable type (to handle cable swaps), so do this
5582 * even on failure to read cable information. We don't
5583 * get here for QME, so IS_QME check not needed here.
5585 if (!ret
&& !ppd
->dd
->cspec
->r1
) {
5586 if (QSFP_IS_ACTIVE_FAR(qd
->cache
.tech
))
5588 else if (qd
->cache
.atten
[1] >= qib_long_atten
&&
5589 QSFP_IS_CU(qd
->cache
.tech
))
5595 ibsd_wr_allchans(ppd
, 13, (le2
<< 7), BMASK(9, 7));
5596 init_txdds_table(ppd
, 0);
5600 * There is little we can do but complain to the user if QSFP
5601 * initialization fails.
5603 static void qib_init_7322_qsfp(struct qib_pportdata
*ppd
)
5605 unsigned long flags
;
5606 struct qib_qsfp_data
*qd
= &ppd
->cpspec
->qsfp_data
;
5607 struct qib_devdata
*dd
= ppd
->dd
;
5608 u64 mod_prs_bit
= QSFP_GPIO_MOD_PRS_N
;
5610 mod_prs_bit
<<= (QSFP_GPIO_PORT2_SHIFT
* ppd
->hw_pidx
);
5612 qib_qsfp_init(qd
, qsfp_7322_event
);
5613 spin_lock_irqsave(&dd
->cspec
->gpio_lock
, flags
);
5614 dd
->cspec
->extctrl
|= (mod_prs_bit
<< SYM_LSB(EXTCtrl
, GPIOInvert
));
5615 dd
->cspec
->gpio_mask
|= mod_prs_bit
;
5616 qib_write_kreg(dd
, kr_extctrl
, dd
->cspec
->extctrl
);
5617 qib_write_kreg(dd
, kr_gpio_mask
, dd
->cspec
->gpio_mask
);
5618 spin_unlock_irqrestore(&dd
->cspec
->gpio_lock
, flags
);
5622 * called at device initialization time, and also if the txselect
5623 * module parameter is changed. This is used for cables that don't
5624 * have valid QSFP EEPROMs (not present, or attenuation is zero).
5625 * We initialize to the default, then if there is a specific
5626 * unit,port match, we use that (and set it immediately, for the
5627 * current speed, if the link is at INIT or better).
5628 * String format is "default# unit#,port#=# ... u,p=#", separators must
5629 * be a SPACE character. A newline terminates. The u,p=# tuples may
5630 * optionally have "u,p=#,#", where the final # is the H1 value
5631 * The last specific match is used (actually, all are used, but last
5632 * one is the one that winds up set); if none at all, fall back on default.
5634 static void set_no_qsfp_atten(struct qib_devdata
*dd
, int change
)
5637 u32 pidx
, unit
, port
, deflt
, h1
;
5642 str
= txselect_list
;
5644 /* default number is validated in setup_txselect() */
5645 deflt
= simple_strtoul(str
, &nxt
, 0);
5646 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
)
5647 dd
->pport
[pidx
].cpspec
->no_eep
= deflt
;
5649 txdds_size
= TXDDS_TABLE_SZ
+ TXDDS_EXTRA_SZ
;
5650 if (IS_QME(dd
) || IS_QMH(dd
))
5651 txdds_size
+= TXDDS_MFG_SZ
;
5653 while (*nxt
&& nxt
[1]) {
5655 unit
= simple_strtoul(str
, &nxt
, 0);
5656 if (nxt
== str
|| !*nxt
|| *nxt
!= ',') {
5657 while (*nxt
&& *nxt
++ != ' ') /* skip to next, if any */
5662 port
= simple_strtoul(str
, &nxt
, 0);
5663 if (nxt
== str
|| *nxt
!= '=') {
5664 while (*nxt
&& *nxt
++ != ' ') /* skip to next, if any */
5669 val
= simple_strtoul(str
, &nxt
, 0);
5671 while (*nxt
&& *nxt
++ != ' ') /* skip to next, if any */
5675 if (val
>= txdds_size
)
5678 h1
= 0; /* gcc thinks it might be used uninitted */
5679 if (*nxt
== ',' && nxt
[1]) {
5681 h1
= (u32
)simple_strtoul(str
, &nxt
, 0);
5683 while (*nxt
&& *nxt
++ != ' ') /* skip */
5688 for (pidx
= 0; dd
->unit
== unit
&& pidx
< dd
->num_pports
;
5690 struct qib_pportdata
*ppd
= &dd
->pport
[pidx
];
5692 if (ppd
->port
!= port
|| !ppd
->link_speed_supported
)
5694 ppd
->cpspec
->no_eep
= val
;
5696 ppd
->cpspec
->h1_val
= h1
;
5697 /* now change the IBC and serdes, overriding generic */
5698 init_txdds_table(ppd
, 1);
5699 /* Re-enable the physical state machine on mezz boards
5700 * now that the correct settings have been set. */
5701 if (IS_QMH(dd
) || IS_QME(dd
))
5702 qib_set_ib_7322_lstate(ppd
, 0,
5703 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP
);
5709 if (change
&& !any
) {
5710 /* no specific setting, use the default.
5711 * Change the IBC and serdes, but since it's
5712 * general, don't override specific settings.
5714 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
)
5715 if (dd
->pport
[pidx
].link_speed_supported
)
5716 init_txdds_table(&dd
->pport
[pidx
], 0);
5720 /* handle the txselect parameter changing */
5721 static int setup_txselect(const char *str
, struct kernel_param
*kp
)
5723 struct qib_devdata
*dd
;
5726 if (strlen(str
) >= MAX_ATTEN_LEN
) {
5727 printk(KERN_INFO QIB_DRV_NAME
" txselect_values string "
5731 val
= simple_strtoul(str
, &n
, 0);
5732 if (n
== str
|| val
>= (TXDDS_TABLE_SZ
+ TXDDS_EXTRA_SZ
+
5734 printk(KERN_INFO QIB_DRV_NAME
5735 "txselect_values must start with a number < %d\n",
5736 TXDDS_TABLE_SZ
+ TXDDS_EXTRA_SZ
+ TXDDS_MFG_SZ
);
5739 strcpy(txselect_list
, str
);
5741 list_for_each_entry(dd
, &qib_dev_list
, list
)
5742 if (dd
->deviceid
== PCI_DEVICE_ID_QLOGIC_IB_7322
)
5743 set_no_qsfp_atten(dd
, 1);
5748 * Write the final few registers that depend on some of the
5749 * init setup. Done late in init, just before bringing up
5752 static int qib_late_7322_initreg(struct qib_devdata
*dd
)
5757 qib_write_kreg(dd
, kr_rcvhdrentsize
, dd
->rcvhdrentsize
);
5758 qib_write_kreg(dd
, kr_rcvhdrsize
, dd
->rcvhdrsize
);
5759 qib_write_kreg(dd
, kr_rcvhdrcnt
, dd
->rcvhdrcnt
);
5760 qib_write_kreg(dd
, kr_sendpioavailaddr
, dd
->pioavailregs_phys
);
5761 val
= qib_read_kreg64(dd
, kr_sendpioavailaddr
);
5762 if (val
!= dd
->pioavailregs_phys
) {
5763 qib_dev_err(dd
, "Catastrophic software error, "
5764 "SendPIOAvailAddr written as %lx, "
5765 "read back as %llx\n",
5766 (unsigned long) dd
->pioavailregs_phys
,
5767 (unsigned long long) val
);
5771 n
= dd
->piobcnt2k
+ dd
->piobcnt4k
+ NUM_VL15_BUFS
;
5772 qib_7322_txchk_change(dd
, 0, n
, TXCHK_CHG_TYPE_KERN
, NULL
);
5773 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
5774 qib_7322_txchk_change(dd
, 0, n
, TXCHK_CHG_TYPE_ENAB1
, NULL
);
5776 qib_register_observer(dd
, &sendctrl_0_observer
);
5777 qib_register_observer(dd
, &sendctrl_1_observer
);
5779 dd
->control
&= ~QLOGIC_IB_C_SDMAFETCHPRIOEN
;
5780 qib_write_kreg(dd
, kr_control
, dd
->control
);
5782 * Set SendDmaFetchPriority and init Tx params, including
5783 * QSFP handler on boards that have QSFP.
5784 * First set our default attenuation entry for cables that
5785 * don't have valid attenuation.
5787 set_no_qsfp_atten(dd
, 0);
5788 for (n
= 0; n
< dd
->num_pports
; ++n
) {
5789 struct qib_pportdata
*ppd
= dd
->pport
+ n
;
5791 qib_write_kreg_port(ppd
, krp_senddmaprioritythld
,
5792 sdma_fetch_prio
& 0xf);
5793 /* Initialize qsfp if present on board. */
5794 if (dd
->flags
& QIB_HAS_QSFP
)
5795 qib_init_7322_qsfp(ppd
);
5797 dd
->control
|= QLOGIC_IB_C_SDMAFETCHPRIOEN
;
5798 qib_write_kreg(dd
, kr_control
, dd
->control
);
5803 /* per IB port errors. */
5804 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
5806 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
5807 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
5808 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
5812 * Write the initialization per-port registers that need to be done at
5813 * driver load and after reset completes (i.e., that aren't done as part
5814 * of other init procedures called from qib_init.c).
5815 * Some of these should be redundant on reset, but play safe.
5817 static void write_7322_init_portregs(struct qib_pportdata
*ppd
)
5822 if (!ppd
->link_speed_supported
) {
5823 /* no buffer credits for this port */
5824 for (i
= 1; i
< 8; i
++)
5825 qib_write_kreg_port(ppd
, krp_rxcreditvl0
+ i
, 0);
5826 qib_write_kreg_port(ppd
, krp_ibcctrl_b
, 0);
5827 qib_write_kreg(ppd
->dd
, kr_scratch
, 0);
5832 * Set the number of supported virtual lanes in IBC,
5833 * for flow control packet handling on unsupported VLs
5835 val
= qib_read_kreg_port(ppd
, krp_ibsdtestiftx
);
5836 val
&= ~SYM_MASK(IB_SDTEST_IF_TX_0
, VL_CAP
);
5837 val
|= (u64
)(ppd
->vls_supported
- 1) <<
5838 SYM_LSB(IB_SDTEST_IF_TX_0
, VL_CAP
);
5839 qib_write_kreg_port(ppd
, krp_ibsdtestiftx
, val
);
5841 qib_write_kreg_port(ppd
, krp_rcvbthqp
, QIB_KD_QP
);
5843 /* enable tx header checking */
5844 qib_write_kreg_port(ppd
, krp_sendcheckcontrol
, IBA7322_SENDCHK_PKEY
|
5845 IBA7322_SENDCHK_BTHQP
| IBA7322_SENDCHK_SLID
|
5846 IBA7322_SENDCHK_RAW_IPV6
| IBA7322_SENDCHK_MINSZ
);
5848 qib_write_kreg_port(ppd
, krp_ncmodectrl
,
5849 SYM_MASK(IBNCModeCtrl_0
, ScrambleCapLocal
));
5852 * Unconditionally clear the bufmask bits. If SDMA is
5853 * enabled, we'll set them appropriately later.
5855 qib_write_kreg_port(ppd
, krp_senddmabufmask0
, 0);
5856 qib_write_kreg_port(ppd
, krp_senddmabufmask1
, 0);
5857 qib_write_kreg_port(ppd
, krp_senddmabufmask2
, 0);
5858 if (ppd
->dd
->cspec
->r1
)
5859 ppd
->p_sendctrl
|= SYM_MASK(SendCtrl_0
, ForceCreditUpToDate
);
5863 * Write the initialization per-device registers that need to be done at
5864 * driver load and after reset completes (i.e., that aren't done as part
5865 * of other init procedures called from qib_init.c). Also write per-port
5866 * registers that are affected by overall device config, such as QP mapping
5867 * Some of these should be redundant on reset, but play safe.
5869 static void write_7322_initregs(struct qib_devdata
*dd
)
5871 struct qib_pportdata
*ppd
;
5875 /* Set Multicast QPs received by port 2 to map to context one. */
5876 qib_write_kreg(dd
, KREG_IDX(RcvQPMulticastContext_1
), 1);
5878 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
5880 unsigned long flags
;
5882 if (dd
->n_krcv_queues
< 2 ||
5883 !dd
->pport
[pidx
].link_speed_supported
)
5886 ppd
= &dd
->pport
[pidx
];
5888 /* be paranoid against later code motion, etc. */
5889 spin_lock_irqsave(&dd
->cspec
->rcvmod_lock
, flags
);
5890 ppd
->p_rcvctrl
|= SYM_MASK(RcvCtrl_0
, RcvQPMapEnable
);
5891 spin_unlock_irqrestore(&dd
->cspec
->rcvmod_lock
, flags
);
5893 /* Initialize QP to context mapping */
5894 regno
= krp_rcvqpmaptable
;
5896 if (dd
->num_pports
> 1)
5897 n
= dd
->first_user_ctxt
/ dd
->num_pports
;
5899 n
= dd
->first_user_ctxt
- 1;
5900 for (i
= 0; i
< 32; ) {
5903 if (dd
->num_pports
> 1)
5904 ctxt
= (i
% n
) * dd
->num_pports
+ pidx
;
5908 ctxt
= ppd
->hw_pidx
;
5909 val
|= ctxt
<< (5 * (i
% 6));
5912 qib_write_kreg_port(ppd
, regno
, val
);
5917 qib_write_kreg_port(ppd
, regno
, val
);
5921 * Setup up interrupt mitigation for kernel contexts, but
5922 * not user contexts (user contexts use interrupts when
5923 * stalled waiting for any packet, so want those interrupts
5926 for (i
= 0; i
< dd
->first_user_ctxt
; i
++) {
5927 dd
->cspec
->rcvavail_timeout
[i
] = rcv_int_timeout
;
5928 qib_write_kreg(dd
, kr_rcvavailtimeout
+ i
, rcv_int_timeout
);
5932 * Initialize as (disabled) rcvflow tables. Application code
5933 * will setup each flow as it uses the flow.
5934 * Doesn't clear any of the error bits that might be set.
5936 val
= TIDFLOW_ERRBITS
; /* these are W1C */
5937 for (i
= 0; i
< dd
->cfgctxts
; i
++) {
5939 for (flow
= 0; flow
< NUM_TIDFLOWS_CTXT
; flow
++)
5940 qib_write_ureg(dd
, ur_rcvflowtable
+flow
, val
, i
);
5944 * dual cards init to dual port recovery, single port cards to
5945 * the one port. Dual port cards may later adjust to 1 port,
5946 * and then back to dual port if both ports are connected
5949 setup_7322_link_recovery(dd
->pport
, dd
->num_pports
> 1);
5952 static int qib_init_7322_variables(struct qib_devdata
*dd
)
5954 struct qib_pportdata
*ppd
;
5955 unsigned features
, pidx
, sbufcnt
;
5957 u32 sbufs
, updthresh
;
5959 /* pport structs are contiguous, allocated after devdata */
5960 ppd
= (struct qib_pportdata
*)(dd
+ 1);
5965 dd
->cspec
= (struct qib_chip_specific
*)(ppd
+ 2);
5967 ppd
[0].cpspec
= (struct qib_chippport_specific
*)(dd
->cspec
+ 1);
5968 ppd
[1].cpspec
= &ppd
[0].cpspec
[1];
5969 ppd
[0].cpspec
->ppd
= &ppd
[0]; /* for autoneg_7322_work() */
5970 ppd
[1].cpspec
->ppd
= &ppd
[1]; /* for autoneg_7322_work() */
5972 spin_lock_init(&dd
->cspec
->rcvmod_lock
);
5973 spin_lock_init(&dd
->cspec
->gpio_lock
);
5975 /* we haven't yet set QIB_PRESENT, so use read directly */
5976 dd
->revision
= readq(&dd
->kregbase
[kr_revision
]);
5978 if ((dd
->revision
& 0xffffffffU
) == 0xffffffffU
) {
5979 qib_dev_err(dd
, "Revision register read failure, "
5980 "giving up initialization\n");
5984 dd
->flags
|= QIB_PRESENT
; /* now register routines work */
5986 dd
->majrev
= (u8
) SYM_FIELD(dd
->revision
, Revision_R
, ChipRevMajor
);
5987 dd
->minrev
= (u8
) SYM_FIELD(dd
->revision
, Revision_R
, ChipRevMinor
);
5988 dd
->cspec
->r1
= dd
->minrev
== 1;
5990 get_7322_chip_params(dd
);
5991 features
= qib_7322_boardname(dd
);
5993 /* now that piobcnt2k and 4k set, we can allocate these */
5994 sbufcnt
= dd
->piobcnt2k
+ dd
->piobcnt4k
+
5995 NUM_VL15_BUFS
+ BITS_PER_LONG
- 1;
5996 sbufcnt
/= BITS_PER_LONG
;
5997 dd
->cspec
->sendchkenable
= kmalloc(sbufcnt
*
5998 sizeof(*dd
->cspec
->sendchkenable
), GFP_KERNEL
);
5999 dd
->cspec
->sendgrhchk
= kmalloc(sbufcnt
*
6000 sizeof(*dd
->cspec
->sendgrhchk
), GFP_KERNEL
);
6001 dd
->cspec
->sendibchk
= kmalloc(sbufcnt
*
6002 sizeof(*dd
->cspec
->sendibchk
), GFP_KERNEL
);
6003 if (!dd
->cspec
->sendchkenable
|| !dd
->cspec
->sendgrhchk
||
6004 !dd
->cspec
->sendibchk
) {
6005 qib_dev_err(dd
, "Failed allocation for hdrchk bitmaps\n");
6013 * GPIO bits for TWSI data and clock,
6014 * used for serial EEPROM.
6016 dd
->gpio_sda_num
= _QIB_GPIO_SDA_NUM
;
6017 dd
->gpio_scl_num
= _QIB_GPIO_SCL_NUM
;
6018 dd
->twsi_eeprom_dev
= QIB_TWSI_EEPROM_DEV
;
6020 dd
->flags
|= QIB_HAS_INTX
| QIB_HAS_LINK_LATENCY
|
6021 QIB_NODMA_RTAIL
| QIB_HAS_VLSUPP
| QIB_HAS_HDRSUPP
|
6022 QIB_HAS_THRESH_UPDATE
|
6023 (sdma_idle_cnt
? QIB_HAS_SDMA_TIMEOUT
: 0);
6024 dd
->flags
|= qib_special_trigger
?
6025 QIB_USE_SPCL_TRIG
: QIB_HAS_SEND_DMA
;
6028 * Setup initial values. These may change when PAT is enabled, but
6029 * we need these to do initial chip register accesses.
6031 qib_7322_set_baseaddrs(dd
);
6033 mtu
= ib_mtu_enum_to_int(qib_ibmtu
);
6035 mtu
= QIB_DEFAULT_MTU
;
6037 dd
->cspec
->int_enable_mask
= QIB_I_BITSEXTANT
;
6038 /* all hwerrors become interrupts, unless special purposed */
6039 dd
->cspec
->hwerrmask
= ~0ULL;
6040 /* link_recovery setup causes these errors, so ignore them,
6041 * other than clearing them when they occur */
6042 dd
->cspec
->hwerrmask
&=
6043 ~(SYM_MASK(HwErrMask
, IBSerdesPClkNotDetectMask_0
) |
6044 SYM_MASK(HwErrMask
, IBSerdesPClkNotDetectMask_1
) |
6045 HWE_MASK(LATriggered
));
6047 for (pidx
= 0; pidx
< NUM_IB_PORTS
; ++pidx
) {
6048 struct qib_chippport_specific
*cp
= ppd
->cpspec
;
6049 ppd
->link_speed_supported
= features
& PORT_SPD_CAP
;
6050 features
>>= PORT_SPD_CAP_SHIFT
;
6051 if (!ppd
->link_speed_supported
) {
6052 /* single port mode (7340, or configured) */
6053 dd
->skip_kctxt_mask
|= 1 << pidx
;
6055 /* Make sure port is disabled. */
6056 qib_write_kreg_port(ppd
, krp_rcvctrl
, 0);
6057 qib_write_kreg_port(ppd
, krp_ibcctrl_a
, 0);
6059 dd
->cspec
->hwerrmask
&= ~(SYM_MASK(HwErrMask
,
6060 IBSerdesPClkNotDetectMask_0
)
6061 | SYM_MASK(HwErrMask
,
6062 SDmaMemReadErrMask_0
));
6063 dd
->cspec
->int_enable_mask
&= ~(
6064 SYM_MASK(IntMask
, SDmaCleanupDoneMask_0
) |
6065 SYM_MASK(IntMask
, SDmaIdleIntMask_0
) |
6066 SYM_MASK(IntMask
, SDmaProgressIntMask_0
) |
6067 SYM_MASK(IntMask
, SDmaIntMask_0
) |
6068 SYM_MASK(IntMask
, ErrIntMask_0
) |
6069 SYM_MASK(IntMask
, SendDoneIntMask_0
));
6071 /* Make sure port is disabled. */
6072 qib_write_kreg_port(ppd
, krp_rcvctrl
, 0);
6073 qib_write_kreg_port(ppd
, krp_ibcctrl_a
, 0);
6074 dd
->cspec
->hwerrmask
&= ~(SYM_MASK(HwErrMask
,
6075 IBSerdesPClkNotDetectMask_1
)
6076 | SYM_MASK(HwErrMask
,
6077 SDmaMemReadErrMask_1
));
6078 dd
->cspec
->int_enable_mask
&= ~(
6079 SYM_MASK(IntMask
, SDmaCleanupDoneMask_1
) |
6080 SYM_MASK(IntMask
, SDmaIdleIntMask_1
) |
6081 SYM_MASK(IntMask
, SDmaProgressIntMask_1
) |
6082 SYM_MASK(IntMask
, SDmaIntMask_1
) |
6083 SYM_MASK(IntMask
, ErrIntMask_1
) |
6084 SYM_MASK(IntMask
, SendDoneIntMask_1
));
6090 qib_init_pportdata(ppd
, dd
, pidx
, dd
->num_pports
);
6092 ppd
->link_width_supported
= IB_WIDTH_1X
| IB_WIDTH_4X
;
6093 ppd
->link_width_enabled
= IB_WIDTH_4X
;
6094 ppd
->link_speed_enabled
= ppd
->link_speed_supported
;
6096 * Set the initial values to reasonable default, will be set
6097 * for real when link is up.
6099 ppd
->link_width_active
= IB_WIDTH_4X
;
6100 ppd
->link_speed_active
= QIB_IB_SDR
;
6101 ppd
->delay_mult
= ib_rate_to_delay
[IB_RATE_10_GBPS
];
6102 switch (qib_num_cfg_vls
) {
6104 ppd
->vls_supported
= IB_VL_VL0
;
6107 ppd
->vls_supported
= IB_VL_VL0_1
;
6110 qib_devinfo(dd
->pcidev
,
6111 "Invalid num_vls %u, using 4 VLs\n",
6113 qib_num_cfg_vls
= 4;
6116 ppd
->vls_supported
= IB_VL_VL0_3
;
6120 ppd
->vls_supported
= IB_VL_VL0_7
;
6122 qib_devinfo(dd
->pcidev
,
6123 "Invalid num_vls %u for MTU %d "
6125 qib_num_cfg_vls
, mtu
);
6126 ppd
->vls_supported
= IB_VL_VL0_3
;
6127 qib_num_cfg_vls
= 4;
6131 ppd
->vls_operational
= ppd
->vls_supported
;
6133 init_waitqueue_head(&cp
->autoneg_wait
);
6134 INIT_DELAYED_WORK(&cp
->autoneg_work
,
6136 if (ppd
->dd
->cspec
->r1
)
6137 INIT_DELAYED_WORK(&cp
->ipg_work
, ipg_7322_work
);
6140 * For Mez and similar cards, no qsfp info, so do
6141 * the "cable info" setup here. Can be overridden
6142 * in adapter-specific routines.
6144 if (!(dd
->flags
& QIB_HAS_QSFP
)) {
6145 if (!IS_QMH(dd
) && !IS_QME(dd
))
6146 qib_devinfo(dd
->pcidev
, "IB%u:%u: "
6147 "Unknown mezzanine card type\n",
6148 dd
->unit
, ppd
->port
);
6149 cp
->h1_val
= IS_QMH(dd
) ? H1_FORCE_QMH
: H1_FORCE_QME
;
6151 * Choose center value as default tx serdes setting
6152 * until changed through module parameter.
6154 ppd
->cpspec
->no_eep
= IS_QMH(dd
) ?
6155 TXDDS_TABLE_SZ
+ 2 : TXDDS_TABLE_SZ
+ 4;
6157 cp
->h1_val
= H1_FORCE_VAL
;
6159 /* Avoid writes to chip for mini_init */
6161 write_7322_init_portregs(ppd
);
6163 init_timer(&cp
->chase_timer
);
6164 cp
->chase_timer
.function
= reenable_chase
;
6165 cp
->chase_timer
.data
= (unsigned long)ppd
;
6170 dd
->rcvhdrentsize
= qib_rcvhdrentsize
?
6171 qib_rcvhdrentsize
: QIB_RCVHDR_ENTSIZE
;
6172 dd
->rcvhdrsize
= qib_rcvhdrsize
?
6173 qib_rcvhdrsize
: QIB_DFLT_RCVHDRSIZE
;
6174 dd
->rhf_offset
= dd
->rcvhdrentsize
- sizeof(u64
) / sizeof(u32
);
6176 /* we always allocate at least 2048 bytes for eager buffers */
6177 dd
->rcvegrbufsize
= max(mtu
, 2048);
6179 qib_7322_tidtemplate(dd
);
6182 * We can request a receive interrupt for 1 or
6183 * more packets from current offset.
6185 dd
->rhdrhead_intr_off
=
6186 (u64
) rcv_int_count
<< IBA7322_HDRHEAD_PKTINT_SHIFT
;
6188 /* setup the stats timer; the add_timer is done at end of init */
6189 init_timer(&dd
->stats_timer
);
6190 dd
->stats_timer
.function
= qib_get_7322_faststats
;
6191 dd
->stats_timer
.data
= (unsigned long) dd
;
6193 dd
->ureg_align
= 0x10000; /* 64KB alignment */
6195 dd
->piosize2kmax_dwords
= dd
->piosize2k
>> 2;
6197 qib_7322_config_ctxts(dd
);
6198 qib_set_ctxtcnt(dd
);
6201 resource_size_t vl15off
;
6203 * We do not set WC on the VL15 buffers to avoid
6204 * a rare problem with unaligned writes from
6205 * interrupt-flushed store buffers, so we need
6206 * to map those separately here. We can't solve
6207 * this for the rarely used mtrr case.
6209 ret
= init_chip_wc_pat(dd
, 0);
6213 /* vl15 buffers start just after the 4k buffers */
6214 vl15off
= dd
->physaddr
+ (dd
->piobufbase
>> 32) +
6215 dd
->piobcnt4k
* dd
->align4k
;
6216 dd
->piovl15base
= ioremap_nocache(vl15off
,
6217 NUM_VL15_BUFS
* dd
->align4k
);
6218 if (!dd
->piovl15base
)
6221 qib_7322_set_baseaddrs(dd
); /* set chip access pointers now */
6226 if (!dd
->num_pports
) {
6227 qib_dev_err(dd
, "No ports enabled, giving up initialization\n");
6228 goto bail
; /* no error, so can still figure out why err */
6231 write_7322_initregs(dd
);
6232 ret
= qib_create_ctxts(dd
);
6233 init_7322_cntrnames(dd
);
6235 updthresh
= 8U; /* update threshold */
6237 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6238 * reserve the update threshold amount for other kernel use, such
6239 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6240 * unless we aren't enabling SDMA, in which case we want to use
6241 * all the 4k bufs for the kernel.
6242 * if this was less than the update threshold, we could wait
6243 * a long time for an update. Coded this way because we
6244 * sometimes change the update threshold for various reasons,
6245 * and we want this to remain robust.
6247 if (dd
->flags
& QIB_HAS_SEND_DMA
) {
6248 dd
->cspec
->sdmabufcnt
= dd
->piobcnt4k
;
6249 sbufs
= updthresh
> 3 ? updthresh
: 3;
6251 dd
->cspec
->sdmabufcnt
= 0;
6252 sbufs
= dd
->piobcnt4k
;
6254 dd
->cspec
->lastbuf_for_pio
= dd
->piobcnt2k
+ dd
->piobcnt4k
-
6255 dd
->cspec
->sdmabufcnt
;
6256 dd
->lastctxt_piobuf
= dd
->cspec
->lastbuf_for_pio
- sbufs
;
6257 dd
->cspec
->lastbuf_for_pio
--; /* range is <= , not < */
6258 dd
->pbufsctxt
= (dd
->cfgctxts
> dd
->first_user_ctxt
) ?
6259 dd
->lastctxt_piobuf
/ (dd
->cfgctxts
- dd
->first_user_ctxt
) : 0;
6262 * If we have 16 user contexts, we will have 7 sbufs
6263 * per context, so reduce the update threshold to match. We
6264 * want to update before we actually run out, at low pbufs/ctxt
6265 * so give ourselves some margin.
6267 if (dd
->pbufsctxt
>= 2 && dd
->pbufsctxt
- 2 < updthresh
)
6268 updthresh
= dd
->pbufsctxt
- 2;
6269 dd
->cspec
->updthresh_dflt
= updthresh
;
6270 dd
->cspec
->updthresh
= updthresh
;
6272 /* before full enable, no interrupts, no locking needed */
6273 dd
->sendctrl
|= ((updthresh
& SYM_RMASK(SendCtrl
, AvailUpdThld
))
6274 << SYM_LSB(SendCtrl
, AvailUpdThld
)) |
6275 SYM_MASK(SendCtrl
, SendBufAvailPad64Byte
);
6277 dd
->psxmitwait_supported
= 1;
6278 dd
->psxmitwait_check_rate
= QIB_7322_PSXMITWAIT_CHECK_RATE
;
6281 dd
->ctxtcnt
= 1; /* for other initialization code */
6286 static u32 __iomem
*qib_7322_getsendbuf(struct qib_pportdata
*ppd
, u64 pbc
,
6289 u32 first
, last
, plen
= pbc
& QIB_PBC_LENGTH_MASK
;
6290 struct qib_devdata
*dd
= ppd
->dd
;
6292 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6293 if (pbc
& PBC_7322_VL15_SEND
) {
6294 first
= dd
->piobcnt2k
+ dd
->piobcnt4k
+ ppd
->hw_pidx
;
6297 if ((plen
+ 1) > dd
->piosize2kmax_dwords
)
6298 first
= dd
->piobcnt2k
;
6301 last
= dd
->cspec
->lastbuf_for_pio
;
6303 return qib_getsendbuf_range(dd
, pbufnum
, first
, last
);
6306 static void qib_set_cntr_7322_sample(struct qib_pportdata
*ppd
, u32 intv
,
6309 qib_write_kreg_port(ppd
, krp_psinterval
, intv
);
6310 qib_write_kreg_port(ppd
, krp_psstart
, start
);
6314 * Must be called with sdma_lock held, or before init finished.
6316 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata
*ppd
, unsigned cnt
)
6318 qib_write_kreg_port(ppd
, krp_senddmadesccnt
, cnt
);
6321 static struct sdma_set_state_action sdma_7322_action_table
[] = {
6322 [qib_sdma_state_s00_hw_down
] = {
6323 .go_s99_running_tofalse
= 1,
6329 [qib_sdma_state_s10_hw_start_up_wait
] = {
6335 [qib_sdma_state_s20_idle
] = {
6341 [qib_sdma_state_s30_sw_clean_up_wait
] = {
6347 [qib_sdma_state_s40_hw_clean_up_wait
] = {
6353 [qib_sdma_state_s50_hw_halt_wait
] = {
6359 [qib_sdma_state_s99_running
] = {
6364 .go_s99_running_totrue
= 1,
6368 static void qib_7322_sdma_init_early(struct qib_pportdata
*ppd
)
6370 ppd
->sdma_state
.set_state_action
= sdma_7322_action_table
;
6373 static int init_sdma_7322_regs(struct qib_pportdata
*ppd
)
6375 struct qib_devdata
*dd
= ppd
->dd
;
6376 unsigned lastbuf
, erstbuf
;
6377 u64 senddmabufmask
[3] = { 0 };
6380 qib_write_kreg_port(ppd
, krp_senddmabase
, ppd
->sdma_descq_phys
);
6381 qib_sdma_7322_setlengen(ppd
);
6382 qib_sdma_update_7322_tail(ppd
, 0); /* Set SendDmaTail */
6383 qib_write_kreg_port(ppd
, krp_senddmareloadcnt
, sdma_idle_cnt
);
6384 qib_write_kreg_port(ppd
, krp_senddmadesccnt
, 0);
6385 qib_write_kreg_port(ppd
, krp_senddmaheadaddr
, ppd
->sdma_head_phys
);
6388 n
= dd
->cspec
->sdmabufcnt
/ dd
->num_pports
; /* no remainder */
6390 n
= dd
->cspec
->sdmabufcnt
; /* failsafe for init */
6391 erstbuf
= (dd
->piobcnt2k
+ dd
->piobcnt4k
) -
6392 ((dd
->num_pports
== 1 || ppd
->port
== 2) ? n
:
6393 dd
->cspec
->sdmabufcnt
);
6394 lastbuf
= erstbuf
+ n
;
6396 ppd
->sdma_state
.first_sendbuf
= erstbuf
;
6397 ppd
->sdma_state
.last_sendbuf
= lastbuf
;
6398 for (; erstbuf
< lastbuf
; ++erstbuf
) {
6399 unsigned word
= erstbuf
/ BITS_PER_LONG
;
6400 unsigned bit
= erstbuf
& (BITS_PER_LONG
- 1);
6403 senddmabufmask
[word
] |= 1ULL << bit
;
6405 qib_write_kreg_port(ppd
, krp_senddmabufmask0
, senddmabufmask
[0]);
6406 qib_write_kreg_port(ppd
, krp_senddmabufmask1
, senddmabufmask
[1]);
6407 qib_write_kreg_port(ppd
, krp_senddmabufmask2
, senddmabufmask
[2]);
6411 /* sdma_lock must be held */
6412 static u16
qib_sdma_7322_gethead(struct qib_pportdata
*ppd
)
6414 struct qib_devdata
*dd
= ppd
->dd
;
6422 use_dmahead
= __qib_sdma_running(ppd
) &&
6423 (dd
->flags
& QIB_HAS_SDMA_TIMEOUT
);
6425 hwhead
= use_dmahead
?
6426 (u16
) le64_to_cpu(*ppd
->sdma_head_dma
) :
6427 (u16
) qib_read_kreg_port(ppd
, krp_senddmahead
);
6429 swhead
= ppd
->sdma_descq_head
;
6430 swtail
= ppd
->sdma_descq_tail
;
6431 cnt
= ppd
->sdma_descq_cnt
;
6433 if (swhead
< swtail
)
6435 sane
= (hwhead
>= swhead
) & (hwhead
<= swtail
);
6436 else if (swhead
> swtail
)
6437 /* wrapped around */
6438 sane
= ((hwhead
>= swhead
) && (hwhead
< cnt
)) ||
6442 sane
= (hwhead
== swhead
);
6444 if (unlikely(!sane
)) {
6446 /* try one more time, directly from the register */
6450 /* proceed as if no progress */
6457 static int qib_sdma_7322_busy(struct qib_pportdata
*ppd
)
6459 u64 hwstatus
= qib_read_kreg_port(ppd
, krp_senddmastatus
);
6461 return (hwstatus
& SYM_MASK(SendDmaStatus_0
, ScoreBoardDrainInProg
)) ||
6462 (hwstatus
& SYM_MASK(SendDmaStatus_0
, HaltInProg
)) ||
6463 !(hwstatus
& SYM_MASK(SendDmaStatus_0
, InternalSDmaHalt
)) ||
6464 !(hwstatus
& SYM_MASK(SendDmaStatus_0
, ScbEmpty
));
6468 * Compute the amount of delay before sending the next packet if the
6469 * port's send rate differs from the static rate set for the QP.
6470 * The delay affects the next packet and the amount of the delay is
6471 * based on the length of the this packet.
6473 static u32
qib_7322_setpbc_control(struct qib_pportdata
*ppd
, u32 plen
,
6476 u8 snd_mult
= ppd
->delay_mult
;
6477 u8 rcv_mult
= ib_rate_to_delay
[srate
];
6480 ret
= rcv_mult
> snd_mult
? ((plen
+ 1) >> 1) * snd_mult
: 0;
6482 /* Indicate VL15, else set the VL in the control word */
6484 ret
|= PBC_7322_VL15_SEND_CTRL
;
6486 ret
|= vl
<< PBC_VL_NUM_LSB
;
6487 ret
|= ((u32
)(ppd
->hw_pidx
)) << PBC_PORT_SEL_LSB
;
6493 * Enable the per-port VL15 send buffers for use.
6494 * They follow the rest of the buffers, without a config parameter.
6495 * This was in initregs, but that is done before the shadow
6496 * is set up, and this has to be done after the shadow is
6499 static void qib_7322_initvl15_bufs(struct qib_devdata
*dd
)
6503 vl15bufs
= dd
->piobcnt2k
+ dd
->piobcnt4k
;
6504 qib_chg_pioavailkernel(dd
, vl15bufs
, NUM_VL15_BUFS
,
6505 TXCHK_CHG_TYPE_KERN
, NULL
);
6508 static void qib_7322_init_ctxt(struct qib_ctxtdata
*rcd
)
6510 if (rcd
->ctxt
< NUM_IB_PORTS
) {
6511 if (rcd
->dd
->num_pports
> 1) {
6512 rcd
->rcvegrcnt
= KCTXT0_EGRCNT
/ 2;
6513 rcd
->rcvegr_tid_base
= rcd
->ctxt
? rcd
->rcvegrcnt
: 0;
6515 rcd
->rcvegrcnt
= KCTXT0_EGRCNT
;
6516 rcd
->rcvegr_tid_base
= 0;
6519 rcd
->rcvegrcnt
= rcd
->dd
->cspec
->rcvegrcnt
;
6520 rcd
->rcvegr_tid_base
= KCTXT0_EGRCNT
+
6521 (rcd
->ctxt
- NUM_IB_PORTS
) * rcd
->rcvegrcnt
;
6525 #define QTXSLEEPS 5000
6526 static void qib_7322_txchk_change(struct qib_devdata
*dd
, u32 start
,
6527 u32 len
, u32 which
, struct qib_ctxtdata
*rcd
)
6530 const int last
= start
+ len
- 1;
6531 const int lastr
= last
/ BITS_PER_LONG
;
6533 int wait
= rcd
!= NULL
;
6534 unsigned long flags
;
6537 unsigned long shadow
;
6538 int cstart
, previ
= -1;
6541 * when flipping from kernel to user, we can't change
6542 * the checking type if the buffer is allocated to the
6543 * driver. It's OK the other direction, because it's
6544 * from close, and we have just disarm'ed all the
6545 * buffers. All the kernel to kernel changes are also
6548 for (cstart
= start
; cstart
<= last
; cstart
++) {
6549 i
= ((2 * cstart
) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT
)
6552 shadow
= (unsigned long)
6553 le64_to_cpu(dd
->pioavailregs_dma
[i
]);
6556 if (test_bit(((2 * cstart
) +
6557 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT
)
6558 % BITS_PER_LONG
, &shadow
))
6565 if (sleeps
== QTXSLEEPS
)
6567 /* make sure we see an updated copy next time around */
6568 sendctrl_7322_mod(dd
->pport
, QIB_SENDCTRL_AVAIL_BLIP
);
6574 case TXCHK_CHG_TYPE_DIS1
:
6576 * disable checking on a range; used by diags; just
6577 * one buffer, but still written generically
6579 for (i
= start
; i
<= last
; i
++)
6580 clear_bit(i
, dd
->cspec
->sendchkenable
);
6583 case TXCHK_CHG_TYPE_ENAB1
:
6585 * (re)enable checking on a range; used by diags; just
6586 * one buffer, but still written generically; read
6587 * scratch to be sure buffer actually triggered, not
6588 * just flushed from processor.
6590 qib_read_kreg32(dd
, kr_scratch
);
6591 for (i
= start
; i
<= last
; i
++)
6592 set_bit(i
, dd
->cspec
->sendchkenable
);
6595 case TXCHK_CHG_TYPE_KERN
:
6596 /* usable by kernel */
6597 for (i
= start
; i
<= last
; i
++) {
6598 set_bit(i
, dd
->cspec
->sendibchk
);
6599 clear_bit(i
, dd
->cspec
->sendgrhchk
);
6601 spin_lock_irqsave(&dd
->uctxt_lock
, flags
);
6602 /* see if we need to raise avail update threshold */
6603 for (i
= dd
->first_user_ctxt
;
6604 dd
->cspec
->updthresh
!= dd
->cspec
->updthresh_dflt
6605 && i
< dd
->cfgctxts
; i
++)
6606 if (dd
->rcd
[i
] && dd
->rcd
[i
]->subctxt_cnt
&&
6607 ((dd
->rcd
[i
]->piocnt
/ dd
->rcd
[i
]->subctxt_cnt
) - 1)
6608 < dd
->cspec
->updthresh_dflt
)
6610 spin_unlock_irqrestore(&dd
->uctxt_lock
, flags
);
6611 if (i
== dd
->cfgctxts
) {
6612 spin_lock_irqsave(&dd
->sendctrl_lock
, flags
);
6613 dd
->cspec
->updthresh
= dd
->cspec
->updthresh_dflt
;
6614 dd
->sendctrl
&= ~SYM_MASK(SendCtrl
, AvailUpdThld
);
6615 dd
->sendctrl
|= (dd
->cspec
->updthresh
&
6616 SYM_RMASK(SendCtrl
, AvailUpdThld
)) <<
6617 SYM_LSB(SendCtrl
, AvailUpdThld
);
6618 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
6619 sendctrl_7322_mod(dd
->pport
, QIB_SENDCTRL_AVAIL_BLIP
);
6623 case TXCHK_CHG_TYPE_USER
:
6624 /* for user process */
6625 for (i
= start
; i
<= last
; i
++) {
6626 clear_bit(i
, dd
->cspec
->sendibchk
);
6627 set_bit(i
, dd
->cspec
->sendgrhchk
);
6629 spin_lock_irqsave(&dd
->sendctrl_lock
, flags
);
6630 if (rcd
&& rcd
->subctxt_cnt
&& ((rcd
->piocnt
6631 / rcd
->subctxt_cnt
) - 1) < dd
->cspec
->updthresh
) {
6632 dd
->cspec
->updthresh
= (rcd
->piocnt
/
6633 rcd
->subctxt_cnt
) - 1;
6634 dd
->sendctrl
&= ~SYM_MASK(SendCtrl
, AvailUpdThld
);
6635 dd
->sendctrl
|= (dd
->cspec
->updthresh
&
6636 SYM_RMASK(SendCtrl
, AvailUpdThld
))
6637 << SYM_LSB(SendCtrl
, AvailUpdThld
);
6638 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
6639 sendctrl_7322_mod(dd
->pport
, QIB_SENDCTRL_AVAIL_BLIP
);
6641 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
6648 for (i
= start
/ BITS_PER_LONG
; which
>= 2 && i
<= lastr
; ++i
)
6649 qib_write_kreg(dd
, kr_sendcheckmask
+ i
,
6650 dd
->cspec
->sendchkenable
[i
]);
6652 for (i
= start
/ BITS_PER_LONG
; which
< 2 && i
<= lastr
; ++i
) {
6653 qib_write_kreg(dd
, kr_sendgrhcheckmask
+ i
,
6654 dd
->cspec
->sendgrhchk
[i
]);
6655 qib_write_kreg(dd
, kr_sendibpktmask
+ i
,
6656 dd
->cspec
->sendibchk
[i
]);
6660 * Be sure whatever we did was seen by the chip and acted upon,
6661 * before we return. Mostly important for which >= 2.
6663 qib_read_kreg32(dd
, kr_scratch
);
6667 /* useful for trigger analyzers, etc. */
6668 static void writescratch(struct qib_devdata
*dd
, u32 val
)
6670 qib_write_kreg(dd
, kr_scratch
, val
);
6673 /* Dummy for now, use chip regs soon */
6674 static int qib_7322_tempsense_rd(struct qib_devdata
*dd
, int regnum
)
6680 * qib_init_iba7322_funcs - set up the chip-specific function pointers
6681 * @dev: the pci_dev for qlogic_ib device
6682 * @ent: pci_device_id struct for this dev
6684 * Also allocates, inits, and returns the devdata struct for this
6687 * This is global, and is called directly at init to set up the
6688 * chip-specific function pointers for later use.
6690 struct qib_devdata
*qib_init_iba7322_funcs(struct pci_dev
*pdev
,
6691 const struct pci_device_id
*ent
)
6693 struct qib_devdata
*dd
;
6695 u32 tabsize
, actual_cnt
= 0;
6697 dd
= qib_alloc_devdata(pdev
,
6698 NUM_IB_PORTS
* sizeof(struct qib_pportdata
) +
6699 sizeof(struct qib_chip_specific
) +
6700 NUM_IB_PORTS
* sizeof(struct qib_chippport_specific
));
6704 dd
->f_bringup_serdes
= qib_7322_bringup_serdes
;
6705 dd
->f_cleanup
= qib_setup_7322_cleanup
;
6706 dd
->f_clear_tids
= qib_7322_clear_tids
;
6707 dd
->f_free_irq
= qib_7322_free_irq
;
6708 dd
->f_get_base_info
= qib_7322_get_base_info
;
6709 dd
->f_get_msgheader
= qib_7322_get_msgheader
;
6710 dd
->f_getsendbuf
= qib_7322_getsendbuf
;
6711 dd
->f_gpio_mod
= gpio_7322_mod
;
6712 dd
->f_eeprom_wen
= qib_7322_eeprom_wen
;
6713 dd
->f_hdrqempty
= qib_7322_hdrqempty
;
6714 dd
->f_ib_updown
= qib_7322_ib_updown
;
6715 dd
->f_init_ctxt
= qib_7322_init_ctxt
;
6716 dd
->f_initvl15_bufs
= qib_7322_initvl15_bufs
;
6717 dd
->f_intr_fallback
= qib_7322_intr_fallback
;
6718 dd
->f_late_initreg
= qib_late_7322_initreg
;
6719 dd
->f_setpbc_control
= qib_7322_setpbc_control
;
6720 dd
->f_portcntr
= qib_portcntr_7322
;
6721 dd
->f_put_tid
= qib_7322_put_tid
;
6722 dd
->f_quiet_serdes
= qib_7322_mini_quiet_serdes
;
6723 dd
->f_rcvctrl
= rcvctrl_7322_mod
;
6724 dd
->f_read_cntrs
= qib_read_7322cntrs
;
6725 dd
->f_read_portcntrs
= qib_read_7322portcntrs
;
6726 dd
->f_reset
= qib_do_7322_reset
;
6727 dd
->f_init_sdma_regs
= init_sdma_7322_regs
;
6728 dd
->f_sdma_busy
= qib_sdma_7322_busy
;
6729 dd
->f_sdma_gethead
= qib_sdma_7322_gethead
;
6730 dd
->f_sdma_sendctrl
= qib_7322_sdma_sendctrl
;
6731 dd
->f_sdma_set_desc_cnt
= qib_sdma_set_7322_desc_cnt
;
6732 dd
->f_sdma_update_tail
= qib_sdma_update_7322_tail
;
6733 dd
->f_sendctrl
= sendctrl_7322_mod
;
6734 dd
->f_set_armlaunch
= qib_set_7322_armlaunch
;
6735 dd
->f_set_cntr_sample
= qib_set_cntr_7322_sample
;
6736 dd
->f_iblink_state
= qib_7322_iblink_state
;
6737 dd
->f_ibphys_portstate
= qib_7322_phys_portstate
;
6738 dd
->f_get_ib_cfg
= qib_7322_get_ib_cfg
;
6739 dd
->f_set_ib_cfg
= qib_7322_set_ib_cfg
;
6740 dd
->f_set_ib_loopback
= qib_7322_set_loopback
;
6741 dd
->f_get_ib_table
= qib_7322_get_ib_table
;
6742 dd
->f_set_ib_table
= qib_7322_set_ib_table
;
6743 dd
->f_set_intr_state
= qib_7322_set_intr_state
;
6744 dd
->f_setextled
= qib_setup_7322_setextled
;
6745 dd
->f_txchk_change
= qib_7322_txchk_change
;
6746 dd
->f_update_usrhead
= qib_update_7322_usrhead
;
6747 dd
->f_wantpiobuf_intr
= qib_wantpiobuf_7322_intr
;
6748 dd
->f_xgxs_reset
= qib_7322_mini_pcs_reset
;
6749 dd
->f_sdma_hw_clean_up
= qib_7322_sdma_hw_clean_up
;
6750 dd
->f_sdma_hw_start_up
= qib_7322_sdma_hw_start_up
;
6751 dd
->f_sdma_init_early
= qib_7322_sdma_init_early
;
6752 dd
->f_writescratch
= writescratch
;
6753 dd
->f_tempsense_rd
= qib_7322_tempsense_rd
;
6755 * Do remaining PCIe setup and save PCIe values in dd.
6756 * Any error printing is already done by the init code.
6757 * On return, we have the chip mapped, but chip registers
6758 * are not set up until start of qib_init_7322_variables.
6760 ret
= qib_pcie_ddinit(dd
, pdev
, ent
);
6764 /* initialize chip-specific variables */
6765 ret
= qib_init_7322_variables(dd
);
6769 if (qib_mini_init
|| !dd
->num_pports
)
6773 * Determine number of vectors we want; depends on port count
6774 * and number of configured kernel receive queues actually used.
6775 * Should also depend on whether sdma is enabled or not, but
6776 * that's such a rare testing case it's not worth worrying about.
6778 tabsize
= dd
->first_user_ctxt
+ ARRAY_SIZE(irq_table
);
6779 for (i
= 0; i
< tabsize
; i
++)
6780 if ((i
< ARRAY_SIZE(irq_table
) &&
6781 irq_table
[i
].port
<= dd
->num_pports
) ||
6782 (i
>= ARRAY_SIZE(irq_table
) &&
6783 dd
->rcd
[i
- ARRAY_SIZE(irq_table
)]))
6785 tabsize
= actual_cnt
;
6786 dd
->cspec
->msix_entries
= kmalloc(tabsize
*
6787 sizeof(struct msix_entry
), GFP_KERNEL
);
6788 dd
->cspec
->msix_arg
= kmalloc(tabsize
*
6789 sizeof(void *), GFP_KERNEL
);
6790 if (!dd
->cspec
->msix_entries
|| !dd
->cspec
->msix_arg
) {
6791 qib_dev_err(dd
, "No memory for MSIx table\n");
6794 for (i
= 0; i
< tabsize
; i
++)
6795 dd
->cspec
->msix_entries
[i
].entry
= i
;
6797 if (qib_pcie_params(dd
, 8, &tabsize
, dd
->cspec
->msix_entries
))
6798 qib_dev_err(dd
, "Failed to setup PCIe or interrupts; "
6799 "continuing anyway\n");
6800 /* may be less than we wanted, if not enough available */
6801 dd
->cspec
->num_msix_entries
= tabsize
;
6803 /* setup interrupt handler */
6804 qib_setup_7322_interrupt(dd
, 1);
6806 /* clear diagctrl register, in case diags were running and crashed */
6807 qib_write_kreg(dd
, kr_hwdiagctrl
, 0);
6812 qib_pcie_ddcleanup(dd
);
6814 qib_free_devdata(dd
);
6821 * Set the table entry at the specified index from the table specifed.
6822 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
6823 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
6824 * 'idx' below addresses the correct entry, while its 4 LSBs select the
6825 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
6827 #define DDS_ENT_AMP_LSB 14
6828 #define DDS_ENT_MAIN_LSB 9
6829 #define DDS_ENT_POST_LSB 5
6830 #define DDS_ENT_PRE_XTRA_LSB 3
6831 #define DDS_ENT_PRE_LSB 0
6834 * Set one entry in the TxDDS table for spec'd port
6835 * ridx picks one of the entries, while tp points
6836 * to the appropriate table entry.
6838 static void set_txdds(struct qib_pportdata
*ppd
, int ridx
,
6839 const struct txdds_ent
*tp
)
6841 struct qib_devdata
*dd
= ppd
->dd
;
6845 /* Get correct offset in chip-space, and in source table */
6846 regidx
= KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE
) + ridx
;
6848 * We do not use qib_write_kreg_port() because it was intended
6849 * only for registers in the lower "port specific" pages.
6850 * So do index calculation by hand.
6853 regidx
+= (dd
->palign
/ sizeof(u64
));
6855 pack_ent
= tp
->amp
<< DDS_ENT_AMP_LSB
;
6856 pack_ent
|= tp
->main
<< DDS_ENT_MAIN_LSB
;
6857 pack_ent
|= tp
->pre
<< DDS_ENT_PRE_LSB
;
6858 pack_ent
|= tp
->post
<< DDS_ENT_POST_LSB
;
6859 qib_write_kreg(dd
, regidx
, pack_ent
);
6860 /* Prevent back-to-back writes by hitting scratch */
6861 qib_write_kreg(ppd
->dd
, kr_scratch
, 0);
6864 static const struct vendor_txdds_ent vendor_txdds
[] = {
6865 { /* Amphenol 1m 30awg NoEq */
6866 { 0x41, 0x50, 0x48 }, "584470002 ",
6867 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
6869 { /* Amphenol 3m 28awg NoEq */
6870 { 0x41, 0x50, 0x48 }, "584470004 ",
6871 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
6873 { /* Finisar 3m OM2 Optical */
6874 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
6875 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
6877 { /* Finisar 30m OM2 Optical */
6878 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
6879 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
6881 { /* Finisar Default OM2 Optical */
6882 { 0x00, 0x90, 0x65 }, NULL
,
6883 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
6885 { /* Gore 1m 30awg NoEq */
6886 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
6887 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
6889 { /* Gore 2m 30awg NoEq */
6890 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
6891 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
6893 { /* Gore 1m 28awg NoEq */
6894 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
6895 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
6897 { /* Gore 3m 28awg NoEq */
6898 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
6899 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
6901 { /* Gore 5m 24awg Eq */
6902 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
6903 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
6905 { /* Gore 7m 24awg Eq */
6906 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
6907 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
6909 { /* Gore 5m 26awg Eq */
6910 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
6911 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
6913 { /* Gore 7m 26awg Eq */
6914 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
6915 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
6917 { /* Intersil 12m 24awg Active */
6918 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
6919 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
6921 { /* Intersil 10m 28awg Active */
6922 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
6923 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
6925 { /* Intersil 7m 30awg Active */
6926 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
6927 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
6929 { /* Intersil 5m 32awg Active */
6930 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
6931 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
6933 { /* Intersil Default Active */
6934 { 0x00, 0x30, 0xB4 }, NULL
,
6935 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
6937 { /* Luxtera 20m Active Optical */
6938 { 0x00, 0x25, 0x63 }, NULL
,
6939 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
6941 { /* Molex 1M Cu loopback */
6942 { 0x00, 0x09, 0x3A }, "74763-0025 ",
6943 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
6945 { /* Molex 2m 28awg NoEq */
6946 { 0x00, 0x09, 0x3A }, "74757-2201 ",
6947 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
6951 static const struct txdds_ent txdds_sdr
[TXDDS_TABLE_SZ
] = {
6952 /* amp, pre, main, post */
6953 { 2, 2, 15, 6 }, /* Loopback */
6954 { 0, 0, 0, 1 }, /* 2 dB */
6955 { 0, 0, 0, 2 }, /* 3 dB */
6956 { 0, 0, 0, 3 }, /* 4 dB */
6957 { 0, 0, 0, 4 }, /* 5 dB */
6958 { 0, 0, 0, 5 }, /* 6 dB */
6959 { 0, 0, 0, 6 }, /* 7 dB */
6960 { 0, 0, 0, 7 }, /* 8 dB */
6961 { 0, 0, 0, 8 }, /* 9 dB */
6962 { 0, 0, 0, 9 }, /* 10 dB */
6963 { 0, 0, 0, 10 }, /* 11 dB */
6964 { 0, 0, 0, 11 }, /* 12 dB */
6965 { 0, 0, 0, 12 }, /* 13 dB */
6966 { 0, 0, 0, 13 }, /* 14 dB */
6967 { 0, 0, 0, 14 }, /* 15 dB */
6968 { 0, 0, 0, 15 }, /* 16 dB */
6971 static const struct txdds_ent txdds_ddr
[TXDDS_TABLE_SZ
] = {
6972 /* amp, pre, main, post */
6973 { 2, 2, 15, 6 }, /* Loopback */
6974 { 0, 0, 0, 8 }, /* 2 dB */
6975 { 0, 0, 0, 8 }, /* 3 dB */
6976 { 0, 0, 0, 9 }, /* 4 dB */
6977 { 0, 0, 0, 9 }, /* 5 dB */
6978 { 0, 0, 0, 10 }, /* 6 dB */
6979 { 0, 0, 0, 10 }, /* 7 dB */
6980 { 0, 0, 0, 11 }, /* 8 dB */
6981 { 0, 0, 0, 11 }, /* 9 dB */
6982 { 0, 0, 0, 12 }, /* 10 dB */
6983 { 0, 0, 0, 12 }, /* 11 dB */
6984 { 0, 0, 0, 13 }, /* 12 dB */
6985 { 0, 0, 0, 13 }, /* 13 dB */
6986 { 0, 0, 0, 14 }, /* 14 dB */
6987 { 0, 0, 0, 14 }, /* 15 dB */
6988 { 0, 0, 0, 15 }, /* 16 dB */
6991 static const struct txdds_ent txdds_qdr
[TXDDS_TABLE_SZ
] = {
6992 /* amp, pre, main, post */
6993 { 2, 2, 15, 6 }, /* Loopback */
6994 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
6995 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
6996 { 0, 1, 0, 11 }, /* 4 dB */
6997 { 0, 1, 0, 13 }, /* 5 dB */
6998 { 0, 1, 0, 15 }, /* 6 dB */
6999 { 0, 1, 3, 15 }, /* 7 dB */
7000 { 0, 1, 7, 15 }, /* 8 dB */
7001 { 0, 1, 7, 15 }, /* 9 dB */
7002 { 0, 1, 8, 15 }, /* 10 dB */
7003 { 0, 1, 9, 15 }, /* 11 dB */
7004 { 0, 1, 10, 15 }, /* 12 dB */
7005 { 0, 2, 6, 15 }, /* 13 dB */
7006 { 0, 2, 7, 15 }, /* 14 dB */
7007 { 0, 2, 8, 15 }, /* 15 dB */
7008 { 0, 2, 9, 15 }, /* 16 dB */
7012 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
7013 * These are mostly used for mez cards going through connectors
7014 * and backplane traces, but can be used to add other "unusual"
7015 * table values as well.
7017 static const struct txdds_ent txdds_extra_sdr
[TXDDS_EXTRA_SZ
] = {
7018 /* amp, pre, main, post */
7019 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7020 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7021 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7022 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7023 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7024 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7025 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7026 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7027 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7028 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7029 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7030 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
7031 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
7034 static const struct txdds_ent txdds_extra_ddr
[TXDDS_EXTRA_SZ
] = {
7035 /* amp, pre, main, post */
7036 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7037 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7038 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7039 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7040 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7041 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7042 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7043 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7044 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7045 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7046 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7047 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
7048 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
7051 static const struct txdds_ent txdds_extra_qdr
[TXDDS_EXTRA_SZ
] = {
7052 /* amp, pre, main, post */
7053 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7054 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7055 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7056 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7057 { 0, 1, 12, 10 }, /* QME7342 backplane setting */
7058 { 0, 1, 12, 11 }, /* QME7342 backplane setting */
7059 { 0, 1, 12, 12 }, /* QME7342 backplane setting */
7060 { 0, 1, 12, 14 }, /* QME7342 backplane setting */
7061 { 0, 1, 12, 6 }, /* QME7342 backplane setting */
7062 { 0, 1, 12, 7 }, /* QME7342 backplane setting */
7063 { 0, 1, 12, 8 }, /* QME7342 backplane setting */
7064 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
7065 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
7068 static const struct txdds_ent txdds_extra_mfg
[TXDDS_MFG_SZ
] = {
7069 /* amp, pre, main, post */
7070 { 0, 0, 0, 0 }, /* QME7342 mfg settings */
7071 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */
7074 static const struct txdds_ent
*get_atten_table(const struct txdds_ent
*txdds
,
7078 * The attenuation table starts at 2dB for entry 1,
7079 * with entry 0 being the loopback entry.
7083 else if (atten
> TXDDS_TABLE_SZ
)
7084 atten
= TXDDS_TABLE_SZ
- 1;
7087 return txdds
+ atten
;
7091 * if override is set, the module parameter txselect has a value
7092 * for this specific port, so use it, rather than our normal mechanism.
7094 static void find_best_ent(struct qib_pportdata
*ppd
,
7095 const struct txdds_ent
**sdr_dds
,
7096 const struct txdds_ent
**ddr_dds
,
7097 const struct txdds_ent
**qdr_dds
, int override
)
7099 struct qib_qsfp_cache
*qd
= &ppd
->cpspec
->qsfp_data
.cache
;
7102 /* Search table of known cables */
7103 for (idx
= 0; !override
&& idx
< ARRAY_SIZE(vendor_txdds
); ++idx
) {
7104 const struct vendor_txdds_ent
*v
= vendor_txdds
+ idx
;
7106 if (!memcmp(v
->oui
, qd
->oui
, QSFP_VOUI_LEN
) &&
7108 !memcmp(v
->partnum
, qd
->partnum
, QSFP_PN_LEN
))) {
7116 /* Lookup serdes setting by cable type and attenuation */
7117 if (!override
&& QSFP_IS_ACTIVE(qd
->tech
)) {
7118 *sdr_dds
= txdds_sdr
+ ppd
->dd
->board_atten
;
7119 *ddr_dds
= txdds_ddr
+ ppd
->dd
->board_atten
;
7120 *qdr_dds
= txdds_qdr
+ ppd
->dd
->board_atten
;
7124 if (!override
&& QSFP_HAS_ATTEN(qd
->tech
) && (qd
->atten
[0] ||
7126 *sdr_dds
= get_atten_table(txdds_sdr
, qd
->atten
[0]);
7127 *ddr_dds
= get_atten_table(txdds_ddr
, qd
->atten
[0]);
7128 *qdr_dds
= get_atten_table(txdds_qdr
, qd
->atten
[1]);
7130 } else if (ppd
->cpspec
->no_eep
< TXDDS_TABLE_SZ
) {
7132 * If we have no (or incomplete) data from the cable
7133 * EEPROM, or no QSFP, or override is set, use the
7134 * module parameter value to index into the attentuation
7137 idx
= ppd
->cpspec
->no_eep
;
7138 *sdr_dds
= &txdds_sdr
[idx
];
7139 *ddr_dds
= &txdds_ddr
[idx
];
7140 *qdr_dds
= &txdds_qdr
[idx
];
7141 } else if (ppd
->cpspec
->no_eep
< (TXDDS_TABLE_SZ
+ TXDDS_EXTRA_SZ
)) {
7142 /* similar to above, but index into the "extra" table. */
7143 idx
= ppd
->cpspec
->no_eep
- TXDDS_TABLE_SZ
;
7144 *sdr_dds
= &txdds_extra_sdr
[idx
];
7145 *ddr_dds
= &txdds_extra_ddr
[idx
];
7146 *qdr_dds
= &txdds_extra_qdr
[idx
];
7147 } else if ((IS_QME(ppd
->dd
) || IS_QMH(ppd
->dd
)) &&
7148 ppd
->cpspec
->no_eep
< (TXDDS_TABLE_SZ
+ TXDDS_EXTRA_SZ
+
7150 idx
= ppd
->cpspec
->no_eep
- (TXDDS_TABLE_SZ
+ TXDDS_EXTRA_SZ
);
7151 printk(KERN_INFO QIB_DRV_NAME
7152 " IB%u:%u use idx %u into txdds_mfg\n",
7153 ppd
->dd
->unit
, ppd
->port
, idx
);
7154 *sdr_dds
= &txdds_extra_mfg
[idx
];
7155 *ddr_dds
= &txdds_extra_mfg
[idx
];
7156 *qdr_dds
= &txdds_extra_mfg
[idx
];
7158 /* this shouldn't happen, it's range checked */
7159 *sdr_dds
= txdds_sdr
+ qib_long_atten
;
7160 *ddr_dds
= txdds_ddr
+ qib_long_atten
;
7161 *qdr_dds
= txdds_qdr
+ qib_long_atten
;
7165 static void init_txdds_table(struct qib_pportdata
*ppd
, int override
)
7167 const struct txdds_ent
*sdr_dds
, *ddr_dds
, *qdr_dds
;
7168 struct txdds_ent
*dds
;
7172 find_best_ent(ppd
, &sdr_dds
, &ddr_dds
, &qdr_dds
, override
);
7174 /* for mez cards or override, use the selected value for all entries */
7175 if (!(ppd
->dd
->flags
& QIB_HAS_QSFP
) || override
)
7178 /* Fill in the first entry with the best entry found. */
7179 set_txdds(ppd
, 0, sdr_dds
);
7180 set_txdds(ppd
, TXDDS_TABLE_SZ
, ddr_dds
);
7181 set_txdds(ppd
, 2 * TXDDS_TABLE_SZ
, qdr_dds
);
7182 if (ppd
->lflags
& (QIBL_LINKINIT
| QIBL_LINKARMED
|
7184 dds
= (struct txdds_ent
*)(ppd
->link_speed_active
==
7185 QIB_IB_QDR
? qdr_dds
:
7186 (ppd
->link_speed_active
==
7187 QIB_IB_DDR
? ddr_dds
: sdr_dds
));
7188 write_tx_serdes_param(ppd
, dds
);
7191 /* Fill in the remaining entries with the default table values. */
7192 for (idx
= 1; idx
< ARRAY_SIZE(txdds_sdr
); ++idx
) {
7193 set_txdds(ppd
, idx
, single_ent
? sdr_dds
: txdds_sdr
+ idx
);
7194 set_txdds(ppd
, idx
+ TXDDS_TABLE_SZ
,
7195 single_ent
? ddr_dds
: txdds_ddr
+ idx
);
7196 set_txdds(ppd
, idx
+ 2 * TXDDS_TABLE_SZ
,
7197 single_ent
? qdr_dds
: txdds_qdr
+ idx
);
7201 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7202 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7203 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7204 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7205 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7206 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7207 #define AHB_TRANS_TRIES 10
7210 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7211 * 5=subsystem which is why most calls have "chan + chan >> 1"
7212 * for the channel argument.
7214 static u32
ahb_mod(struct qib_devdata
*dd
, int quad
, int chan
, int addr
,
7217 u32 rd_data
, wr_data
, sz_mask
;
7218 u64 trans
, acc
, prev_acc
;
7219 u32 ret
= 0xBAD0BAD;
7222 prev_acc
= qib_read_kreg64(dd
, KR_AHB_ACC
);
7223 /* From this point on, make sure we return access */
7224 acc
= (quad
<< 1) | 1;
7225 qib_write_kreg(dd
, KR_AHB_ACC
, acc
);
7227 for (tries
= 1; tries
< AHB_TRANS_TRIES
; ++tries
) {
7228 trans
= qib_read_kreg64(dd
, KR_AHB_TRANS
);
7229 if (trans
& AHB_TRANS_RDY
)
7232 if (tries
>= AHB_TRANS_TRIES
) {
7233 qib_dev_err(dd
, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES
);
7237 /* If mask is not all 1s, we need to read, but different SerDes
7238 * entities have different sizes
7240 sz_mask
= (1UL << ((quad
== 1) ? 32 : 16)) - 1;
7241 wr_data
= data
& mask
& sz_mask
;
7242 if ((~mask
& sz_mask
) != 0) {
7243 trans
= ((chan
<< 6) | addr
) << (AHB_ADDR_LSB
+ 1);
7244 qib_write_kreg(dd
, KR_AHB_TRANS
, trans
);
7246 for (tries
= 1; tries
< AHB_TRANS_TRIES
; ++tries
) {
7247 trans
= qib_read_kreg64(dd
, KR_AHB_TRANS
);
7248 if (trans
& AHB_TRANS_RDY
)
7251 if (tries
>= AHB_TRANS_TRIES
) {
7252 qib_dev_err(dd
, "No Rd ahb_rdy in %d tries\n",
7256 /* Re-read in case host split reads and read data first */
7257 trans
= qib_read_kreg64(dd
, KR_AHB_TRANS
);
7258 rd_data
= (uint32_t)(trans
>> AHB_DATA_LSB
);
7259 wr_data
|= (rd_data
& ~mask
& sz_mask
);
7262 /* If mask is not zero, we need to write. */
7263 if (mask
& sz_mask
) {
7264 trans
= ((chan
<< 6) | addr
) << (AHB_ADDR_LSB
+ 1);
7265 trans
|= ((uint64_t)wr_data
<< AHB_DATA_LSB
);
7267 qib_write_kreg(dd
, KR_AHB_TRANS
, trans
);
7269 for (tries
= 1; tries
< AHB_TRANS_TRIES
; ++tries
) {
7270 trans
= qib_read_kreg64(dd
, KR_AHB_TRANS
);
7271 if (trans
& AHB_TRANS_RDY
)
7274 if (tries
>= AHB_TRANS_TRIES
) {
7275 qib_dev_err(dd
, "No Wr ahb_rdy in %d tries\n",
7282 qib_write_kreg(dd
, KR_AHB_ACC
, prev_acc
);
7286 static void ibsd_wr_allchans(struct qib_pportdata
*ppd
, int addr
, unsigned data
,
7289 struct qib_devdata
*dd
= ppd
->dd
;
7293 for (chan
= 0; chan
< SERDES_CHANS
; ++chan
) {
7294 ahb_mod(dd
, IBSD(ppd
->hw_pidx
), (chan
+ (chan
>> 1)), addr
,
7296 rbc
= ahb_mod(dd
, IBSD(ppd
->hw_pidx
), (chan
+ (chan
>> 1)),
7301 static void serdes_7322_los_enable(struct qib_pportdata
*ppd
, int enable
)
7303 u64 data
= qib_read_kreg_port(ppd
, krp_serdesctrl
);
7304 printk(KERN_INFO QIB_DRV_NAME
" IB%u:%u Turning LOS %s\n",
7305 ppd
->dd
->unit
, ppd
->port
, (enable
? "on" : "off"));
7307 data
|= SYM_MASK(IBSerdesCtrl_0
, RXLOSEN
);
7309 data
&= ~SYM_MASK(IBSerdesCtrl_0
, RXLOSEN
);
7310 qib_write_kreg_port(ppd
, krp_serdesctrl
, data
);
7313 static int serdes_7322_init(struct qib_pportdata
*ppd
)
7316 if (ppd
->dd
->cspec
->r1
)
7317 ret
= serdes_7322_init_old(ppd
);
7319 ret
= serdes_7322_init_new(ppd
);
7323 static int serdes_7322_init_old(struct qib_pportdata
*ppd
)
7328 * Initialize the Tx DDS tables. Also done every QSFP event,
7329 * for adapters with QSFP
7331 init_txdds_table(ppd
, 0);
7333 /* ensure no tx overrides from earlier driver loads */
7334 qib_write_kreg_port(ppd
, krp_tx_deemph_override
,
7335 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0
,
7336 reset_tx_deemphasis_override
));
7338 /* Patch some SerDes defaults to "Better for IB" */
7339 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7340 ibsd_wr_allchans(ppd
, 2, 0, BMASK(11, 9));
7342 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7343 ibsd_wr_allchans(ppd
, 11, (1 << 11), BMASK(12, 11));
7344 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7345 ibsd_wr_allchans(ppd
, 13, (1 << 6), (1 << 6));
7347 /* May be overridden in qsfp_7322_event */
7348 le_val
= IS_QME(ppd
->dd
) ? LE2_QME
: LE2_DEFAULT
;
7349 ibsd_wr_allchans(ppd
, 13, (le_val
<< 7), BMASK(9, 7));
7351 /* enable LE1 adaptation for all but QME, which is disabled */
7352 le_val
= IS_QME(ppd
->dd
) ? 0 : 1;
7353 ibsd_wr_allchans(ppd
, 13, (le_val
<< 5), (1 << 5));
7355 /* Clear cmode-override, may be set from older driver */
7356 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 10, 0 << 14, 1 << 14);
7358 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7359 ibsd_wr_allchans(ppd
, 5, (0 << 8), BMASK(9, 8));
7361 /* setup LoS params; these are subsystem, so chan == 5 */
7362 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7363 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 5, 8 << 11, BMASK(14, 11));
7364 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 7, 8 << 4, BMASK(7, 4));
7365 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 8, 8 << 11, BMASK(14, 11));
7366 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 10, 8 << 4, BMASK(7, 4));
7368 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7369 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 6, 4 << 0, BMASK(3, 0));
7370 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 7, 4 << 8, BMASK(11, 8));
7371 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 9, 4 << 0, BMASK(3, 0));
7372 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 10, 4 << 8, BMASK(11, 8));
7374 /* LoS filter select enabled */
7375 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 9, 1 << 15, 1 << 15);
7377 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7378 ibsd_wr_allchans(ppd
, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7379 ibsd_wr_allchans(ppd
, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7380 ibsd_wr_allchans(ppd
, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7382 serdes_7322_los_enable(ppd
, 1);
7384 /* rxbistena; set 0 to avoid effects of it switch later */
7385 ibsd_wr_allchans(ppd
, 9, 0 << 15, 1 << 15);
7387 /* Configure 4 DFE taps, and only they adapt */
7388 ibsd_wr_allchans(ppd
, 16, 0 << 0, BMASK(1, 0));
7390 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7391 le_val
= (ppd
->dd
->cspec
->r1
|| IS_QME(ppd
->dd
)) ? 0xb6c0 : 0x6bac;
7392 ibsd_wr_allchans(ppd
, 21, le_val
, 0xfffe);
7395 * Set receive adaptation mode. SDR and DDR adaptation are
7396 * always on, and QDR is initially enabled; later disabled.
7398 qib_write_kreg_port(ppd
, krp_static_adapt_dis(0), 0ULL);
7399 qib_write_kreg_port(ppd
, krp_static_adapt_dis(1), 0ULL);
7400 qib_write_kreg_port(ppd
, krp_static_adapt_dis(2),
7401 ppd
->dd
->cspec
->r1
?
7402 QDR_STATIC_ADAPT_DOWN_R1
: QDR_STATIC_ADAPT_DOWN
);
7403 ppd
->cpspec
->qdr_dfe_on
= 1;
7405 /* FLoop LOS gate: PPM filter enabled */
7406 ibsd_wr_allchans(ppd
, 38, 0 << 10, 1 << 10);
7408 /* rx offset center enabled */
7409 ibsd_wr_allchans(ppd
, 12, 1 << 4, 1 << 4);
7411 if (!ppd
->dd
->cspec
->r1
) {
7412 ibsd_wr_allchans(ppd
, 12, 1 << 12, 1 << 12);
7413 ibsd_wr_allchans(ppd
, 12, 2 << 8, 0x0f << 8);
7416 /* Set the frequency loop bandwidth to 15 */
7417 ibsd_wr_allchans(ppd
, 2, 15 << 5, BMASK(8, 5));
7422 static int serdes_7322_init_new(struct qib_pportdata
*ppd
)
7425 u32 le_val
, rxcaldone
;
7426 int chan
, chan_done
= (1 << SERDES_CHANS
) - 1;
7429 * Initialize the Tx DDS tables. Also done every QSFP event,
7430 * for adapters with QSFP
7432 init_txdds_table(ppd
, 0);
7434 /* Clear cmode-override, may be set from older driver */
7435 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 10, 0 << 14, 1 << 14);
7437 /* ensure no tx overrides from earlier driver loads */
7438 qib_write_kreg_port(ppd
, krp_tx_deemph_override
,
7439 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0
,
7440 reset_tx_deemphasis_override
));
7442 /* START OF LSI SUGGESTED SERDES BRINGUP */
7443 /* Reset - Calibration Setup */
7444 /* Stop DFE adaptaion */
7445 ibsd_wr_allchans(ppd
, 1, 0, BMASK(9, 1));
7447 ibsd_wr_allchans(ppd
, 13, 0, BMASK(5, 5));
7448 /* Disable autoadapt for LE1 */
7449 ibsd_wr_allchans(ppd
, 1, 0, BMASK(15, 15));
7451 ibsd_wr_allchans(ppd
, 13, 0, BMASK(6, 6));
7453 ibsd_wr_allchans(ppd
, 5, 0, BMASK(0, 0));
7454 /* Disable AFE Offset Cancel */
7455 ibsd_wr_allchans(ppd
, 12, 0, BMASK(12, 12));
7456 /* Disable Timing Loop */
7457 ibsd_wr_allchans(ppd
, 2, 0, BMASK(3, 3));
7458 /* Disable Frequency Loop */
7459 ibsd_wr_allchans(ppd
, 2, 0, BMASK(4, 4));
7460 /* Disable Baseline Wander Correction */
7461 ibsd_wr_allchans(ppd
, 13, 0, BMASK(13, 13));
7462 /* Disable RX Calibration */
7463 ibsd_wr_allchans(ppd
, 4, 0, BMASK(10, 10));
7464 /* Disable RX Offset Calibration */
7465 ibsd_wr_allchans(ppd
, 12, 0, BMASK(4, 4));
7467 ibsd_wr_allchans(ppd
, 2, (1 << 15), BMASK(15, 15));
7469 ibsd_wr_allchans(ppd
, 5, 0, BMASK(9, 8));
7470 /* Enable phase Calibration */
7471 ibsd_wr_allchans(ppd
, 12, (1 << 5), BMASK(5, 5));
7472 /* DFE Bandwidth [2:14-12] */
7473 ibsd_wr_allchans(ppd
, 2, (4 << 12), BMASK(14, 12));
7474 /* DFE Config (4 taps only) */
7475 ibsd_wr_allchans(ppd
, 16, 0, BMASK(1, 0));
7476 /* Gain Loop Bandwidth */
7477 if (!ppd
->dd
->cspec
->r1
) {
7478 ibsd_wr_allchans(ppd
, 12, 1 << 12, BMASK(12, 12));
7479 ibsd_wr_allchans(ppd
, 12, 2 << 8, BMASK(11, 8));
7481 ibsd_wr_allchans(ppd
, 19, (3 << 11), BMASK(13, 11));
7483 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */
7484 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */
7485 /* Data Rate Select [5:7-6] (leave as default) */
7486 /* RX Parallel Word Width [3:10-8] (leave as default) */
7489 /* Single- or Multi-channel reset */
7490 /* RX Analog reset */
7491 /* RX Digital reset */
7492 ibsd_wr_allchans(ppd
, 0, 0, BMASK(15, 13));
7494 /* RX Analog reset */
7495 ibsd_wr_allchans(ppd
, 0, (1 << 14), BMASK(14, 14));
7497 /* RX Digital reset */
7498 ibsd_wr_allchans(ppd
, 0, (1 << 13), BMASK(13, 13));
7501 /* setup LoS params; these are subsystem, so chan == 5 */
7502 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7503 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 5, 8 << 11, BMASK(14, 11));
7504 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 7, 8 << 4, BMASK(7, 4));
7505 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 8, 8 << 11, BMASK(14, 11));
7506 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 10, 8 << 4, BMASK(7, 4));
7508 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7509 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 6, 4 << 0, BMASK(3, 0));
7510 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 7, 4 << 8, BMASK(11, 8));
7511 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 9, 4 << 0, BMASK(3, 0));
7512 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 10, 4 << 8, BMASK(11, 8));
7514 /* LoS filter select enabled */
7515 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), 5, 9, 1 << 15, 1 << 15);
7517 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7518 ibsd_wr_allchans(ppd
, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7519 ibsd_wr_allchans(ppd
, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7520 ibsd_wr_allchans(ppd
, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7522 /* Turn on LOS on initial SERDES init */
7523 serdes_7322_los_enable(ppd
, 1);
7524 /* FLoop LOS gate: PPM filter enabled */
7525 ibsd_wr_allchans(ppd
, 38, 0 << 10, 1 << 10);
7527 /* RX LATCH CALIBRATION */
7528 /* Enable Eyefinder Phase Calibration latch */
7529 ibsd_wr_allchans(ppd
, 15, 1, BMASK(0, 0));
7530 /* Enable RX Offset Calibration latch */
7531 ibsd_wr_allchans(ppd
, 12, (1 << 4), BMASK(4, 4));
7533 /* Start Calibration */
7534 ibsd_wr_allchans(ppd
, 4, (1 << 10), BMASK(10, 10));
7535 tstart
= get_jiffies_64();
7537 !time_after64(get_jiffies_64(),
7538 tstart
+ msecs_to_jiffies(500))) {
7540 for (chan
= 0; chan
< SERDES_CHANS
; ++chan
) {
7541 rxcaldone
= ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
),
7542 (chan
+ (chan
>> 1)),
7544 if ((~rxcaldone
& (u32
)BMASK(9, 9)) == 0 &&
7545 (~chan_done
& (1 << chan
)) == 0)
7546 chan_done
&= ~(1 << chan
);
7550 printk(KERN_INFO QIB_DRV_NAME
7551 " Serdes %d calibration not done after .5 sec: 0x%x\n",
7552 IBSD(ppd
->hw_pidx
), chan_done
);
7554 for (chan
= 0; chan
< SERDES_CHANS
; ++chan
) {
7555 rxcaldone
= ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
),
7556 (chan
+ (chan
>> 1)),
7558 if ((~rxcaldone
& (u32
)BMASK(10, 10)) == 0)
7559 printk(KERN_INFO QIB_DRV_NAME
7560 " Serdes %d chan %d calibration "
7561 "failed\n", IBSD(ppd
->hw_pidx
), chan
);
7565 /* Turn off Calibration */
7566 ibsd_wr_allchans(ppd
, 4, 0, BMASK(10, 10));
7570 /* Set LE2 value (May be overridden in qsfp_7322_event) */
7571 le_val
= IS_QME(ppd
->dd
) ? LE2_QME
: LE2_DEFAULT
;
7572 ibsd_wr_allchans(ppd
, 13, (le_val
<< 7), BMASK(9, 7));
7573 /* Set LE2 Loop bandwidth */
7574 ibsd_wr_allchans(ppd
, 3, (7 << 5), BMASK(7, 5));
7576 ibsd_wr_allchans(ppd
, 13, (1 << 6), BMASK(6, 6));
7578 /* Enable H0 only */
7579 ibsd_wr_allchans(ppd
, 1, 1, BMASK(9, 1));
7580 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7581 le_val
= (ppd
->dd
->cspec
->r1
|| IS_QME(ppd
->dd
)) ? 0xb6c0 : 0x6bac;
7582 ibsd_wr_allchans(ppd
, 21, le_val
, 0xfffe);
7584 ibsd_wr_allchans(ppd
, 5, 0, BMASK(0, 0));
7586 /* Set Frequency Loop Bandwidth */
7587 ibsd_wr_allchans(ppd
, 2, (7 << 5), BMASK(8, 5));
7588 /* Enable Frequency Loop */
7589 ibsd_wr_allchans(ppd
, 2, (1 << 4), BMASK(4, 4));
7590 /* Set Timing Loop Bandwidth */
7591 ibsd_wr_allchans(ppd
, 2, 0, BMASK(11, 9));
7592 /* Enable Timing Loop */
7593 ibsd_wr_allchans(ppd
, 2, (1 << 3), BMASK(3, 3));
7596 * Set receive adaptation mode. SDR and DDR adaptation are
7597 * always on, and QDR is initially enabled; later disabled.
7599 qib_write_kreg_port(ppd
, krp_static_adapt_dis(0), 0ULL);
7600 qib_write_kreg_port(ppd
, krp_static_adapt_dis(1), 0ULL);
7601 qib_write_kreg_port(ppd
, krp_static_adapt_dis(2),
7602 ppd
->dd
->cspec
->r1
?
7603 QDR_STATIC_ADAPT_DOWN_R1
: QDR_STATIC_ADAPT_DOWN
);
7604 ppd
->cpspec
->qdr_dfe_on
= 1;
7606 ibsd_wr_allchans(ppd
, 13, (0 << 5), (1 << 5));
7607 /* Disable auto adapt for LE1 */
7608 ibsd_wr_allchans(ppd
, 1, (0 << 15), BMASK(15, 15));
7610 /* Enable AFE Offset Cancel */
7611 ibsd_wr_allchans(ppd
, 12, (1 << 12), BMASK(12, 12));
7612 /* Enable Baseline Wander Correction */
7613 ibsd_wr_allchans(ppd
, 12, (1 << 13), BMASK(13, 13));
7614 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7615 ibsd_wr_allchans(ppd
, 11, (1 << 11), BMASK(12, 11));
7616 /* VGA output common mode */
7617 ibsd_wr_allchans(ppd
, 12, (3 << 2), BMASK(3, 2));
7622 /* start adjust QMH serdes parameters */
7624 static void set_man_code(struct qib_pportdata
*ppd
, int chan
, int code
)
7626 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), (chan
+ (chan
>> 1)),
7627 9, code
<< 9, 0x3f << 9);
7630 static void set_man_mode_h1(struct qib_pportdata
*ppd
, int chan
,
7631 int enable
, u32 tapenable
)
7634 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), (chan
+ (chan
>> 1)),
7635 1, 3 << 10, 0x1f << 10);
7637 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), (chan
+ (chan
>> 1)),
7641 /* Set clock to 1, 0, 1, 0 */
7642 static void clock_man(struct qib_pportdata
*ppd
, int chan
)
7644 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), (chan
+ (chan
>> 1)),
7646 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), (chan
+ (chan
>> 1)),
7648 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), (chan
+ (chan
>> 1)),
7650 ahb_mod(ppd
->dd
, IBSD(ppd
->hw_pidx
), (chan
+ (chan
>> 1)),
7655 * write the current Tx serdes pre,post,main,amp settings into the serdes.
7656 * The caller must pass the settings appropriate for the current speed,
7657 * or not care if they are correct for the current speed.
7659 static void write_tx_serdes_param(struct qib_pportdata
*ppd
,
7660 struct txdds_ent
*txdds
)
7664 deemph
= qib_read_kreg_port(ppd
, krp_tx_deemph_override
);
7665 /* field names for amp, main, post, pre, respectively */
7666 deemph
&= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0
, txampcntl_d2a
) |
7667 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0
, txc0_ena
) |
7668 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0
, txcp1_ena
) |
7669 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0
, txcn1_ena
));
7671 deemph
|= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0
,
7672 tx_override_deemphasis_select
);
7673 deemph
|= (txdds
->amp
& SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0
,
7674 txampcntl_d2a
)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0
,
7676 deemph
|= (txdds
->main
& SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0
,
7677 txc0_ena
)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0
,
7679 deemph
|= (txdds
->post
& SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0
,
7680 txcp1_ena
)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0
,
7682 deemph
|= (txdds
->pre
& SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0
,
7683 txcn1_ena
)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0
,
7685 qib_write_kreg_port(ppd
, krp_tx_deemph_override
, deemph
);
7689 * Set the parameters for mez cards on link bounce, so they are
7690 * always exactly what was requested. Similar logic to init_txdds
7691 * but does just the serdes.
7693 static void adj_tx_serdes(struct qib_pportdata
*ppd
)
7695 const struct txdds_ent
*sdr_dds
, *ddr_dds
, *qdr_dds
;
7696 struct txdds_ent
*dds
;
7698 find_best_ent(ppd
, &sdr_dds
, &ddr_dds
, &qdr_dds
, 1);
7699 dds
= (struct txdds_ent
*)(ppd
->link_speed_active
== QIB_IB_QDR
?
7700 qdr_dds
: (ppd
->link_speed_active
== QIB_IB_DDR
?
7701 ddr_dds
: sdr_dds
));
7702 write_tx_serdes_param(ppd
, dds
);
7705 /* set QDR forced value for H1, if needed */
7706 static void force_h1(struct qib_pportdata
*ppd
)
7710 ppd
->cpspec
->qdr_reforce
= 0;
7711 if (!ppd
->dd
->cspec
->r1
)
7714 for (chan
= 0; chan
< SERDES_CHANS
; chan
++) {
7715 set_man_mode_h1(ppd
, chan
, 1, 0);
7716 set_man_code(ppd
, chan
, ppd
->cpspec
->h1_val
);
7717 clock_man(ppd
, chan
);
7718 set_man_mode_h1(ppd
, chan
, 0, 0);
7722 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
7723 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
7725 #define R_OPCODE_LSB 3
7727 #define R_OP_SHIFT 2
7728 #define R_OP_UPDATE 3
7733 static int qib_r_grab(struct qib_devdata
*dd
)
7737 qib_write_kreg(dd
, kr_r_access
, val
);
7738 qib_read_kreg32(dd
, kr_scratch
);
7742 /* qib_r_wait_for_rdy() not only waits for the ready bit, it
7743 * returns the current state of R_TDO
7745 static int qib_r_wait_for_rdy(struct qib_devdata
*dd
)
7749 for (timeout
= 0; timeout
< 100 ; ++timeout
) {
7750 val
= qib_read_kreg32(dd
, kr_r_access
);
7752 return (val
>> R_TDO_LSB
) & 1;
7757 static int qib_r_shift(struct qib_devdata
*dd
, int bisten
,
7758 int len
, u8
*inp
, u8
*outp
)
7763 valbase
= SJA_EN
| (bisten
<< BISTEN_LSB
) |
7764 (R_OP_SHIFT
<< R_OPCODE_LSB
);
7765 ret
= qib_r_wait_for_rdy(dd
);
7768 for (pos
= 0; pos
< len
; ++pos
) {
7771 outp
[pos
>> 3] &= ~(1 << (pos
& 7));
7772 outp
[pos
>> 3] |= (ret
<< (pos
& 7));
7775 int tdi
= inp
[pos
>> 3] >> (pos
& 7);
7776 val
|= ((tdi
& 1) << R_TDI_LSB
);
7778 qib_write_kreg(dd
, kr_r_access
, val
);
7779 qib_read_kreg32(dd
, kr_scratch
);
7780 ret
= qib_r_wait_for_rdy(dd
);
7784 /* Restore to NOP between operations. */
7785 val
= SJA_EN
| (bisten
<< BISTEN_LSB
);
7786 qib_write_kreg(dd
, kr_r_access
, val
);
7787 qib_read_kreg32(dd
, kr_scratch
);
7788 ret
= qib_r_wait_for_rdy(dd
);
7796 static int qib_r_update(struct qib_devdata
*dd
, int bisten
)
7801 val
= SJA_EN
| (bisten
<< BISTEN_LSB
) | (R_OP_UPDATE
<< R_OPCODE_LSB
);
7802 ret
= qib_r_wait_for_rdy(dd
);
7804 qib_write_kreg(dd
, kr_r_access
, val
);
7805 qib_read_kreg32(dd
, kr_scratch
);
7810 #define BISTEN_PORT_SEL 15
7811 #define LEN_PORT_SEL 625
7812 #define BISTEN_AT 17
7814 #define BISTEN_ETM 16
7817 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
7819 /* these are common for all IB port use cases. */
7820 static u8 reset_at
[BIT2BYTE(LEN_AT
)] = {
7821 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7822 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7824 static u8 reset_atetm
[BIT2BYTE(LEN_ETM
)] = {
7825 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7826 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7827 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
7828 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
7829 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
7830 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
7831 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7832 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
7834 static u8 at
[BIT2BYTE(LEN_AT
)] = {
7835 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
7836 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7839 /* used for IB1 or IB2, only one in use */
7840 static u8 atetm_1port
[BIT2BYTE(LEN_ETM
)] = {
7841 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7842 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7843 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7844 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
7845 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7846 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
7847 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
7848 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
7851 /* used when both IB1 and IB2 are in use */
7852 static u8 atetm_2port
[BIT2BYTE(LEN_ETM
)] = {
7853 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7854 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
7855 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7856 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
7857 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
7858 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
7859 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
7860 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
7863 /* used when only IB1 is in use */
7864 static u8 portsel_port1
[BIT2BYTE(LEN_PORT_SEL
)] = {
7865 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7866 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7867 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7868 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7869 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7870 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7871 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7872 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7875 /* used when only IB2 is in use */
7876 static u8 portsel_port2
[BIT2BYTE(LEN_PORT_SEL
)] = {
7877 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
7878 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
7879 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7880 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7881 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
7882 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7883 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7884 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
7887 /* used when both IB1 and IB2 are in use */
7888 static u8 portsel_2port
[BIT2BYTE(LEN_PORT_SEL
)] = {
7889 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7890 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7891 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7892 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7893 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7894 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
7895 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7896 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7900 * Do setup to properly handle IB link recovery; if port is zero, we
7901 * are initializing to cover both ports; otherwise we are initializing
7902 * to cover a single port card, or the port has reached INIT and we may
7903 * need to switch coverage types.
7905 static void setup_7322_link_recovery(struct qib_pportdata
*ppd
, u32 both
)
7908 struct qib_devdata
*dd
= ppd
->dd
;
7910 if (!ppd
->dd
->cspec
->r1
)
7913 dd
->cspec
->recovery_ports_initted
++;
7914 ppd
->cpspec
->recovery_init
= 1;
7916 if (!both
&& dd
->cspec
->recovery_ports_initted
== 1) {
7917 portsel
= ppd
->port
== 1 ? portsel_port1
: portsel_port2
;
7920 portsel
= portsel_2port
;
7924 if (qib_r_grab(dd
) < 0 ||
7925 qib_r_shift(dd
, BISTEN_ETM
, LEN_ETM
, reset_atetm
, NULL
) < 0 ||
7926 qib_r_update(dd
, BISTEN_ETM
) < 0 ||
7927 qib_r_shift(dd
, BISTEN_AT
, LEN_AT
, reset_at
, NULL
) < 0 ||
7928 qib_r_update(dd
, BISTEN_AT
) < 0 ||
7929 qib_r_shift(dd
, BISTEN_PORT_SEL
, LEN_PORT_SEL
,
7930 portsel
, NULL
) < 0 ||
7931 qib_r_update(dd
, BISTEN_PORT_SEL
) < 0 ||
7932 qib_r_shift(dd
, BISTEN_AT
, LEN_AT
, at
, NULL
) < 0 ||
7933 qib_r_update(dd
, BISTEN_AT
) < 0 ||
7934 qib_r_shift(dd
, BISTEN_ETM
, LEN_ETM
, etm
, NULL
) < 0 ||
7935 qib_r_update(dd
, BISTEN_ETM
) < 0)
7936 qib_dev_err(dd
, "Failed IB link recovery setup\n");
7939 static void check_7322_rxe_status(struct qib_pportdata
*ppd
)
7941 struct qib_devdata
*dd
= ppd
->dd
;
7944 if (dd
->cspec
->recovery_ports_initted
!= 1)
7945 return; /* rest doesn't apply to dualport */
7946 qib_write_kreg(dd
, kr_control
, dd
->control
|
7947 SYM_MASK(Control
, FreezeMode
));
7948 (void)qib_read_kreg64(dd
, kr_scratch
);
7949 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
7950 fmask
= qib_read_kreg64(dd
, kr_act_fmask
);
7953 * require a powercycle before we'll work again, and make
7954 * sure we get no more interrupts, and don't turn off
7957 ppd
->dd
->cspec
->stay_in_freeze
= 1;
7958 qib_7322_set_intr_state(ppd
->dd
, 0);
7959 qib_write_kreg(dd
, kr_fmask
, 0ULL);
7960 qib_dev_err(dd
, "HCA unusable until powercycled\n");
7961 return; /* eventually reset */
7964 qib_write_kreg(ppd
->dd
, kr_hwerrclear
,
7965 SYM_MASK(HwErrClear
, IBSerdesPClkNotDetectClear_1
));
7967 /* don't do the full clear_freeze(), not needed for this */
7968 qib_write_kreg(dd
, kr_control
, dd
->control
);
7969 qib_read_kreg32(dd
, kr_scratch
);
7970 /* take IBC out of reset */
7971 if (ppd
->link_speed_supported
) {
7972 ppd
->cpspec
->ibcctrl_a
&=
7973 ~SYM_MASK(IBCCtrlA_0
, IBStatIntReductionEn
);
7974 qib_write_kreg_port(ppd
, krp_ibcctrl_a
,
7975 ppd
->cpspec
->ibcctrl_a
);
7976 qib_read_kreg32(dd
, kr_scratch
);
7977 if (ppd
->lflags
& QIBL_IB_LINK_DISABLED
)
7978 qib_set_ib_7322_lstate(ppd
, 0,
7979 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE
);