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ALSA: hda_intel: add position_fix quirk for Asus K53E
[deliverable/linux.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <asm/msidef.h>
35 #include <asm/proto.h>
36 #include <asm/iommu.h>
37 #include <asm/gart.h>
38 #include <asm/dma.h>
39
40 #include "amd_iommu_proto.h"
41 #include "amd_iommu_types.h"
42
43 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
44
45 #define LOOP_TIMEOUT 100000
46
47 /*
48 * This bitmap is used to advertise the page sizes our hardware support
49 * to the IOMMU core, which will then use this information to split
50 * physically contiguous memory regions it is mapping into page sizes
51 * that we support.
52 *
53 * Traditionally the IOMMU core just handed us the mappings directly,
54 * after making sure the size is an order of a 4KiB page and that the
55 * mapping has natural alignment.
56 *
57 * To retain this behavior, we currently advertise that we support
58 * all page sizes that are an order of 4KiB.
59 *
60 * If at some point we'd like to utilize the IOMMU core's new behavior,
61 * we could change this to advertise the real page sizes we support.
62 */
63 #define AMD_IOMMU_PGSIZES (~0xFFFUL)
64
65 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
66
67 /* A list of preallocated protection domains */
68 static LIST_HEAD(iommu_pd_list);
69 static DEFINE_SPINLOCK(iommu_pd_list_lock);
70
71 /* List of all available dev_data structures */
72 static LIST_HEAD(dev_data_list);
73 static DEFINE_SPINLOCK(dev_data_list_lock);
74
75 /*
76 * Domain for untranslated devices - only allocated
77 * if iommu=pt passed on kernel cmd line.
78 */
79 static struct protection_domain *pt_domain;
80
81 static struct iommu_ops amd_iommu_ops;
82
83 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
84 int amd_iommu_max_glx_val = -1;
85
86 static struct dma_map_ops amd_iommu_dma_ops;
87
88 /*
89 * general struct to manage commands send to an IOMMU
90 */
91 struct iommu_cmd {
92 u32 data[4];
93 };
94
95 static void update_domain(struct protection_domain *domain);
96 static int __init alloc_passthrough_domain(void);
97
98 /****************************************************************************
99 *
100 * Helper functions
101 *
102 ****************************************************************************/
103
104 static struct iommu_dev_data *alloc_dev_data(u16 devid)
105 {
106 struct iommu_dev_data *dev_data;
107 unsigned long flags;
108
109 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
110 if (!dev_data)
111 return NULL;
112
113 dev_data->devid = devid;
114 atomic_set(&dev_data->bind, 0);
115
116 spin_lock_irqsave(&dev_data_list_lock, flags);
117 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
118 spin_unlock_irqrestore(&dev_data_list_lock, flags);
119
120 return dev_data;
121 }
122
123 static void free_dev_data(struct iommu_dev_data *dev_data)
124 {
125 unsigned long flags;
126
127 spin_lock_irqsave(&dev_data_list_lock, flags);
128 list_del(&dev_data->dev_data_list);
129 spin_unlock_irqrestore(&dev_data_list_lock, flags);
130
131 kfree(dev_data);
132 }
133
134 static struct iommu_dev_data *search_dev_data(u16 devid)
135 {
136 struct iommu_dev_data *dev_data;
137 unsigned long flags;
138
139 spin_lock_irqsave(&dev_data_list_lock, flags);
140 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
141 if (dev_data->devid == devid)
142 goto out_unlock;
143 }
144
145 dev_data = NULL;
146
147 out_unlock:
148 spin_unlock_irqrestore(&dev_data_list_lock, flags);
149
150 return dev_data;
151 }
152
153 static struct iommu_dev_data *find_dev_data(u16 devid)
154 {
155 struct iommu_dev_data *dev_data;
156
157 dev_data = search_dev_data(devid);
158
159 if (dev_data == NULL)
160 dev_data = alloc_dev_data(devid);
161
162 return dev_data;
163 }
164
165 static inline u16 get_device_id(struct device *dev)
166 {
167 struct pci_dev *pdev = to_pci_dev(dev);
168
169 return calc_devid(pdev->bus->number, pdev->devfn);
170 }
171
172 static struct iommu_dev_data *get_dev_data(struct device *dev)
173 {
174 return dev->archdata.iommu;
175 }
176
177 static bool pci_iommuv2_capable(struct pci_dev *pdev)
178 {
179 static const int caps[] = {
180 PCI_EXT_CAP_ID_ATS,
181 PCI_EXT_CAP_ID_PRI,
182 PCI_EXT_CAP_ID_PASID,
183 };
184 int i, pos;
185
186 for (i = 0; i < 3; ++i) {
187 pos = pci_find_ext_capability(pdev, caps[i]);
188 if (pos == 0)
189 return false;
190 }
191
192 return true;
193 }
194
195 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
196 {
197 struct iommu_dev_data *dev_data;
198
199 dev_data = get_dev_data(&pdev->dev);
200
201 return dev_data->errata & (1 << erratum) ? true : false;
202 }
203
204 /*
205 * In this function the list of preallocated protection domains is traversed to
206 * find the domain for a specific device
207 */
208 static struct dma_ops_domain *find_protection_domain(u16 devid)
209 {
210 struct dma_ops_domain *entry, *ret = NULL;
211 unsigned long flags;
212 u16 alias = amd_iommu_alias_table[devid];
213
214 if (list_empty(&iommu_pd_list))
215 return NULL;
216
217 spin_lock_irqsave(&iommu_pd_list_lock, flags);
218
219 list_for_each_entry(entry, &iommu_pd_list, list) {
220 if (entry->target_dev == devid ||
221 entry->target_dev == alias) {
222 ret = entry;
223 break;
224 }
225 }
226
227 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
228
229 return ret;
230 }
231
232 /*
233 * This function checks if the driver got a valid device from the caller to
234 * avoid dereferencing invalid pointers.
235 */
236 static bool check_device(struct device *dev)
237 {
238 u16 devid;
239
240 if (!dev || !dev->dma_mask)
241 return false;
242
243 /* No device or no PCI device */
244 if (dev->bus != &pci_bus_type)
245 return false;
246
247 devid = get_device_id(dev);
248
249 /* Out of our scope? */
250 if (devid > amd_iommu_last_bdf)
251 return false;
252
253 if (amd_iommu_rlookup_table[devid] == NULL)
254 return false;
255
256 return true;
257 }
258
259 static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to)
260 {
261 pci_dev_put(*from);
262 *from = to;
263 }
264
265 #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
266
267 static int iommu_init_device(struct device *dev)
268 {
269 struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev);
270 struct iommu_dev_data *dev_data;
271 struct iommu_group *group;
272 u16 alias;
273 int ret;
274
275 if (dev->archdata.iommu)
276 return 0;
277
278 dev_data = find_dev_data(get_device_id(dev));
279 if (!dev_data)
280 return -ENOMEM;
281
282 alias = amd_iommu_alias_table[dev_data->devid];
283 if (alias != dev_data->devid) {
284 struct iommu_dev_data *alias_data;
285
286 alias_data = find_dev_data(alias);
287 if (alias_data == NULL) {
288 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
289 dev_name(dev));
290 free_dev_data(dev_data);
291 return -ENOTSUPP;
292 }
293 dev_data->alias_data = alias_data;
294
295 dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff);
296 } else
297 dma_pdev = pci_dev_get(pdev);
298
299 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
300
301 if (dma_pdev->multifunction &&
302 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS))
303 swap_pci_ref(&dma_pdev,
304 pci_get_slot(dma_pdev->bus,
305 PCI_DEVFN(PCI_SLOT(dma_pdev->devfn),
306 0)));
307
308 while (!pci_is_root_bus(dma_pdev->bus)) {
309 if (pci_acs_path_enabled(dma_pdev->bus->self,
310 NULL, REQ_ACS_FLAGS))
311 break;
312
313 swap_pci_ref(&dma_pdev, pci_dev_get(dma_pdev->bus->self));
314 }
315
316 group = iommu_group_get(&dma_pdev->dev);
317 pci_dev_put(dma_pdev);
318 if (!group) {
319 group = iommu_group_alloc();
320 if (IS_ERR(group))
321 return PTR_ERR(group);
322 }
323
324 ret = iommu_group_add_device(group, dev);
325
326 iommu_group_put(group);
327
328 if (ret)
329 return ret;
330
331 if (pci_iommuv2_capable(pdev)) {
332 struct amd_iommu *iommu;
333
334 iommu = amd_iommu_rlookup_table[dev_data->devid];
335 dev_data->iommu_v2 = iommu->is_iommu_v2;
336 }
337
338 dev->archdata.iommu = dev_data;
339
340 return 0;
341 }
342
343 static void iommu_ignore_device(struct device *dev)
344 {
345 u16 devid, alias;
346
347 devid = get_device_id(dev);
348 alias = amd_iommu_alias_table[devid];
349
350 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
351 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
352
353 amd_iommu_rlookup_table[devid] = NULL;
354 amd_iommu_rlookup_table[alias] = NULL;
355 }
356
357 static void iommu_uninit_device(struct device *dev)
358 {
359 iommu_group_remove_device(dev);
360
361 /*
362 * Nothing to do here - we keep dev_data around for unplugged devices
363 * and reuse it when the device is re-plugged - not doing so would
364 * introduce a ton of races.
365 */
366 }
367
368 void __init amd_iommu_uninit_devices(void)
369 {
370 struct iommu_dev_data *dev_data, *n;
371 struct pci_dev *pdev = NULL;
372
373 for_each_pci_dev(pdev) {
374
375 if (!check_device(&pdev->dev))
376 continue;
377
378 iommu_uninit_device(&pdev->dev);
379 }
380
381 /* Free all of our dev_data structures */
382 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
383 free_dev_data(dev_data);
384 }
385
386 int __init amd_iommu_init_devices(void)
387 {
388 struct pci_dev *pdev = NULL;
389 int ret = 0;
390
391 for_each_pci_dev(pdev) {
392
393 if (!check_device(&pdev->dev))
394 continue;
395
396 ret = iommu_init_device(&pdev->dev);
397 if (ret == -ENOTSUPP)
398 iommu_ignore_device(&pdev->dev);
399 else if (ret)
400 goto out_free;
401 }
402
403 return 0;
404
405 out_free:
406
407 amd_iommu_uninit_devices();
408
409 return ret;
410 }
411 #ifdef CONFIG_AMD_IOMMU_STATS
412
413 /*
414 * Initialization code for statistics collection
415 */
416
417 DECLARE_STATS_COUNTER(compl_wait);
418 DECLARE_STATS_COUNTER(cnt_map_single);
419 DECLARE_STATS_COUNTER(cnt_unmap_single);
420 DECLARE_STATS_COUNTER(cnt_map_sg);
421 DECLARE_STATS_COUNTER(cnt_unmap_sg);
422 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
423 DECLARE_STATS_COUNTER(cnt_free_coherent);
424 DECLARE_STATS_COUNTER(cross_page);
425 DECLARE_STATS_COUNTER(domain_flush_single);
426 DECLARE_STATS_COUNTER(domain_flush_all);
427 DECLARE_STATS_COUNTER(alloced_io_mem);
428 DECLARE_STATS_COUNTER(total_map_requests);
429 DECLARE_STATS_COUNTER(complete_ppr);
430 DECLARE_STATS_COUNTER(invalidate_iotlb);
431 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
432 DECLARE_STATS_COUNTER(pri_requests);
433
434 static struct dentry *stats_dir;
435 static struct dentry *de_fflush;
436
437 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
438 {
439 if (stats_dir == NULL)
440 return;
441
442 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
443 &cnt->value);
444 }
445
446 static void amd_iommu_stats_init(void)
447 {
448 stats_dir = debugfs_create_dir("amd-iommu", NULL);
449 if (stats_dir == NULL)
450 return;
451
452 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
453 &amd_iommu_unmap_flush);
454
455 amd_iommu_stats_add(&compl_wait);
456 amd_iommu_stats_add(&cnt_map_single);
457 amd_iommu_stats_add(&cnt_unmap_single);
458 amd_iommu_stats_add(&cnt_map_sg);
459 amd_iommu_stats_add(&cnt_unmap_sg);
460 amd_iommu_stats_add(&cnt_alloc_coherent);
461 amd_iommu_stats_add(&cnt_free_coherent);
462 amd_iommu_stats_add(&cross_page);
463 amd_iommu_stats_add(&domain_flush_single);
464 amd_iommu_stats_add(&domain_flush_all);
465 amd_iommu_stats_add(&alloced_io_mem);
466 amd_iommu_stats_add(&total_map_requests);
467 amd_iommu_stats_add(&complete_ppr);
468 amd_iommu_stats_add(&invalidate_iotlb);
469 amd_iommu_stats_add(&invalidate_iotlb_all);
470 amd_iommu_stats_add(&pri_requests);
471 }
472
473 #endif
474
475 /****************************************************************************
476 *
477 * Interrupt handling functions
478 *
479 ****************************************************************************/
480
481 static void dump_dte_entry(u16 devid)
482 {
483 int i;
484
485 for (i = 0; i < 4; ++i)
486 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
487 amd_iommu_dev_table[devid].data[i]);
488 }
489
490 static void dump_command(unsigned long phys_addr)
491 {
492 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
493 int i;
494
495 for (i = 0; i < 4; ++i)
496 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
497 }
498
499 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
500 {
501 int type, devid, domid, flags;
502 volatile u32 *event = __evt;
503 int count = 0;
504 u64 address;
505
506 retry:
507 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
508 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
509 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
510 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
511 address = (u64)(((u64)event[3]) << 32) | event[2];
512
513 if (type == 0) {
514 /* Did we hit the erratum? */
515 if (++count == LOOP_TIMEOUT) {
516 pr_err("AMD-Vi: No event written to event log\n");
517 return;
518 }
519 udelay(1);
520 goto retry;
521 }
522
523 printk(KERN_ERR "AMD-Vi: Event logged [");
524
525 switch (type) {
526 case EVENT_TYPE_ILL_DEV:
527 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
528 "address=0x%016llx flags=0x%04x]\n",
529 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
530 address, flags);
531 dump_dte_entry(devid);
532 break;
533 case EVENT_TYPE_IO_FAULT:
534 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
535 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
536 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
537 domid, address, flags);
538 break;
539 case EVENT_TYPE_DEV_TAB_ERR:
540 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
541 "address=0x%016llx flags=0x%04x]\n",
542 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
543 address, flags);
544 break;
545 case EVENT_TYPE_PAGE_TAB_ERR:
546 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
547 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
548 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
549 domid, address, flags);
550 break;
551 case EVENT_TYPE_ILL_CMD:
552 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
553 dump_command(address);
554 break;
555 case EVENT_TYPE_CMD_HARD_ERR:
556 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
557 "flags=0x%04x]\n", address, flags);
558 break;
559 case EVENT_TYPE_IOTLB_INV_TO:
560 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
561 "address=0x%016llx]\n",
562 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
563 address);
564 break;
565 case EVENT_TYPE_INV_DEV_REQ:
566 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
567 "address=0x%016llx flags=0x%04x]\n",
568 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
569 address, flags);
570 break;
571 default:
572 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
573 }
574
575 memset(__evt, 0, 4 * sizeof(u32));
576 }
577
578 static void iommu_poll_events(struct amd_iommu *iommu)
579 {
580 u32 head, tail;
581 unsigned long flags;
582
583 spin_lock_irqsave(&iommu->lock, flags);
584
585 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
586 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
587
588 while (head != tail) {
589 iommu_print_event(iommu, iommu->evt_buf + head);
590 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
591 }
592
593 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
594
595 spin_unlock_irqrestore(&iommu->lock, flags);
596 }
597
598 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
599 {
600 struct amd_iommu_fault fault;
601
602 INC_STATS_COUNTER(pri_requests);
603
604 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
605 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
606 return;
607 }
608
609 fault.address = raw[1];
610 fault.pasid = PPR_PASID(raw[0]);
611 fault.device_id = PPR_DEVID(raw[0]);
612 fault.tag = PPR_TAG(raw[0]);
613 fault.flags = PPR_FLAGS(raw[0]);
614
615 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
616 }
617
618 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
619 {
620 unsigned long flags;
621 u32 head, tail;
622
623 if (iommu->ppr_log == NULL)
624 return;
625
626 /* enable ppr interrupts again */
627 writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
628
629 spin_lock_irqsave(&iommu->lock, flags);
630
631 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
632 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
633
634 while (head != tail) {
635 volatile u64 *raw;
636 u64 entry[2];
637 int i;
638
639 raw = (u64 *)(iommu->ppr_log + head);
640
641 /*
642 * Hardware bug: Interrupt may arrive before the entry is
643 * written to memory. If this happens we need to wait for the
644 * entry to arrive.
645 */
646 for (i = 0; i < LOOP_TIMEOUT; ++i) {
647 if (PPR_REQ_TYPE(raw[0]) != 0)
648 break;
649 udelay(1);
650 }
651
652 /* Avoid memcpy function-call overhead */
653 entry[0] = raw[0];
654 entry[1] = raw[1];
655
656 /*
657 * To detect the hardware bug we need to clear the entry
658 * back to zero.
659 */
660 raw[0] = raw[1] = 0UL;
661
662 /* Update head pointer of hardware ring-buffer */
663 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
664 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
665
666 /*
667 * Release iommu->lock because ppr-handling might need to
668 * re-aquire it
669 */
670 spin_unlock_irqrestore(&iommu->lock, flags);
671
672 /* Handle PPR entry */
673 iommu_handle_ppr_entry(iommu, entry);
674
675 spin_lock_irqsave(&iommu->lock, flags);
676
677 /* Refresh ring-buffer information */
678 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
679 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
680 }
681
682 spin_unlock_irqrestore(&iommu->lock, flags);
683 }
684
685 irqreturn_t amd_iommu_int_thread(int irq, void *data)
686 {
687 struct amd_iommu *iommu;
688
689 for_each_iommu(iommu) {
690 iommu_poll_events(iommu);
691 iommu_poll_ppr_log(iommu);
692 }
693
694 return IRQ_HANDLED;
695 }
696
697 irqreturn_t amd_iommu_int_handler(int irq, void *data)
698 {
699 return IRQ_WAKE_THREAD;
700 }
701
702 /****************************************************************************
703 *
704 * IOMMU command queuing functions
705 *
706 ****************************************************************************/
707
708 static int wait_on_sem(volatile u64 *sem)
709 {
710 int i = 0;
711
712 while (*sem == 0 && i < LOOP_TIMEOUT) {
713 udelay(1);
714 i += 1;
715 }
716
717 if (i == LOOP_TIMEOUT) {
718 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
719 return -EIO;
720 }
721
722 return 0;
723 }
724
725 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
726 struct iommu_cmd *cmd,
727 u32 tail)
728 {
729 u8 *target;
730
731 target = iommu->cmd_buf + tail;
732 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
733
734 /* Copy command to buffer */
735 memcpy(target, cmd, sizeof(*cmd));
736
737 /* Tell the IOMMU about it */
738 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
739 }
740
741 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
742 {
743 WARN_ON(address & 0x7ULL);
744
745 memset(cmd, 0, sizeof(*cmd));
746 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
747 cmd->data[1] = upper_32_bits(__pa(address));
748 cmd->data[2] = 1;
749 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
750 }
751
752 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
753 {
754 memset(cmd, 0, sizeof(*cmd));
755 cmd->data[0] = devid;
756 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
757 }
758
759 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
760 size_t size, u16 domid, int pde)
761 {
762 u64 pages;
763 int s;
764
765 pages = iommu_num_pages(address, size, PAGE_SIZE);
766 s = 0;
767
768 if (pages > 1) {
769 /*
770 * If we have to flush more than one page, flush all
771 * TLB entries for this domain
772 */
773 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
774 s = 1;
775 }
776
777 address &= PAGE_MASK;
778
779 memset(cmd, 0, sizeof(*cmd));
780 cmd->data[1] |= domid;
781 cmd->data[2] = lower_32_bits(address);
782 cmd->data[3] = upper_32_bits(address);
783 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
784 if (s) /* size bit - we flush more than one 4kb page */
785 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
786 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
787 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
788 }
789
790 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
791 u64 address, size_t size)
792 {
793 u64 pages;
794 int s;
795
796 pages = iommu_num_pages(address, size, PAGE_SIZE);
797 s = 0;
798
799 if (pages > 1) {
800 /*
801 * If we have to flush more than one page, flush all
802 * TLB entries for this domain
803 */
804 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
805 s = 1;
806 }
807
808 address &= PAGE_MASK;
809
810 memset(cmd, 0, sizeof(*cmd));
811 cmd->data[0] = devid;
812 cmd->data[0] |= (qdep & 0xff) << 24;
813 cmd->data[1] = devid;
814 cmd->data[2] = lower_32_bits(address);
815 cmd->data[3] = upper_32_bits(address);
816 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
817 if (s)
818 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
819 }
820
821 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
822 u64 address, bool size)
823 {
824 memset(cmd, 0, sizeof(*cmd));
825
826 address &= ~(0xfffULL);
827
828 cmd->data[0] = pasid & PASID_MASK;
829 cmd->data[1] = domid;
830 cmd->data[2] = lower_32_bits(address);
831 cmd->data[3] = upper_32_bits(address);
832 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
833 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
834 if (size)
835 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
836 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
837 }
838
839 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
840 int qdep, u64 address, bool size)
841 {
842 memset(cmd, 0, sizeof(*cmd));
843
844 address &= ~(0xfffULL);
845
846 cmd->data[0] = devid;
847 cmd->data[0] |= (pasid & 0xff) << 16;
848 cmd->data[0] |= (qdep & 0xff) << 24;
849 cmd->data[1] = devid;
850 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
851 cmd->data[2] = lower_32_bits(address);
852 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
853 cmd->data[3] = upper_32_bits(address);
854 if (size)
855 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
856 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
857 }
858
859 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
860 int status, int tag, bool gn)
861 {
862 memset(cmd, 0, sizeof(*cmd));
863
864 cmd->data[0] = devid;
865 if (gn) {
866 cmd->data[1] = pasid & PASID_MASK;
867 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
868 }
869 cmd->data[3] = tag & 0x1ff;
870 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
871
872 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
873 }
874
875 static void build_inv_all(struct iommu_cmd *cmd)
876 {
877 memset(cmd, 0, sizeof(*cmd));
878 CMD_SET_TYPE(cmd, CMD_INV_ALL);
879 }
880
881 /*
882 * Writes the command to the IOMMUs command buffer and informs the
883 * hardware about the new command.
884 */
885 static int iommu_queue_command_sync(struct amd_iommu *iommu,
886 struct iommu_cmd *cmd,
887 bool sync)
888 {
889 u32 left, tail, head, next_tail;
890 unsigned long flags;
891
892 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
893
894 again:
895 spin_lock_irqsave(&iommu->lock, flags);
896
897 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
898 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
899 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
900 left = (head - next_tail) % iommu->cmd_buf_size;
901
902 if (left <= 2) {
903 struct iommu_cmd sync_cmd;
904 volatile u64 sem = 0;
905 int ret;
906
907 build_completion_wait(&sync_cmd, (u64)&sem);
908 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
909
910 spin_unlock_irqrestore(&iommu->lock, flags);
911
912 if ((ret = wait_on_sem(&sem)) != 0)
913 return ret;
914
915 goto again;
916 }
917
918 copy_cmd_to_buffer(iommu, cmd, tail);
919
920 /* We need to sync now to make sure all commands are processed */
921 iommu->need_sync = sync;
922
923 spin_unlock_irqrestore(&iommu->lock, flags);
924
925 return 0;
926 }
927
928 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
929 {
930 return iommu_queue_command_sync(iommu, cmd, true);
931 }
932
933 /*
934 * This function queues a completion wait command into the command
935 * buffer of an IOMMU
936 */
937 static int iommu_completion_wait(struct amd_iommu *iommu)
938 {
939 struct iommu_cmd cmd;
940 volatile u64 sem = 0;
941 int ret;
942
943 if (!iommu->need_sync)
944 return 0;
945
946 build_completion_wait(&cmd, (u64)&sem);
947
948 ret = iommu_queue_command_sync(iommu, &cmd, false);
949 if (ret)
950 return ret;
951
952 return wait_on_sem(&sem);
953 }
954
955 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
956 {
957 struct iommu_cmd cmd;
958
959 build_inv_dte(&cmd, devid);
960
961 return iommu_queue_command(iommu, &cmd);
962 }
963
964 static void iommu_flush_dte_all(struct amd_iommu *iommu)
965 {
966 u32 devid;
967
968 for (devid = 0; devid <= 0xffff; ++devid)
969 iommu_flush_dte(iommu, devid);
970
971 iommu_completion_wait(iommu);
972 }
973
974 /*
975 * This function uses heavy locking and may disable irqs for some time. But
976 * this is no issue because it is only called during resume.
977 */
978 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
979 {
980 u32 dom_id;
981
982 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
983 struct iommu_cmd cmd;
984 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
985 dom_id, 1);
986 iommu_queue_command(iommu, &cmd);
987 }
988
989 iommu_completion_wait(iommu);
990 }
991
992 static void iommu_flush_all(struct amd_iommu *iommu)
993 {
994 struct iommu_cmd cmd;
995
996 build_inv_all(&cmd);
997
998 iommu_queue_command(iommu, &cmd);
999 iommu_completion_wait(iommu);
1000 }
1001
1002 void iommu_flush_all_caches(struct amd_iommu *iommu)
1003 {
1004 if (iommu_feature(iommu, FEATURE_IA)) {
1005 iommu_flush_all(iommu);
1006 } else {
1007 iommu_flush_dte_all(iommu);
1008 iommu_flush_tlb_all(iommu);
1009 }
1010 }
1011
1012 /*
1013 * Command send function for flushing on-device TLB
1014 */
1015 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1016 u64 address, size_t size)
1017 {
1018 struct amd_iommu *iommu;
1019 struct iommu_cmd cmd;
1020 int qdep;
1021
1022 qdep = dev_data->ats.qdep;
1023 iommu = amd_iommu_rlookup_table[dev_data->devid];
1024
1025 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1026
1027 return iommu_queue_command(iommu, &cmd);
1028 }
1029
1030 /*
1031 * Command send function for invalidating a device table entry
1032 */
1033 static int device_flush_dte(struct iommu_dev_data *dev_data)
1034 {
1035 struct amd_iommu *iommu;
1036 int ret;
1037
1038 iommu = amd_iommu_rlookup_table[dev_data->devid];
1039
1040 ret = iommu_flush_dte(iommu, dev_data->devid);
1041 if (ret)
1042 return ret;
1043
1044 if (dev_data->ats.enabled)
1045 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1046
1047 return ret;
1048 }
1049
1050 /*
1051 * TLB invalidation function which is called from the mapping functions.
1052 * It invalidates a single PTE if the range to flush is within a single
1053 * page. Otherwise it flushes the whole TLB of the IOMMU.
1054 */
1055 static void __domain_flush_pages(struct protection_domain *domain,
1056 u64 address, size_t size, int pde)
1057 {
1058 struct iommu_dev_data *dev_data;
1059 struct iommu_cmd cmd;
1060 int ret = 0, i;
1061
1062 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1063
1064 for (i = 0; i < amd_iommus_present; ++i) {
1065 if (!domain->dev_iommu[i])
1066 continue;
1067
1068 /*
1069 * Devices of this domain are behind this IOMMU
1070 * We need a TLB flush
1071 */
1072 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1073 }
1074
1075 list_for_each_entry(dev_data, &domain->dev_list, list) {
1076
1077 if (!dev_data->ats.enabled)
1078 continue;
1079
1080 ret |= device_flush_iotlb(dev_data, address, size);
1081 }
1082
1083 WARN_ON(ret);
1084 }
1085
1086 static void domain_flush_pages(struct protection_domain *domain,
1087 u64 address, size_t size)
1088 {
1089 __domain_flush_pages(domain, address, size, 0);
1090 }
1091
1092 /* Flush the whole IO/TLB for a given protection domain */
1093 static void domain_flush_tlb(struct protection_domain *domain)
1094 {
1095 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1096 }
1097
1098 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1099 static void domain_flush_tlb_pde(struct protection_domain *domain)
1100 {
1101 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1102 }
1103
1104 static void domain_flush_complete(struct protection_domain *domain)
1105 {
1106 int i;
1107
1108 for (i = 0; i < amd_iommus_present; ++i) {
1109 if (!domain->dev_iommu[i])
1110 continue;
1111
1112 /*
1113 * Devices of this domain are behind this IOMMU
1114 * We need to wait for completion of all commands.
1115 */
1116 iommu_completion_wait(amd_iommus[i]);
1117 }
1118 }
1119
1120
1121 /*
1122 * This function flushes the DTEs for all devices in domain
1123 */
1124 static void domain_flush_devices(struct protection_domain *domain)
1125 {
1126 struct iommu_dev_data *dev_data;
1127
1128 list_for_each_entry(dev_data, &domain->dev_list, list)
1129 device_flush_dte(dev_data);
1130 }
1131
1132 /****************************************************************************
1133 *
1134 * The functions below are used the create the page table mappings for
1135 * unity mapped regions.
1136 *
1137 ****************************************************************************/
1138
1139 /*
1140 * This function is used to add another level to an IO page table. Adding
1141 * another level increases the size of the address space by 9 bits to a size up
1142 * to 64 bits.
1143 */
1144 static bool increase_address_space(struct protection_domain *domain,
1145 gfp_t gfp)
1146 {
1147 u64 *pte;
1148
1149 if (domain->mode == PAGE_MODE_6_LEVEL)
1150 /* address space already 64 bit large */
1151 return false;
1152
1153 pte = (void *)get_zeroed_page(gfp);
1154 if (!pte)
1155 return false;
1156
1157 *pte = PM_LEVEL_PDE(domain->mode,
1158 virt_to_phys(domain->pt_root));
1159 domain->pt_root = pte;
1160 domain->mode += 1;
1161 domain->updated = true;
1162
1163 return true;
1164 }
1165
1166 static u64 *alloc_pte(struct protection_domain *domain,
1167 unsigned long address,
1168 unsigned long page_size,
1169 u64 **pte_page,
1170 gfp_t gfp)
1171 {
1172 int level, end_lvl;
1173 u64 *pte, *page;
1174
1175 BUG_ON(!is_power_of_2(page_size));
1176
1177 while (address > PM_LEVEL_SIZE(domain->mode))
1178 increase_address_space(domain, gfp);
1179
1180 level = domain->mode - 1;
1181 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1182 address = PAGE_SIZE_ALIGN(address, page_size);
1183 end_lvl = PAGE_SIZE_LEVEL(page_size);
1184
1185 while (level > end_lvl) {
1186 if (!IOMMU_PTE_PRESENT(*pte)) {
1187 page = (u64 *)get_zeroed_page(gfp);
1188 if (!page)
1189 return NULL;
1190 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1191 }
1192
1193 /* No level skipping support yet */
1194 if (PM_PTE_LEVEL(*pte) != level)
1195 return NULL;
1196
1197 level -= 1;
1198
1199 pte = IOMMU_PTE_PAGE(*pte);
1200
1201 if (pte_page && level == end_lvl)
1202 *pte_page = pte;
1203
1204 pte = &pte[PM_LEVEL_INDEX(level, address)];
1205 }
1206
1207 return pte;
1208 }
1209
1210 /*
1211 * This function checks if there is a PTE for a given dma address. If
1212 * there is one, it returns the pointer to it.
1213 */
1214 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
1215 {
1216 int level;
1217 u64 *pte;
1218
1219 if (address > PM_LEVEL_SIZE(domain->mode))
1220 return NULL;
1221
1222 level = domain->mode - 1;
1223 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1224
1225 while (level > 0) {
1226
1227 /* Not Present */
1228 if (!IOMMU_PTE_PRESENT(*pte))
1229 return NULL;
1230
1231 /* Large PTE */
1232 if (PM_PTE_LEVEL(*pte) == 0x07) {
1233 unsigned long pte_mask, __pte;
1234
1235 /*
1236 * If we have a series of large PTEs, make
1237 * sure to return a pointer to the first one.
1238 */
1239 pte_mask = PTE_PAGE_SIZE(*pte);
1240 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1241 __pte = ((unsigned long)pte) & pte_mask;
1242
1243 return (u64 *)__pte;
1244 }
1245
1246 /* No level skipping support yet */
1247 if (PM_PTE_LEVEL(*pte) != level)
1248 return NULL;
1249
1250 level -= 1;
1251
1252 /* Walk to the next level */
1253 pte = IOMMU_PTE_PAGE(*pte);
1254 pte = &pte[PM_LEVEL_INDEX(level, address)];
1255 }
1256
1257 return pte;
1258 }
1259
1260 /*
1261 * Generic mapping functions. It maps a physical address into a DMA
1262 * address space. It allocates the page table pages if necessary.
1263 * In the future it can be extended to a generic mapping function
1264 * supporting all features of AMD IOMMU page tables like level skipping
1265 * and full 64 bit address spaces.
1266 */
1267 static int iommu_map_page(struct protection_domain *dom,
1268 unsigned long bus_addr,
1269 unsigned long phys_addr,
1270 int prot,
1271 unsigned long page_size)
1272 {
1273 u64 __pte, *pte;
1274 int i, count;
1275
1276 if (!(prot & IOMMU_PROT_MASK))
1277 return -EINVAL;
1278
1279 bus_addr = PAGE_ALIGN(bus_addr);
1280 phys_addr = PAGE_ALIGN(phys_addr);
1281 count = PAGE_SIZE_PTE_COUNT(page_size);
1282 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1283
1284 for (i = 0; i < count; ++i)
1285 if (IOMMU_PTE_PRESENT(pte[i]))
1286 return -EBUSY;
1287
1288 if (page_size > PAGE_SIZE) {
1289 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1290 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1291 } else
1292 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1293
1294 if (prot & IOMMU_PROT_IR)
1295 __pte |= IOMMU_PTE_IR;
1296 if (prot & IOMMU_PROT_IW)
1297 __pte |= IOMMU_PTE_IW;
1298
1299 for (i = 0; i < count; ++i)
1300 pte[i] = __pte;
1301
1302 update_domain(dom);
1303
1304 return 0;
1305 }
1306
1307 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1308 unsigned long bus_addr,
1309 unsigned long page_size)
1310 {
1311 unsigned long long unmap_size, unmapped;
1312 u64 *pte;
1313
1314 BUG_ON(!is_power_of_2(page_size));
1315
1316 unmapped = 0;
1317
1318 while (unmapped < page_size) {
1319
1320 pte = fetch_pte(dom, bus_addr);
1321
1322 if (!pte) {
1323 /*
1324 * No PTE for this address
1325 * move forward in 4kb steps
1326 */
1327 unmap_size = PAGE_SIZE;
1328 } else if (PM_PTE_LEVEL(*pte) == 0) {
1329 /* 4kb PTE found for this address */
1330 unmap_size = PAGE_SIZE;
1331 *pte = 0ULL;
1332 } else {
1333 int count, i;
1334
1335 /* Large PTE found which maps this address */
1336 unmap_size = PTE_PAGE_SIZE(*pte);
1337 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1338 for (i = 0; i < count; i++)
1339 pte[i] = 0ULL;
1340 }
1341
1342 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1343 unmapped += unmap_size;
1344 }
1345
1346 BUG_ON(!is_power_of_2(unmapped));
1347
1348 return unmapped;
1349 }
1350
1351 /*
1352 * This function checks if a specific unity mapping entry is needed for
1353 * this specific IOMMU.
1354 */
1355 static int iommu_for_unity_map(struct amd_iommu *iommu,
1356 struct unity_map_entry *entry)
1357 {
1358 u16 bdf, i;
1359
1360 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1361 bdf = amd_iommu_alias_table[i];
1362 if (amd_iommu_rlookup_table[bdf] == iommu)
1363 return 1;
1364 }
1365
1366 return 0;
1367 }
1368
1369 /*
1370 * This function actually applies the mapping to the page table of the
1371 * dma_ops domain.
1372 */
1373 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1374 struct unity_map_entry *e)
1375 {
1376 u64 addr;
1377 int ret;
1378
1379 for (addr = e->address_start; addr < e->address_end;
1380 addr += PAGE_SIZE) {
1381 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1382 PAGE_SIZE);
1383 if (ret)
1384 return ret;
1385 /*
1386 * if unity mapping is in aperture range mark the page
1387 * as allocated in the aperture
1388 */
1389 if (addr < dma_dom->aperture_size)
1390 __set_bit(addr >> PAGE_SHIFT,
1391 dma_dom->aperture[0]->bitmap);
1392 }
1393
1394 return 0;
1395 }
1396
1397 /*
1398 * Init the unity mappings for a specific IOMMU in the system
1399 *
1400 * Basically iterates over all unity mapping entries and applies them to
1401 * the default domain DMA of that IOMMU if necessary.
1402 */
1403 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1404 {
1405 struct unity_map_entry *entry;
1406 int ret;
1407
1408 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1409 if (!iommu_for_unity_map(iommu, entry))
1410 continue;
1411 ret = dma_ops_unity_map(iommu->default_dom, entry);
1412 if (ret)
1413 return ret;
1414 }
1415
1416 return 0;
1417 }
1418
1419 /*
1420 * Inits the unity mappings required for a specific device
1421 */
1422 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1423 u16 devid)
1424 {
1425 struct unity_map_entry *e;
1426 int ret;
1427
1428 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1429 if (!(devid >= e->devid_start && devid <= e->devid_end))
1430 continue;
1431 ret = dma_ops_unity_map(dma_dom, e);
1432 if (ret)
1433 return ret;
1434 }
1435
1436 return 0;
1437 }
1438
1439 /****************************************************************************
1440 *
1441 * The next functions belong to the address allocator for the dma_ops
1442 * interface functions. They work like the allocators in the other IOMMU
1443 * drivers. Its basically a bitmap which marks the allocated pages in
1444 * the aperture. Maybe it could be enhanced in the future to a more
1445 * efficient allocator.
1446 *
1447 ****************************************************************************/
1448
1449 /*
1450 * The address allocator core functions.
1451 *
1452 * called with domain->lock held
1453 */
1454
1455 /*
1456 * Used to reserve address ranges in the aperture (e.g. for exclusion
1457 * ranges.
1458 */
1459 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1460 unsigned long start_page,
1461 unsigned int pages)
1462 {
1463 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1464
1465 if (start_page + pages > last_page)
1466 pages = last_page - start_page;
1467
1468 for (i = start_page; i < start_page + pages; ++i) {
1469 int index = i / APERTURE_RANGE_PAGES;
1470 int page = i % APERTURE_RANGE_PAGES;
1471 __set_bit(page, dom->aperture[index]->bitmap);
1472 }
1473 }
1474
1475 /*
1476 * This function is used to add a new aperture range to an existing
1477 * aperture in case of dma_ops domain allocation or address allocation
1478 * failure.
1479 */
1480 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1481 bool populate, gfp_t gfp)
1482 {
1483 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1484 struct amd_iommu *iommu;
1485 unsigned long i, old_size;
1486
1487 #ifdef CONFIG_IOMMU_STRESS
1488 populate = false;
1489 #endif
1490
1491 if (index >= APERTURE_MAX_RANGES)
1492 return -ENOMEM;
1493
1494 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1495 if (!dma_dom->aperture[index])
1496 return -ENOMEM;
1497
1498 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1499 if (!dma_dom->aperture[index]->bitmap)
1500 goto out_free;
1501
1502 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1503
1504 if (populate) {
1505 unsigned long address = dma_dom->aperture_size;
1506 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1507 u64 *pte, *pte_page;
1508
1509 for (i = 0; i < num_ptes; ++i) {
1510 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1511 &pte_page, gfp);
1512 if (!pte)
1513 goto out_free;
1514
1515 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1516
1517 address += APERTURE_RANGE_SIZE / 64;
1518 }
1519 }
1520
1521 old_size = dma_dom->aperture_size;
1522 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1523
1524 /* Reserve address range used for MSI messages */
1525 if (old_size < MSI_ADDR_BASE_LO &&
1526 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1527 unsigned long spage;
1528 int pages;
1529
1530 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1531 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1532
1533 dma_ops_reserve_addresses(dma_dom, spage, pages);
1534 }
1535
1536 /* Initialize the exclusion range if necessary */
1537 for_each_iommu(iommu) {
1538 if (iommu->exclusion_start &&
1539 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1540 && iommu->exclusion_start < dma_dom->aperture_size) {
1541 unsigned long startpage;
1542 int pages = iommu_num_pages(iommu->exclusion_start,
1543 iommu->exclusion_length,
1544 PAGE_SIZE);
1545 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1546 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1547 }
1548 }
1549
1550 /*
1551 * Check for areas already mapped as present in the new aperture
1552 * range and mark those pages as reserved in the allocator. Such
1553 * mappings may already exist as a result of requested unity
1554 * mappings for devices.
1555 */
1556 for (i = dma_dom->aperture[index]->offset;
1557 i < dma_dom->aperture_size;
1558 i += PAGE_SIZE) {
1559 u64 *pte = fetch_pte(&dma_dom->domain, i);
1560 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1561 continue;
1562
1563 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
1564 }
1565
1566 update_domain(&dma_dom->domain);
1567
1568 return 0;
1569
1570 out_free:
1571 update_domain(&dma_dom->domain);
1572
1573 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1574
1575 kfree(dma_dom->aperture[index]);
1576 dma_dom->aperture[index] = NULL;
1577
1578 return -ENOMEM;
1579 }
1580
1581 static unsigned long dma_ops_area_alloc(struct device *dev,
1582 struct dma_ops_domain *dom,
1583 unsigned int pages,
1584 unsigned long align_mask,
1585 u64 dma_mask,
1586 unsigned long start)
1587 {
1588 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1589 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1590 int i = start >> APERTURE_RANGE_SHIFT;
1591 unsigned long boundary_size;
1592 unsigned long address = -1;
1593 unsigned long limit;
1594
1595 next_bit >>= PAGE_SHIFT;
1596
1597 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1598 PAGE_SIZE) >> PAGE_SHIFT;
1599
1600 for (;i < max_index; ++i) {
1601 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1602
1603 if (dom->aperture[i]->offset >= dma_mask)
1604 break;
1605
1606 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1607 dma_mask >> PAGE_SHIFT);
1608
1609 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1610 limit, next_bit, pages, 0,
1611 boundary_size, align_mask);
1612 if (address != -1) {
1613 address = dom->aperture[i]->offset +
1614 (address << PAGE_SHIFT);
1615 dom->next_address = address + (pages << PAGE_SHIFT);
1616 break;
1617 }
1618
1619 next_bit = 0;
1620 }
1621
1622 return address;
1623 }
1624
1625 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1626 struct dma_ops_domain *dom,
1627 unsigned int pages,
1628 unsigned long align_mask,
1629 u64 dma_mask)
1630 {
1631 unsigned long address;
1632
1633 #ifdef CONFIG_IOMMU_STRESS
1634 dom->next_address = 0;
1635 dom->need_flush = true;
1636 #endif
1637
1638 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1639 dma_mask, dom->next_address);
1640
1641 if (address == -1) {
1642 dom->next_address = 0;
1643 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1644 dma_mask, 0);
1645 dom->need_flush = true;
1646 }
1647
1648 if (unlikely(address == -1))
1649 address = DMA_ERROR_CODE;
1650
1651 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1652
1653 return address;
1654 }
1655
1656 /*
1657 * The address free function.
1658 *
1659 * called with domain->lock held
1660 */
1661 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1662 unsigned long address,
1663 unsigned int pages)
1664 {
1665 unsigned i = address >> APERTURE_RANGE_SHIFT;
1666 struct aperture_range *range = dom->aperture[i];
1667
1668 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1669
1670 #ifdef CONFIG_IOMMU_STRESS
1671 if (i < 4)
1672 return;
1673 #endif
1674
1675 if (address >= dom->next_address)
1676 dom->need_flush = true;
1677
1678 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1679
1680 bitmap_clear(range->bitmap, address, pages);
1681
1682 }
1683
1684 /****************************************************************************
1685 *
1686 * The next functions belong to the domain allocation. A domain is
1687 * allocated for every IOMMU as the default domain. If device isolation
1688 * is enabled, every device get its own domain. The most important thing
1689 * about domains is the page table mapping the DMA address space they
1690 * contain.
1691 *
1692 ****************************************************************************/
1693
1694 /*
1695 * This function adds a protection domain to the global protection domain list
1696 */
1697 static void add_domain_to_list(struct protection_domain *domain)
1698 {
1699 unsigned long flags;
1700
1701 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1702 list_add(&domain->list, &amd_iommu_pd_list);
1703 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1704 }
1705
1706 /*
1707 * This function removes a protection domain to the global
1708 * protection domain list
1709 */
1710 static void del_domain_from_list(struct protection_domain *domain)
1711 {
1712 unsigned long flags;
1713
1714 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1715 list_del(&domain->list);
1716 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1717 }
1718
1719 static u16 domain_id_alloc(void)
1720 {
1721 unsigned long flags;
1722 int id;
1723
1724 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1725 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1726 BUG_ON(id == 0);
1727 if (id > 0 && id < MAX_DOMAIN_ID)
1728 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1729 else
1730 id = 0;
1731 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1732
1733 return id;
1734 }
1735
1736 static void domain_id_free(int id)
1737 {
1738 unsigned long flags;
1739
1740 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1741 if (id > 0 && id < MAX_DOMAIN_ID)
1742 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1743 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1744 }
1745
1746 static void free_pagetable(struct protection_domain *domain)
1747 {
1748 int i, j;
1749 u64 *p1, *p2, *p3;
1750
1751 p1 = domain->pt_root;
1752
1753 if (!p1)
1754 return;
1755
1756 for (i = 0; i < 512; ++i) {
1757 if (!IOMMU_PTE_PRESENT(p1[i]))
1758 continue;
1759
1760 p2 = IOMMU_PTE_PAGE(p1[i]);
1761 for (j = 0; j < 512; ++j) {
1762 if (!IOMMU_PTE_PRESENT(p2[j]))
1763 continue;
1764 p3 = IOMMU_PTE_PAGE(p2[j]);
1765 free_page((unsigned long)p3);
1766 }
1767
1768 free_page((unsigned long)p2);
1769 }
1770
1771 free_page((unsigned long)p1);
1772
1773 domain->pt_root = NULL;
1774 }
1775
1776 static void free_gcr3_tbl_level1(u64 *tbl)
1777 {
1778 u64 *ptr;
1779 int i;
1780
1781 for (i = 0; i < 512; ++i) {
1782 if (!(tbl[i] & GCR3_VALID))
1783 continue;
1784
1785 ptr = __va(tbl[i] & PAGE_MASK);
1786
1787 free_page((unsigned long)ptr);
1788 }
1789 }
1790
1791 static void free_gcr3_tbl_level2(u64 *tbl)
1792 {
1793 u64 *ptr;
1794 int i;
1795
1796 for (i = 0; i < 512; ++i) {
1797 if (!(tbl[i] & GCR3_VALID))
1798 continue;
1799
1800 ptr = __va(tbl[i] & PAGE_MASK);
1801
1802 free_gcr3_tbl_level1(ptr);
1803 }
1804 }
1805
1806 static void free_gcr3_table(struct protection_domain *domain)
1807 {
1808 if (domain->glx == 2)
1809 free_gcr3_tbl_level2(domain->gcr3_tbl);
1810 else if (domain->glx == 1)
1811 free_gcr3_tbl_level1(domain->gcr3_tbl);
1812 else if (domain->glx != 0)
1813 BUG();
1814
1815 free_page((unsigned long)domain->gcr3_tbl);
1816 }
1817
1818 /*
1819 * Free a domain, only used if something went wrong in the
1820 * allocation path and we need to free an already allocated page table
1821 */
1822 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1823 {
1824 int i;
1825
1826 if (!dom)
1827 return;
1828
1829 del_domain_from_list(&dom->domain);
1830
1831 free_pagetable(&dom->domain);
1832
1833 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1834 if (!dom->aperture[i])
1835 continue;
1836 free_page((unsigned long)dom->aperture[i]->bitmap);
1837 kfree(dom->aperture[i]);
1838 }
1839
1840 kfree(dom);
1841 }
1842
1843 /*
1844 * Allocates a new protection domain usable for the dma_ops functions.
1845 * It also initializes the page table and the address allocator data
1846 * structures required for the dma_ops interface
1847 */
1848 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1849 {
1850 struct dma_ops_domain *dma_dom;
1851
1852 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1853 if (!dma_dom)
1854 return NULL;
1855
1856 spin_lock_init(&dma_dom->domain.lock);
1857
1858 dma_dom->domain.id = domain_id_alloc();
1859 if (dma_dom->domain.id == 0)
1860 goto free_dma_dom;
1861 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1862 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1863 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1864 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1865 dma_dom->domain.priv = dma_dom;
1866 if (!dma_dom->domain.pt_root)
1867 goto free_dma_dom;
1868
1869 dma_dom->need_flush = false;
1870 dma_dom->target_dev = 0xffff;
1871
1872 add_domain_to_list(&dma_dom->domain);
1873
1874 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1875 goto free_dma_dom;
1876
1877 /*
1878 * mark the first page as allocated so we never return 0 as
1879 * a valid dma-address. So we can use 0 as error value
1880 */
1881 dma_dom->aperture[0]->bitmap[0] = 1;
1882 dma_dom->next_address = 0;
1883
1884
1885 return dma_dom;
1886
1887 free_dma_dom:
1888 dma_ops_domain_free(dma_dom);
1889
1890 return NULL;
1891 }
1892
1893 /*
1894 * little helper function to check whether a given protection domain is a
1895 * dma_ops domain
1896 */
1897 static bool dma_ops_domain(struct protection_domain *domain)
1898 {
1899 return domain->flags & PD_DMA_OPS_MASK;
1900 }
1901
1902 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1903 {
1904 u64 pte_root = 0;
1905 u64 flags = 0;
1906
1907 if (domain->mode != PAGE_MODE_NONE)
1908 pte_root = virt_to_phys(domain->pt_root);
1909
1910 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1911 << DEV_ENTRY_MODE_SHIFT;
1912 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1913
1914 flags = amd_iommu_dev_table[devid].data[1];
1915
1916 if (ats)
1917 flags |= DTE_FLAG_IOTLB;
1918
1919 if (domain->flags & PD_IOMMUV2_MASK) {
1920 u64 gcr3 = __pa(domain->gcr3_tbl);
1921 u64 glx = domain->glx;
1922 u64 tmp;
1923
1924 pte_root |= DTE_FLAG_GV;
1925 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1926
1927 /* First mask out possible old values for GCR3 table */
1928 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1929 flags &= ~tmp;
1930
1931 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1932 flags &= ~tmp;
1933
1934 /* Encode GCR3 table into DTE */
1935 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1936 pte_root |= tmp;
1937
1938 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1939 flags |= tmp;
1940
1941 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1942 flags |= tmp;
1943 }
1944
1945 flags &= ~(0xffffUL);
1946 flags |= domain->id;
1947
1948 amd_iommu_dev_table[devid].data[1] = flags;
1949 amd_iommu_dev_table[devid].data[0] = pte_root;
1950 }
1951
1952 static void clear_dte_entry(u16 devid)
1953 {
1954 /* remove entry from the device table seen by the hardware */
1955 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1956 amd_iommu_dev_table[devid].data[1] = 0;
1957
1958 amd_iommu_apply_erratum_63(devid);
1959 }
1960
1961 static void do_attach(struct iommu_dev_data *dev_data,
1962 struct protection_domain *domain)
1963 {
1964 struct amd_iommu *iommu;
1965 bool ats;
1966
1967 iommu = amd_iommu_rlookup_table[dev_data->devid];
1968 ats = dev_data->ats.enabled;
1969
1970 /* Update data structures */
1971 dev_data->domain = domain;
1972 list_add(&dev_data->list, &domain->dev_list);
1973 set_dte_entry(dev_data->devid, domain, ats);
1974
1975 /* Do reference counting */
1976 domain->dev_iommu[iommu->index] += 1;
1977 domain->dev_cnt += 1;
1978
1979 /* Flush the DTE entry */
1980 device_flush_dte(dev_data);
1981 }
1982
1983 static void do_detach(struct iommu_dev_data *dev_data)
1984 {
1985 struct amd_iommu *iommu;
1986
1987 iommu = amd_iommu_rlookup_table[dev_data->devid];
1988
1989 /* decrease reference counters */
1990 dev_data->domain->dev_iommu[iommu->index] -= 1;
1991 dev_data->domain->dev_cnt -= 1;
1992
1993 /* Update data structures */
1994 dev_data->domain = NULL;
1995 list_del(&dev_data->list);
1996 clear_dte_entry(dev_data->devid);
1997
1998 /* Flush the DTE entry */
1999 device_flush_dte(dev_data);
2000 }
2001
2002 /*
2003 * If a device is not yet associated with a domain, this function does
2004 * assigns it visible for the hardware
2005 */
2006 static int __attach_device(struct iommu_dev_data *dev_data,
2007 struct protection_domain *domain)
2008 {
2009 int ret;
2010
2011 /* lock domain */
2012 spin_lock(&domain->lock);
2013
2014 if (dev_data->alias_data != NULL) {
2015 struct iommu_dev_data *alias_data = dev_data->alias_data;
2016
2017 /* Some sanity checks */
2018 ret = -EBUSY;
2019 if (alias_data->domain != NULL &&
2020 alias_data->domain != domain)
2021 goto out_unlock;
2022
2023 if (dev_data->domain != NULL &&
2024 dev_data->domain != domain)
2025 goto out_unlock;
2026
2027 /* Do real assignment */
2028 if (alias_data->domain == NULL)
2029 do_attach(alias_data, domain);
2030
2031 atomic_inc(&alias_data->bind);
2032 }
2033
2034 if (dev_data->domain == NULL)
2035 do_attach(dev_data, domain);
2036
2037 atomic_inc(&dev_data->bind);
2038
2039 ret = 0;
2040
2041 out_unlock:
2042
2043 /* ready */
2044 spin_unlock(&domain->lock);
2045
2046 return ret;
2047 }
2048
2049
2050 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2051 {
2052 pci_disable_ats(pdev);
2053 pci_disable_pri(pdev);
2054 pci_disable_pasid(pdev);
2055 }
2056
2057 /* FIXME: Change generic reset-function to do the same */
2058 static int pri_reset_while_enabled(struct pci_dev *pdev)
2059 {
2060 u16 control;
2061 int pos;
2062
2063 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2064 if (!pos)
2065 return -EINVAL;
2066
2067 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2068 control |= PCI_PRI_CTRL_RESET;
2069 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2070
2071 return 0;
2072 }
2073
2074 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2075 {
2076 bool reset_enable;
2077 int reqs, ret;
2078
2079 /* FIXME: Hardcode number of outstanding requests for now */
2080 reqs = 32;
2081 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2082 reqs = 1;
2083 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2084
2085 /* Only allow access to user-accessible pages */
2086 ret = pci_enable_pasid(pdev, 0);
2087 if (ret)
2088 goto out_err;
2089
2090 /* First reset the PRI state of the device */
2091 ret = pci_reset_pri(pdev);
2092 if (ret)
2093 goto out_err;
2094
2095 /* Enable PRI */
2096 ret = pci_enable_pri(pdev, reqs);
2097 if (ret)
2098 goto out_err;
2099
2100 if (reset_enable) {
2101 ret = pri_reset_while_enabled(pdev);
2102 if (ret)
2103 goto out_err;
2104 }
2105
2106 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2107 if (ret)
2108 goto out_err;
2109
2110 return 0;
2111
2112 out_err:
2113 pci_disable_pri(pdev);
2114 pci_disable_pasid(pdev);
2115
2116 return ret;
2117 }
2118
2119 /* FIXME: Move this to PCI code */
2120 #define PCI_PRI_TLP_OFF (1 << 15)
2121
2122 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2123 {
2124 u16 status;
2125 int pos;
2126
2127 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2128 if (!pos)
2129 return false;
2130
2131 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2132
2133 return (status & PCI_PRI_TLP_OFF) ? true : false;
2134 }
2135
2136 /*
2137 * If a device is not yet associated with a domain, this function does
2138 * assigns it visible for the hardware
2139 */
2140 static int attach_device(struct device *dev,
2141 struct protection_domain *domain)
2142 {
2143 struct pci_dev *pdev = to_pci_dev(dev);
2144 struct iommu_dev_data *dev_data;
2145 unsigned long flags;
2146 int ret;
2147
2148 dev_data = get_dev_data(dev);
2149
2150 if (domain->flags & PD_IOMMUV2_MASK) {
2151 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2152 return -EINVAL;
2153
2154 if (pdev_iommuv2_enable(pdev) != 0)
2155 return -EINVAL;
2156
2157 dev_data->ats.enabled = true;
2158 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2159 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2160 } else if (amd_iommu_iotlb_sup &&
2161 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2162 dev_data->ats.enabled = true;
2163 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2164 }
2165
2166 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2167 ret = __attach_device(dev_data, domain);
2168 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2169
2170 /*
2171 * We might boot into a crash-kernel here. The crashed kernel
2172 * left the caches in the IOMMU dirty. So we have to flush
2173 * here to evict all dirty stuff.
2174 */
2175 domain_flush_tlb_pde(domain);
2176
2177 return ret;
2178 }
2179
2180 /*
2181 * Removes a device from a protection domain (unlocked)
2182 */
2183 static void __detach_device(struct iommu_dev_data *dev_data)
2184 {
2185 struct protection_domain *domain;
2186 unsigned long flags;
2187
2188 BUG_ON(!dev_data->domain);
2189
2190 domain = dev_data->domain;
2191
2192 spin_lock_irqsave(&domain->lock, flags);
2193
2194 if (dev_data->alias_data != NULL) {
2195 struct iommu_dev_data *alias_data = dev_data->alias_data;
2196
2197 if (atomic_dec_and_test(&alias_data->bind))
2198 do_detach(alias_data);
2199 }
2200
2201 if (atomic_dec_and_test(&dev_data->bind))
2202 do_detach(dev_data);
2203
2204 spin_unlock_irqrestore(&domain->lock, flags);
2205
2206 /*
2207 * If we run in passthrough mode the device must be assigned to the
2208 * passthrough domain if it is detached from any other domain.
2209 * Make sure we can deassign from the pt_domain itself.
2210 */
2211 if (dev_data->passthrough &&
2212 (dev_data->domain == NULL && domain != pt_domain))
2213 __attach_device(dev_data, pt_domain);
2214 }
2215
2216 /*
2217 * Removes a device from a protection domain (with devtable_lock held)
2218 */
2219 static void detach_device(struct device *dev)
2220 {
2221 struct protection_domain *domain;
2222 struct iommu_dev_data *dev_data;
2223 unsigned long flags;
2224
2225 dev_data = get_dev_data(dev);
2226 domain = dev_data->domain;
2227
2228 /* lock device table */
2229 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2230 __detach_device(dev_data);
2231 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2232
2233 if (domain->flags & PD_IOMMUV2_MASK)
2234 pdev_iommuv2_disable(to_pci_dev(dev));
2235 else if (dev_data->ats.enabled)
2236 pci_disable_ats(to_pci_dev(dev));
2237
2238 dev_data->ats.enabled = false;
2239 }
2240
2241 /*
2242 * Find out the protection domain structure for a given PCI device. This
2243 * will give us the pointer to the page table root for example.
2244 */
2245 static struct protection_domain *domain_for_device(struct device *dev)
2246 {
2247 struct iommu_dev_data *dev_data;
2248 struct protection_domain *dom = NULL;
2249 unsigned long flags;
2250
2251 dev_data = get_dev_data(dev);
2252
2253 if (dev_data->domain)
2254 return dev_data->domain;
2255
2256 if (dev_data->alias_data != NULL) {
2257 struct iommu_dev_data *alias_data = dev_data->alias_data;
2258
2259 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2260 if (alias_data->domain != NULL) {
2261 __attach_device(dev_data, alias_data->domain);
2262 dom = alias_data->domain;
2263 }
2264 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2265 }
2266
2267 return dom;
2268 }
2269
2270 static int device_change_notifier(struct notifier_block *nb,
2271 unsigned long action, void *data)
2272 {
2273 struct dma_ops_domain *dma_domain;
2274 struct protection_domain *domain;
2275 struct iommu_dev_data *dev_data;
2276 struct device *dev = data;
2277 struct amd_iommu *iommu;
2278 unsigned long flags;
2279 u16 devid;
2280
2281 if (!check_device(dev))
2282 return 0;
2283
2284 devid = get_device_id(dev);
2285 iommu = amd_iommu_rlookup_table[devid];
2286 dev_data = get_dev_data(dev);
2287
2288 switch (action) {
2289 case BUS_NOTIFY_UNBOUND_DRIVER:
2290
2291 domain = domain_for_device(dev);
2292
2293 if (!domain)
2294 goto out;
2295 if (dev_data->passthrough)
2296 break;
2297 detach_device(dev);
2298 break;
2299 case BUS_NOTIFY_ADD_DEVICE:
2300
2301 iommu_init_device(dev);
2302
2303 /*
2304 * dev_data is still NULL and
2305 * got initialized in iommu_init_device
2306 */
2307 dev_data = get_dev_data(dev);
2308
2309 if (iommu_pass_through || dev_data->iommu_v2) {
2310 dev_data->passthrough = true;
2311 attach_device(dev, pt_domain);
2312 break;
2313 }
2314
2315 domain = domain_for_device(dev);
2316
2317 /* allocate a protection domain if a device is added */
2318 dma_domain = find_protection_domain(devid);
2319 if (dma_domain)
2320 goto out;
2321 dma_domain = dma_ops_domain_alloc();
2322 if (!dma_domain)
2323 goto out;
2324 dma_domain->target_dev = devid;
2325
2326 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2327 list_add_tail(&dma_domain->list, &iommu_pd_list);
2328 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2329
2330 dev_data = get_dev_data(dev);
2331
2332 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2333
2334 break;
2335 case BUS_NOTIFY_DEL_DEVICE:
2336
2337 iommu_uninit_device(dev);
2338
2339 default:
2340 goto out;
2341 }
2342
2343 iommu_completion_wait(iommu);
2344
2345 out:
2346 return 0;
2347 }
2348
2349 static struct notifier_block device_nb = {
2350 .notifier_call = device_change_notifier,
2351 };
2352
2353 void amd_iommu_init_notifier(void)
2354 {
2355 bus_register_notifier(&pci_bus_type, &device_nb);
2356 }
2357
2358 /*****************************************************************************
2359 *
2360 * The next functions belong to the dma_ops mapping/unmapping code.
2361 *
2362 *****************************************************************************/
2363
2364 /*
2365 * In the dma_ops path we only have the struct device. This function
2366 * finds the corresponding IOMMU, the protection domain and the
2367 * requestor id for a given device.
2368 * If the device is not yet associated with a domain this is also done
2369 * in this function.
2370 */
2371 static struct protection_domain *get_domain(struct device *dev)
2372 {
2373 struct protection_domain *domain;
2374 struct dma_ops_domain *dma_dom;
2375 u16 devid = get_device_id(dev);
2376
2377 if (!check_device(dev))
2378 return ERR_PTR(-EINVAL);
2379
2380 domain = domain_for_device(dev);
2381 if (domain != NULL && !dma_ops_domain(domain))
2382 return ERR_PTR(-EBUSY);
2383
2384 if (domain != NULL)
2385 return domain;
2386
2387 /* Device not bount yet - bind it */
2388 dma_dom = find_protection_domain(devid);
2389 if (!dma_dom)
2390 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2391 attach_device(dev, &dma_dom->domain);
2392 DUMP_printk("Using protection domain %d for device %s\n",
2393 dma_dom->domain.id, dev_name(dev));
2394
2395 return &dma_dom->domain;
2396 }
2397
2398 static void update_device_table(struct protection_domain *domain)
2399 {
2400 struct iommu_dev_data *dev_data;
2401
2402 list_for_each_entry(dev_data, &domain->dev_list, list)
2403 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2404 }
2405
2406 static void update_domain(struct protection_domain *domain)
2407 {
2408 if (!domain->updated)
2409 return;
2410
2411 update_device_table(domain);
2412
2413 domain_flush_devices(domain);
2414 domain_flush_tlb_pde(domain);
2415
2416 domain->updated = false;
2417 }
2418
2419 /*
2420 * This function fetches the PTE for a given address in the aperture
2421 */
2422 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2423 unsigned long address)
2424 {
2425 struct aperture_range *aperture;
2426 u64 *pte, *pte_page;
2427
2428 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2429 if (!aperture)
2430 return NULL;
2431
2432 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2433 if (!pte) {
2434 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2435 GFP_ATOMIC);
2436 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2437 } else
2438 pte += PM_LEVEL_INDEX(0, address);
2439
2440 update_domain(&dom->domain);
2441
2442 return pte;
2443 }
2444
2445 /*
2446 * This is the generic map function. It maps one 4kb page at paddr to
2447 * the given address in the DMA address space for the domain.
2448 */
2449 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2450 unsigned long address,
2451 phys_addr_t paddr,
2452 int direction)
2453 {
2454 u64 *pte, __pte;
2455
2456 WARN_ON(address > dom->aperture_size);
2457
2458 paddr &= PAGE_MASK;
2459
2460 pte = dma_ops_get_pte(dom, address);
2461 if (!pte)
2462 return DMA_ERROR_CODE;
2463
2464 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2465
2466 if (direction == DMA_TO_DEVICE)
2467 __pte |= IOMMU_PTE_IR;
2468 else if (direction == DMA_FROM_DEVICE)
2469 __pte |= IOMMU_PTE_IW;
2470 else if (direction == DMA_BIDIRECTIONAL)
2471 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2472
2473 WARN_ON(*pte);
2474
2475 *pte = __pte;
2476
2477 return (dma_addr_t)address;
2478 }
2479
2480 /*
2481 * The generic unmapping function for on page in the DMA address space.
2482 */
2483 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2484 unsigned long address)
2485 {
2486 struct aperture_range *aperture;
2487 u64 *pte;
2488
2489 if (address >= dom->aperture_size)
2490 return;
2491
2492 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2493 if (!aperture)
2494 return;
2495
2496 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2497 if (!pte)
2498 return;
2499
2500 pte += PM_LEVEL_INDEX(0, address);
2501
2502 WARN_ON(!*pte);
2503
2504 *pte = 0ULL;
2505 }
2506
2507 /*
2508 * This function contains common code for mapping of a physically
2509 * contiguous memory region into DMA address space. It is used by all
2510 * mapping functions provided with this IOMMU driver.
2511 * Must be called with the domain lock held.
2512 */
2513 static dma_addr_t __map_single(struct device *dev,
2514 struct dma_ops_domain *dma_dom,
2515 phys_addr_t paddr,
2516 size_t size,
2517 int dir,
2518 bool align,
2519 u64 dma_mask)
2520 {
2521 dma_addr_t offset = paddr & ~PAGE_MASK;
2522 dma_addr_t address, start, ret;
2523 unsigned int pages;
2524 unsigned long align_mask = 0;
2525 int i;
2526
2527 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2528 paddr &= PAGE_MASK;
2529
2530 INC_STATS_COUNTER(total_map_requests);
2531
2532 if (pages > 1)
2533 INC_STATS_COUNTER(cross_page);
2534
2535 if (align)
2536 align_mask = (1UL << get_order(size)) - 1;
2537
2538 retry:
2539 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2540 dma_mask);
2541 if (unlikely(address == DMA_ERROR_CODE)) {
2542 /*
2543 * setting next_address here will let the address
2544 * allocator only scan the new allocated range in the
2545 * first run. This is a small optimization.
2546 */
2547 dma_dom->next_address = dma_dom->aperture_size;
2548
2549 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2550 goto out;
2551
2552 /*
2553 * aperture was successfully enlarged by 128 MB, try
2554 * allocation again
2555 */
2556 goto retry;
2557 }
2558
2559 start = address;
2560 for (i = 0; i < pages; ++i) {
2561 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2562 if (ret == DMA_ERROR_CODE)
2563 goto out_unmap;
2564
2565 paddr += PAGE_SIZE;
2566 start += PAGE_SIZE;
2567 }
2568 address += offset;
2569
2570 ADD_STATS_COUNTER(alloced_io_mem, size);
2571
2572 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2573 domain_flush_tlb(&dma_dom->domain);
2574 dma_dom->need_flush = false;
2575 } else if (unlikely(amd_iommu_np_cache))
2576 domain_flush_pages(&dma_dom->domain, address, size);
2577
2578 out:
2579 return address;
2580
2581 out_unmap:
2582
2583 for (--i; i >= 0; --i) {
2584 start -= PAGE_SIZE;
2585 dma_ops_domain_unmap(dma_dom, start);
2586 }
2587
2588 dma_ops_free_addresses(dma_dom, address, pages);
2589
2590 return DMA_ERROR_CODE;
2591 }
2592
2593 /*
2594 * Does the reverse of the __map_single function. Must be called with
2595 * the domain lock held too
2596 */
2597 static void __unmap_single(struct dma_ops_domain *dma_dom,
2598 dma_addr_t dma_addr,
2599 size_t size,
2600 int dir)
2601 {
2602 dma_addr_t flush_addr;
2603 dma_addr_t i, start;
2604 unsigned int pages;
2605
2606 if ((dma_addr == DMA_ERROR_CODE) ||
2607 (dma_addr + size > dma_dom->aperture_size))
2608 return;
2609
2610 flush_addr = dma_addr;
2611 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2612 dma_addr &= PAGE_MASK;
2613 start = dma_addr;
2614
2615 for (i = 0; i < pages; ++i) {
2616 dma_ops_domain_unmap(dma_dom, start);
2617 start += PAGE_SIZE;
2618 }
2619
2620 SUB_STATS_COUNTER(alloced_io_mem, size);
2621
2622 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2623
2624 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2625 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2626 dma_dom->need_flush = false;
2627 }
2628 }
2629
2630 /*
2631 * The exported map_single function for dma_ops.
2632 */
2633 static dma_addr_t map_page(struct device *dev, struct page *page,
2634 unsigned long offset, size_t size,
2635 enum dma_data_direction dir,
2636 struct dma_attrs *attrs)
2637 {
2638 unsigned long flags;
2639 struct protection_domain *domain;
2640 dma_addr_t addr;
2641 u64 dma_mask;
2642 phys_addr_t paddr = page_to_phys(page) + offset;
2643
2644 INC_STATS_COUNTER(cnt_map_single);
2645
2646 domain = get_domain(dev);
2647 if (PTR_ERR(domain) == -EINVAL)
2648 return (dma_addr_t)paddr;
2649 else if (IS_ERR(domain))
2650 return DMA_ERROR_CODE;
2651
2652 dma_mask = *dev->dma_mask;
2653
2654 spin_lock_irqsave(&domain->lock, flags);
2655
2656 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2657 dma_mask);
2658 if (addr == DMA_ERROR_CODE)
2659 goto out;
2660
2661 domain_flush_complete(domain);
2662
2663 out:
2664 spin_unlock_irqrestore(&domain->lock, flags);
2665
2666 return addr;
2667 }
2668
2669 /*
2670 * The exported unmap_single function for dma_ops.
2671 */
2672 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2673 enum dma_data_direction dir, struct dma_attrs *attrs)
2674 {
2675 unsigned long flags;
2676 struct protection_domain *domain;
2677
2678 INC_STATS_COUNTER(cnt_unmap_single);
2679
2680 domain = get_domain(dev);
2681 if (IS_ERR(domain))
2682 return;
2683
2684 spin_lock_irqsave(&domain->lock, flags);
2685
2686 __unmap_single(domain->priv, dma_addr, size, dir);
2687
2688 domain_flush_complete(domain);
2689
2690 spin_unlock_irqrestore(&domain->lock, flags);
2691 }
2692
2693 /*
2694 * This is a special map_sg function which is used if we should map a
2695 * device which is not handled by an AMD IOMMU in the system.
2696 */
2697 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2698 int nelems, int dir)
2699 {
2700 struct scatterlist *s;
2701 int i;
2702
2703 for_each_sg(sglist, s, nelems, i) {
2704 s->dma_address = (dma_addr_t)sg_phys(s);
2705 s->dma_length = s->length;
2706 }
2707
2708 return nelems;
2709 }
2710
2711 /*
2712 * The exported map_sg function for dma_ops (handles scatter-gather
2713 * lists).
2714 */
2715 static int map_sg(struct device *dev, struct scatterlist *sglist,
2716 int nelems, enum dma_data_direction dir,
2717 struct dma_attrs *attrs)
2718 {
2719 unsigned long flags;
2720 struct protection_domain *domain;
2721 int i;
2722 struct scatterlist *s;
2723 phys_addr_t paddr;
2724 int mapped_elems = 0;
2725 u64 dma_mask;
2726
2727 INC_STATS_COUNTER(cnt_map_sg);
2728
2729 domain = get_domain(dev);
2730 if (PTR_ERR(domain) == -EINVAL)
2731 return map_sg_no_iommu(dev, sglist, nelems, dir);
2732 else if (IS_ERR(domain))
2733 return 0;
2734
2735 dma_mask = *dev->dma_mask;
2736
2737 spin_lock_irqsave(&domain->lock, flags);
2738
2739 for_each_sg(sglist, s, nelems, i) {
2740 paddr = sg_phys(s);
2741
2742 s->dma_address = __map_single(dev, domain->priv,
2743 paddr, s->length, dir, false,
2744 dma_mask);
2745
2746 if (s->dma_address) {
2747 s->dma_length = s->length;
2748 mapped_elems++;
2749 } else
2750 goto unmap;
2751 }
2752
2753 domain_flush_complete(domain);
2754
2755 out:
2756 spin_unlock_irqrestore(&domain->lock, flags);
2757
2758 return mapped_elems;
2759 unmap:
2760 for_each_sg(sglist, s, mapped_elems, i) {
2761 if (s->dma_address)
2762 __unmap_single(domain->priv, s->dma_address,
2763 s->dma_length, dir);
2764 s->dma_address = s->dma_length = 0;
2765 }
2766
2767 mapped_elems = 0;
2768
2769 goto out;
2770 }
2771
2772 /*
2773 * The exported map_sg function for dma_ops (handles scatter-gather
2774 * lists).
2775 */
2776 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2777 int nelems, enum dma_data_direction dir,
2778 struct dma_attrs *attrs)
2779 {
2780 unsigned long flags;
2781 struct protection_domain *domain;
2782 struct scatterlist *s;
2783 int i;
2784
2785 INC_STATS_COUNTER(cnt_unmap_sg);
2786
2787 domain = get_domain(dev);
2788 if (IS_ERR(domain))
2789 return;
2790
2791 spin_lock_irqsave(&domain->lock, flags);
2792
2793 for_each_sg(sglist, s, nelems, i) {
2794 __unmap_single(domain->priv, s->dma_address,
2795 s->dma_length, dir);
2796 s->dma_address = s->dma_length = 0;
2797 }
2798
2799 domain_flush_complete(domain);
2800
2801 spin_unlock_irqrestore(&domain->lock, flags);
2802 }
2803
2804 /*
2805 * The exported alloc_coherent function for dma_ops.
2806 */
2807 static void *alloc_coherent(struct device *dev, size_t size,
2808 dma_addr_t *dma_addr, gfp_t flag,
2809 struct dma_attrs *attrs)
2810 {
2811 unsigned long flags;
2812 void *virt_addr;
2813 struct protection_domain *domain;
2814 phys_addr_t paddr;
2815 u64 dma_mask = dev->coherent_dma_mask;
2816
2817 INC_STATS_COUNTER(cnt_alloc_coherent);
2818
2819 domain = get_domain(dev);
2820 if (PTR_ERR(domain) == -EINVAL) {
2821 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2822 *dma_addr = __pa(virt_addr);
2823 return virt_addr;
2824 } else if (IS_ERR(domain))
2825 return NULL;
2826
2827 dma_mask = dev->coherent_dma_mask;
2828 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2829 flag |= __GFP_ZERO;
2830
2831 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2832 if (!virt_addr)
2833 return NULL;
2834
2835 paddr = virt_to_phys(virt_addr);
2836
2837 if (!dma_mask)
2838 dma_mask = *dev->dma_mask;
2839
2840 spin_lock_irqsave(&domain->lock, flags);
2841
2842 *dma_addr = __map_single(dev, domain->priv, paddr,
2843 size, DMA_BIDIRECTIONAL, true, dma_mask);
2844
2845 if (*dma_addr == DMA_ERROR_CODE) {
2846 spin_unlock_irqrestore(&domain->lock, flags);
2847 goto out_free;
2848 }
2849
2850 domain_flush_complete(domain);
2851
2852 spin_unlock_irqrestore(&domain->lock, flags);
2853
2854 return virt_addr;
2855
2856 out_free:
2857
2858 free_pages((unsigned long)virt_addr, get_order(size));
2859
2860 return NULL;
2861 }
2862
2863 /*
2864 * The exported free_coherent function for dma_ops.
2865 */
2866 static void free_coherent(struct device *dev, size_t size,
2867 void *virt_addr, dma_addr_t dma_addr,
2868 struct dma_attrs *attrs)
2869 {
2870 unsigned long flags;
2871 struct protection_domain *domain;
2872
2873 INC_STATS_COUNTER(cnt_free_coherent);
2874
2875 domain = get_domain(dev);
2876 if (IS_ERR(domain))
2877 goto free_mem;
2878
2879 spin_lock_irqsave(&domain->lock, flags);
2880
2881 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2882
2883 domain_flush_complete(domain);
2884
2885 spin_unlock_irqrestore(&domain->lock, flags);
2886
2887 free_mem:
2888 free_pages((unsigned long)virt_addr, get_order(size));
2889 }
2890
2891 /*
2892 * This function is called by the DMA layer to find out if we can handle a
2893 * particular device. It is part of the dma_ops.
2894 */
2895 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2896 {
2897 return check_device(dev);
2898 }
2899
2900 /*
2901 * The function for pre-allocating protection domains.
2902 *
2903 * If the driver core informs the DMA layer if a driver grabs a device
2904 * we don't need to preallocate the protection domains anymore.
2905 * For now we have to.
2906 */
2907 static void __init prealloc_protection_domains(void)
2908 {
2909 struct iommu_dev_data *dev_data;
2910 struct dma_ops_domain *dma_dom;
2911 struct pci_dev *dev = NULL;
2912 u16 devid;
2913
2914 for_each_pci_dev(dev) {
2915
2916 /* Do we handle this device? */
2917 if (!check_device(&dev->dev))
2918 continue;
2919
2920 dev_data = get_dev_data(&dev->dev);
2921 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
2922 /* Make sure passthrough domain is allocated */
2923 alloc_passthrough_domain();
2924 dev_data->passthrough = true;
2925 attach_device(&dev->dev, pt_domain);
2926 pr_info("AMD-Vi: Using passthough domain for device %s\n",
2927 dev_name(&dev->dev));
2928 }
2929
2930 /* Is there already any domain for it? */
2931 if (domain_for_device(&dev->dev))
2932 continue;
2933
2934 devid = get_device_id(&dev->dev);
2935
2936 dma_dom = dma_ops_domain_alloc();
2937 if (!dma_dom)
2938 continue;
2939 init_unity_mappings_for_device(dma_dom, devid);
2940 dma_dom->target_dev = devid;
2941
2942 attach_device(&dev->dev, &dma_dom->domain);
2943
2944 list_add_tail(&dma_dom->list, &iommu_pd_list);
2945 }
2946 }
2947
2948 static struct dma_map_ops amd_iommu_dma_ops = {
2949 .alloc = alloc_coherent,
2950 .free = free_coherent,
2951 .map_page = map_page,
2952 .unmap_page = unmap_page,
2953 .map_sg = map_sg,
2954 .unmap_sg = unmap_sg,
2955 .dma_supported = amd_iommu_dma_supported,
2956 };
2957
2958 static unsigned device_dma_ops_init(void)
2959 {
2960 struct iommu_dev_data *dev_data;
2961 struct pci_dev *pdev = NULL;
2962 unsigned unhandled = 0;
2963
2964 for_each_pci_dev(pdev) {
2965 if (!check_device(&pdev->dev)) {
2966
2967 iommu_ignore_device(&pdev->dev);
2968
2969 unhandled += 1;
2970 continue;
2971 }
2972
2973 dev_data = get_dev_data(&pdev->dev);
2974
2975 if (!dev_data->passthrough)
2976 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
2977 else
2978 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
2979 }
2980
2981 return unhandled;
2982 }
2983
2984 /*
2985 * The function which clues the AMD IOMMU driver into dma_ops.
2986 */
2987
2988 void __init amd_iommu_init_api(void)
2989 {
2990 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2991 }
2992
2993 int __init amd_iommu_init_dma_ops(void)
2994 {
2995 struct amd_iommu *iommu;
2996 int ret, unhandled;
2997
2998 /*
2999 * first allocate a default protection domain for every IOMMU we
3000 * found in the system. Devices not assigned to any other
3001 * protection domain will be assigned to the default one.
3002 */
3003 for_each_iommu(iommu) {
3004 iommu->default_dom = dma_ops_domain_alloc();
3005 if (iommu->default_dom == NULL)
3006 return -ENOMEM;
3007 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
3008 ret = iommu_init_unity_mappings(iommu);
3009 if (ret)
3010 goto free_domains;
3011 }
3012
3013 /*
3014 * Pre-allocate the protection domains for each device.
3015 */
3016 prealloc_protection_domains();
3017
3018 iommu_detected = 1;
3019 swiotlb = 0;
3020
3021 /* Make the driver finally visible to the drivers */
3022 unhandled = device_dma_ops_init();
3023 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3024 /* There are unhandled devices - initialize swiotlb for them */
3025 swiotlb = 1;
3026 }
3027
3028 amd_iommu_stats_init();
3029
3030 if (amd_iommu_unmap_flush)
3031 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3032 else
3033 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3034
3035 return 0;
3036
3037 free_domains:
3038
3039 for_each_iommu(iommu) {
3040 if (iommu->default_dom)
3041 dma_ops_domain_free(iommu->default_dom);
3042 }
3043
3044 return ret;
3045 }
3046
3047 /*****************************************************************************
3048 *
3049 * The following functions belong to the exported interface of AMD IOMMU
3050 *
3051 * This interface allows access to lower level functions of the IOMMU
3052 * like protection domain handling and assignement of devices to domains
3053 * which is not possible with the dma_ops interface.
3054 *
3055 *****************************************************************************/
3056
3057 static void cleanup_domain(struct protection_domain *domain)
3058 {
3059 struct iommu_dev_data *dev_data, *next;
3060 unsigned long flags;
3061
3062 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3063
3064 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
3065 __detach_device(dev_data);
3066 atomic_set(&dev_data->bind, 0);
3067 }
3068
3069 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3070 }
3071
3072 static void protection_domain_free(struct protection_domain *domain)
3073 {
3074 if (!domain)
3075 return;
3076
3077 del_domain_from_list(domain);
3078
3079 if (domain->id)
3080 domain_id_free(domain->id);
3081
3082 kfree(domain);
3083 }
3084
3085 static struct protection_domain *protection_domain_alloc(void)
3086 {
3087 struct protection_domain *domain;
3088
3089 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3090 if (!domain)
3091 return NULL;
3092
3093 spin_lock_init(&domain->lock);
3094 mutex_init(&domain->api_lock);
3095 domain->id = domain_id_alloc();
3096 if (!domain->id)
3097 goto out_err;
3098 INIT_LIST_HEAD(&domain->dev_list);
3099
3100 add_domain_to_list(domain);
3101
3102 return domain;
3103
3104 out_err:
3105 kfree(domain);
3106
3107 return NULL;
3108 }
3109
3110 static int __init alloc_passthrough_domain(void)
3111 {
3112 if (pt_domain != NULL)
3113 return 0;
3114
3115 /* allocate passthrough domain */
3116 pt_domain = protection_domain_alloc();
3117 if (!pt_domain)
3118 return -ENOMEM;
3119
3120 pt_domain->mode = PAGE_MODE_NONE;
3121
3122 return 0;
3123 }
3124 static int amd_iommu_domain_init(struct iommu_domain *dom)
3125 {
3126 struct protection_domain *domain;
3127
3128 domain = protection_domain_alloc();
3129 if (!domain)
3130 goto out_free;
3131
3132 domain->mode = PAGE_MODE_3_LEVEL;
3133 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3134 if (!domain->pt_root)
3135 goto out_free;
3136
3137 domain->iommu_domain = dom;
3138
3139 dom->priv = domain;
3140
3141 dom->geometry.aperture_start = 0;
3142 dom->geometry.aperture_end = ~0ULL;
3143 dom->geometry.force_aperture = true;
3144
3145 return 0;
3146
3147 out_free:
3148 protection_domain_free(domain);
3149
3150 return -ENOMEM;
3151 }
3152
3153 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3154 {
3155 struct protection_domain *domain = dom->priv;
3156
3157 if (!domain)
3158 return;
3159
3160 if (domain->dev_cnt > 0)
3161 cleanup_domain(domain);
3162
3163 BUG_ON(domain->dev_cnt != 0);
3164
3165 if (domain->mode != PAGE_MODE_NONE)
3166 free_pagetable(domain);
3167
3168 if (domain->flags & PD_IOMMUV2_MASK)
3169 free_gcr3_table(domain);
3170
3171 protection_domain_free(domain);
3172
3173 dom->priv = NULL;
3174 }
3175
3176 static void amd_iommu_detach_device(struct iommu_domain *dom,
3177 struct device *dev)
3178 {
3179 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3180 struct amd_iommu *iommu;
3181 u16 devid;
3182
3183 if (!check_device(dev))
3184 return;
3185
3186 devid = get_device_id(dev);
3187
3188 if (dev_data->domain != NULL)
3189 detach_device(dev);
3190
3191 iommu = amd_iommu_rlookup_table[devid];
3192 if (!iommu)
3193 return;
3194
3195 iommu_completion_wait(iommu);
3196 }
3197
3198 static int amd_iommu_attach_device(struct iommu_domain *dom,
3199 struct device *dev)
3200 {
3201 struct protection_domain *domain = dom->priv;
3202 struct iommu_dev_data *dev_data;
3203 struct amd_iommu *iommu;
3204 int ret;
3205
3206 if (!check_device(dev))
3207 return -EINVAL;
3208
3209 dev_data = dev->archdata.iommu;
3210
3211 iommu = amd_iommu_rlookup_table[dev_data->devid];
3212 if (!iommu)
3213 return -EINVAL;
3214
3215 if (dev_data->domain)
3216 detach_device(dev);
3217
3218 ret = attach_device(dev, domain);
3219
3220 iommu_completion_wait(iommu);
3221
3222 return ret;
3223 }
3224
3225 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3226 phys_addr_t paddr, size_t page_size, int iommu_prot)
3227 {
3228 struct protection_domain *domain = dom->priv;
3229 int prot = 0;
3230 int ret;
3231
3232 if (domain->mode == PAGE_MODE_NONE)
3233 return -EINVAL;
3234
3235 if (iommu_prot & IOMMU_READ)
3236 prot |= IOMMU_PROT_IR;
3237 if (iommu_prot & IOMMU_WRITE)
3238 prot |= IOMMU_PROT_IW;
3239
3240 mutex_lock(&domain->api_lock);
3241 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3242 mutex_unlock(&domain->api_lock);
3243
3244 return ret;
3245 }
3246
3247 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3248 size_t page_size)
3249 {
3250 struct protection_domain *domain = dom->priv;
3251 size_t unmap_size;
3252
3253 if (domain->mode == PAGE_MODE_NONE)
3254 return -EINVAL;
3255
3256 mutex_lock(&domain->api_lock);
3257 unmap_size = iommu_unmap_page(domain, iova, page_size);
3258 mutex_unlock(&domain->api_lock);
3259
3260 domain_flush_tlb_pde(domain);
3261
3262 return unmap_size;
3263 }
3264
3265 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3266 unsigned long iova)
3267 {
3268 struct protection_domain *domain = dom->priv;
3269 unsigned long offset_mask;
3270 phys_addr_t paddr;
3271 u64 *pte, __pte;
3272
3273 if (domain->mode == PAGE_MODE_NONE)
3274 return iova;
3275
3276 pte = fetch_pte(domain, iova);
3277
3278 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3279 return 0;
3280
3281 if (PM_PTE_LEVEL(*pte) == 0)
3282 offset_mask = PAGE_SIZE - 1;
3283 else
3284 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3285
3286 __pte = *pte & PM_ADDR_MASK;
3287 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
3288
3289 return paddr;
3290 }
3291
3292 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3293 unsigned long cap)
3294 {
3295 switch (cap) {
3296 case IOMMU_CAP_CACHE_COHERENCY:
3297 return 1;
3298 }
3299
3300 return 0;
3301 }
3302
3303 static struct iommu_ops amd_iommu_ops = {
3304 .domain_init = amd_iommu_domain_init,
3305 .domain_destroy = amd_iommu_domain_destroy,
3306 .attach_dev = amd_iommu_attach_device,
3307 .detach_dev = amd_iommu_detach_device,
3308 .map = amd_iommu_map,
3309 .unmap = amd_iommu_unmap,
3310 .iova_to_phys = amd_iommu_iova_to_phys,
3311 .domain_has_cap = amd_iommu_domain_has_cap,
3312 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3313 };
3314
3315 /*****************************************************************************
3316 *
3317 * The next functions do a basic initialization of IOMMU for pass through
3318 * mode
3319 *
3320 * In passthrough mode the IOMMU is initialized and enabled but not used for
3321 * DMA-API translation.
3322 *
3323 *****************************************************************************/
3324
3325 int __init amd_iommu_init_passthrough(void)
3326 {
3327 struct iommu_dev_data *dev_data;
3328 struct pci_dev *dev = NULL;
3329 struct amd_iommu *iommu;
3330 u16 devid;
3331 int ret;
3332
3333 ret = alloc_passthrough_domain();
3334 if (ret)
3335 return ret;
3336
3337 for_each_pci_dev(dev) {
3338 if (!check_device(&dev->dev))
3339 continue;
3340
3341 dev_data = get_dev_data(&dev->dev);
3342 dev_data->passthrough = true;
3343
3344 devid = get_device_id(&dev->dev);
3345
3346 iommu = amd_iommu_rlookup_table[devid];
3347 if (!iommu)
3348 continue;
3349
3350 attach_device(&dev->dev, pt_domain);
3351 }
3352
3353 amd_iommu_stats_init();
3354
3355 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3356
3357 return 0;
3358 }
3359
3360 /* IOMMUv2 specific functions */
3361 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3362 {
3363 return atomic_notifier_chain_register(&ppr_notifier, nb);
3364 }
3365 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3366
3367 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3368 {
3369 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3370 }
3371 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3372
3373 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3374 {
3375 struct protection_domain *domain = dom->priv;
3376 unsigned long flags;
3377
3378 spin_lock_irqsave(&domain->lock, flags);
3379
3380 /* Update data structure */
3381 domain->mode = PAGE_MODE_NONE;
3382 domain->updated = true;
3383
3384 /* Make changes visible to IOMMUs */
3385 update_domain(domain);
3386
3387 /* Page-table is not visible to IOMMU anymore, so free it */
3388 free_pagetable(domain);
3389
3390 spin_unlock_irqrestore(&domain->lock, flags);
3391 }
3392 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3393
3394 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3395 {
3396 struct protection_domain *domain = dom->priv;
3397 unsigned long flags;
3398 int levels, ret;
3399
3400 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3401 return -EINVAL;
3402
3403 /* Number of GCR3 table levels required */
3404 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3405 levels += 1;
3406
3407 if (levels > amd_iommu_max_glx_val)
3408 return -EINVAL;
3409
3410 spin_lock_irqsave(&domain->lock, flags);
3411
3412 /*
3413 * Save us all sanity checks whether devices already in the
3414 * domain support IOMMUv2. Just force that the domain has no
3415 * devices attached when it is switched into IOMMUv2 mode.
3416 */
3417 ret = -EBUSY;
3418 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3419 goto out;
3420
3421 ret = -ENOMEM;
3422 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3423 if (domain->gcr3_tbl == NULL)
3424 goto out;
3425
3426 domain->glx = levels;
3427 domain->flags |= PD_IOMMUV2_MASK;
3428 domain->updated = true;
3429
3430 update_domain(domain);
3431
3432 ret = 0;
3433
3434 out:
3435 spin_unlock_irqrestore(&domain->lock, flags);
3436
3437 return ret;
3438 }
3439 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3440
3441 static int __flush_pasid(struct protection_domain *domain, int pasid,
3442 u64 address, bool size)
3443 {
3444 struct iommu_dev_data *dev_data;
3445 struct iommu_cmd cmd;
3446 int i, ret;
3447
3448 if (!(domain->flags & PD_IOMMUV2_MASK))
3449 return -EINVAL;
3450
3451 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3452
3453 /*
3454 * IOMMU TLB needs to be flushed before Device TLB to
3455 * prevent device TLB refill from IOMMU TLB
3456 */
3457 for (i = 0; i < amd_iommus_present; ++i) {
3458 if (domain->dev_iommu[i] == 0)
3459 continue;
3460
3461 ret = iommu_queue_command(amd_iommus[i], &cmd);
3462 if (ret != 0)
3463 goto out;
3464 }
3465
3466 /* Wait until IOMMU TLB flushes are complete */
3467 domain_flush_complete(domain);
3468
3469 /* Now flush device TLBs */
3470 list_for_each_entry(dev_data, &domain->dev_list, list) {
3471 struct amd_iommu *iommu;
3472 int qdep;
3473
3474 BUG_ON(!dev_data->ats.enabled);
3475
3476 qdep = dev_data->ats.qdep;
3477 iommu = amd_iommu_rlookup_table[dev_data->devid];
3478
3479 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3480 qdep, address, size);
3481
3482 ret = iommu_queue_command(iommu, &cmd);
3483 if (ret != 0)
3484 goto out;
3485 }
3486
3487 /* Wait until all device TLBs are flushed */
3488 domain_flush_complete(domain);
3489
3490 ret = 0;
3491
3492 out:
3493
3494 return ret;
3495 }
3496
3497 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3498 u64 address)
3499 {
3500 INC_STATS_COUNTER(invalidate_iotlb);
3501
3502 return __flush_pasid(domain, pasid, address, false);
3503 }
3504
3505 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3506 u64 address)
3507 {
3508 struct protection_domain *domain = dom->priv;
3509 unsigned long flags;
3510 int ret;
3511
3512 spin_lock_irqsave(&domain->lock, flags);
3513 ret = __amd_iommu_flush_page(domain, pasid, address);
3514 spin_unlock_irqrestore(&domain->lock, flags);
3515
3516 return ret;
3517 }
3518 EXPORT_SYMBOL(amd_iommu_flush_page);
3519
3520 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3521 {
3522 INC_STATS_COUNTER(invalidate_iotlb_all);
3523
3524 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3525 true);
3526 }
3527
3528 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3529 {
3530 struct protection_domain *domain = dom->priv;
3531 unsigned long flags;
3532 int ret;
3533
3534 spin_lock_irqsave(&domain->lock, flags);
3535 ret = __amd_iommu_flush_tlb(domain, pasid);
3536 spin_unlock_irqrestore(&domain->lock, flags);
3537
3538 return ret;
3539 }
3540 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3541
3542 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3543 {
3544 int index;
3545 u64 *pte;
3546
3547 while (true) {
3548
3549 index = (pasid >> (9 * level)) & 0x1ff;
3550 pte = &root[index];
3551
3552 if (level == 0)
3553 break;
3554
3555 if (!(*pte & GCR3_VALID)) {
3556 if (!alloc)
3557 return NULL;
3558
3559 root = (void *)get_zeroed_page(GFP_ATOMIC);
3560 if (root == NULL)
3561 return NULL;
3562
3563 *pte = __pa(root) | GCR3_VALID;
3564 }
3565
3566 root = __va(*pte & PAGE_MASK);
3567
3568 level -= 1;
3569 }
3570
3571 return pte;
3572 }
3573
3574 static int __set_gcr3(struct protection_domain *domain, int pasid,
3575 unsigned long cr3)
3576 {
3577 u64 *pte;
3578
3579 if (domain->mode != PAGE_MODE_NONE)
3580 return -EINVAL;
3581
3582 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3583 if (pte == NULL)
3584 return -ENOMEM;
3585
3586 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3587
3588 return __amd_iommu_flush_tlb(domain, pasid);
3589 }
3590
3591 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3592 {
3593 u64 *pte;
3594
3595 if (domain->mode != PAGE_MODE_NONE)
3596 return -EINVAL;
3597
3598 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3599 if (pte == NULL)
3600 return 0;
3601
3602 *pte = 0;
3603
3604 return __amd_iommu_flush_tlb(domain, pasid);
3605 }
3606
3607 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3608 unsigned long cr3)
3609 {
3610 struct protection_domain *domain = dom->priv;
3611 unsigned long flags;
3612 int ret;
3613
3614 spin_lock_irqsave(&domain->lock, flags);
3615 ret = __set_gcr3(domain, pasid, cr3);
3616 spin_unlock_irqrestore(&domain->lock, flags);
3617
3618 return ret;
3619 }
3620 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3621
3622 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3623 {
3624 struct protection_domain *domain = dom->priv;
3625 unsigned long flags;
3626 int ret;
3627
3628 spin_lock_irqsave(&domain->lock, flags);
3629 ret = __clear_gcr3(domain, pasid);
3630 spin_unlock_irqrestore(&domain->lock, flags);
3631
3632 return ret;
3633 }
3634 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3635
3636 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3637 int status, int tag)
3638 {
3639 struct iommu_dev_data *dev_data;
3640 struct amd_iommu *iommu;
3641 struct iommu_cmd cmd;
3642
3643 INC_STATS_COUNTER(complete_ppr);
3644
3645 dev_data = get_dev_data(&pdev->dev);
3646 iommu = amd_iommu_rlookup_table[dev_data->devid];
3647
3648 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3649 tag, dev_data->pri_tlp);
3650
3651 return iommu_queue_command(iommu, &cmd);
3652 }
3653 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3654
3655 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3656 {
3657 struct protection_domain *domain;
3658
3659 domain = get_domain(&pdev->dev);
3660 if (IS_ERR(domain))
3661 return NULL;
3662
3663 /* Only return IOMMUv2 domains */
3664 if (!(domain->flags & PD_IOMMUV2_MASK))
3665 return NULL;
3666
3667 return domain->iommu_domain;
3668 }
3669 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3670
3671 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3672 {
3673 struct iommu_dev_data *dev_data;
3674
3675 if (!amd_iommu_v2_supported())
3676 return;
3677
3678 dev_data = get_dev_data(&pdev->dev);
3679 dev_data->errata |= (1 << erratum);
3680 }
3681 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3682
3683 int amd_iommu_device_info(struct pci_dev *pdev,
3684 struct amd_iommu_device_info *info)
3685 {
3686 int max_pasids;
3687 int pos;
3688
3689 if (pdev == NULL || info == NULL)
3690 return -EINVAL;
3691
3692 if (!amd_iommu_v2_supported())
3693 return -EINVAL;
3694
3695 memset(info, 0, sizeof(*info));
3696
3697 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3698 if (pos)
3699 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3700
3701 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3702 if (pos)
3703 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3704
3705 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3706 if (pos) {
3707 int features;
3708
3709 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3710 max_pasids = min(max_pasids, (1 << 20));
3711
3712 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3713 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3714
3715 features = pci_pasid_features(pdev);
3716 if (features & PCI_PASID_CAP_EXEC)
3717 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3718 if (features & PCI_PASID_CAP_PRIV)
3719 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3720 }
3721
3722 return 0;
3723 }
3724 EXPORT_SYMBOL(amd_iommu_device_info);
Linux kernel - Deliverables
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