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Merge tag 'gpio-v3.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[deliverable/linux.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <asm/irq_remapping.h>
37 #include <asm/io_apic.h>
38 #include <asm/apic.h>
39 #include <asm/hw_irq.h>
40 #include <asm/msidef.h>
41 #include <asm/proto.h>
42 #include <asm/iommu.h>
43 #include <asm/gart.h>
44 #include <asm/dma.h>
45
46 #include "amd_iommu_proto.h"
47 #include "amd_iommu_types.h"
48 #include "irq_remapping.h"
49 #include "pci.h"
50
51 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
52
53 #define LOOP_TIMEOUT 100000
54
55 /*
56 * This bitmap is used to advertise the page sizes our hardware support
57 * to the IOMMU core, which will then use this information to split
58 * physically contiguous memory regions it is mapping into page sizes
59 * that we support.
60 *
61 * 512GB Pages are not supported due to a hardware bug
62 */
63 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
64
65 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
66
67 /* A list of preallocated protection domains */
68 static LIST_HEAD(iommu_pd_list);
69 static DEFINE_SPINLOCK(iommu_pd_list_lock);
70
71 /* List of all available dev_data structures */
72 static LIST_HEAD(dev_data_list);
73 static DEFINE_SPINLOCK(dev_data_list_lock);
74
75 LIST_HEAD(ioapic_map);
76 LIST_HEAD(hpet_map);
77
78 /*
79 * Domain for untranslated devices - only allocated
80 * if iommu=pt passed on kernel cmd line.
81 */
82 static struct protection_domain *pt_domain;
83
84 static struct iommu_ops amd_iommu_ops;
85
86 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
87 int amd_iommu_max_glx_val = -1;
88
89 static struct dma_map_ops amd_iommu_dma_ops;
90
91 /*
92 * general struct to manage commands send to an IOMMU
93 */
94 struct iommu_cmd {
95 u32 data[4];
96 };
97
98 struct kmem_cache *amd_iommu_irq_cache;
99
100 static void update_domain(struct protection_domain *domain);
101 static int __init alloc_passthrough_domain(void);
102
103 /****************************************************************************
104 *
105 * Helper functions
106 *
107 ****************************************************************************/
108
109 static struct iommu_dev_data *alloc_dev_data(u16 devid)
110 {
111 struct iommu_dev_data *dev_data;
112 unsigned long flags;
113
114 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
115 if (!dev_data)
116 return NULL;
117
118 dev_data->devid = devid;
119 atomic_set(&dev_data->bind, 0);
120
121 spin_lock_irqsave(&dev_data_list_lock, flags);
122 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
123 spin_unlock_irqrestore(&dev_data_list_lock, flags);
124
125 return dev_data;
126 }
127
128 static void free_dev_data(struct iommu_dev_data *dev_data)
129 {
130 unsigned long flags;
131
132 spin_lock_irqsave(&dev_data_list_lock, flags);
133 list_del(&dev_data->dev_data_list);
134 spin_unlock_irqrestore(&dev_data_list_lock, flags);
135
136 if (dev_data->group)
137 iommu_group_put(dev_data->group);
138
139 kfree(dev_data);
140 }
141
142 static struct iommu_dev_data *search_dev_data(u16 devid)
143 {
144 struct iommu_dev_data *dev_data;
145 unsigned long flags;
146
147 spin_lock_irqsave(&dev_data_list_lock, flags);
148 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
149 if (dev_data->devid == devid)
150 goto out_unlock;
151 }
152
153 dev_data = NULL;
154
155 out_unlock:
156 spin_unlock_irqrestore(&dev_data_list_lock, flags);
157
158 return dev_data;
159 }
160
161 static struct iommu_dev_data *find_dev_data(u16 devid)
162 {
163 struct iommu_dev_data *dev_data;
164
165 dev_data = search_dev_data(devid);
166
167 if (dev_data == NULL)
168 dev_data = alloc_dev_data(devid);
169
170 return dev_data;
171 }
172
173 static inline u16 get_device_id(struct device *dev)
174 {
175 struct pci_dev *pdev = to_pci_dev(dev);
176
177 return PCI_DEVID(pdev->bus->number, pdev->devfn);
178 }
179
180 static struct iommu_dev_data *get_dev_data(struct device *dev)
181 {
182 return dev->archdata.iommu;
183 }
184
185 static bool pci_iommuv2_capable(struct pci_dev *pdev)
186 {
187 static const int caps[] = {
188 PCI_EXT_CAP_ID_ATS,
189 PCI_EXT_CAP_ID_PRI,
190 PCI_EXT_CAP_ID_PASID,
191 };
192 int i, pos;
193
194 for (i = 0; i < 3; ++i) {
195 pos = pci_find_ext_capability(pdev, caps[i]);
196 if (pos == 0)
197 return false;
198 }
199
200 return true;
201 }
202
203 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
204 {
205 struct iommu_dev_data *dev_data;
206
207 dev_data = get_dev_data(&pdev->dev);
208
209 return dev_data->errata & (1 << erratum) ? true : false;
210 }
211
212 /*
213 * In this function the list of preallocated protection domains is traversed to
214 * find the domain for a specific device
215 */
216 static struct dma_ops_domain *find_protection_domain(u16 devid)
217 {
218 struct dma_ops_domain *entry, *ret = NULL;
219 unsigned long flags;
220 u16 alias = amd_iommu_alias_table[devid];
221
222 if (list_empty(&iommu_pd_list))
223 return NULL;
224
225 spin_lock_irqsave(&iommu_pd_list_lock, flags);
226
227 list_for_each_entry(entry, &iommu_pd_list, list) {
228 if (entry->target_dev == devid ||
229 entry->target_dev == alias) {
230 ret = entry;
231 break;
232 }
233 }
234
235 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
236
237 return ret;
238 }
239
240 /*
241 * This function checks if the driver got a valid device from the caller to
242 * avoid dereferencing invalid pointers.
243 */
244 static bool check_device(struct device *dev)
245 {
246 u16 devid;
247
248 if (!dev || !dev->dma_mask)
249 return false;
250
251 /* No device or no PCI device */
252 if (dev->bus != &pci_bus_type)
253 return false;
254
255 devid = get_device_id(dev);
256
257 /* Out of our scope? */
258 if (devid > amd_iommu_last_bdf)
259 return false;
260
261 if (amd_iommu_rlookup_table[devid] == NULL)
262 return false;
263
264 return true;
265 }
266
267 static struct pci_bus *find_hosted_bus(struct pci_bus *bus)
268 {
269 while (!bus->self) {
270 if (!pci_is_root_bus(bus))
271 bus = bus->parent;
272 else
273 return ERR_PTR(-ENODEV);
274 }
275
276 return bus;
277 }
278
279 #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
280
281 static struct pci_dev *get_isolation_root(struct pci_dev *pdev)
282 {
283 struct pci_dev *dma_pdev = pdev;
284
285 /* Account for quirked devices */
286 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
287
288 /*
289 * If it's a multifunction device that does not support our
290 * required ACS flags, add to the same group as lowest numbered
291 * function that also does not suport the required ACS flags.
292 */
293 if (dma_pdev->multifunction &&
294 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) {
295 u8 i, slot = PCI_SLOT(dma_pdev->devfn);
296
297 for (i = 0; i < 8; i++) {
298 struct pci_dev *tmp;
299
300 tmp = pci_get_slot(dma_pdev->bus, PCI_DEVFN(slot, i));
301 if (!tmp)
302 continue;
303
304 if (!pci_acs_enabled(tmp, REQ_ACS_FLAGS)) {
305 swap_pci_ref(&dma_pdev, tmp);
306 break;
307 }
308 pci_dev_put(tmp);
309 }
310 }
311
312 /*
313 * Devices on the root bus go through the iommu. If that's not us,
314 * find the next upstream device and test ACS up to the root bus.
315 * Finding the next device may require skipping virtual buses.
316 */
317 while (!pci_is_root_bus(dma_pdev->bus)) {
318 struct pci_bus *bus = find_hosted_bus(dma_pdev->bus);
319 if (IS_ERR(bus))
320 break;
321
322 if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
323 break;
324
325 swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
326 }
327
328 return dma_pdev;
329 }
330
331 static int use_pdev_iommu_group(struct pci_dev *pdev, struct device *dev)
332 {
333 struct iommu_group *group = iommu_group_get(&pdev->dev);
334 int ret;
335
336 if (!group) {
337 group = iommu_group_alloc();
338 if (IS_ERR(group))
339 return PTR_ERR(group);
340
341 WARN_ON(&pdev->dev != dev);
342 }
343
344 ret = iommu_group_add_device(group, dev);
345 iommu_group_put(group);
346 return ret;
347 }
348
349 static int use_dev_data_iommu_group(struct iommu_dev_data *dev_data,
350 struct device *dev)
351 {
352 if (!dev_data->group) {
353 struct iommu_group *group = iommu_group_alloc();
354 if (IS_ERR(group))
355 return PTR_ERR(group);
356
357 dev_data->group = group;
358 }
359
360 return iommu_group_add_device(dev_data->group, dev);
361 }
362
363 static int init_iommu_group(struct device *dev)
364 {
365 struct iommu_dev_data *dev_data;
366 struct iommu_group *group;
367 struct pci_dev *dma_pdev;
368 int ret;
369
370 group = iommu_group_get(dev);
371 if (group) {
372 iommu_group_put(group);
373 return 0;
374 }
375
376 dev_data = find_dev_data(get_device_id(dev));
377 if (!dev_data)
378 return -ENOMEM;
379
380 if (dev_data->alias_data) {
381 u16 alias;
382 struct pci_bus *bus;
383
384 if (dev_data->alias_data->group)
385 goto use_group;
386
387 /*
388 * If the alias device exists, it's effectively just a first
389 * level quirk for finding the DMA source.
390 */
391 alias = amd_iommu_alias_table[dev_data->devid];
392 dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff);
393 if (dma_pdev) {
394 dma_pdev = get_isolation_root(dma_pdev);
395 goto use_pdev;
396 }
397
398 /*
399 * If the alias is virtual, try to find a parent device
400 * and test whether the IOMMU group is actualy rooted above
401 * the alias. Be careful to also test the parent device if
402 * we think the alias is the root of the group.
403 */
404 bus = pci_find_bus(0, alias >> 8);
405 if (!bus)
406 goto use_group;
407
408 bus = find_hosted_bus(bus);
409 if (IS_ERR(bus) || !bus->self)
410 goto use_group;
411
412 dma_pdev = get_isolation_root(pci_dev_get(bus->self));
413 if (dma_pdev != bus->self || (dma_pdev->multifunction &&
414 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)))
415 goto use_pdev;
416
417 pci_dev_put(dma_pdev);
418 goto use_group;
419 }
420
421 dma_pdev = get_isolation_root(pci_dev_get(to_pci_dev(dev)));
422 use_pdev:
423 ret = use_pdev_iommu_group(dma_pdev, dev);
424 pci_dev_put(dma_pdev);
425 return ret;
426 use_group:
427 return use_dev_data_iommu_group(dev_data->alias_data, dev);
428 }
429
430 static int iommu_init_device(struct device *dev)
431 {
432 struct pci_dev *pdev = to_pci_dev(dev);
433 struct iommu_dev_data *dev_data;
434 u16 alias;
435 int ret;
436
437 if (dev->archdata.iommu)
438 return 0;
439
440 dev_data = find_dev_data(get_device_id(dev));
441 if (!dev_data)
442 return -ENOMEM;
443
444 alias = amd_iommu_alias_table[dev_data->devid];
445 if (alias != dev_data->devid) {
446 struct iommu_dev_data *alias_data;
447
448 alias_data = find_dev_data(alias);
449 if (alias_data == NULL) {
450 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
451 dev_name(dev));
452 free_dev_data(dev_data);
453 return -ENOTSUPP;
454 }
455 dev_data->alias_data = alias_data;
456 }
457
458 ret = init_iommu_group(dev);
459 if (ret)
460 return ret;
461
462 if (pci_iommuv2_capable(pdev)) {
463 struct amd_iommu *iommu;
464
465 iommu = amd_iommu_rlookup_table[dev_data->devid];
466 dev_data->iommu_v2 = iommu->is_iommu_v2;
467 }
468
469 dev->archdata.iommu = dev_data;
470
471 return 0;
472 }
473
474 static void iommu_ignore_device(struct device *dev)
475 {
476 u16 devid, alias;
477
478 devid = get_device_id(dev);
479 alias = amd_iommu_alias_table[devid];
480
481 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
482 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
483
484 amd_iommu_rlookup_table[devid] = NULL;
485 amd_iommu_rlookup_table[alias] = NULL;
486 }
487
488 static void iommu_uninit_device(struct device *dev)
489 {
490 iommu_group_remove_device(dev);
491
492 /*
493 * Nothing to do here - we keep dev_data around for unplugged devices
494 * and reuse it when the device is re-plugged - not doing so would
495 * introduce a ton of races.
496 */
497 }
498
499 void __init amd_iommu_uninit_devices(void)
500 {
501 struct iommu_dev_data *dev_data, *n;
502 struct pci_dev *pdev = NULL;
503
504 for_each_pci_dev(pdev) {
505
506 if (!check_device(&pdev->dev))
507 continue;
508
509 iommu_uninit_device(&pdev->dev);
510 }
511
512 /* Free all of our dev_data structures */
513 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
514 free_dev_data(dev_data);
515 }
516
517 int __init amd_iommu_init_devices(void)
518 {
519 struct pci_dev *pdev = NULL;
520 int ret = 0;
521
522 for_each_pci_dev(pdev) {
523
524 if (!check_device(&pdev->dev))
525 continue;
526
527 ret = iommu_init_device(&pdev->dev);
528 if (ret == -ENOTSUPP)
529 iommu_ignore_device(&pdev->dev);
530 else if (ret)
531 goto out_free;
532 }
533
534 return 0;
535
536 out_free:
537
538 amd_iommu_uninit_devices();
539
540 return ret;
541 }
542 #ifdef CONFIG_AMD_IOMMU_STATS
543
544 /*
545 * Initialization code for statistics collection
546 */
547
548 DECLARE_STATS_COUNTER(compl_wait);
549 DECLARE_STATS_COUNTER(cnt_map_single);
550 DECLARE_STATS_COUNTER(cnt_unmap_single);
551 DECLARE_STATS_COUNTER(cnt_map_sg);
552 DECLARE_STATS_COUNTER(cnt_unmap_sg);
553 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
554 DECLARE_STATS_COUNTER(cnt_free_coherent);
555 DECLARE_STATS_COUNTER(cross_page);
556 DECLARE_STATS_COUNTER(domain_flush_single);
557 DECLARE_STATS_COUNTER(domain_flush_all);
558 DECLARE_STATS_COUNTER(alloced_io_mem);
559 DECLARE_STATS_COUNTER(total_map_requests);
560 DECLARE_STATS_COUNTER(complete_ppr);
561 DECLARE_STATS_COUNTER(invalidate_iotlb);
562 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
563 DECLARE_STATS_COUNTER(pri_requests);
564
565 static struct dentry *stats_dir;
566 static struct dentry *de_fflush;
567
568 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
569 {
570 if (stats_dir == NULL)
571 return;
572
573 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
574 &cnt->value);
575 }
576
577 static void amd_iommu_stats_init(void)
578 {
579 stats_dir = debugfs_create_dir("amd-iommu", NULL);
580 if (stats_dir == NULL)
581 return;
582
583 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
584 &amd_iommu_unmap_flush);
585
586 amd_iommu_stats_add(&compl_wait);
587 amd_iommu_stats_add(&cnt_map_single);
588 amd_iommu_stats_add(&cnt_unmap_single);
589 amd_iommu_stats_add(&cnt_map_sg);
590 amd_iommu_stats_add(&cnt_unmap_sg);
591 amd_iommu_stats_add(&cnt_alloc_coherent);
592 amd_iommu_stats_add(&cnt_free_coherent);
593 amd_iommu_stats_add(&cross_page);
594 amd_iommu_stats_add(&domain_flush_single);
595 amd_iommu_stats_add(&domain_flush_all);
596 amd_iommu_stats_add(&alloced_io_mem);
597 amd_iommu_stats_add(&total_map_requests);
598 amd_iommu_stats_add(&complete_ppr);
599 amd_iommu_stats_add(&invalidate_iotlb);
600 amd_iommu_stats_add(&invalidate_iotlb_all);
601 amd_iommu_stats_add(&pri_requests);
602 }
603
604 #endif
605
606 /****************************************************************************
607 *
608 * Interrupt handling functions
609 *
610 ****************************************************************************/
611
612 static void dump_dte_entry(u16 devid)
613 {
614 int i;
615
616 for (i = 0; i < 4; ++i)
617 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
618 amd_iommu_dev_table[devid].data[i]);
619 }
620
621 static void dump_command(unsigned long phys_addr)
622 {
623 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
624 int i;
625
626 for (i = 0; i < 4; ++i)
627 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
628 }
629
630 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
631 {
632 int type, devid, domid, flags;
633 volatile u32 *event = __evt;
634 int count = 0;
635 u64 address;
636
637 retry:
638 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
639 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
640 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
641 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
642 address = (u64)(((u64)event[3]) << 32) | event[2];
643
644 if (type == 0) {
645 /* Did we hit the erratum? */
646 if (++count == LOOP_TIMEOUT) {
647 pr_err("AMD-Vi: No event written to event log\n");
648 return;
649 }
650 udelay(1);
651 goto retry;
652 }
653
654 printk(KERN_ERR "AMD-Vi: Event logged [");
655
656 switch (type) {
657 case EVENT_TYPE_ILL_DEV:
658 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
659 "address=0x%016llx flags=0x%04x]\n",
660 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
661 address, flags);
662 dump_dte_entry(devid);
663 break;
664 case EVENT_TYPE_IO_FAULT:
665 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
666 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
667 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
668 domid, address, flags);
669 break;
670 case EVENT_TYPE_DEV_TAB_ERR:
671 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
672 "address=0x%016llx flags=0x%04x]\n",
673 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
674 address, flags);
675 break;
676 case EVENT_TYPE_PAGE_TAB_ERR:
677 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
678 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
679 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
680 domid, address, flags);
681 break;
682 case EVENT_TYPE_ILL_CMD:
683 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
684 dump_command(address);
685 break;
686 case EVENT_TYPE_CMD_HARD_ERR:
687 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
688 "flags=0x%04x]\n", address, flags);
689 break;
690 case EVENT_TYPE_IOTLB_INV_TO:
691 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
692 "address=0x%016llx]\n",
693 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
694 address);
695 break;
696 case EVENT_TYPE_INV_DEV_REQ:
697 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
698 "address=0x%016llx flags=0x%04x]\n",
699 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
700 address, flags);
701 break;
702 default:
703 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
704 }
705
706 memset(__evt, 0, 4 * sizeof(u32));
707 }
708
709 static void iommu_poll_events(struct amd_iommu *iommu)
710 {
711 u32 head, tail;
712
713 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
714 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
715
716 while (head != tail) {
717 iommu_print_event(iommu, iommu->evt_buf + head);
718 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
719 }
720
721 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
722 }
723
724 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
725 {
726 struct amd_iommu_fault fault;
727
728 INC_STATS_COUNTER(pri_requests);
729
730 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
731 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
732 return;
733 }
734
735 fault.address = raw[1];
736 fault.pasid = PPR_PASID(raw[0]);
737 fault.device_id = PPR_DEVID(raw[0]);
738 fault.tag = PPR_TAG(raw[0]);
739 fault.flags = PPR_FLAGS(raw[0]);
740
741 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
742 }
743
744 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
745 {
746 u32 head, tail;
747
748 if (iommu->ppr_log == NULL)
749 return;
750
751 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
752 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
753
754 while (head != tail) {
755 volatile u64 *raw;
756 u64 entry[2];
757 int i;
758
759 raw = (u64 *)(iommu->ppr_log + head);
760
761 /*
762 * Hardware bug: Interrupt may arrive before the entry is
763 * written to memory. If this happens we need to wait for the
764 * entry to arrive.
765 */
766 for (i = 0; i < LOOP_TIMEOUT; ++i) {
767 if (PPR_REQ_TYPE(raw[0]) != 0)
768 break;
769 udelay(1);
770 }
771
772 /* Avoid memcpy function-call overhead */
773 entry[0] = raw[0];
774 entry[1] = raw[1];
775
776 /*
777 * To detect the hardware bug we need to clear the entry
778 * back to zero.
779 */
780 raw[0] = raw[1] = 0UL;
781
782 /* Update head pointer of hardware ring-buffer */
783 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
784 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
785
786 /* Handle PPR entry */
787 iommu_handle_ppr_entry(iommu, entry);
788
789 /* Refresh ring-buffer information */
790 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
791 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
792 }
793 }
794
795 irqreturn_t amd_iommu_int_thread(int irq, void *data)
796 {
797 struct amd_iommu *iommu = (struct amd_iommu *) data;
798 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
799
800 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
801 /* Enable EVT and PPR interrupts again */
802 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
803 iommu->mmio_base + MMIO_STATUS_OFFSET);
804
805 if (status & MMIO_STATUS_EVT_INT_MASK) {
806 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
807 iommu_poll_events(iommu);
808 }
809
810 if (status & MMIO_STATUS_PPR_INT_MASK) {
811 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
812 iommu_poll_ppr_log(iommu);
813 }
814
815 /*
816 * Hardware bug: ERBT1312
817 * When re-enabling interrupt (by writing 1
818 * to clear the bit), the hardware might also try to set
819 * the interrupt bit in the event status register.
820 * In this scenario, the bit will be set, and disable
821 * subsequent interrupts.
822 *
823 * Workaround: The IOMMU driver should read back the
824 * status register and check if the interrupt bits are cleared.
825 * If not, driver will need to go through the interrupt handler
826 * again and re-clear the bits
827 */
828 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
829 }
830 return IRQ_HANDLED;
831 }
832
833 irqreturn_t amd_iommu_int_handler(int irq, void *data)
834 {
835 return IRQ_WAKE_THREAD;
836 }
837
838 /****************************************************************************
839 *
840 * IOMMU command queuing functions
841 *
842 ****************************************************************************/
843
844 static int wait_on_sem(volatile u64 *sem)
845 {
846 int i = 0;
847
848 while (*sem == 0 && i < LOOP_TIMEOUT) {
849 udelay(1);
850 i += 1;
851 }
852
853 if (i == LOOP_TIMEOUT) {
854 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
855 return -EIO;
856 }
857
858 return 0;
859 }
860
861 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
862 struct iommu_cmd *cmd,
863 u32 tail)
864 {
865 u8 *target;
866
867 target = iommu->cmd_buf + tail;
868 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
869
870 /* Copy command to buffer */
871 memcpy(target, cmd, sizeof(*cmd));
872
873 /* Tell the IOMMU about it */
874 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
875 }
876
877 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
878 {
879 WARN_ON(address & 0x7ULL);
880
881 memset(cmd, 0, sizeof(*cmd));
882 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
883 cmd->data[1] = upper_32_bits(__pa(address));
884 cmd->data[2] = 1;
885 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
886 }
887
888 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
889 {
890 memset(cmd, 0, sizeof(*cmd));
891 cmd->data[0] = devid;
892 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
893 }
894
895 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
896 size_t size, u16 domid, int pde)
897 {
898 u64 pages;
899 int s;
900
901 pages = iommu_num_pages(address, size, PAGE_SIZE);
902 s = 0;
903
904 if (pages > 1) {
905 /*
906 * If we have to flush more than one page, flush all
907 * TLB entries for this domain
908 */
909 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
910 s = 1;
911 }
912
913 address &= PAGE_MASK;
914
915 memset(cmd, 0, sizeof(*cmd));
916 cmd->data[1] |= domid;
917 cmd->data[2] = lower_32_bits(address);
918 cmd->data[3] = upper_32_bits(address);
919 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
920 if (s) /* size bit - we flush more than one 4kb page */
921 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
922 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
923 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
924 }
925
926 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
927 u64 address, size_t size)
928 {
929 u64 pages;
930 int s;
931
932 pages = iommu_num_pages(address, size, PAGE_SIZE);
933 s = 0;
934
935 if (pages > 1) {
936 /*
937 * If we have to flush more than one page, flush all
938 * TLB entries for this domain
939 */
940 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
941 s = 1;
942 }
943
944 address &= PAGE_MASK;
945
946 memset(cmd, 0, sizeof(*cmd));
947 cmd->data[0] = devid;
948 cmd->data[0] |= (qdep & 0xff) << 24;
949 cmd->data[1] = devid;
950 cmd->data[2] = lower_32_bits(address);
951 cmd->data[3] = upper_32_bits(address);
952 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
953 if (s)
954 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
955 }
956
957 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
958 u64 address, bool size)
959 {
960 memset(cmd, 0, sizeof(*cmd));
961
962 address &= ~(0xfffULL);
963
964 cmd->data[0] = pasid & PASID_MASK;
965 cmd->data[1] = domid;
966 cmd->data[2] = lower_32_bits(address);
967 cmd->data[3] = upper_32_bits(address);
968 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
969 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
970 if (size)
971 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
972 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
973 }
974
975 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
976 int qdep, u64 address, bool size)
977 {
978 memset(cmd, 0, sizeof(*cmd));
979
980 address &= ~(0xfffULL);
981
982 cmd->data[0] = devid;
983 cmd->data[0] |= (pasid & 0xff) << 16;
984 cmd->data[0] |= (qdep & 0xff) << 24;
985 cmd->data[1] = devid;
986 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
987 cmd->data[2] = lower_32_bits(address);
988 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
989 cmd->data[3] = upper_32_bits(address);
990 if (size)
991 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
992 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
993 }
994
995 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
996 int status, int tag, bool gn)
997 {
998 memset(cmd, 0, sizeof(*cmd));
999
1000 cmd->data[0] = devid;
1001 if (gn) {
1002 cmd->data[1] = pasid & PASID_MASK;
1003 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1004 }
1005 cmd->data[3] = tag & 0x1ff;
1006 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1007
1008 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1009 }
1010
1011 static void build_inv_all(struct iommu_cmd *cmd)
1012 {
1013 memset(cmd, 0, sizeof(*cmd));
1014 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1015 }
1016
1017 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1018 {
1019 memset(cmd, 0, sizeof(*cmd));
1020 cmd->data[0] = devid;
1021 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1022 }
1023
1024 /*
1025 * Writes the command to the IOMMUs command buffer and informs the
1026 * hardware about the new command.
1027 */
1028 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1029 struct iommu_cmd *cmd,
1030 bool sync)
1031 {
1032 u32 left, tail, head, next_tail;
1033 unsigned long flags;
1034
1035 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
1036
1037 again:
1038 spin_lock_irqsave(&iommu->lock, flags);
1039
1040 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
1041 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
1042 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
1043 left = (head - next_tail) % iommu->cmd_buf_size;
1044
1045 if (left <= 2) {
1046 struct iommu_cmd sync_cmd;
1047 volatile u64 sem = 0;
1048 int ret;
1049
1050 build_completion_wait(&sync_cmd, (u64)&sem);
1051 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
1052
1053 spin_unlock_irqrestore(&iommu->lock, flags);
1054
1055 if ((ret = wait_on_sem(&sem)) != 0)
1056 return ret;
1057
1058 goto again;
1059 }
1060
1061 copy_cmd_to_buffer(iommu, cmd, tail);
1062
1063 /* We need to sync now to make sure all commands are processed */
1064 iommu->need_sync = sync;
1065
1066 spin_unlock_irqrestore(&iommu->lock, flags);
1067
1068 return 0;
1069 }
1070
1071 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1072 {
1073 return iommu_queue_command_sync(iommu, cmd, true);
1074 }
1075
1076 /*
1077 * This function queues a completion wait command into the command
1078 * buffer of an IOMMU
1079 */
1080 static int iommu_completion_wait(struct amd_iommu *iommu)
1081 {
1082 struct iommu_cmd cmd;
1083 volatile u64 sem = 0;
1084 int ret;
1085
1086 if (!iommu->need_sync)
1087 return 0;
1088
1089 build_completion_wait(&cmd, (u64)&sem);
1090
1091 ret = iommu_queue_command_sync(iommu, &cmd, false);
1092 if (ret)
1093 return ret;
1094
1095 return wait_on_sem(&sem);
1096 }
1097
1098 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1099 {
1100 struct iommu_cmd cmd;
1101
1102 build_inv_dte(&cmd, devid);
1103
1104 return iommu_queue_command(iommu, &cmd);
1105 }
1106
1107 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1108 {
1109 u32 devid;
1110
1111 for (devid = 0; devid <= 0xffff; ++devid)
1112 iommu_flush_dte(iommu, devid);
1113
1114 iommu_completion_wait(iommu);
1115 }
1116
1117 /*
1118 * This function uses heavy locking and may disable irqs for some time. But
1119 * this is no issue because it is only called during resume.
1120 */
1121 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1122 {
1123 u32 dom_id;
1124
1125 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1126 struct iommu_cmd cmd;
1127 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1128 dom_id, 1);
1129 iommu_queue_command(iommu, &cmd);
1130 }
1131
1132 iommu_completion_wait(iommu);
1133 }
1134
1135 static void iommu_flush_all(struct amd_iommu *iommu)
1136 {
1137 struct iommu_cmd cmd;
1138
1139 build_inv_all(&cmd);
1140
1141 iommu_queue_command(iommu, &cmd);
1142 iommu_completion_wait(iommu);
1143 }
1144
1145 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1146 {
1147 struct iommu_cmd cmd;
1148
1149 build_inv_irt(&cmd, devid);
1150
1151 iommu_queue_command(iommu, &cmd);
1152 }
1153
1154 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1155 {
1156 u32 devid;
1157
1158 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1159 iommu_flush_irt(iommu, devid);
1160
1161 iommu_completion_wait(iommu);
1162 }
1163
1164 void iommu_flush_all_caches(struct amd_iommu *iommu)
1165 {
1166 if (iommu_feature(iommu, FEATURE_IA)) {
1167 iommu_flush_all(iommu);
1168 } else {
1169 iommu_flush_dte_all(iommu);
1170 iommu_flush_irt_all(iommu);
1171 iommu_flush_tlb_all(iommu);
1172 }
1173 }
1174
1175 /*
1176 * Command send function for flushing on-device TLB
1177 */
1178 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1179 u64 address, size_t size)
1180 {
1181 struct amd_iommu *iommu;
1182 struct iommu_cmd cmd;
1183 int qdep;
1184
1185 qdep = dev_data->ats.qdep;
1186 iommu = amd_iommu_rlookup_table[dev_data->devid];
1187
1188 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1189
1190 return iommu_queue_command(iommu, &cmd);
1191 }
1192
1193 /*
1194 * Command send function for invalidating a device table entry
1195 */
1196 static int device_flush_dte(struct iommu_dev_data *dev_data)
1197 {
1198 struct amd_iommu *iommu;
1199 int ret;
1200
1201 iommu = amd_iommu_rlookup_table[dev_data->devid];
1202
1203 ret = iommu_flush_dte(iommu, dev_data->devid);
1204 if (ret)
1205 return ret;
1206
1207 if (dev_data->ats.enabled)
1208 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1209
1210 return ret;
1211 }
1212
1213 /*
1214 * TLB invalidation function which is called from the mapping functions.
1215 * It invalidates a single PTE if the range to flush is within a single
1216 * page. Otherwise it flushes the whole TLB of the IOMMU.
1217 */
1218 static void __domain_flush_pages(struct protection_domain *domain,
1219 u64 address, size_t size, int pde)
1220 {
1221 struct iommu_dev_data *dev_data;
1222 struct iommu_cmd cmd;
1223 int ret = 0, i;
1224
1225 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1226
1227 for (i = 0; i < amd_iommus_present; ++i) {
1228 if (!domain->dev_iommu[i])
1229 continue;
1230
1231 /*
1232 * Devices of this domain are behind this IOMMU
1233 * We need a TLB flush
1234 */
1235 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1236 }
1237
1238 list_for_each_entry(dev_data, &domain->dev_list, list) {
1239
1240 if (!dev_data->ats.enabled)
1241 continue;
1242
1243 ret |= device_flush_iotlb(dev_data, address, size);
1244 }
1245
1246 WARN_ON(ret);
1247 }
1248
1249 static void domain_flush_pages(struct protection_domain *domain,
1250 u64 address, size_t size)
1251 {
1252 __domain_flush_pages(domain, address, size, 0);
1253 }
1254
1255 /* Flush the whole IO/TLB for a given protection domain */
1256 static void domain_flush_tlb(struct protection_domain *domain)
1257 {
1258 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1259 }
1260
1261 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1262 static void domain_flush_tlb_pde(struct protection_domain *domain)
1263 {
1264 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1265 }
1266
1267 static void domain_flush_complete(struct protection_domain *domain)
1268 {
1269 int i;
1270
1271 for (i = 0; i < amd_iommus_present; ++i) {
1272 if (!domain->dev_iommu[i])
1273 continue;
1274
1275 /*
1276 * Devices of this domain are behind this IOMMU
1277 * We need to wait for completion of all commands.
1278 */
1279 iommu_completion_wait(amd_iommus[i]);
1280 }
1281 }
1282
1283
1284 /*
1285 * This function flushes the DTEs for all devices in domain
1286 */
1287 static void domain_flush_devices(struct protection_domain *domain)
1288 {
1289 struct iommu_dev_data *dev_data;
1290
1291 list_for_each_entry(dev_data, &domain->dev_list, list)
1292 device_flush_dte(dev_data);
1293 }
1294
1295 /****************************************************************************
1296 *
1297 * The functions below are used the create the page table mappings for
1298 * unity mapped regions.
1299 *
1300 ****************************************************************************/
1301
1302 /*
1303 * This function is used to add another level to an IO page table. Adding
1304 * another level increases the size of the address space by 9 bits to a size up
1305 * to 64 bits.
1306 */
1307 static bool increase_address_space(struct protection_domain *domain,
1308 gfp_t gfp)
1309 {
1310 u64 *pte;
1311
1312 if (domain->mode == PAGE_MODE_6_LEVEL)
1313 /* address space already 64 bit large */
1314 return false;
1315
1316 pte = (void *)get_zeroed_page(gfp);
1317 if (!pte)
1318 return false;
1319
1320 *pte = PM_LEVEL_PDE(domain->mode,
1321 virt_to_phys(domain->pt_root));
1322 domain->pt_root = pte;
1323 domain->mode += 1;
1324 domain->updated = true;
1325
1326 return true;
1327 }
1328
1329 static u64 *alloc_pte(struct protection_domain *domain,
1330 unsigned long address,
1331 unsigned long page_size,
1332 u64 **pte_page,
1333 gfp_t gfp)
1334 {
1335 int level, end_lvl;
1336 u64 *pte, *page;
1337
1338 BUG_ON(!is_power_of_2(page_size));
1339
1340 while (address > PM_LEVEL_SIZE(domain->mode))
1341 increase_address_space(domain, gfp);
1342
1343 level = domain->mode - 1;
1344 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1345 address = PAGE_SIZE_ALIGN(address, page_size);
1346 end_lvl = PAGE_SIZE_LEVEL(page_size);
1347
1348 while (level > end_lvl) {
1349 if (!IOMMU_PTE_PRESENT(*pte)) {
1350 page = (u64 *)get_zeroed_page(gfp);
1351 if (!page)
1352 return NULL;
1353 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1354 }
1355
1356 /* No level skipping support yet */
1357 if (PM_PTE_LEVEL(*pte) != level)
1358 return NULL;
1359
1360 level -= 1;
1361
1362 pte = IOMMU_PTE_PAGE(*pte);
1363
1364 if (pte_page && level == end_lvl)
1365 *pte_page = pte;
1366
1367 pte = &pte[PM_LEVEL_INDEX(level, address)];
1368 }
1369
1370 return pte;
1371 }
1372
1373 /*
1374 * This function checks if there is a PTE for a given dma address. If
1375 * there is one, it returns the pointer to it.
1376 */
1377 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
1378 {
1379 int level;
1380 u64 *pte;
1381
1382 if (address > PM_LEVEL_SIZE(domain->mode))
1383 return NULL;
1384
1385 level = domain->mode - 1;
1386 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1387
1388 while (level > 0) {
1389
1390 /* Not Present */
1391 if (!IOMMU_PTE_PRESENT(*pte))
1392 return NULL;
1393
1394 /* Large PTE */
1395 if (PM_PTE_LEVEL(*pte) == 0x07) {
1396 unsigned long pte_mask, __pte;
1397
1398 /*
1399 * If we have a series of large PTEs, make
1400 * sure to return a pointer to the first one.
1401 */
1402 pte_mask = PTE_PAGE_SIZE(*pte);
1403 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1404 __pte = ((unsigned long)pte) & pte_mask;
1405
1406 return (u64 *)__pte;
1407 }
1408
1409 /* No level skipping support yet */
1410 if (PM_PTE_LEVEL(*pte) != level)
1411 return NULL;
1412
1413 level -= 1;
1414
1415 /* Walk to the next level */
1416 pte = IOMMU_PTE_PAGE(*pte);
1417 pte = &pte[PM_LEVEL_INDEX(level, address)];
1418 }
1419
1420 return pte;
1421 }
1422
1423 /*
1424 * Generic mapping functions. It maps a physical address into a DMA
1425 * address space. It allocates the page table pages if necessary.
1426 * In the future it can be extended to a generic mapping function
1427 * supporting all features of AMD IOMMU page tables like level skipping
1428 * and full 64 bit address spaces.
1429 */
1430 static int iommu_map_page(struct protection_domain *dom,
1431 unsigned long bus_addr,
1432 unsigned long phys_addr,
1433 int prot,
1434 unsigned long page_size)
1435 {
1436 u64 __pte, *pte;
1437 int i, count;
1438
1439 if (!(prot & IOMMU_PROT_MASK))
1440 return -EINVAL;
1441
1442 bus_addr = PAGE_ALIGN(bus_addr);
1443 phys_addr = PAGE_ALIGN(phys_addr);
1444 count = PAGE_SIZE_PTE_COUNT(page_size);
1445 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1446
1447 for (i = 0; i < count; ++i)
1448 if (IOMMU_PTE_PRESENT(pte[i]))
1449 return -EBUSY;
1450
1451 if (page_size > PAGE_SIZE) {
1452 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1453 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1454 } else
1455 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1456
1457 if (prot & IOMMU_PROT_IR)
1458 __pte |= IOMMU_PTE_IR;
1459 if (prot & IOMMU_PROT_IW)
1460 __pte |= IOMMU_PTE_IW;
1461
1462 for (i = 0; i < count; ++i)
1463 pte[i] = __pte;
1464
1465 update_domain(dom);
1466
1467 return 0;
1468 }
1469
1470 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1471 unsigned long bus_addr,
1472 unsigned long page_size)
1473 {
1474 unsigned long long unmap_size, unmapped;
1475 u64 *pte;
1476
1477 BUG_ON(!is_power_of_2(page_size));
1478
1479 unmapped = 0;
1480
1481 while (unmapped < page_size) {
1482
1483 pte = fetch_pte(dom, bus_addr);
1484
1485 if (!pte) {
1486 /*
1487 * No PTE for this address
1488 * move forward in 4kb steps
1489 */
1490 unmap_size = PAGE_SIZE;
1491 } else if (PM_PTE_LEVEL(*pte) == 0) {
1492 /* 4kb PTE found for this address */
1493 unmap_size = PAGE_SIZE;
1494 *pte = 0ULL;
1495 } else {
1496 int count, i;
1497
1498 /* Large PTE found which maps this address */
1499 unmap_size = PTE_PAGE_SIZE(*pte);
1500
1501 /* Only unmap from the first pte in the page */
1502 if ((unmap_size - 1) & bus_addr)
1503 break;
1504 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1505 for (i = 0; i < count; i++)
1506 pte[i] = 0ULL;
1507 }
1508
1509 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1510 unmapped += unmap_size;
1511 }
1512
1513 BUG_ON(unmapped && !is_power_of_2(unmapped));
1514
1515 return unmapped;
1516 }
1517
1518 /*
1519 * This function checks if a specific unity mapping entry is needed for
1520 * this specific IOMMU.
1521 */
1522 static int iommu_for_unity_map(struct amd_iommu *iommu,
1523 struct unity_map_entry *entry)
1524 {
1525 u16 bdf, i;
1526
1527 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1528 bdf = amd_iommu_alias_table[i];
1529 if (amd_iommu_rlookup_table[bdf] == iommu)
1530 return 1;
1531 }
1532
1533 return 0;
1534 }
1535
1536 /*
1537 * This function actually applies the mapping to the page table of the
1538 * dma_ops domain.
1539 */
1540 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1541 struct unity_map_entry *e)
1542 {
1543 u64 addr;
1544 int ret;
1545
1546 for (addr = e->address_start; addr < e->address_end;
1547 addr += PAGE_SIZE) {
1548 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1549 PAGE_SIZE);
1550 if (ret)
1551 return ret;
1552 /*
1553 * if unity mapping is in aperture range mark the page
1554 * as allocated in the aperture
1555 */
1556 if (addr < dma_dom->aperture_size)
1557 __set_bit(addr >> PAGE_SHIFT,
1558 dma_dom->aperture[0]->bitmap);
1559 }
1560
1561 return 0;
1562 }
1563
1564 /*
1565 * Init the unity mappings for a specific IOMMU in the system
1566 *
1567 * Basically iterates over all unity mapping entries and applies them to
1568 * the default domain DMA of that IOMMU if necessary.
1569 */
1570 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1571 {
1572 struct unity_map_entry *entry;
1573 int ret;
1574
1575 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1576 if (!iommu_for_unity_map(iommu, entry))
1577 continue;
1578 ret = dma_ops_unity_map(iommu->default_dom, entry);
1579 if (ret)
1580 return ret;
1581 }
1582
1583 return 0;
1584 }
1585
1586 /*
1587 * Inits the unity mappings required for a specific device
1588 */
1589 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1590 u16 devid)
1591 {
1592 struct unity_map_entry *e;
1593 int ret;
1594
1595 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1596 if (!(devid >= e->devid_start && devid <= e->devid_end))
1597 continue;
1598 ret = dma_ops_unity_map(dma_dom, e);
1599 if (ret)
1600 return ret;
1601 }
1602
1603 return 0;
1604 }
1605
1606 /****************************************************************************
1607 *
1608 * The next functions belong to the address allocator for the dma_ops
1609 * interface functions. They work like the allocators in the other IOMMU
1610 * drivers. Its basically a bitmap which marks the allocated pages in
1611 * the aperture. Maybe it could be enhanced in the future to a more
1612 * efficient allocator.
1613 *
1614 ****************************************************************************/
1615
1616 /*
1617 * The address allocator core functions.
1618 *
1619 * called with domain->lock held
1620 */
1621
1622 /*
1623 * Used to reserve address ranges in the aperture (e.g. for exclusion
1624 * ranges.
1625 */
1626 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1627 unsigned long start_page,
1628 unsigned int pages)
1629 {
1630 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1631
1632 if (start_page + pages > last_page)
1633 pages = last_page - start_page;
1634
1635 for (i = start_page; i < start_page + pages; ++i) {
1636 int index = i / APERTURE_RANGE_PAGES;
1637 int page = i % APERTURE_RANGE_PAGES;
1638 __set_bit(page, dom->aperture[index]->bitmap);
1639 }
1640 }
1641
1642 /*
1643 * This function is used to add a new aperture range to an existing
1644 * aperture in case of dma_ops domain allocation or address allocation
1645 * failure.
1646 */
1647 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1648 bool populate, gfp_t gfp)
1649 {
1650 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1651 struct amd_iommu *iommu;
1652 unsigned long i, old_size;
1653
1654 #ifdef CONFIG_IOMMU_STRESS
1655 populate = false;
1656 #endif
1657
1658 if (index >= APERTURE_MAX_RANGES)
1659 return -ENOMEM;
1660
1661 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1662 if (!dma_dom->aperture[index])
1663 return -ENOMEM;
1664
1665 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1666 if (!dma_dom->aperture[index]->bitmap)
1667 goto out_free;
1668
1669 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1670
1671 if (populate) {
1672 unsigned long address = dma_dom->aperture_size;
1673 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1674 u64 *pte, *pte_page;
1675
1676 for (i = 0; i < num_ptes; ++i) {
1677 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1678 &pte_page, gfp);
1679 if (!pte)
1680 goto out_free;
1681
1682 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1683
1684 address += APERTURE_RANGE_SIZE / 64;
1685 }
1686 }
1687
1688 old_size = dma_dom->aperture_size;
1689 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1690
1691 /* Reserve address range used for MSI messages */
1692 if (old_size < MSI_ADDR_BASE_LO &&
1693 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1694 unsigned long spage;
1695 int pages;
1696
1697 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1698 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1699
1700 dma_ops_reserve_addresses(dma_dom, spage, pages);
1701 }
1702
1703 /* Initialize the exclusion range if necessary */
1704 for_each_iommu(iommu) {
1705 if (iommu->exclusion_start &&
1706 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1707 && iommu->exclusion_start < dma_dom->aperture_size) {
1708 unsigned long startpage;
1709 int pages = iommu_num_pages(iommu->exclusion_start,
1710 iommu->exclusion_length,
1711 PAGE_SIZE);
1712 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1713 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1714 }
1715 }
1716
1717 /*
1718 * Check for areas already mapped as present in the new aperture
1719 * range and mark those pages as reserved in the allocator. Such
1720 * mappings may already exist as a result of requested unity
1721 * mappings for devices.
1722 */
1723 for (i = dma_dom->aperture[index]->offset;
1724 i < dma_dom->aperture_size;
1725 i += PAGE_SIZE) {
1726 u64 *pte = fetch_pte(&dma_dom->domain, i);
1727 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1728 continue;
1729
1730 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
1731 }
1732
1733 update_domain(&dma_dom->domain);
1734
1735 return 0;
1736
1737 out_free:
1738 update_domain(&dma_dom->domain);
1739
1740 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1741
1742 kfree(dma_dom->aperture[index]);
1743 dma_dom->aperture[index] = NULL;
1744
1745 return -ENOMEM;
1746 }
1747
1748 static unsigned long dma_ops_area_alloc(struct device *dev,
1749 struct dma_ops_domain *dom,
1750 unsigned int pages,
1751 unsigned long align_mask,
1752 u64 dma_mask,
1753 unsigned long start)
1754 {
1755 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1756 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1757 int i = start >> APERTURE_RANGE_SHIFT;
1758 unsigned long boundary_size;
1759 unsigned long address = -1;
1760 unsigned long limit;
1761
1762 next_bit >>= PAGE_SHIFT;
1763
1764 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1765 PAGE_SIZE) >> PAGE_SHIFT;
1766
1767 for (;i < max_index; ++i) {
1768 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1769
1770 if (dom->aperture[i]->offset >= dma_mask)
1771 break;
1772
1773 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1774 dma_mask >> PAGE_SHIFT);
1775
1776 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1777 limit, next_bit, pages, 0,
1778 boundary_size, align_mask);
1779 if (address != -1) {
1780 address = dom->aperture[i]->offset +
1781 (address << PAGE_SHIFT);
1782 dom->next_address = address + (pages << PAGE_SHIFT);
1783 break;
1784 }
1785
1786 next_bit = 0;
1787 }
1788
1789 return address;
1790 }
1791
1792 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1793 struct dma_ops_domain *dom,
1794 unsigned int pages,
1795 unsigned long align_mask,
1796 u64 dma_mask)
1797 {
1798 unsigned long address;
1799
1800 #ifdef CONFIG_IOMMU_STRESS
1801 dom->next_address = 0;
1802 dom->need_flush = true;
1803 #endif
1804
1805 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1806 dma_mask, dom->next_address);
1807
1808 if (address == -1) {
1809 dom->next_address = 0;
1810 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1811 dma_mask, 0);
1812 dom->need_flush = true;
1813 }
1814
1815 if (unlikely(address == -1))
1816 address = DMA_ERROR_CODE;
1817
1818 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1819
1820 return address;
1821 }
1822
1823 /*
1824 * The address free function.
1825 *
1826 * called with domain->lock held
1827 */
1828 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1829 unsigned long address,
1830 unsigned int pages)
1831 {
1832 unsigned i = address >> APERTURE_RANGE_SHIFT;
1833 struct aperture_range *range = dom->aperture[i];
1834
1835 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1836
1837 #ifdef CONFIG_IOMMU_STRESS
1838 if (i < 4)
1839 return;
1840 #endif
1841
1842 if (address >= dom->next_address)
1843 dom->need_flush = true;
1844
1845 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1846
1847 bitmap_clear(range->bitmap, address, pages);
1848
1849 }
1850
1851 /****************************************************************************
1852 *
1853 * The next functions belong to the domain allocation. A domain is
1854 * allocated for every IOMMU as the default domain. If device isolation
1855 * is enabled, every device get its own domain. The most important thing
1856 * about domains is the page table mapping the DMA address space they
1857 * contain.
1858 *
1859 ****************************************************************************/
1860
1861 /*
1862 * This function adds a protection domain to the global protection domain list
1863 */
1864 static void add_domain_to_list(struct protection_domain *domain)
1865 {
1866 unsigned long flags;
1867
1868 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1869 list_add(&domain->list, &amd_iommu_pd_list);
1870 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1871 }
1872
1873 /*
1874 * This function removes a protection domain to the global
1875 * protection domain list
1876 */
1877 static void del_domain_from_list(struct protection_domain *domain)
1878 {
1879 unsigned long flags;
1880
1881 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1882 list_del(&domain->list);
1883 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1884 }
1885
1886 static u16 domain_id_alloc(void)
1887 {
1888 unsigned long flags;
1889 int id;
1890
1891 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1892 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1893 BUG_ON(id == 0);
1894 if (id > 0 && id < MAX_DOMAIN_ID)
1895 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1896 else
1897 id = 0;
1898 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1899
1900 return id;
1901 }
1902
1903 static void domain_id_free(int id)
1904 {
1905 unsigned long flags;
1906
1907 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1908 if (id > 0 && id < MAX_DOMAIN_ID)
1909 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1910 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1911 }
1912
1913 #define DEFINE_FREE_PT_FN(LVL, FN) \
1914 static void free_pt_##LVL (unsigned long __pt) \
1915 { \
1916 unsigned long p; \
1917 u64 *pt; \
1918 int i; \
1919 \
1920 pt = (u64 *)__pt; \
1921 \
1922 for (i = 0; i < 512; ++i) { \
1923 if (!IOMMU_PTE_PRESENT(pt[i])) \
1924 continue; \
1925 \
1926 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1927 FN(p); \
1928 } \
1929 free_page((unsigned long)pt); \
1930 }
1931
1932 DEFINE_FREE_PT_FN(l2, free_page)
1933 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1934 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1935 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1936 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1937
1938 static void free_pagetable(struct protection_domain *domain)
1939 {
1940 unsigned long root = (unsigned long)domain->pt_root;
1941
1942 switch (domain->mode) {
1943 case PAGE_MODE_NONE:
1944 break;
1945 case PAGE_MODE_1_LEVEL:
1946 free_page(root);
1947 break;
1948 case PAGE_MODE_2_LEVEL:
1949 free_pt_l2(root);
1950 break;
1951 case PAGE_MODE_3_LEVEL:
1952 free_pt_l3(root);
1953 break;
1954 case PAGE_MODE_4_LEVEL:
1955 free_pt_l4(root);
1956 break;
1957 case PAGE_MODE_5_LEVEL:
1958 free_pt_l5(root);
1959 break;
1960 case PAGE_MODE_6_LEVEL:
1961 free_pt_l6(root);
1962 break;
1963 default:
1964 BUG();
1965 }
1966 }
1967
1968 static void free_gcr3_tbl_level1(u64 *tbl)
1969 {
1970 u64 *ptr;
1971 int i;
1972
1973 for (i = 0; i < 512; ++i) {
1974 if (!(tbl[i] & GCR3_VALID))
1975 continue;
1976
1977 ptr = __va(tbl[i] & PAGE_MASK);
1978
1979 free_page((unsigned long)ptr);
1980 }
1981 }
1982
1983 static void free_gcr3_tbl_level2(u64 *tbl)
1984 {
1985 u64 *ptr;
1986 int i;
1987
1988 for (i = 0; i < 512; ++i) {
1989 if (!(tbl[i] & GCR3_VALID))
1990 continue;
1991
1992 ptr = __va(tbl[i] & PAGE_MASK);
1993
1994 free_gcr3_tbl_level1(ptr);
1995 }
1996 }
1997
1998 static void free_gcr3_table(struct protection_domain *domain)
1999 {
2000 if (domain->glx == 2)
2001 free_gcr3_tbl_level2(domain->gcr3_tbl);
2002 else if (domain->glx == 1)
2003 free_gcr3_tbl_level1(domain->gcr3_tbl);
2004 else if (domain->glx != 0)
2005 BUG();
2006
2007 free_page((unsigned long)domain->gcr3_tbl);
2008 }
2009
2010 /*
2011 * Free a domain, only used if something went wrong in the
2012 * allocation path and we need to free an already allocated page table
2013 */
2014 static void dma_ops_domain_free(struct dma_ops_domain *dom)
2015 {
2016 int i;
2017
2018 if (!dom)
2019 return;
2020
2021 del_domain_from_list(&dom->domain);
2022
2023 free_pagetable(&dom->domain);
2024
2025 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
2026 if (!dom->aperture[i])
2027 continue;
2028 free_page((unsigned long)dom->aperture[i]->bitmap);
2029 kfree(dom->aperture[i]);
2030 }
2031
2032 kfree(dom);
2033 }
2034
2035 /*
2036 * Allocates a new protection domain usable for the dma_ops functions.
2037 * It also initializes the page table and the address allocator data
2038 * structures required for the dma_ops interface
2039 */
2040 static struct dma_ops_domain *dma_ops_domain_alloc(void)
2041 {
2042 struct dma_ops_domain *dma_dom;
2043
2044 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
2045 if (!dma_dom)
2046 return NULL;
2047
2048 spin_lock_init(&dma_dom->domain.lock);
2049
2050 dma_dom->domain.id = domain_id_alloc();
2051 if (dma_dom->domain.id == 0)
2052 goto free_dma_dom;
2053 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
2054 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
2055 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2056 dma_dom->domain.flags = PD_DMA_OPS_MASK;
2057 dma_dom->domain.priv = dma_dom;
2058 if (!dma_dom->domain.pt_root)
2059 goto free_dma_dom;
2060
2061 dma_dom->need_flush = false;
2062 dma_dom->target_dev = 0xffff;
2063
2064 add_domain_to_list(&dma_dom->domain);
2065
2066 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
2067 goto free_dma_dom;
2068
2069 /*
2070 * mark the first page as allocated so we never return 0 as
2071 * a valid dma-address. So we can use 0 as error value
2072 */
2073 dma_dom->aperture[0]->bitmap[0] = 1;
2074 dma_dom->next_address = 0;
2075
2076
2077 return dma_dom;
2078
2079 free_dma_dom:
2080 dma_ops_domain_free(dma_dom);
2081
2082 return NULL;
2083 }
2084
2085 /*
2086 * little helper function to check whether a given protection domain is a
2087 * dma_ops domain
2088 */
2089 static bool dma_ops_domain(struct protection_domain *domain)
2090 {
2091 return domain->flags & PD_DMA_OPS_MASK;
2092 }
2093
2094 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
2095 {
2096 u64 pte_root = 0;
2097 u64 flags = 0;
2098
2099 if (domain->mode != PAGE_MODE_NONE)
2100 pte_root = virt_to_phys(domain->pt_root);
2101
2102 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2103 << DEV_ENTRY_MODE_SHIFT;
2104 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
2105
2106 flags = amd_iommu_dev_table[devid].data[1];
2107
2108 if (ats)
2109 flags |= DTE_FLAG_IOTLB;
2110
2111 if (domain->flags & PD_IOMMUV2_MASK) {
2112 u64 gcr3 = __pa(domain->gcr3_tbl);
2113 u64 glx = domain->glx;
2114 u64 tmp;
2115
2116 pte_root |= DTE_FLAG_GV;
2117 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2118
2119 /* First mask out possible old values for GCR3 table */
2120 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2121 flags &= ~tmp;
2122
2123 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2124 flags &= ~tmp;
2125
2126 /* Encode GCR3 table into DTE */
2127 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2128 pte_root |= tmp;
2129
2130 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2131 flags |= tmp;
2132
2133 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2134 flags |= tmp;
2135 }
2136
2137 flags &= ~(0xffffUL);
2138 flags |= domain->id;
2139
2140 amd_iommu_dev_table[devid].data[1] = flags;
2141 amd_iommu_dev_table[devid].data[0] = pte_root;
2142 }
2143
2144 static void clear_dte_entry(u16 devid)
2145 {
2146 /* remove entry from the device table seen by the hardware */
2147 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2148 amd_iommu_dev_table[devid].data[1] = 0;
2149
2150 amd_iommu_apply_erratum_63(devid);
2151 }
2152
2153 static void do_attach(struct iommu_dev_data *dev_data,
2154 struct protection_domain *domain)
2155 {
2156 struct amd_iommu *iommu;
2157 bool ats;
2158
2159 iommu = amd_iommu_rlookup_table[dev_data->devid];
2160 ats = dev_data->ats.enabled;
2161
2162 /* Update data structures */
2163 dev_data->domain = domain;
2164 list_add(&dev_data->list, &domain->dev_list);
2165 set_dte_entry(dev_data->devid, domain, ats);
2166
2167 /* Do reference counting */
2168 domain->dev_iommu[iommu->index] += 1;
2169 domain->dev_cnt += 1;
2170
2171 /* Flush the DTE entry */
2172 device_flush_dte(dev_data);
2173 }
2174
2175 static void do_detach(struct iommu_dev_data *dev_data)
2176 {
2177 struct amd_iommu *iommu;
2178
2179 iommu = amd_iommu_rlookup_table[dev_data->devid];
2180
2181 /* decrease reference counters */
2182 dev_data->domain->dev_iommu[iommu->index] -= 1;
2183 dev_data->domain->dev_cnt -= 1;
2184
2185 /* Update data structures */
2186 dev_data->domain = NULL;
2187 list_del(&dev_data->list);
2188 clear_dte_entry(dev_data->devid);
2189
2190 /* Flush the DTE entry */
2191 device_flush_dte(dev_data);
2192 }
2193
2194 /*
2195 * If a device is not yet associated with a domain, this function does
2196 * assigns it visible for the hardware
2197 */
2198 static int __attach_device(struct iommu_dev_data *dev_data,
2199 struct protection_domain *domain)
2200 {
2201 int ret;
2202
2203 /* lock domain */
2204 spin_lock(&domain->lock);
2205
2206 if (dev_data->alias_data != NULL) {
2207 struct iommu_dev_data *alias_data = dev_data->alias_data;
2208
2209 /* Some sanity checks */
2210 ret = -EBUSY;
2211 if (alias_data->domain != NULL &&
2212 alias_data->domain != domain)
2213 goto out_unlock;
2214
2215 if (dev_data->domain != NULL &&
2216 dev_data->domain != domain)
2217 goto out_unlock;
2218
2219 /* Do real assignment */
2220 if (alias_data->domain == NULL)
2221 do_attach(alias_data, domain);
2222
2223 atomic_inc(&alias_data->bind);
2224 }
2225
2226 if (dev_data->domain == NULL)
2227 do_attach(dev_data, domain);
2228
2229 atomic_inc(&dev_data->bind);
2230
2231 ret = 0;
2232
2233 out_unlock:
2234
2235 /* ready */
2236 spin_unlock(&domain->lock);
2237
2238 return ret;
2239 }
2240
2241
2242 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2243 {
2244 pci_disable_ats(pdev);
2245 pci_disable_pri(pdev);
2246 pci_disable_pasid(pdev);
2247 }
2248
2249 /* FIXME: Change generic reset-function to do the same */
2250 static int pri_reset_while_enabled(struct pci_dev *pdev)
2251 {
2252 u16 control;
2253 int pos;
2254
2255 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2256 if (!pos)
2257 return -EINVAL;
2258
2259 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2260 control |= PCI_PRI_CTRL_RESET;
2261 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2262
2263 return 0;
2264 }
2265
2266 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2267 {
2268 bool reset_enable;
2269 int reqs, ret;
2270
2271 /* FIXME: Hardcode number of outstanding requests for now */
2272 reqs = 32;
2273 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2274 reqs = 1;
2275 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2276
2277 /* Only allow access to user-accessible pages */
2278 ret = pci_enable_pasid(pdev, 0);
2279 if (ret)
2280 goto out_err;
2281
2282 /* First reset the PRI state of the device */
2283 ret = pci_reset_pri(pdev);
2284 if (ret)
2285 goto out_err;
2286
2287 /* Enable PRI */
2288 ret = pci_enable_pri(pdev, reqs);
2289 if (ret)
2290 goto out_err;
2291
2292 if (reset_enable) {
2293 ret = pri_reset_while_enabled(pdev);
2294 if (ret)
2295 goto out_err;
2296 }
2297
2298 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2299 if (ret)
2300 goto out_err;
2301
2302 return 0;
2303
2304 out_err:
2305 pci_disable_pri(pdev);
2306 pci_disable_pasid(pdev);
2307
2308 return ret;
2309 }
2310
2311 /* FIXME: Move this to PCI code */
2312 #define PCI_PRI_TLP_OFF (1 << 15)
2313
2314 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2315 {
2316 u16 status;
2317 int pos;
2318
2319 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2320 if (!pos)
2321 return false;
2322
2323 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2324
2325 return (status & PCI_PRI_TLP_OFF) ? true : false;
2326 }
2327
2328 /*
2329 * If a device is not yet associated with a domain, this function
2330 * assigns it visible for the hardware
2331 */
2332 static int attach_device(struct device *dev,
2333 struct protection_domain *domain)
2334 {
2335 struct pci_dev *pdev = to_pci_dev(dev);
2336 struct iommu_dev_data *dev_data;
2337 unsigned long flags;
2338 int ret;
2339
2340 dev_data = get_dev_data(dev);
2341
2342 if (domain->flags & PD_IOMMUV2_MASK) {
2343 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2344 return -EINVAL;
2345
2346 if (pdev_iommuv2_enable(pdev) != 0)
2347 return -EINVAL;
2348
2349 dev_data->ats.enabled = true;
2350 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2351 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2352 } else if (amd_iommu_iotlb_sup &&
2353 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2354 dev_data->ats.enabled = true;
2355 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2356 }
2357
2358 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2359 ret = __attach_device(dev_data, domain);
2360 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2361
2362 /*
2363 * We might boot into a crash-kernel here. The crashed kernel
2364 * left the caches in the IOMMU dirty. So we have to flush
2365 * here to evict all dirty stuff.
2366 */
2367 domain_flush_tlb_pde(domain);
2368
2369 return ret;
2370 }
2371
2372 /*
2373 * Removes a device from a protection domain (unlocked)
2374 */
2375 static void __detach_device(struct iommu_dev_data *dev_data)
2376 {
2377 struct protection_domain *domain;
2378 unsigned long flags;
2379
2380 BUG_ON(!dev_data->domain);
2381
2382 domain = dev_data->domain;
2383
2384 spin_lock_irqsave(&domain->lock, flags);
2385
2386 if (dev_data->alias_data != NULL) {
2387 struct iommu_dev_data *alias_data = dev_data->alias_data;
2388
2389 if (atomic_dec_and_test(&alias_data->bind))
2390 do_detach(alias_data);
2391 }
2392
2393 if (atomic_dec_and_test(&dev_data->bind))
2394 do_detach(dev_data);
2395
2396 spin_unlock_irqrestore(&domain->lock, flags);
2397
2398 /*
2399 * If we run in passthrough mode the device must be assigned to the
2400 * passthrough domain if it is detached from any other domain.
2401 * Make sure we can deassign from the pt_domain itself.
2402 */
2403 if (dev_data->passthrough &&
2404 (dev_data->domain == NULL && domain != pt_domain))
2405 __attach_device(dev_data, pt_domain);
2406 }
2407
2408 /*
2409 * Removes a device from a protection domain (with devtable_lock held)
2410 */
2411 static void detach_device(struct device *dev)
2412 {
2413 struct protection_domain *domain;
2414 struct iommu_dev_data *dev_data;
2415 unsigned long flags;
2416
2417 dev_data = get_dev_data(dev);
2418 domain = dev_data->domain;
2419
2420 /* lock device table */
2421 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2422 __detach_device(dev_data);
2423 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2424
2425 if (domain->flags & PD_IOMMUV2_MASK)
2426 pdev_iommuv2_disable(to_pci_dev(dev));
2427 else if (dev_data->ats.enabled)
2428 pci_disable_ats(to_pci_dev(dev));
2429
2430 dev_data->ats.enabled = false;
2431 }
2432
2433 /*
2434 * Find out the protection domain structure for a given PCI device. This
2435 * will give us the pointer to the page table root for example.
2436 */
2437 static struct protection_domain *domain_for_device(struct device *dev)
2438 {
2439 struct iommu_dev_data *dev_data;
2440 struct protection_domain *dom = NULL;
2441 unsigned long flags;
2442
2443 dev_data = get_dev_data(dev);
2444
2445 if (dev_data->domain)
2446 return dev_data->domain;
2447
2448 if (dev_data->alias_data != NULL) {
2449 struct iommu_dev_data *alias_data = dev_data->alias_data;
2450
2451 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2452 if (alias_data->domain != NULL) {
2453 __attach_device(dev_data, alias_data->domain);
2454 dom = alias_data->domain;
2455 }
2456 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2457 }
2458
2459 return dom;
2460 }
2461
2462 static int device_change_notifier(struct notifier_block *nb,
2463 unsigned long action, void *data)
2464 {
2465 struct dma_ops_domain *dma_domain;
2466 struct protection_domain *domain;
2467 struct iommu_dev_data *dev_data;
2468 struct device *dev = data;
2469 struct amd_iommu *iommu;
2470 unsigned long flags;
2471 u16 devid;
2472
2473 if (!check_device(dev))
2474 return 0;
2475
2476 devid = get_device_id(dev);
2477 iommu = amd_iommu_rlookup_table[devid];
2478 dev_data = get_dev_data(dev);
2479
2480 switch (action) {
2481 case BUS_NOTIFY_UNBOUND_DRIVER:
2482
2483 domain = domain_for_device(dev);
2484
2485 if (!domain)
2486 goto out;
2487 if (dev_data->passthrough)
2488 break;
2489 detach_device(dev);
2490 break;
2491 case BUS_NOTIFY_ADD_DEVICE:
2492
2493 iommu_init_device(dev);
2494
2495 /*
2496 * dev_data is still NULL and
2497 * got initialized in iommu_init_device
2498 */
2499 dev_data = get_dev_data(dev);
2500
2501 if (iommu_pass_through || dev_data->iommu_v2) {
2502 dev_data->passthrough = true;
2503 attach_device(dev, pt_domain);
2504 break;
2505 }
2506
2507 domain = domain_for_device(dev);
2508
2509 /* allocate a protection domain if a device is added */
2510 dma_domain = find_protection_domain(devid);
2511 if (!dma_domain) {
2512 dma_domain = dma_ops_domain_alloc();
2513 if (!dma_domain)
2514 goto out;
2515 dma_domain->target_dev = devid;
2516
2517 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2518 list_add_tail(&dma_domain->list, &iommu_pd_list);
2519 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2520 }
2521
2522 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2523
2524 break;
2525 case BUS_NOTIFY_DEL_DEVICE:
2526
2527 iommu_uninit_device(dev);
2528
2529 default:
2530 goto out;
2531 }
2532
2533 iommu_completion_wait(iommu);
2534
2535 out:
2536 return 0;
2537 }
2538
2539 static struct notifier_block device_nb = {
2540 .notifier_call = device_change_notifier,
2541 };
2542
2543 void amd_iommu_init_notifier(void)
2544 {
2545 bus_register_notifier(&pci_bus_type, &device_nb);
2546 }
2547
2548 /*****************************************************************************
2549 *
2550 * The next functions belong to the dma_ops mapping/unmapping code.
2551 *
2552 *****************************************************************************/
2553
2554 /*
2555 * In the dma_ops path we only have the struct device. This function
2556 * finds the corresponding IOMMU, the protection domain and the
2557 * requestor id for a given device.
2558 * If the device is not yet associated with a domain this is also done
2559 * in this function.
2560 */
2561 static struct protection_domain *get_domain(struct device *dev)
2562 {
2563 struct protection_domain *domain;
2564 struct dma_ops_domain *dma_dom;
2565 u16 devid = get_device_id(dev);
2566
2567 if (!check_device(dev))
2568 return ERR_PTR(-EINVAL);
2569
2570 domain = domain_for_device(dev);
2571 if (domain != NULL && !dma_ops_domain(domain))
2572 return ERR_PTR(-EBUSY);
2573
2574 if (domain != NULL)
2575 return domain;
2576
2577 /* Device not bound yet - bind it */
2578 dma_dom = find_protection_domain(devid);
2579 if (!dma_dom)
2580 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2581 attach_device(dev, &dma_dom->domain);
2582 DUMP_printk("Using protection domain %d for device %s\n",
2583 dma_dom->domain.id, dev_name(dev));
2584
2585 return &dma_dom->domain;
2586 }
2587
2588 static void update_device_table(struct protection_domain *domain)
2589 {
2590 struct iommu_dev_data *dev_data;
2591
2592 list_for_each_entry(dev_data, &domain->dev_list, list)
2593 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2594 }
2595
2596 static void update_domain(struct protection_domain *domain)
2597 {
2598 if (!domain->updated)
2599 return;
2600
2601 update_device_table(domain);
2602
2603 domain_flush_devices(domain);
2604 domain_flush_tlb_pde(domain);
2605
2606 domain->updated = false;
2607 }
2608
2609 /*
2610 * This function fetches the PTE for a given address in the aperture
2611 */
2612 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2613 unsigned long address)
2614 {
2615 struct aperture_range *aperture;
2616 u64 *pte, *pte_page;
2617
2618 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2619 if (!aperture)
2620 return NULL;
2621
2622 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2623 if (!pte) {
2624 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2625 GFP_ATOMIC);
2626 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2627 } else
2628 pte += PM_LEVEL_INDEX(0, address);
2629
2630 update_domain(&dom->domain);
2631
2632 return pte;
2633 }
2634
2635 /*
2636 * This is the generic map function. It maps one 4kb page at paddr to
2637 * the given address in the DMA address space for the domain.
2638 */
2639 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2640 unsigned long address,
2641 phys_addr_t paddr,
2642 int direction)
2643 {
2644 u64 *pte, __pte;
2645
2646 WARN_ON(address > dom->aperture_size);
2647
2648 paddr &= PAGE_MASK;
2649
2650 pte = dma_ops_get_pte(dom, address);
2651 if (!pte)
2652 return DMA_ERROR_CODE;
2653
2654 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2655
2656 if (direction == DMA_TO_DEVICE)
2657 __pte |= IOMMU_PTE_IR;
2658 else if (direction == DMA_FROM_DEVICE)
2659 __pte |= IOMMU_PTE_IW;
2660 else if (direction == DMA_BIDIRECTIONAL)
2661 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2662
2663 WARN_ON(*pte);
2664
2665 *pte = __pte;
2666
2667 return (dma_addr_t)address;
2668 }
2669
2670 /*
2671 * The generic unmapping function for on page in the DMA address space.
2672 */
2673 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2674 unsigned long address)
2675 {
2676 struct aperture_range *aperture;
2677 u64 *pte;
2678
2679 if (address >= dom->aperture_size)
2680 return;
2681
2682 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2683 if (!aperture)
2684 return;
2685
2686 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2687 if (!pte)
2688 return;
2689
2690 pte += PM_LEVEL_INDEX(0, address);
2691
2692 WARN_ON(!*pte);
2693
2694 *pte = 0ULL;
2695 }
2696
2697 /*
2698 * This function contains common code for mapping of a physically
2699 * contiguous memory region into DMA address space. It is used by all
2700 * mapping functions provided with this IOMMU driver.
2701 * Must be called with the domain lock held.
2702 */
2703 static dma_addr_t __map_single(struct device *dev,
2704 struct dma_ops_domain *dma_dom,
2705 phys_addr_t paddr,
2706 size_t size,
2707 int dir,
2708 bool align,
2709 u64 dma_mask)
2710 {
2711 dma_addr_t offset = paddr & ~PAGE_MASK;
2712 dma_addr_t address, start, ret;
2713 unsigned int pages;
2714 unsigned long align_mask = 0;
2715 int i;
2716
2717 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2718 paddr &= PAGE_MASK;
2719
2720 INC_STATS_COUNTER(total_map_requests);
2721
2722 if (pages > 1)
2723 INC_STATS_COUNTER(cross_page);
2724
2725 if (align)
2726 align_mask = (1UL << get_order(size)) - 1;
2727
2728 retry:
2729 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2730 dma_mask);
2731 if (unlikely(address == DMA_ERROR_CODE)) {
2732 /*
2733 * setting next_address here will let the address
2734 * allocator only scan the new allocated range in the
2735 * first run. This is a small optimization.
2736 */
2737 dma_dom->next_address = dma_dom->aperture_size;
2738
2739 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2740 goto out;
2741
2742 /*
2743 * aperture was successfully enlarged by 128 MB, try
2744 * allocation again
2745 */
2746 goto retry;
2747 }
2748
2749 start = address;
2750 for (i = 0; i < pages; ++i) {
2751 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2752 if (ret == DMA_ERROR_CODE)
2753 goto out_unmap;
2754
2755 paddr += PAGE_SIZE;
2756 start += PAGE_SIZE;
2757 }
2758 address += offset;
2759
2760 ADD_STATS_COUNTER(alloced_io_mem, size);
2761
2762 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2763 domain_flush_tlb(&dma_dom->domain);
2764 dma_dom->need_flush = false;
2765 } else if (unlikely(amd_iommu_np_cache))
2766 domain_flush_pages(&dma_dom->domain, address, size);
2767
2768 out:
2769 return address;
2770
2771 out_unmap:
2772
2773 for (--i; i >= 0; --i) {
2774 start -= PAGE_SIZE;
2775 dma_ops_domain_unmap(dma_dom, start);
2776 }
2777
2778 dma_ops_free_addresses(dma_dom, address, pages);
2779
2780 return DMA_ERROR_CODE;
2781 }
2782
2783 /*
2784 * Does the reverse of the __map_single function. Must be called with
2785 * the domain lock held too
2786 */
2787 static void __unmap_single(struct dma_ops_domain *dma_dom,
2788 dma_addr_t dma_addr,
2789 size_t size,
2790 int dir)
2791 {
2792 dma_addr_t flush_addr;
2793 dma_addr_t i, start;
2794 unsigned int pages;
2795
2796 if ((dma_addr == DMA_ERROR_CODE) ||
2797 (dma_addr + size > dma_dom->aperture_size))
2798 return;
2799
2800 flush_addr = dma_addr;
2801 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2802 dma_addr &= PAGE_MASK;
2803 start = dma_addr;
2804
2805 for (i = 0; i < pages; ++i) {
2806 dma_ops_domain_unmap(dma_dom, start);
2807 start += PAGE_SIZE;
2808 }
2809
2810 SUB_STATS_COUNTER(alloced_io_mem, size);
2811
2812 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2813
2814 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2815 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2816 dma_dom->need_flush = false;
2817 }
2818 }
2819
2820 /*
2821 * The exported map_single function for dma_ops.
2822 */
2823 static dma_addr_t map_page(struct device *dev, struct page *page,
2824 unsigned long offset, size_t size,
2825 enum dma_data_direction dir,
2826 struct dma_attrs *attrs)
2827 {
2828 unsigned long flags;
2829 struct protection_domain *domain;
2830 dma_addr_t addr;
2831 u64 dma_mask;
2832 phys_addr_t paddr = page_to_phys(page) + offset;
2833
2834 INC_STATS_COUNTER(cnt_map_single);
2835
2836 domain = get_domain(dev);
2837 if (PTR_ERR(domain) == -EINVAL)
2838 return (dma_addr_t)paddr;
2839 else if (IS_ERR(domain))
2840 return DMA_ERROR_CODE;
2841
2842 dma_mask = *dev->dma_mask;
2843
2844 spin_lock_irqsave(&domain->lock, flags);
2845
2846 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2847 dma_mask);
2848 if (addr == DMA_ERROR_CODE)
2849 goto out;
2850
2851 domain_flush_complete(domain);
2852
2853 out:
2854 spin_unlock_irqrestore(&domain->lock, flags);
2855
2856 return addr;
2857 }
2858
2859 /*
2860 * The exported unmap_single function for dma_ops.
2861 */
2862 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2863 enum dma_data_direction dir, struct dma_attrs *attrs)
2864 {
2865 unsigned long flags;
2866 struct protection_domain *domain;
2867
2868 INC_STATS_COUNTER(cnt_unmap_single);
2869
2870 domain = get_domain(dev);
2871 if (IS_ERR(domain))
2872 return;
2873
2874 spin_lock_irqsave(&domain->lock, flags);
2875
2876 __unmap_single(domain->priv, dma_addr, size, dir);
2877
2878 domain_flush_complete(domain);
2879
2880 spin_unlock_irqrestore(&domain->lock, flags);
2881 }
2882
2883 /*
2884 * The exported map_sg function for dma_ops (handles scatter-gather
2885 * lists).
2886 */
2887 static int map_sg(struct device *dev, struct scatterlist *sglist,
2888 int nelems, enum dma_data_direction dir,
2889 struct dma_attrs *attrs)
2890 {
2891 unsigned long flags;
2892 struct protection_domain *domain;
2893 int i;
2894 struct scatterlist *s;
2895 phys_addr_t paddr;
2896 int mapped_elems = 0;
2897 u64 dma_mask;
2898
2899 INC_STATS_COUNTER(cnt_map_sg);
2900
2901 domain = get_domain(dev);
2902 if (IS_ERR(domain))
2903 return 0;
2904
2905 dma_mask = *dev->dma_mask;
2906
2907 spin_lock_irqsave(&domain->lock, flags);
2908
2909 for_each_sg(sglist, s, nelems, i) {
2910 paddr = sg_phys(s);
2911
2912 s->dma_address = __map_single(dev, domain->priv,
2913 paddr, s->length, dir, false,
2914 dma_mask);
2915
2916 if (s->dma_address) {
2917 s->dma_length = s->length;
2918 mapped_elems++;
2919 } else
2920 goto unmap;
2921 }
2922
2923 domain_flush_complete(domain);
2924
2925 out:
2926 spin_unlock_irqrestore(&domain->lock, flags);
2927
2928 return mapped_elems;
2929 unmap:
2930 for_each_sg(sglist, s, mapped_elems, i) {
2931 if (s->dma_address)
2932 __unmap_single(domain->priv, s->dma_address,
2933 s->dma_length, dir);
2934 s->dma_address = s->dma_length = 0;
2935 }
2936
2937 mapped_elems = 0;
2938
2939 goto out;
2940 }
2941
2942 /*
2943 * The exported map_sg function for dma_ops (handles scatter-gather
2944 * lists).
2945 */
2946 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2947 int nelems, enum dma_data_direction dir,
2948 struct dma_attrs *attrs)
2949 {
2950 unsigned long flags;
2951 struct protection_domain *domain;
2952 struct scatterlist *s;
2953 int i;
2954
2955 INC_STATS_COUNTER(cnt_unmap_sg);
2956
2957 domain = get_domain(dev);
2958 if (IS_ERR(domain))
2959 return;
2960
2961 spin_lock_irqsave(&domain->lock, flags);
2962
2963 for_each_sg(sglist, s, nelems, i) {
2964 __unmap_single(domain->priv, s->dma_address,
2965 s->dma_length, dir);
2966 s->dma_address = s->dma_length = 0;
2967 }
2968
2969 domain_flush_complete(domain);
2970
2971 spin_unlock_irqrestore(&domain->lock, flags);
2972 }
2973
2974 /*
2975 * The exported alloc_coherent function for dma_ops.
2976 */
2977 static void *alloc_coherent(struct device *dev, size_t size,
2978 dma_addr_t *dma_addr, gfp_t flag,
2979 struct dma_attrs *attrs)
2980 {
2981 unsigned long flags;
2982 void *virt_addr;
2983 struct protection_domain *domain;
2984 phys_addr_t paddr;
2985 u64 dma_mask = dev->coherent_dma_mask;
2986
2987 INC_STATS_COUNTER(cnt_alloc_coherent);
2988
2989 domain = get_domain(dev);
2990 if (PTR_ERR(domain) == -EINVAL) {
2991 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2992 *dma_addr = __pa(virt_addr);
2993 return virt_addr;
2994 } else if (IS_ERR(domain))
2995 return NULL;
2996
2997 dma_mask = dev->coherent_dma_mask;
2998 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2999 flag |= __GFP_ZERO;
3000
3001 virt_addr = (void *)__get_free_pages(flag, get_order(size));
3002 if (!virt_addr)
3003 return NULL;
3004
3005 paddr = virt_to_phys(virt_addr);
3006
3007 if (!dma_mask)
3008 dma_mask = *dev->dma_mask;
3009
3010 spin_lock_irqsave(&domain->lock, flags);
3011
3012 *dma_addr = __map_single(dev, domain->priv, paddr,
3013 size, DMA_BIDIRECTIONAL, true, dma_mask);
3014
3015 if (*dma_addr == DMA_ERROR_CODE) {
3016 spin_unlock_irqrestore(&domain->lock, flags);
3017 goto out_free;
3018 }
3019
3020 domain_flush_complete(domain);
3021
3022 spin_unlock_irqrestore(&domain->lock, flags);
3023
3024 return virt_addr;
3025
3026 out_free:
3027
3028 free_pages((unsigned long)virt_addr, get_order(size));
3029
3030 return NULL;
3031 }
3032
3033 /*
3034 * The exported free_coherent function for dma_ops.
3035 */
3036 static void free_coherent(struct device *dev, size_t size,
3037 void *virt_addr, dma_addr_t dma_addr,
3038 struct dma_attrs *attrs)
3039 {
3040 unsigned long flags;
3041 struct protection_domain *domain;
3042
3043 INC_STATS_COUNTER(cnt_free_coherent);
3044
3045 domain = get_domain(dev);
3046 if (IS_ERR(domain))
3047 goto free_mem;
3048
3049 spin_lock_irqsave(&domain->lock, flags);
3050
3051 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
3052
3053 domain_flush_complete(domain);
3054
3055 spin_unlock_irqrestore(&domain->lock, flags);
3056
3057 free_mem:
3058 free_pages((unsigned long)virt_addr, get_order(size));
3059 }
3060
3061 /*
3062 * This function is called by the DMA layer to find out if we can handle a
3063 * particular device. It is part of the dma_ops.
3064 */
3065 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
3066 {
3067 return check_device(dev);
3068 }
3069
3070 /*
3071 * The function for pre-allocating protection domains.
3072 *
3073 * If the driver core informs the DMA layer if a driver grabs a device
3074 * we don't need to preallocate the protection domains anymore.
3075 * For now we have to.
3076 */
3077 static void __init prealloc_protection_domains(void)
3078 {
3079 struct iommu_dev_data *dev_data;
3080 struct dma_ops_domain *dma_dom;
3081 struct pci_dev *dev = NULL;
3082 u16 devid;
3083
3084 for_each_pci_dev(dev) {
3085
3086 /* Do we handle this device? */
3087 if (!check_device(&dev->dev))
3088 continue;
3089
3090 dev_data = get_dev_data(&dev->dev);
3091 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
3092 /* Make sure passthrough domain is allocated */
3093 alloc_passthrough_domain();
3094 dev_data->passthrough = true;
3095 attach_device(&dev->dev, pt_domain);
3096 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
3097 dev_name(&dev->dev));
3098 }
3099
3100 /* Is there already any domain for it? */
3101 if (domain_for_device(&dev->dev))
3102 continue;
3103
3104 devid = get_device_id(&dev->dev);
3105
3106 dma_dom = dma_ops_domain_alloc();
3107 if (!dma_dom)
3108 continue;
3109 init_unity_mappings_for_device(dma_dom, devid);
3110 dma_dom->target_dev = devid;
3111
3112 attach_device(&dev->dev, &dma_dom->domain);
3113
3114 list_add_tail(&dma_dom->list, &iommu_pd_list);
3115 }
3116 }
3117
3118 static struct dma_map_ops amd_iommu_dma_ops = {
3119 .alloc = alloc_coherent,
3120 .free = free_coherent,
3121 .map_page = map_page,
3122 .unmap_page = unmap_page,
3123 .map_sg = map_sg,
3124 .unmap_sg = unmap_sg,
3125 .dma_supported = amd_iommu_dma_supported,
3126 };
3127
3128 static unsigned device_dma_ops_init(void)
3129 {
3130 struct iommu_dev_data *dev_data;
3131 struct pci_dev *pdev = NULL;
3132 unsigned unhandled = 0;
3133
3134 for_each_pci_dev(pdev) {
3135 if (!check_device(&pdev->dev)) {
3136
3137 iommu_ignore_device(&pdev->dev);
3138
3139 unhandled += 1;
3140 continue;
3141 }
3142
3143 dev_data = get_dev_data(&pdev->dev);
3144
3145 if (!dev_data->passthrough)
3146 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
3147 else
3148 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
3149 }
3150
3151 return unhandled;
3152 }
3153
3154 /*
3155 * The function which clues the AMD IOMMU driver into dma_ops.
3156 */
3157
3158 void __init amd_iommu_init_api(void)
3159 {
3160 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
3161 }
3162
3163 int __init amd_iommu_init_dma_ops(void)
3164 {
3165 struct amd_iommu *iommu;
3166 int ret, unhandled;
3167
3168 /*
3169 * first allocate a default protection domain for every IOMMU we
3170 * found in the system. Devices not assigned to any other
3171 * protection domain will be assigned to the default one.
3172 */
3173 for_each_iommu(iommu) {
3174 iommu->default_dom = dma_ops_domain_alloc();
3175 if (iommu->default_dom == NULL)
3176 return -ENOMEM;
3177 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
3178 ret = iommu_init_unity_mappings(iommu);
3179 if (ret)
3180 goto free_domains;
3181 }
3182
3183 /*
3184 * Pre-allocate the protection domains for each device.
3185 */
3186 prealloc_protection_domains();
3187
3188 iommu_detected = 1;
3189 swiotlb = 0;
3190
3191 /* Make the driver finally visible to the drivers */
3192 unhandled = device_dma_ops_init();
3193 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3194 /* There are unhandled devices - initialize swiotlb for them */
3195 swiotlb = 1;
3196 }
3197
3198 amd_iommu_stats_init();
3199
3200 if (amd_iommu_unmap_flush)
3201 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3202 else
3203 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3204
3205 return 0;
3206
3207 free_domains:
3208
3209 for_each_iommu(iommu) {
3210 dma_ops_domain_free(iommu->default_dom);
3211 }
3212
3213 return ret;
3214 }
3215
3216 /*****************************************************************************
3217 *
3218 * The following functions belong to the exported interface of AMD IOMMU
3219 *
3220 * This interface allows access to lower level functions of the IOMMU
3221 * like protection domain handling and assignement of devices to domains
3222 * which is not possible with the dma_ops interface.
3223 *
3224 *****************************************************************************/
3225
3226 static void cleanup_domain(struct protection_domain *domain)
3227 {
3228 struct iommu_dev_data *dev_data, *next;
3229 unsigned long flags;
3230
3231 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3232
3233 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
3234 __detach_device(dev_data);
3235 atomic_set(&dev_data->bind, 0);
3236 }
3237
3238 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3239 }
3240
3241 static void protection_domain_free(struct protection_domain *domain)
3242 {
3243 if (!domain)
3244 return;
3245
3246 del_domain_from_list(domain);
3247
3248 if (domain->id)
3249 domain_id_free(domain->id);
3250
3251 kfree(domain);
3252 }
3253
3254 static struct protection_domain *protection_domain_alloc(void)
3255 {
3256 struct protection_domain *domain;
3257
3258 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3259 if (!domain)
3260 return NULL;
3261
3262 spin_lock_init(&domain->lock);
3263 mutex_init(&domain->api_lock);
3264 domain->id = domain_id_alloc();
3265 if (!domain->id)
3266 goto out_err;
3267 INIT_LIST_HEAD(&domain->dev_list);
3268
3269 add_domain_to_list(domain);
3270
3271 return domain;
3272
3273 out_err:
3274 kfree(domain);
3275
3276 return NULL;
3277 }
3278
3279 static int __init alloc_passthrough_domain(void)
3280 {
3281 if (pt_domain != NULL)
3282 return 0;
3283
3284 /* allocate passthrough domain */
3285 pt_domain = protection_domain_alloc();
3286 if (!pt_domain)
3287 return -ENOMEM;
3288
3289 pt_domain->mode = PAGE_MODE_NONE;
3290
3291 return 0;
3292 }
3293 static int amd_iommu_domain_init(struct iommu_domain *dom)
3294 {
3295 struct protection_domain *domain;
3296
3297 domain = protection_domain_alloc();
3298 if (!domain)
3299 goto out_free;
3300
3301 domain->mode = PAGE_MODE_3_LEVEL;
3302 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3303 if (!domain->pt_root)
3304 goto out_free;
3305
3306 domain->iommu_domain = dom;
3307
3308 dom->priv = domain;
3309
3310 dom->geometry.aperture_start = 0;
3311 dom->geometry.aperture_end = ~0ULL;
3312 dom->geometry.force_aperture = true;
3313
3314 return 0;
3315
3316 out_free:
3317 protection_domain_free(domain);
3318
3319 return -ENOMEM;
3320 }
3321
3322 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3323 {
3324 struct protection_domain *domain = dom->priv;
3325
3326 if (!domain)
3327 return;
3328
3329 if (domain->dev_cnt > 0)
3330 cleanup_domain(domain);
3331
3332 BUG_ON(domain->dev_cnt != 0);
3333
3334 if (domain->mode != PAGE_MODE_NONE)
3335 free_pagetable(domain);
3336
3337 if (domain->flags & PD_IOMMUV2_MASK)
3338 free_gcr3_table(domain);
3339
3340 protection_domain_free(domain);
3341
3342 dom->priv = NULL;
3343 }
3344
3345 static void amd_iommu_detach_device(struct iommu_domain *dom,
3346 struct device *dev)
3347 {
3348 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3349 struct amd_iommu *iommu;
3350 u16 devid;
3351
3352 if (!check_device(dev))
3353 return;
3354
3355 devid = get_device_id(dev);
3356
3357 if (dev_data->domain != NULL)
3358 detach_device(dev);
3359
3360 iommu = amd_iommu_rlookup_table[devid];
3361 if (!iommu)
3362 return;
3363
3364 iommu_completion_wait(iommu);
3365 }
3366
3367 static int amd_iommu_attach_device(struct iommu_domain *dom,
3368 struct device *dev)
3369 {
3370 struct protection_domain *domain = dom->priv;
3371 struct iommu_dev_data *dev_data;
3372 struct amd_iommu *iommu;
3373 int ret;
3374
3375 if (!check_device(dev))
3376 return -EINVAL;
3377
3378 dev_data = dev->archdata.iommu;
3379
3380 iommu = amd_iommu_rlookup_table[dev_data->devid];
3381 if (!iommu)
3382 return -EINVAL;
3383
3384 if (dev_data->domain)
3385 detach_device(dev);
3386
3387 ret = attach_device(dev, domain);
3388
3389 iommu_completion_wait(iommu);
3390
3391 return ret;
3392 }
3393
3394 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3395 phys_addr_t paddr, size_t page_size, int iommu_prot)
3396 {
3397 struct protection_domain *domain = dom->priv;
3398 int prot = 0;
3399 int ret;
3400
3401 if (domain->mode == PAGE_MODE_NONE)
3402 return -EINVAL;
3403
3404 if (iommu_prot & IOMMU_READ)
3405 prot |= IOMMU_PROT_IR;
3406 if (iommu_prot & IOMMU_WRITE)
3407 prot |= IOMMU_PROT_IW;
3408
3409 mutex_lock(&domain->api_lock);
3410 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3411 mutex_unlock(&domain->api_lock);
3412
3413 return ret;
3414 }
3415
3416 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3417 size_t page_size)
3418 {
3419 struct protection_domain *domain = dom->priv;
3420 size_t unmap_size;
3421
3422 if (domain->mode == PAGE_MODE_NONE)
3423 return -EINVAL;
3424
3425 mutex_lock(&domain->api_lock);
3426 unmap_size = iommu_unmap_page(domain, iova, page_size);
3427 mutex_unlock(&domain->api_lock);
3428
3429 domain_flush_tlb_pde(domain);
3430
3431 return unmap_size;
3432 }
3433
3434 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3435 dma_addr_t iova)
3436 {
3437 struct protection_domain *domain = dom->priv;
3438 unsigned long offset_mask;
3439 phys_addr_t paddr;
3440 u64 *pte, __pte;
3441
3442 if (domain->mode == PAGE_MODE_NONE)
3443 return iova;
3444
3445 pte = fetch_pte(domain, iova);
3446
3447 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3448 return 0;
3449
3450 if (PM_PTE_LEVEL(*pte) == 0)
3451 offset_mask = PAGE_SIZE - 1;
3452 else
3453 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3454
3455 __pte = *pte & PM_ADDR_MASK;
3456 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
3457
3458 return paddr;
3459 }
3460
3461 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3462 unsigned long cap)
3463 {
3464 switch (cap) {
3465 case IOMMU_CAP_CACHE_COHERENCY:
3466 return 1;
3467 case IOMMU_CAP_INTR_REMAP:
3468 return irq_remapping_enabled;
3469 }
3470
3471 return 0;
3472 }
3473
3474 static struct iommu_ops amd_iommu_ops = {
3475 .domain_init = amd_iommu_domain_init,
3476 .domain_destroy = amd_iommu_domain_destroy,
3477 .attach_dev = amd_iommu_attach_device,
3478 .detach_dev = amd_iommu_detach_device,
3479 .map = amd_iommu_map,
3480 .unmap = amd_iommu_unmap,
3481 .iova_to_phys = amd_iommu_iova_to_phys,
3482 .domain_has_cap = amd_iommu_domain_has_cap,
3483 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3484 };
3485
3486 /*****************************************************************************
3487 *
3488 * The next functions do a basic initialization of IOMMU for pass through
3489 * mode
3490 *
3491 * In passthrough mode the IOMMU is initialized and enabled but not used for
3492 * DMA-API translation.
3493 *
3494 *****************************************************************************/
3495
3496 int __init amd_iommu_init_passthrough(void)
3497 {
3498 struct iommu_dev_data *dev_data;
3499 struct pci_dev *dev = NULL;
3500 struct amd_iommu *iommu;
3501 u16 devid;
3502 int ret;
3503
3504 ret = alloc_passthrough_domain();
3505 if (ret)
3506 return ret;
3507
3508 for_each_pci_dev(dev) {
3509 if (!check_device(&dev->dev))
3510 continue;
3511
3512 dev_data = get_dev_data(&dev->dev);
3513 dev_data->passthrough = true;
3514
3515 devid = get_device_id(&dev->dev);
3516
3517 iommu = amd_iommu_rlookup_table[devid];
3518 if (!iommu)
3519 continue;
3520
3521 attach_device(&dev->dev, pt_domain);
3522 }
3523
3524 amd_iommu_stats_init();
3525
3526 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3527
3528 return 0;
3529 }
3530
3531 /* IOMMUv2 specific functions */
3532 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3533 {
3534 return atomic_notifier_chain_register(&ppr_notifier, nb);
3535 }
3536 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3537
3538 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3539 {
3540 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3541 }
3542 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3543
3544 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3545 {
3546 struct protection_domain *domain = dom->priv;
3547 unsigned long flags;
3548
3549 spin_lock_irqsave(&domain->lock, flags);
3550
3551 /* Update data structure */
3552 domain->mode = PAGE_MODE_NONE;
3553 domain->updated = true;
3554
3555 /* Make changes visible to IOMMUs */
3556 update_domain(domain);
3557
3558 /* Page-table is not visible to IOMMU anymore, so free it */
3559 free_pagetable(domain);
3560
3561 spin_unlock_irqrestore(&domain->lock, flags);
3562 }
3563 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3564
3565 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3566 {
3567 struct protection_domain *domain = dom->priv;
3568 unsigned long flags;
3569 int levels, ret;
3570
3571 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3572 return -EINVAL;
3573
3574 /* Number of GCR3 table levels required */
3575 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3576 levels += 1;
3577
3578 if (levels > amd_iommu_max_glx_val)
3579 return -EINVAL;
3580
3581 spin_lock_irqsave(&domain->lock, flags);
3582
3583 /*
3584 * Save us all sanity checks whether devices already in the
3585 * domain support IOMMUv2. Just force that the domain has no
3586 * devices attached when it is switched into IOMMUv2 mode.
3587 */
3588 ret = -EBUSY;
3589 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3590 goto out;
3591
3592 ret = -ENOMEM;
3593 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3594 if (domain->gcr3_tbl == NULL)
3595 goto out;
3596
3597 domain->glx = levels;
3598 domain->flags |= PD_IOMMUV2_MASK;
3599 domain->updated = true;
3600
3601 update_domain(domain);
3602
3603 ret = 0;
3604
3605 out:
3606 spin_unlock_irqrestore(&domain->lock, flags);
3607
3608 return ret;
3609 }
3610 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3611
3612 static int __flush_pasid(struct protection_domain *domain, int pasid,
3613 u64 address, bool size)
3614 {
3615 struct iommu_dev_data *dev_data;
3616 struct iommu_cmd cmd;
3617 int i, ret;
3618
3619 if (!(domain->flags & PD_IOMMUV2_MASK))
3620 return -EINVAL;
3621
3622 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3623
3624 /*
3625 * IOMMU TLB needs to be flushed before Device TLB to
3626 * prevent device TLB refill from IOMMU TLB
3627 */
3628 for (i = 0; i < amd_iommus_present; ++i) {
3629 if (domain->dev_iommu[i] == 0)
3630 continue;
3631
3632 ret = iommu_queue_command(amd_iommus[i], &cmd);
3633 if (ret != 0)
3634 goto out;
3635 }
3636
3637 /* Wait until IOMMU TLB flushes are complete */
3638 domain_flush_complete(domain);
3639
3640 /* Now flush device TLBs */
3641 list_for_each_entry(dev_data, &domain->dev_list, list) {
3642 struct amd_iommu *iommu;
3643 int qdep;
3644
3645 BUG_ON(!dev_data->ats.enabled);
3646
3647 qdep = dev_data->ats.qdep;
3648 iommu = amd_iommu_rlookup_table[dev_data->devid];
3649
3650 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3651 qdep, address, size);
3652
3653 ret = iommu_queue_command(iommu, &cmd);
3654 if (ret != 0)
3655 goto out;
3656 }
3657
3658 /* Wait until all device TLBs are flushed */
3659 domain_flush_complete(domain);
3660
3661 ret = 0;
3662
3663 out:
3664
3665 return ret;
3666 }
3667
3668 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3669 u64 address)
3670 {
3671 INC_STATS_COUNTER(invalidate_iotlb);
3672
3673 return __flush_pasid(domain, pasid, address, false);
3674 }
3675
3676 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3677 u64 address)
3678 {
3679 struct protection_domain *domain = dom->priv;
3680 unsigned long flags;
3681 int ret;
3682
3683 spin_lock_irqsave(&domain->lock, flags);
3684 ret = __amd_iommu_flush_page(domain, pasid, address);
3685 spin_unlock_irqrestore(&domain->lock, flags);
3686
3687 return ret;
3688 }
3689 EXPORT_SYMBOL(amd_iommu_flush_page);
3690
3691 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3692 {
3693 INC_STATS_COUNTER(invalidate_iotlb_all);
3694
3695 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3696 true);
3697 }
3698
3699 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3700 {
3701 struct protection_domain *domain = dom->priv;
3702 unsigned long flags;
3703 int ret;
3704
3705 spin_lock_irqsave(&domain->lock, flags);
3706 ret = __amd_iommu_flush_tlb(domain, pasid);
3707 spin_unlock_irqrestore(&domain->lock, flags);
3708
3709 return ret;
3710 }
3711 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3712
3713 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3714 {
3715 int index;
3716 u64 *pte;
3717
3718 while (true) {
3719
3720 index = (pasid >> (9 * level)) & 0x1ff;
3721 pte = &root[index];
3722
3723 if (level == 0)
3724 break;
3725
3726 if (!(*pte & GCR3_VALID)) {
3727 if (!alloc)
3728 return NULL;
3729
3730 root = (void *)get_zeroed_page(GFP_ATOMIC);
3731 if (root == NULL)
3732 return NULL;
3733
3734 *pte = __pa(root) | GCR3_VALID;
3735 }
3736
3737 root = __va(*pte & PAGE_MASK);
3738
3739 level -= 1;
3740 }
3741
3742 return pte;
3743 }
3744
3745 static int __set_gcr3(struct protection_domain *domain, int pasid,
3746 unsigned long cr3)
3747 {
3748 u64 *pte;
3749
3750 if (domain->mode != PAGE_MODE_NONE)
3751 return -EINVAL;
3752
3753 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3754 if (pte == NULL)
3755 return -ENOMEM;
3756
3757 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3758
3759 return __amd_iommu_flush_tlb(domain, pasid);
3760 }
3761
3762 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3763 {
3764 u64 *pte;
3765
3766 if (domain->mode != PAGE_MODE_NONE)
3767 return -EINVAL;
3768
3769 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3770 if (pte == NULL)
3771 return 0;
3772
3773 *pte = 0;
3774
3775 return __amd_iommu_flush_tlb(domain, pasid);
3776 }
3777
3778 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3779 unsigned long cr3)
3780 {
3781 struct protection_domain *domain = dom->priv;
3782 unsigned long flags;
3783 int ret;
3784
3785 spin_lock_irqsave(&domain->lock, flags);
3786 ret = __set_gcr3(domain, pasid, cr3);
3787 spin_unlock_irqrestore(&domain->lock, flags);
3788
3789 return ret;
3790 }
3791 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3792
3793 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3794 {
3795 struct protection_domain *domain = dom->priv;
3796 unsigned long flags;
3797 int ret;
3798
3799 spin_lock_irqsave(&domain->lock, flags);
3800 ret = __clear_gcr3(domain, pasid);
3801 spin_unlock_irqrestore(&domain->lock, flags);
3802
3803 return ret;
3804 }
3805 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3806
3807 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3808 int status, int tag)
3809 {
3810 struct iommu_dev_data *dev_data;
3811 struct amd_iommu *iommu;
3812 struct iommu_cmd cmd;
3813
3814 INC_STATS_COUNTER(complete_ppr);
3815
3816 dev_data = get_dev_data(&pdev->dev);
3817 iommu = amd_iommu_rlookup_table[dev_data->devid];
3818
3819 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3820 tag, dev_data->pri_tlp);
3821
3822 return iommu_queue_command(iommu, &cmd);
3823 }
3824 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3825
3826 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3827 {
3828 struct protection_domain *domain;
3829
3830 domain = get_domain(&pdev->dev);
3831 if (IS_ERR(domain))
3832 return NULL;
3833
3834 /* Only return IOMMUv2 domains */
3835 if (!(domain->flags & PD_IOMMUV2_MASK))
3836 return NULL;
3837
3838 return domain->iommu_domain;
3839 }
3840 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3841
3842 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3843 {
3844 struct iommu_dev_data *dev_data;
3845
3846 if (!amd_iommu_v2_supported())
3847 return;
3848
3849 dev_data = get_dev_data(&pdev->dev);
3850 dev_data->errata |= (1 << erratum);
3851 }
3852 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3853
3854 int amd_iommu_device_info(struct pci_dev *pdev,
3855 struct amd_iommu_device_info *info)
3856 {
3857 int max_pasids;
3858 int pos;
3859
3860 if (pdev == NULL || info == NULL)
3861 return -EINVAL;
3862
3863 if (!amd_iommu_v2_supported())
3864 return -EINVAL;
3865
3866 memset(info, 0, sizeof(*info));
3867
3868 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3869 if (pos)
3870 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3871
3872 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3873 if (pos)
3874 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3875
3876 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3877 if (pos) {
3878 int features;
3879
3880 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3881 max_pasids = min(max_pasids, (1 << 20));
3882
3883 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3884 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3885
3886 features = pci_pasid_features(pdev);
3887 if (features & PCI_PASID_CAP_EXEC)
3888 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3889 if (features & PCI_PASID_CAP_PRIV)
3890 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3891 }
3892
3893 return 0;
3894 }
3895 EXPORT_SYMBOL(amd_iommu_device_info);
3896
3897 #ifdef CONFIG_IRQ_REMAP
3898
3899 /*****************************************************************************
3900 *
3901 * Interrupt Remapping Implementation
3902 *
3903 *****************************************************************************/
3904
3905 union irte {
3906 u32 val;
3907 struct {
3908 u32 valid : 1,
3909 no_fault : 1,
3910 int_type : 3,
3911 rq_eoi : 1,
3912 dm : 1,
3913 rsvd_1 : 1,
3914 destination : 8,
3915 vector : 8,
3916 rsvd_2 : 8;
3917 } fields;
3918 };
3919
3920 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3921 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3922 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3923 #define DTE_IRQ_REMAP_ENABLE 1ULL
3924
3925 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3926 {
3927 u64 dte;
3928
3929 dte = amd_iommu_dev_table[devid].data[2];
3930 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3931 dte |= virt_to_phys(table->table);
3932 dte |= DTE_IRQ_REMAP_INTCTL;
3933 dte |= DTE_IRQ_TABLE_LEN;
3934 dte |= DTE_IRQ_REMAP_ENABLE;
3935
3936 amd_iommu_dev_table[devid].data[2] = dte;
3937 }
3938
3939 #define IRTE_ALLOCATED (~1U)
3940
3941 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3942 {
3943 struct irq_remap_table *table = NULL;
3944 struct amd_iommu *iommu;
3945 unsigned long flags;
3946 u16 alias;
3947
3948 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3949
3950 iommu = amd_iommu_rlookup_table[devid];
3951 if (!iommu)
3952 goto out_unlock;
3953
3954 table = irq_lookup_table[devid];
3955 if (table)
3956 goto out;
3957
3958 alias = amd_iommu_alias_table[devid];
3959 table = irq_lookup_table[alias];
3960 if (table) {
3961 irq_lookup_table[devid] = table;
3962 set_dte_irq_entry(devid, table);
3963 iommu_flush_dte(iommu, devid);
3964 goto out;
3965 }
3966
3967 /* Nothing there yet, allocate new irq remapping table */
3968 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3969 if (!table)
3970 goto out;
3971
3972 /* Initialize table spin-lock */
3973 spin_lock_init(&table->lock);
3974
3975 if (ioapic)
3976 /* Keep the first 32 indexes free for IOAPIC interrupts */
3977 table->min_index = 32;
3978
3979 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3980 if (!table->table) {
3981 kfree(table);
3982 table = NULL;
3983 goto out;
3984 }
3985
3986 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3987
3988 if (ioapic) {
3989 int i;
3990
3991 for (i = 0; i < 32; ++i)
3992 table->table[i] = IRTE_ALLOCATED;
3993 }
3994
3995 irq_lookup_table[devid] = table;
3996 set_dte_irq_entry(devid, table);
3997 iommu_flush_dte(iommu, devid);
3998 if (devid != alias) {
3999 irq_lookup_table[alias] = table;
4000 set_dte_irq_entry(devid, table);
4001 iommu_flush_dte(iommu, alias);
4002 }
4003
4004 out:
4005 iommu_completion_wait(iommu);
4006
4007 out_unlock:
4008 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
4009
4010 return table;
4011 }
4012
4013 static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
4014 {
4015 struct irq_remap_table *table;
4016 unsigned long flags;
4017 int index, c;
4018
4019 table = get_irq_table(devid, false);
4020 if (!table)
4021 return -ENODEV;
4022
4023 spin_lock_irqsave(&table->lock, flags);
4024
4025 /* Scan table for free entries */
4026 for (c = 0, index = table->min_index;
4027 index < MAX_IRQS_PER_TABLE;
4028 ++index) {
4029 if (table->table[index] == 0)
4030 c += 1;
4031 else
4032 c = 0;
4033
4034 if (c == count) {
4035 struct irq_2_irte *irte_info;
4036
4037 for (; c != 0; --c)
4038 table->table[index - c + 1] = IRTE_ALLOCATED;
4039
4040 index -= count - 1;
4041
4042 cfg->remapped = 1;
4043 irte_info = &cfg->irq_2_irte;
4044 irte_info->devid = devid;
4045 irte_info->index = index;
4046
4047 goto out;
4048 }
4049 }
4050
4051 index = -ENOSPC;
4052
4053 out:
4054 spin_unlock_irqrestore(&table->lock, flags);
4055
4056 return index;
4057 }
4058
4059 static int get_irte(u16 devid, int index, union irte *irte)
4060 {
4061 struct irq_remap_table *table;
4062 unsigned long flags;
4063
4064 table = get_irq_table(devid, false);
4065 if (!table)
4066 return -ENOMEM;
4067
4068 spin_lock_irqsave(&table->lock, flags);
4069 irte->val = table->table[index];
4070 spin_unlock_irqrestore(&table->lock, flags);
4071
4072 return 0;
4073 }
4074
4075 static int modify_irte(u16 devid, int index, union irte irte)
4076 {
4077 struct irq_remap_table *table;
4078 struct amd_iommu *iommu;
4079 unsigned long flags;
4080
4081 iommu = amd_iommu_rlookup_table[devid];
4082 if (iommu == NULL)
4083 return -EINVAL;
4084
4085 table = get_irq_table(devid, false);
4086 if (!table)
4087 return -ENOMEM;
4088
4089 spin_lock_irqsave(&table->lock, flags);
4090 table->table[index] = irte.val;
4091 spin_unlock_irqrestore(&table->lock, flags);
4092
4093 iommu_flush_irt(iommu, devid);
4094 iommu_completion_wait(iommu);
4095
4096 return 0;
4097 }
4098
4099 static void free_irte(u16 devid, int index)
4100 {
4101 struct irq_remap_table *table;
4102 struct amd_iommu *iommu;
4103 unsigned long flags;
4104
4105 iommu = amd_iommu_rlookup_table[devid];
4106 if (iommu == NULL)
4107 return;
4108
4109 table = get_irq_table(devid, false);
4110 if (!table)
4111 return;
4112
4113 spin_lock_irqsave(&table->lock, flags);
4114 table->table[index] = 0;
4115 spin_unlock_irqrestore(&table->lock, flags);
4116
4117 iommu_flush_irt(iommu, devid);
4118 iommu_completion_wait(iommu);
4119 }
4120
4121 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4122 unsigned int destination, int vector,
4123 struct io_apic_irq_attr *attr)
4124 {
4125 struct irq_remap_table *table;
4126 struct irq_2_irte *irte_info;
4127 struct irq_cfg *cfg;
4128 union irte irte;
4129 int ioapic_id;
4130 int index;
4131 int devid;
4132 int ret;
4133
4134 cfg = irq_get_chip_data(irq);
4135 if (!cfg)
4136 return -EINVAL;
4137
4138 irte_info = &cfg->irq_2_irte;
4139 ioapic_id = mpc_ioapic_id(attr->ioapic);
4140 devid = get_ioapic_devid(ioapic_id);
4141
4142 if (devid < 0)
4143 return devid;
4144
4145 table = get_irq_table(devid, true);
4146 if (table == NULL)
4147 return -ENOMEM;
4148
4149 index = attr->ioapic_pin;
4150
4151 /* Setup IRQ remapping info */
4152 cfg->remapped = 1;
4153 irte_info->devid = devid;
4154 irte_info->index = index;
4155
4156 /* Setup IRTE for IOMMU */
4157 irte.val = 0;
4158 irte.fields.vector = vector;
4159 irte.fields.int_type = apic->irq_delivery_mode;
4160 irte.fields.destination = destination;
4161 irte.fields.dm = apic->irq_dest_mode;
4162 irte.fields.valid = 1;
4163
4164 ret = modify_irte(devid, index, irte);
4165 if (ret)
4166 return ret;
4167
4168 /* Setup IOAPIC entry */
4169 memset(entry, 0, sizeof(*entry));
4170
4171 entry->vector = index;
4172 entry->mask = 0;
4173 entry->trigger = attr->trigger;
4174 entry->polarity = attr->polarity;
4175
4176 /*
4177 * Mask level triggered irqs.
4178 */
4179 if (attr->trigger)
4180 entry->mask = 1;
4181
4182 return 0;
4183 }
4184
4185 static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4186 bool force)
4187 {
4188 struct irq_2_irte *irte_info;
4189 unsigned int dest, irq;
4190 struct irq_cfg *cfg;
4191 union irte irte;
4192 int err;
4193
4194 if (!config_enabled(CONFIG_SMP))
4195 return -1;
4196
4197 cfg = data->chip_data;
4198 irq = data->irq;
4199 irte_info = &cfg->irq_2_irte;
4200
4201 if (!cpumask_intersects(mask, cpu_online_mask))
4202 return -EINVAL;
4203
4204 if (get_irte(irte_info->devid, irte_info->index, &irte))
4205 return -EBUSY;
4206
4207 if (assign_irq_vector(irq, cfg, mask))
4208 return -EBUSY;
4209
4210 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
4211 if (err) {
4212 if (assign_irq_vector(irq, cfg, data->affinity))
4213 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
4214 return err;
4215 }
4216
4217 irte.fields.vector = cfg->vector;
4218 irte.fields.destination = dest;
4219
4220 modify_irte(irte_info->devid, irte_info->index, irte);
4221
4222 if (cfg->move_in_progress)
4223 send_cleanup_vector(cfg);
4224
4225 cpumask_copy(data->affinity, mask);
4226
4227 return 0;
4228 }
4229
4230 static int free_irq(int irq)
4231 {
4232 struct irq_2_irte *irte_info;
4233 struct irq_cfg *cfg;
4234
4235 cfg = irq_get_chip_data(irq);
4236 if (!cfg)
4237 return -EINVAL;
4238
4239 irte_info = &cfg->irq_2_irte;
4240
4241 free_irte(irte_info->devid, irte_info->index);
4242
4243 return 0;
4244 }
4245
4246 static void compose_msi_msg(struct pci_dev *pdev,
4247 unsigned int irq, unsigned int dest,
4248 struct msi_msg *msg, u8 hpet_id)
4249 {
4250 struct irq_2_irte *irte_info;
4251 struct irq_cfg *cfg;
4252 union irte irte;
4253
4254 cfg = irq_get_chip_data(irq);
4255 if (!cfg)
4256 return;
4257
4258 irte_info = &cfg->irq_2_irte;
4259
4260 irte.val = 0;
4261 irte.fields.vector = cfg->vector;
4262 irte.fields.int_type = apic->irq_delivery_mode;
4263 irte.fields.destination = dest;
4264 irte.fields.dm = apic->irq_dest_mode;
4265 irte.fields.valid = 1;
4266
4267 modify_irte(irte_info->devid, irte_info->index, irte);
4268
4269 msg->address_hi = MSI_ADDR_BASE_HI;
4270 msg->address_lo = MSI_ADDR_BASE_LO;
4271 msg->data = irte_info->index;
4272 }
4273
4274 static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
4275 {
4276 struct irq_cfg *cfg;
4277 int index;
4278 u16 devid;
4279
4280 if (!pdev)
4281 return -EINVAL;
4282
4283 cfg = irq_get_chip_data(irq);
4284 if (!cfg)
4285 return -EINVAL;
4286
4287 devid = get_device_id(&pdev->dev);
4288 index = alloc_irq_index(cfg, devid, nvec);
4289
4290 return index < 0 ? MAX_IRQS_PER_TABLE : index;
4291 }
4292
4293 static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4294 int index, int offset)
4295 {
4296 struct irq_2_irte *irte_info;
4297 struct irq_cfg *cfg;
4298 u16 devid;
4299
4300 if (!pdev)
4301 return -EINVAL;
4302
4303 cfg = irq_get_chip_data(irq);
4304 if (!cfg)
4305 return -EINVAL;
4306
4307 if (index >= MAX_IRQS_PER_TABLE)
4308 return 0;
4309
4310 devid = get_device_id(&pdev->dev);
4311 irte_info = &cfg->irq_2_irte;
4312
4313 cfg->remapped = 1;
4314 irte_info->devid = devid;
4315 irte_info->index = index + offset;
4316
4317 return 0;
4318 }
4319
4320 static int setup_hpet_msi(unsigned int irq, unsigned int id)
4321 {
4322 struct irq_2_irte *irte_info;
4323 struct irq_cfg *cfg;
4324 int index, devid;
4325
4326 cfg = irq_get_chip_data(irq);
4327 if (!cfg)
4328 return -EINVAL;
4329
4330 irte_info = &cfg->irq_2_irte;
4331 devid = get_hpet_devid(id);
4332 if (devid < 0)
4333 return devid;
4334
4335 index = alloc_irq_index(cfg, devid, 1);
4336 if (index < 0)
4337 return index;
4338
4339 cfg->remapped = 1;
4340 irte_info->devid = devid;
4341 irte_info->index = index;
4342
4343 return 0;
4344 }
4345
4346 struct irq_remap_ops amd_iommu_irq_ops = {
4347 .supported = amd_iommu_supported,
4348 .prepare = amd_iommu_prepare,
4349 .enable = amd_iommu_enable,
4350 .disable = amd_iommu_disable,
4351 .reenable = amd_iommu_reenable,
4352 .enable_faulting = amd_iommu_enable_faulting,
4353 .setup_ioapic_entry = setup_ioapic_entry,
4354 .set_affinity = set_affinity,
4355 .free_irq = free_irq,
4356 .compose_msi_msg = compose_msi_msg,
4357 .msi_alloc_irq = msi_alloc_irq,
4358 .msi_setup_irq = msi_setup_irq,
4359 .setup_hpet_msi = setup_hpet_msi,
4360 };
4361 #endif
Linux kernel - Deliverables
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