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cedbf004c8ef93020ef69568ee4d797d0c589bb9
[deliverable/linux.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <linux/dma-contiguous.h>
37 #include <asm/irq_remapping.h>
38 #include <asm/io_apic.h>
39 #include <asm/apic.h>
40 #include <asm/hw_irq.h>
41 #include <asm/msidef.h>
42 #include <asm/proto.h>
43 #include <asm/iommu.h>
44 #include <asm/gart.h>
45 #include <asm/dma.h>
46
47 #include "amd_iommu_proto.h"
48 #include "amd_iommu_types.h"
49 #include "irq_remapping.h"
50
51 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
52
53 #define LOOP_TIMEOUT 100000
54
55 /*
56 * This bitmap is used to advertise the page sizes our hardware support
57 * to the IOMMU core, which will then use this information to split
58 * physically contiguous memory regions it is mapping into page sizes
59 * that we support.
60 *
61 * 512GB Pages are not supported due to a hardware bug
62 */
63 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
64
65 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
66
67 /* List of all available dev_data structures */
68 static LIST_HEAD(dev_data_list);
69 static DEFINE_SPINLOCK(dev_data_list_lock);
70
71 LIST_HEAD(ioapic_map);
72 LIST_HEAD(hpet_map);
73
74 /*
75 * Domain for untranslated devices - only allocated
76 * if iommu=pt passed on kernel cmd line.
77 */
78 static struct protection_domain *pt_domain;
79
80 static const struct iommu_ops amd_iommu_ops;
81
82 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
83 int amd_iommu_max_glx_val = -1;
84
85 static struct dma_map_ops amd_iommu_dma_ops;
86
87 /*
88 * This struct contains device specific data for the IOMMU
89 */
90 struct iommu_dev_data {
91 struct list_head list; /* For domain->dev_list */
92 struct list_head dev_data_list; /* For global dev_data_list */
93 struct list_head alias_list; /* Link alias-groups together */
94 struct iommu_dev_data *alias_data;/* The alias dev_data */
95 struct protection_domain *domain; /* Domain the device is bound to */
96 u16 devid; /* PCI Device ID */
97 bool iommu_v2; /* Device can make use of IOMMUv2 */
98 bool passthrough; /* Default for device is pt_domain */
99 struct {
100 bool enabled;
101 int qdep;
102 } ats; /* ATS state */
103 bool pri_tlp; /* PASID TLB required for
104 PPR completions */
105 u32 errata; /* Bitmap for errata to apply */
106 };
107
108 /*
109 * general struct to manage commands send to an IOMMU
110 */
111 struct iommu_cmd {
112 u32 data[4];
113 };
114
115 struct kmem_cache *amd_iommu_irq_cache;
116
117 static void update_domain(struct protection_domain *domain);
118 static int alloc_passthrough_domain(void);
119 static int protection_domain_init(struct protection_domain *domain);
120
121 /****************************************************************************
122 *
123 * Helper functions
124 *
125 ****************************************************************************/
126
127 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
128 {
129 return container_of(dom, struct protection_domain, domain);
130 }
131
132 static struct iommu_dev_data *alloc_dev_data(u16 devid)
133 {
134 struct iommu_dev_data *dev_data;
135 unsigned long flags;
136
137 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
138 if (!dev_data)
139 return NULL;
140
141 INIT_LIST_HEAD(&dev_data->alias_list);
142
143 dev_data->devid = devid;
144
145 spin_lock_irqsave(&dev_data_list_lock, flags);
146 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
147 spin_unlock_irqrestore(&dev_data_list_lock, flags);
148
149 return dev_data;
150 }
151
152 static void free_dev_data(struct iommu_dev_data *dev_data)
153 {
154 unsigned long flags;
155
156 spin_lock_irqsave(&dev_data_list_lock, flags);
157 list_del(&dev_data->dev_data_list);
158 spin_unlock_irqrestore(&dev_data_list_lock, flags);
159
160 kfree(dev_data);
161 }
162
163 static struct iommu_dev_data *search_dev_data(u16 devid)
164 {
165 struct iommu_dev_data *dev_data;
166 unsigned long flags;
167
168 spin_lock_irqsave(&dev_data_list_lock, flags);
169 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
170 if (dev_data->devid == devid)
171 goto out_unlock;
172 }
173
174 dev_data = NULL;
175
176 out_unlock:
177 spin_unlock_irqrestore(&dev_data_list_lock, flags);
178
179 return dev_data;
180 }
181
182 static struct iommu_dev_data *find_dev_data(u16 devid)
183 {
184 struct iommu_dev_data *dev_data;
185
186 dev_data = search_dev_data(devid);
187
188 if (dev_data == NULL)
189 dev_data = alloc_dev_data(devid);
190
191 return dev_data;
192 }
193
194 static inline u16 get_device_id(struct device *dev)
195 {
196 struct pci_dev *pdev = to_pci_dev(dev);
197
198 return PCI_DEVID(pdev->bus->number, pdev->devfn);
199 }
200
201 static struct iommu_dev_data *get_dev_data(struct device *dev)
202 {
203 return dev->archdata.iommu;
204 }
205
206 static bool pci_iommuv2_capable(struct pci_dev *pdev)
207 {
208 static const int caps[] = {
209 PCI_EXT_CAP_ID_ATS,
210 PCI_EXT_CAP_ID_PRI,
211 PCI_EXT_CAP_ID_PASID,
212 };
213 int i, pos;
214
215 for (i = 0; i < 3; ++i) {
216 pos = pci_find_ext_capability(pdev, caps[i]);
217 if (pos == 0)
218 return false;
219 }
220
221 return true;
222 }
223
224 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
225 {
226 struct iommu_dev_data *dev_data;
227
228 dev_data = get_dev_data(&pdev->dev);
229
230 return dev_data->errata & (1 << erratum) ? true : false;
231 }
232
233 /*
234 * This function actually applies the mapping to the page table of the
235 * dma_ops domain.
236 */
237 static void alloc_unity_mapping(struct dma_ops_domain *dma_dom,
238 struct unity_map_entry *e)
239 {
240 u64 addr;
241
242 for (addr = e->address_start; addr < e->address_end;
243 addr += PAGE_SIZE) {
244 if (addr < dma_dom->aperture_size)
245 __set_bit(addr >> PAGE_SHIFT,
246 dma_dom->aperture[0]->bitmap);
247 }
248 }
249
250 /*
251 * Inits the unity mappings required for a specific device
252 */
253 static void init_unity_mappings_for_device(struct device *dev,
254 struct dma_ops_domain *dma_dom)
255 {
256 struct unity_map_entry *e;
257 u16 devid;
258
259 devid = get_device_id(dev);
260
261 list_for_each_entry(e, &amd_iommu_unity_map, list) {
262 if (!(devid >= e->devid_start && devid <= e->devid_end))
263 continue;
264 alloc_unity_mapping(dma_dom, e);
265 }
266 }
267
268 /*
269 * This function checks if the driver got a valid device from the caller to
270 * avoid dereferencing invalid pointers.
271 */
272 static bool check_device(struct device *dev)
273 {
274 u16 devid;
275
276 if (!dev || !dev->dma_mask)
277 return false;
278
279 /* No PCI device */
280 if (!dev_is_pci(dev))
281 return false;
282
283 devid = get_device_id(dev);
284
285 /* Out of our scope? */
286 if (devid > amd_iommu_last_bdf)
287 return false;
288
289 if (amd_iommu_rlookup_table[devid] == NULL)
290 return false;
291
292 return true;
293 }
294
295 static void init_iommu_group(struct device *dev)
296 {
297 struct dma_ops_domain *dma_domain;
298 struct iommu_domain *domain;
299 struct iommu_group *group;
300
301 group = iommu_group_get_for_dev(dev);
302 if (IS_ERR(group))
303 return;
304
305 domain = iommu_group_default_domain(group);
306 if (!domain)
307 goto out;
308
309 dma_domain = to_pdomain(domain)->priv;
310
311 init_unity_mappings_for_device(dev, dma_domain);
312 out:
313 iommu_group_put(group);
314 }
315
316 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
317 {
318 *(u16 *)data = alias;
319 return 0;
320 }
321
322 static u16 get_alias(struct device *dev)
323 {
324 struct pci_dev *pdev = to_pci_dev(dev);
325 u16 devid, ivrs_alias, pci_alias;
326
327 devid = get_device_id(dev);
328 ivrs_alias = amd_iommu_alias_table[devid];
329 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
330
331 if (ivrs_alias == pci_alias)
332 return ivrs_alias;
333
334 /*
335 * DMA alias showdown
336 *
337 * The IVRS is fairly reliable in telling us about aliases, but it
338 * can't know about every screwy device. If we don't have an IVRS
339 * reported alias, use the PCI reported alias. In that case we may
340 * still need to initialize the rlookup and dev_table entries if the
341 * alias is to a non-existent device.
342 */
343 if (ivrs_alias == devid) {
344 if (!amd_iommu_rlookup_table[pci_alias]) {
345 amd_iommu_rlookup_table[pci_alias] =
346 amd_iommu_rlookup_table[devid];
347 memcpy(amd_iommu_dev_table[pci_alias].data,
348 amd_iommu_dev_table[devid].data,
349 sizeof(amd_iommu_dev_table[pci_alias].data));
350 }
351
352 return pci_alias;
353 }
354
355 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
356 "for device %s[%04x:%04x], kernel reported alias "
357 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
358 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
359 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
360 PCI_FUNC(pci_alias));
361
362 /*
363 * If we don't have a PCI DMA alias and the IVRS alias is on the same
364 * bus, then the IVRS table may know about a quirk that we don't.
365 */
366 if (pci_alias == devid &&
367 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
368 pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
369 pdev->dma_alias_devfn = ivrs_alias & 0xff;
370 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
371 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
372 dev_name(dev));
373 }
374
375 return ivrs_alias;
376 }
377
378 static int iommu_init_device(struct device *dev)
379 {
380 struct pci_dev *pdev = to_pci_dev(dev);
381 struct iommu_dev_data *dev_data;
382 u16 alias;
383
384 if (dev->archdata.iommu)
385 return 0;
386
387 dev_data = find_dev_data(get_device_id(dev));
388 if (!dev_data)
389 return -ENOMEM;
390
391 alias = get_alias(dev);
392
393 if (alias != dev_data->devid) {
394 struct iommu_dev_data *alias_data;
395
396 alias_data = find_dev_data(alias);
397 if (alias_data == NULL) {
398 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
399 dev_name(dev));
400 free_dev_data(dev_data);
401 return -ENOTSUPP;
402 }
403 dev_data->alias_data = alias_data;
404
405 /* Add device to the alias_list */
406 list_add(&dev_data->alias_list, &alias_data->alias_list);
407 }
408
409 if (pci_iommuv2_capable(pdev)) {
410 struct amd_iommu *iommu;
411
412 iommu = amd_iommu_rlookup_table[dev_data->devid];
413 dev_data->iommu_v2 = iommu->is_iommu_v2;
414 }
415
416 dev->archdata.iommu = dev_data;
417
418 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
419 dev);
420
421 return 0;
422 }
423
424 static void iommu_ignore_device(struct device *dev)
425 {
426 u16 devid, alias;
427
428 devid = get_device_id(dev);
429 alias = amd_iommu_alias_table[devid];
430
431 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
432 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
433
434 amd_iommu_rlookup_table[devid] = NULL;
435 amd_iommu_rlookup_table[alias] = NULL;
436 }
437
438 static void iommu_uninit_device(struct device *dev)
439 {
440 struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev));
441
442 if (!dev_data)
443 return;
444
445 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
446 dev);
447
448 iommu_group_remove_device(dev);
449
450 /* Unlink from alias, it may change if another device is re-plugged */
451 dev_data->alias_data = NULL;
452
453 /* Remove dma-ops */
454 dev->archdata.dma_ops = NULL;
455
456 /*
457 * We keep dev_data around for unplugged devices and reuse it when the
458 * device is re-plugged - not doing so would introduce a ton of races.
459 */
460 }
461
462 #ifdef CONFIG_AMD_IOMMU_STATS
463
464 /*
465 * Initialization code for statistics collection
466 */
467
468 DECLARE_STATS_COUNTER(compl_wait);
469 DECLARE_STATS_COUNTER(cnt_map_single);
470 DECLARE_STATS_COUNTER(cnt_unmap_single);
471 DECLARE_STATS_COUNTER(cnt_map_sg);
472 DECLARE_STATS_COUNTER(cnt_unmap_sg);
473 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
474 DECLARE_STATS_COUNTER(cnt_free_coherent);
475 DECLARE_STATS_COUNTER(cross_page);
476 DECLARE_STATS_COUNTER(domain_flush_single);
477 DECLARE_STATS_COUNTER(domain_flush_all);
478 DECLARE_STATS_COUNTER(alloced_io_mem);
479 DECLARE_STATS_COUNTER(total_map_requests);
480 DECLARE_STATS_COUNTER(complete_ppr);
481 DECLARE_STATS_COUNTER(invalidate_iotlb);
482 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
483 DECLARE_STATS_COUNTER(pri_requests);
484
485 static struct dentry *stats_dir;
486 static struct dentry *de_fflush;
487
488 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
489 {
490 if (stats_dir == NULL)
491 return;
492
493 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
494 &cnt->value);
495 }
496
497 static void amd_iommu_stats_init(void)
498 {
499 stats_dir = debugfs_create_dir("amd-iommu", NULL);
500 if (stats_dir == NULL)
501 return;
502
503 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
504 &amd_iommu_unmap_flush);
505
506 amd_iommu_stats_add(&compl_wait);
507 amd_iommu_stats_add(&cnt_map_single);
508 amd_iommu_stats_add(&cnt_unmap_single);
509 amd_iommu_stats_add(&cnt_map_sg);
510 amd_iommu_stats_add(&cnt_unmap_sg);
511 amd_iommu_stats_add(&cnt_alloc_coherent);
512 amd_iommu_stats_add(&cnt_free_coherent);
513 amd_iommu_stats_add(&cross_page);
514 amd_iommu_stats_add(&domain_flush_single);
515 amd_iommu_stats_add(&domain_flush_all);
516 amd_iommu_stats_add(&alloced_io_mem);
517 amd_iommu_stats_add(&total_map_requests);
518 amd_iommu_stats_add(&complete_ppr);
519 amd_iommu_stats_add(&invalidate_iotlb);
520 amd_iommu_stats_add(&invalidate_iotlb_all);
521 amd_iommu_stats_add(&pri_requests);
522 }
523
524 #endif
525
526 /****************************************************************************
527 *
528 * Interrupt handling functions
529 *
530 ****************************************************************************/
531
532 static void dump_dte_entry(u16 devid)
533 {
534 int i;
535
536 for (i = 0; i < 4; ++i)
537 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
538 amd_iommu_dev_table[devid].data[i]);
539 }
540
541 static void dump_command(unsigned long phys_addr)
542 {
543 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
544 int i;
545
546 for (i = 0; i < 4; ++i)
547 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
548 }
549
550 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
551 {
552 int type, devid, domid, flags;
553 volatile u32 *event = __evt;
554 int count = 0;
555 u64 address;
556
557 retry:
558 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
559 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
560 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
561 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
562 address = (u64)(((u64)event[3]) << 32) | event[2];
563
564 if (type == 0) {
565 /* Did we hit the erratum? */
566 if (++count == LOOP_TIMEOUT) {
567 pr_err("AMD-Vi: No event written to event log\n");
568 return;
569 }
570 udelay(1);
571 goto retry;
572 }
573
574 printk(KERN_ERR "AMD-Vi: Event logged [");
575
576 switch (type) {
577 case EVENT_TYPE_ILL_DEV:
578 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
579 "address=0x%016llx flags=0x%04x]\n",
580 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
581 address, flags);
582 dump_dte_entry(devid);
583 break;
584 case EVENT_TYPE_IO_FAULT:
585 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
586 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
587 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
588 domid, address, flags);
589 break;
590 case EVENT_TYPE_DEV_TAB_ERR:
591 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
592 "address=0x%016llx flags=0x%04x]\n",
593 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
594 address, flags);
595 break;
596 case EVENT_TYPE_PAGE_TAB_ERR:
597 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
598 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
599 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
600 domid, address, flags);
601 break;
602 case EVENT_TYPE_ILL_CMD:
603 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
604 dump_command(address);
605 break;
606 case EVENT_TYPE_CMD_HARD_ERR:
607 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
608 "flags=0x%04x]\n", address, flags);
609 break;
610 case EVENT_TYPE_IOTLB_INV_TO:
611 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
612 "address=0x%016llx]\n",
613 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
614 address);
615 break;
616 case EVENT_TYPE_INV_DEV_REQ:
617 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
618 "address=0x%016llx flags=0x%04x]\n",
619 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
620 address, flags);
621 break;
622 default:
623 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
624 }
625
626 memset(__evt, 0, 4 * sizeof(u32));
627 }
628
629 static void iommu_poll_events(struct amd_iommu *iommu)
630 {
631 u32 head, tail;
632
633 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
634 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
635
636 while (head != tail) {
637 iommu_print_event(iommu, iommu->evt_buf + head);
638 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
639 }
640
641 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
642 }
643
644 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
645 {
646 struct amd_iommu_fault fault;
647
648 INC_STATS_COUNTER(pri_requests);
649
650 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
651 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
652 return;
653 }
654
655 fault.address = raw[1];
656 fault.pasid = PPR_PASID(raw[0]);
657 fault.device_id = PPR_DEVID(raw[0]);
658 fault.tag = PPR_TAG(raw[0]);
659 fault.flags = PPR_FLAGS(raw[0]);
660
661 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
662 }
663
664 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
665 {
666 u32 head, tail;
667
668 if (iommu->ppr_log == NULL)
669 return;
670
671 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
672 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
673
674 while (head != tail) {
675 volatile u64 *raw;
676 u64 entry[2];
677 int i;
678
679 raw = (u64 *)(iommu->ppr_log + head);
680
681 /*
682 * Hardware bug: Interrupt may arrive before the entry is
683 * written to memory. If this happens we need to wait for the
684 * entry to arrive.
685 */
686 for (i = 0; i < LOOP_TIMEOUT; ++i) {
687 if (PPR_REQ_TYPE(raw[0]) != 0)
688 break;
689 udelay(1);
690 }
691
692 /* Avoid memcpy function-call overhead */
693 entry[0] = raw[0];
694 entry[1] = raw[1];
695
696 /*
697 * To detect the hardware bug we need to clear the entry
698 * back to zero.
699 */
700 raw[0] = raw[1] = 0UL;
701
702 /* Update head pointer of hardware ring-buffer */
703 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
704 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
705
706 /* Handle PPR entry */
707 iommu_handle_ppr_entry(iommu, entry);
708
709 /* Refresh ring-buffer information */
710 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
711 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
712 }
713 }
714
715 irqreturn_t amd_iommu_int_thread(int irq, void *data)
716 {
717 struct amd_iommu *iommu = (struct amd_iommu *) data;
718 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
719
720 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
721 /* Enable EVT and PPR interrupts again */
722 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
723 iommu->mmio_base + MMIO_STATUS_OFFSET);
724
725 if (status & MMIO_STATUS_EVT_INT_MASK) {
726 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
727 iommu_poll_events(iommu);
728 }
729
730 if (status & MMIO_STATUS_PPR_INT_MASK) {
731 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
732 iommu_poll_ppr_log(iommu);
733 }
734
735 /*
736 * Hardware bug: ERBT1312
737 * When re-enabling interrupt (by writing 1
738 * to clear the bit), the hardware might also try to set
739 * the interrupt bit in the event status register.
740 * In this scenario, the bit will be set, and disable
741 * subsequent interrupts.
742 *
743 * Workaround: The IOMMU driver should read back the
744 * status register and check if the interrupt bits are cleared.
745 * If not, driver will need to go through the interrupt handler
746 * again and re-clear the bits
747 */
748 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
749 }
750 return IRQ_HANDLED;
751 }
752
753 irqreturn_t amd_iommu_int_handler(int irq, void *data)
754 {
755 return IRQ_WAKE_THREAD;
756 }
757
758 /****************************************************************************
759 *
760 * IOMMU command queuing functions
761 *
762 ****************************************************************************/
763
764 static int wait_on_sem(volatile u64 *sem)
765 {
766 int i = 0;
767
768 while (*sem == 0 && i < LOOP_TIMEOUT) {
769 udelay(1);
770 i += 1;
771 }
772
773 if (i == LOOP_TIMEOUT) {
774 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
775 return -EIO;
776 }
777
778 return 0;
779 }
780
781 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
782 struct iommu_cmd *cmd,
783 u32 tail)
784 {
785 u8 *target;
786
787 target = iommu->cmd_buf + tail;
788 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
789
790 /* Copy command to buffer */
791 memcpy(target, cmd, sizeof(*cmd));
792
793 /* Tell the IOMMU about it */
794 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
795 }
796
797 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
798 {
799 WARN_ON(address & 0x7ULL);
800
801 memset(cmd, 0, sizeof(*cmd));
802 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
803 cmd->data[1] = upper_32_bits(__pa(address));
804 cmd->data[2] = 1;
805 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
806 }
807
808 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
809 {
810 memset(cmd, 0, sizeof(*cmd));
811 cmd->data[0] = devid;
812 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
813 }
814
815 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
816 size_t size, u16 domid, int pde)
817 {
818 u64 pages;
819 bool s;
820
821 pages = iommu_num_pages(address, size, PAGE_SIZE);
822 s = false;
823
824 if (pages > 1) {
825 /*
826 * If we have to flush more than one page, flush all
827 * TLB entries for this domain
828 */
829 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
830 s = true;
831 }
832
833 address &= PAGE_MASK;
834
835 memset(cmd, 0, sizeof(*cmd));
836 cmd->data[1] |= domid;
837 cmd->data[2] = lower_32_bits(address);
838 cmd->data[3] = upper_32_bits(address);
839 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
840 if (s) /* size bit - we flush more than one 4kb page */
841 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
842 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
843 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
844 }
845
846 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
847 u64 address, size_t size)
848 {
849 u64 pages;
850 bool s;
851
852 pages = iommu_num_pages(address, size, PAGE_SIZE);
853 s = false;
854
855 if (pages > 1) {
856 /*
857 * If we have to flush more than one page, flush all
858 * TLB entries for this domain
859 */
860 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
861 s = true;
862 }
863
864 address &= PAGE_MASK;
865
866 memset(cmd, 0, sizeof(*cmd));
867 cmd->data[0] = devid;
868 cmd->data[0] |= (qdep & 0xff) << 24;
869 cmd->data[1] = devid;
870 cmd->data[2] = lower_32_bits(address);
871 cmd->data[3] = upper_32_bits(address);
872 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
873 if (s)
874 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
875 }
876
877 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
878 u64 address, bool size)
879 {
880 memset(cmd, 0, sizeof(*cmd));
881
882 address &= ~(0xfffULL);
883
884 cmd->data[0] = pasid;
885 cmd->data[1] = domid;
886 cmd->data[2] = lower_32_bits(address);
887 cmd->data[3] = upper_32_bits(address);
888 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
889 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
890 if (size)
891 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
892 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
893 }
894
895 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
896 int qdep, u64 address, bool size)
897 {
898 memset(cmd, 0, sizeof(*cmd));
899
900 address &= ~(0xfffULL);
901
902 cmd->data[0] = devid;
903 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
904 cmd->data[0] |= (qdep & 0xff) << 24;
905 cmd->data[1] = devid;
906 cmd->data[1] |= (pasid & 0xff) << 16;
907 cmd->data[2] = lower_32_bits(address);
908 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
909 cmd->data[3] = upper_32_bits(address);
910 if (size)
911 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
912 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
913 }
914
915 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
916 int status, int tag, bool gn)
917 {
918 memset(cmd, 0, sizeof(*cmd));
919
920 cmd->data[0] = devid;
921 if (gn) {
922 cmd->data[1] = pasid;
923 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
924 }
925 cmd->data[3] = tag & 0x1ff;
926 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
927
928 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
929 }
930
931 static void build_inv_all(struct iommu_cmd *cmd)
932 {
933 memset(cmd, 0, sizeof(*cmd));
934 CMD_SET_TYPE(cmd, CMD_INV_ALL);
935 }
936
937 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
938 {
939 memset(cmd, 0, sizeof(*cmd));
940 cmd->data[0] = devid;
941 CMD_SET_TYPE(cmd, CMD_INV_IRT);
942 }
943
944 /*
945 * Writes the command to the IOMMUs command buffer and informs the
946 * hardware about the new command.
947 */
948 static int iommu_queue_command_sync(struct amd_iommu *iommu,
949 struct iommu_cmd *cmd,
950 bool sync)
951 {
952 u32 left, tail, head, next_tail;
953 unsigned long flags;
954
955 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
956
957 again:
958 spin_lock_irqsave(&iommu->lock, flags);
959
960 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
961 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
962 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
963 left = (head - next_tail) % iommu->cmd_buf_size;
964
965 if (left <= 2) {
966 struct iommu_cmd sync_cmd;
967 volatile u64 sem = 0;
968 int ret;
969
970 build_completion_wait(&sync_cmd, (u64)&sem);
971 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
972
973 spin_unlock_irqrestore(&iommu->lock, flags);
974
975 if ((ret = wait_on_sem(&sem)) != 0)
976 return ret;
977
978 goto again;
979 }
980
981 copy_cmd_to_buffer(iommu, cmd, tail);
982
983 /* We need to sync now to make sure all commands are processed */
984 iommu->need_sync = sync;
985
986 spin_unlock_irqrestore(&iommu->lock, flags);
987
988 return 0;
989 }
990
991 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
992 {
993 return iommu_queue_command_sync(iommu, cmd, true);
994 }
995
996 /*
997 * This function queues a completion wait command into the command
998 * buffer of an IOMMU
999 */
1000 static int iommu_completion_wait(struct amd_iommu *iommu)
1001 {
1002 struct iommu_cmd cmd;
1003 volatile u64 sem = 0;
1004 int ret;
1005
1006 if (!iommu->need_sync)
1007 return 0;
1008
1009 build_completion_wait(&cmd, (u64)&sem);
1010
1011 ret = iommu_queue_command_sync(iommu, &cmd, false);
1012 if (ret)
1013 return ret;
1014
1015 return wait_on_sem(&sem);
1016 }
1017
1018 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1019 {
1020 struct iommu_cmd cmd;
1021
1022 build_inv_dte(&cmd, devid);
1023
1024 return iommu_queue_command(iommu, &cmd);
1025 }
1026
1027 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1028 {
1029 u32 devid;
1030
1031 for (devid = 0; devid <= 0xffff; ++devid)
1032 iommu_flush_dte(iommu, devid);
1033
1034 iommu_completion_wait(iommu);
1035 }
1036
1037 /*
1038 * This function uses heavy locking and may disable irqs for some time. But
1039 * this is no issue because it is only called during resume.
1040 */
1041 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1042 {
1043 u32 dom_id;
1044
1045 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1046 struct iommu_cmd cmd;
1047 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1048 dom_id, 1);
1049 iommu_queue_command(iommu, &cmd);
1050 }
1051
1052 iommu_completion_wait(iommu);
1053 }
1054
1055 static void iommu_flush_all(struct amd_iommu *iommu)
1056 {
1057 struct iommu_cmd cmd;
1058
1059 build_inv_all(&cmd);
1060
1061 iommu_queue_command(iommu, &cmd);
1062 iommu_completion_wait(iommu);
1063 }
1064
1065 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1066 {
1067 struct iommu_cmd cmd;
1068
1069 build_inv_irt(&cmd, devid);
1070
1071 iommu_queue_command(iommu, &cmd);
1072 }
1073
1074 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1075 {
1076 u32 devid;
1077
1078 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1079 iommu_flush_irt(iommu, devid);
1080
1081 iommu_completion_wait(iommu);
1082 }
1083
1084 void iommu_flush_all_caches(struct amd_iommu *iommu)
1085 {
1086 if (iommu_feature(iommu, FEATURE_IA)) {
1087 iommu_flush_all(iommu);
1088 } else {
1089 iommu_flush_dte_all(iommu);
1090 iommu_flush_irt_all(iommu);
1091 iommu_flush_tlb_all(iommu);
1092 }
1093 }
1094
1095 /*
1096 * Command send function for flushing on-device TLB
1097 */
1098 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1099 u64 address, size_t size)
1100 {
1101 struct amd_iommu *iommu;
1102 struct iommu_cmd cmd;
1103 int qdep;
1104
1105 qdep = dev_data->ats.qdep;
1106 iommu = amd_iommu_rlookup_table[dev_data->devid];
1107
1108 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1109
1110 return iommu_queue_command(iommu, &cmd);
1111 }
1112
1113 /*
1114 * Command send function for invalidating a device table entry
1115 */
1116 static int device_flush_dte(struct iommu_dev_data *dev_data)
1117 {
1118 struct amd_iommu *iommu;
1119 int ret;
1120
1121 iommu = amd_iommu_rlookup_table[dev_data->devid];
1122
1123 ret = iommu_flush_dte(iommu, dev_data->devid);
1124 if (ret)
1125 return ret;
1126
1127 if (dev_data->ats.enabled)
1128 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1129
1130 return ret;
1131 }
1132
1133 /*
1134 * TLB invalidation function which is called from the mapping functions.
1135 * It invalidates a single PTE if the range to flush is within a single
1136 * page. Otherwise it flushes the whole TLB of the IOMMU.
1137 */
1138 static void __domain_flush_pages(struct protection_domain *domain,
1139 u64 address, size_t size, int pde)
1140 {
1141 struct iommu_dev_data *dev_data;
1142 struct iommu_cmd cmd;
1143 int ret = 0, i;
1144
1145 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1146
1147 for (i = 0; i < amd_iommus_present; ++i) {
1148 if (!domain->dev_iommu[i])
1149 continue;
1150
1151 /*
1152 * Devices of this domain are behind this IOMMU
1153 * We need a TLB flush
1154 */
1155 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1156 }
1157
1158 list_for_each_entry(dev_data, &domain->dev_list, list) {
1159
1160 if (!dev_data->ats.enabled)
1161 continue;
1162
1163 ret |= device_flush_iotlb(dev_data, address, size);
1164 }
1165
1166 WARN_ON(ret);
1167 }
1168
1169 static void domain_flush_pages(struct protection_domain *domain,
1170 u64 address, size_t size)
1171 {
1172 __domain_flush_pages(domain, address, size, 0);
1173 }
1174
1175 /* Flush the whole IO/TLB for a given protection domain */
1176 static void domain_flush_tlb(struct protection_domain *domain)
1177 {
1178 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1179 }
1180
1181 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1182 static void domain_flush_tlb_pde(struct protection_domain *domain)
1183 {
1184 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1185 }
1186
1187 static void domain_flush_complete(struct protection_domain *domain)
1188 {
1189 int i;
1190
1191 for (i = 0; i < amd_iommus_present; ++i) {
1192 if (!domain->dev_iommu[i])
1193 continue;
1194
1195 /*
1196 * Devices of this domain are behind this IOMMU
1197 * We need to wait for completion of all commands.
1198 */
1199 iommu_completion_wait(amd_iommus[i]);
1200 }
1201 }
1202
1203
1204 /*
1205 * This function flushes the DTEs for all devices in domain
1206 */
1207 static void domain_flush_devices(struct protection_domain *domain)
1208 {
1209 struct iommu_dev_data *dev_data;
1210
1211 list_for_each_entry(dev_data, &domain->dev_list, list)
1212 device_flush_dte(dev_data);
1213 }
1214
1215 /****************************************************************************
1216 *
1217 * The functions below are used the create the page table mappings for
1218 * unity mapped regions.
1219 *
1220 ****************************************************************************/
1221
1222 /*
1223 * This function is used to add another level to an IO page table. Adding
1224 * another level increases the size of the address space by 9 bits to a size up
1225 * to 64 bits.
1226 */
1227 static bool increase_address_space(struct protection_domain *domain,
1228 gfp_t gfp)
1229 {
1230 u64 *pte;
1231
1232 if (domain->mode == PAGE_MODE_6_LEVEL)
1233 /* address space already 64 bit large */
1234 return false;
1235
1236 pte = (void *)get_zeroed_page(gfp);
1237 if (!pte)
1238 return false;
1239
1240 *pte = PM_LEVEL_PDE(domain->mode,
1241 virt_to_phys(domain->pt_root));
1242 domain->pt_root = pte;
1243 domain->mode += 1;
1244 domain->updated = true;
1245
1246 return true;
1247 }
1248
1249 static u64 *alloc_pte(struct protection_domain *domain,
1250 unsigned long address,
1251 unsigned long page_size,
1252 u64 **pte_page,
1253 gfp_t gfp)
1254 {
1255 int level, end_lvl;
1256 u64 *pte, *page;
1257
1258 BUG_ON(!is_power_of_2(page_size));
1259
1260 while (address > PM_LEVEL_SIZE(domain->mode))
1261 increase_address_space(domain, gfp);
1262
1263 level = domain->mode - 1;
1264 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1265 address = PAGE_SIZE_ALIGN(address, page_size);
1266 end_lvl = PAGE_SIZE_LEVEL(page_size);
1267
1268 while (level > end_lvl) {
1269 if (!IOMMU_PTE_PRESENT(*pte)) {
1270 page = (u64 *)get_zeroed_page(gfp);
1271 if (!page)
1272 return NULL;
1273 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1274 }
1275
1276 /* No level skipping support yet */
1277 if (PM_PTE_LEVEL(*pte) != level)
1278 return NULL;
1279
1280 level -= 1;
1281
1282 pte = IOMMU_PTE_PAGE(*pte);
1283
1284 if (pte_page && level == end_lvl)
1285 *pte_page = pte;
1286
1287 pte = &pte[PM_LEVEL_INDEX(level, address)];
1288 }
1289
1290 return pte;
1291 }
1292
1293 /*
1294 * This function checks if there is a PTE for a given dma address. If
1295 * there is one, it returns the pointer to it.
1296 */
1297 static u64 *fetch_pte(struct protection_domain *domain,
1298 unsigned long address,
1299 unsigned long *page_size)
1300 {
1301 int level;
1302 u64 *pte;
1303
1304 if (address > PM_LEVEL_SIZE(domain->mode))
1305 return NULL;
1306
1307 level = domain->mode - 1;
1308 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1309 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1310
1311 while (level > 0) {
1312
1313 /* Not Present */
1314 if (!IOMMU_PTE_PRESENT(*pte))
1315 return NULL;
1316
1317 /* Large PTE */
1318 if (PM_PTE_LEVEL(*pte) == 7 ||
1319 PM_PTE_LEVEL(*pte) == 0)
1320 break;
1321
1322 /* No level skipping support yet */
1323 if (PM_PTE_LEVEL(*pte) != level)
1324 return NULL;
1325
1326 level -= 1;
1327
1328 /* Walk to the next level */
1329 pte = IOMMU_PTE_PAGE(*pte);
1330 pte = &pte[PM_LEVEL_INDEX(level, address)];
1331 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1332 }
1333
1334 if (PM_PTE_LEVEL(*pte) == 0x07) {
1335 unsigned long pte_mask;
1336
1337 /*
1338 * If we have a series of large PTEs, make
1339 * sure to return a pointer to the first one.
1340 */
1341 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1342 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1343 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1344 }
1345
1346 return pte;
1347 }
1348
1349 /*
1350 * Generic mapping functions. It maps a physical address into a DMA
1351 * address space. It allocates the page table pages if necessary.
1352 * In the future it can be extended to a generic mapping function
1353 * supporting all features of AMD IOMMU page tables like level skipping
1354 * and full 64 bit address spaces.
1355 */
1356 static int iommu_map_page(struct protection_domain *dom,
1357 unsigned long bus_addr,
1358 unsigned long phys_addr,
1359 int prot,
1360 unsigned long page_size)
1361 {
1362 u64 __pte, *pte;
1363 int i, count;
1364
1365 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1366 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1367
1368 if (!(prot & IOMMU_PROT_MASK))
1369 return -EINVAL;
1370
1371 count = PAGE_SIZE_PTE_COUNT(page_size);
1372 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1373
1374 if (!pte)
1375 return -ENOMEM;
1376
1377 for (i = 0; i < count; ++i)
1378 if (IOMMU_PTE_PRESENT(pte[i]))
1379 return -EBUSY;
1380
1381 if (count > 1) {
1382 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1383 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1384 } else
1385 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1386
1387 if (prot & IOMMU_PROT_IR)
1388 __pte |= IOMMU_PTE_IR;
1389 if (prot & IOMMU_PROT_IW)
1390 __pte |= IOMMU_PTE_IW;
1391
1392 for (i = 0; i < count; ++i)
1393 pte[i] = __pte;
1394
1395 update_domain(dom);
1396
1397 return 0;
1398 }
1399
1400 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1401 unsigned long bus_addr,
1402 unsigned long page_size)
1403 {
1404 unsigned long long unmapped;
1405 unsigned long unmap_size;
1406 u64 *pte;
1407
1408 BUG_ON(!is_power_of_2(page_size));
1409
1410 unmapped = 0;
1411
1412 while (unmapped < page_size) {
1413
1414 pte = fetch_pte(dom, bus_addr, &unmap_size);
1415
1416 if (pte) {
1417 int i, count;
1418
1419 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1420 for (i = 0; i < count; i++)
1421 pte[i] = 0ULL;
1422 }
1423
1424 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1425 unmapped += unmap_size;
1426 }
1427
1428 BUG_ON(unmapped && !is_power_of_2(unmapped));
1429
1430 return unmapped;
1431 }
1432
1433 /****************************************************************************
1434 *
1435 * The next functions belong to the address allocator for the dma_ops
1436 * interface functions. They work like the allocators in the other IOMMU
1437 * drivers. Its basically a bitmap which marks the allocated pages in
1438 * the aperture. Maybe it could be enhanced in the future to a more
1439 * efficient allocator.
1440 *
1441 ****************************************************************************/
1442
1443 /*
1444 * The address allocator core functions.
1445 *
1446 * called with domain->lock held
1447 */
1448
1449 /*
1450 * Used to reserve address ranges in the aperture (e.g. for exclusion
1451 * ranges.
1452 */
1453 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1454 unsigned long start_page,
1455 unsigned int pages)
1456 {
1457 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1458
1459 if (start_page + pages > last_page)
1460 pages = last_page - start_page;
1461
1462 for (i = start_page; i < start_page + pages; ++i) {
1463 int index = i / APERTURE_RANGE_PAGES;
1464 int page = i % APERTURE_RANGE_PAGES;
1465 __set_bit(page, dom->aperture[index]->bitmap);
1466 }
1467 }
1468
1469 /*
1470 * This function is used to add a new aperture range to an existing
1471 * aperture in case of dma_ops domain allocation or address allocation
1472 * failure.
1473 */
1474 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1475 bool populate, gfp_t gfp)
1476 {
1477 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1478 struct amd_iommu *iommu;
1479 unsigned long i, old_size, pte_pgsize;
1480
1481 #ifdef CONFIG_IOMMU_STRESS
1482 populate = false;
1483 #endif
1484
1485 if (index >= APERTURE_MAX_RANGES)
1486 return -ENOMEM;
1487
1488 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1489 if (!dma_dom->aperture[index])
1490 return -ENOMEM;
1491
1492 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1493 if (!dma_dom->aperture[index]->bitmap)
1494 goto out_free;
1495
1496 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1497
1498 if (populate) {
1499 unsigned long address = dma_dom->aperture_size;
1500 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1501 u64 *pte, *pte_page;
1502
1503 for (i = 0; i < num_ptes; ++i) {
1504 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1505 &pte_page, gfp);
1506 if (!pte)
1507 goto out_free;
1508
1509 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1510
1511 address += APERTURE_RANGE_SIZE / 64;
1512 }
1513 }
1514
1515 old_size = dma_dom->aperture_size;
1516 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1517
1518 /* Reserve address range used for MSI messages */
1519 if (old_size < MSI_ADDR_BASE_LO &&
1520 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1521 unsigned long spage;
1522 int pages;
1523
1524 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1525 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1526
1527 dma_ops_reserve_addresses(dma_dom, spage, pages);
1528 }
1529
1530 /* Initialize the exclusion range if necessary */
1531 for_each_iommu(iommu) {
1532 if (iommu->exclusion_start &&
1533 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1534 && iommu->exclusion_start < dma_dom->aperture_size) {
1535 unsigned long startpage;
1536 int pages = iommu_num_pages(iommu->exclusion_start,
1537 iommu->exclusion_length,
1538 PAGE_SIZE);
1539 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1540 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1541 }
1542 }
1543
1544 /*
1545 * Check for areas already mapped as present in the new aperture
1546 * range and mark those pages as reserved in the allocator. Such
1547 * mappings may already exist as a result of requested unity
1548 * mappings for devices.
1549 */
1550 for (i = dma_dom->aperture[index]->offset;
1551 i < dma_dom->aperture_size;
1552 i += pte_pgsize) {
1553 u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize);
1554 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1555 continue;
1556
1557 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT,
1558 pte_pgsize >> 12);
1559 }
1560
1561 update_domain(&dma_dom->domain);
1562
1563 return 0;
1564
1565 out_free:
1566 update_domain(&dma_dom->domain);
1567
1568 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1569
1570 kfree(dma_dom->aperture[index]);
1571 dma_dom->aperture[index] = NULL;
1572
1573 return -ENOMEM;
1574 }
1575
1576 static unsigned long dma_ops_area_alloc(struct device *dev,
1577 struct dma_ops_domain *dom,
1578 unsigned int pages,
1579 unsigned long align_mask,
1580 u64 dma_mask,
1581 unsigned long start)
1582 {
1583 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1584 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1585 int i = start >> APERTURE_RANGE_SHIFT;
1586 unsigned long boundary_size, mask;
1587 unsigned long address = -1;
1588 unsigned long limit;
1589
1590 next_bit >>= PAGE_SHIFT;
1591
1592 mask = dma_get_seg_boundary(dev);
1593
1594 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
1595 1UL << (BITS_PER_LONG - PAGE_SHIFT);
1596
1597 for (;i < max_index; ++i) {
1598 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1599
1600 if (dom->aperture[i]->offset >= dma_mask)
1601 break;
1602
1603 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1604 dma_mask >> PAGE_SHIFT);
1605
1606 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1607 limit, next_bit, pages, 0,
1608 boundary_size, align_mask);
1609 if (address != -1) {
1610 address = dom->aperture[i]->offset +
1611 (address << PAGE_SHIFT);
1612 dom->next_address = address + (pages << PAGE_SHIFT);
1613 break;
1614 }
1615
1616 next_bit = 0;
1617 }
1618
1619 return address;
1620 }
1621
1622 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1623 struct dma_ops_domain *dom,
1624 unsigned int pages,
1625 unsigned long align_mask,
1626 u64 dma_mask)
1627 {
1628 unsigned long address;
1629
1630 #ifdef CONFIG_IOMMU_STRESS
1631 dom->next_address = 0;
1632 dom->need_flush = true;
1633 #endif
1634
1635 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1636 dma_mask, dom->next_address);
1637
1638 if (address == -1) {
1639 dom->next_address = 0;
1640 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1641 dma_mask, 0);
1642 dom->need_flush = true;
1643 }
1644
1645 if (unlikely(address == -1))
1646 address = DMA_ERROR_CODE;
1647
1648 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1649
1650 return address;
1651 }
1652
1653 /*
1654 * The address free function.
1655 *
1656 * called with domain->lock held
1657 */
1658 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1659 unsigned long address,
1660 unsigned int pages)
1661 {
1662 unsigned i = address >> APERTURE_RANGE_SHIFT;
1663 struct aperture_range *range = dom->aperture[i];
1664
1665 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1666
1667 #ifdef CONFIG_IOMMU_STRESS
1668 if (i < 4)
1669 return;
1670 #endif
1671
1672 if (address >= dom->next_address)
1673 dom->need_flush = true;
1674
1675 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1676
1677 bitmap_clear(range->bitmap, address, pages);
1678
1679 }
1680
1681 /****************************************************************************
1682 *
1683 * The next functions belong to the domain allocation. A domain is
1684 * allocated for every IOMMU as the default domain. If device isolation
1685 * is enabled, every device get its own domain. The most important thing
1686 * about domains is the page table mapping the DMA address space they
1687 * contain.
1688 *
1689 ****************************************************************************/
1690
1691 /*
1692 * This function adds a protection domain to the global protection domain list
1693 */
1694 static void add_domain_to_list(struct protection_domain *domain)
1695 {
1696 unsigned long flags;
1697
1698 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1699 list_add(&domain->list, &amd_iommu_pd_list);
1700 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1701 }
1702
1703 /*
1704 * This function removes a protection domain to the global
1705 * protection domain list
1706 */
1707 static void del_domain_from_list(struct protection_domain *domain)
1708 {
1709 unsigned long flags;
1710
1711 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1712 list_del(&domain->list);
1713 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1714 }
1715
1716 static u16 domain_id_alloc(void)
1717 {
1718 unsigned long flags;
1719 int id;
1720
1721 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1722 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1723 BUG_ON(id == 0);
1724 if (id > 0 && id < MAX_DOMAIN_ID)
1725 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1726 else
1727 id = 0;
1728 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1729
1730 return id;
1731 }
1732
1733 static void domain_id_free(int id)
1734 {
1735 unsigned long flags;
1736
1737 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1738 if (id > 0 && id < MAX_DOMAIN_ID)
1739 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1740 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1741 }
1742
1743 #define DEFINE_FREE_PT_FN(LVL, FN) \
1744 static void free_pt_##LVL (unsigned long __pt) \
1745 { \
1746 unsigned long p; \
1747 u64 *pt; \
1748 int i; \
1749 \
1750 pt = (u64 *)__pt; \
1751 \
1752 for (i = 0; i < 512; ++i) { \
1753 /* PTE present? */ \
1754 if (!IOMMU_PTE_PRESENT(pt[i])) \
1755 continue; \
1756 \
1757 /* Large PTE? */ \
1758 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1759 PM_PTE_LEVEL(pt[i]) == 7) \
1760 continue; \
1761 \
1762 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1763 FN(p); \
1764 } \
1765 free_page((unsigned long)pt); \
1766 }
1767
1768 DEFINE_FREE_PT_FN(l2, free_page)
1769 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1770 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1771 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1772 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1773
1774 static void free_pagetable(struct protection_domain *domain)
1775 {
1776 unsigned long root = (unsigned long)domain->pt_root;
1777
1778 switch (domain->mode) {
1779 case PAGE_MODE_NONE:
1780 break;
1781 case PAGE_MODE_1_LEVEL:
1782 free_page(root);
1783 break;
1784 case PAGE_MODE_2_LEVEL:
1785 free_pt_l2(root);
1786 break;
1787 case PAGE_MODE_3_LEVEL:
1788 free_pt_l3(root);
1789 break;
1790 case PAGE_MODE_4_LEVEL:
1791 free_pt_l4(root);
1792 break;
1793 case PAGE_MODE_5_LEVEL:
1794 free_pt_l5(root);
1795 break;
1796 case PAGE_MODE_6_LEVEL:
1797 free_pt_l6(root);
1798 break;
1799 default:
1800 BUG();
1801 }
1802 }
1803
1804 static void free_gcr3_tbl_level1(u64 *tbl)
1805 {
1806 u64 *ptr;
1807 int i;
1808
1809 for (i = 0; i < 512; ++i) {
1810 if (!(tbl[i] & GCR3_VALID))
1811 continue;
1812
1813 ptr = __va(tbl[i] & PAGE_MASK);
1814
1815 free_page((unsigned long)ptr);
1816 }
1817 }
1818
1819 static void free_gcr3_tbl_level2(u64 *tbl)
1820 {
1821 u64 *ptr;
1822 int i;
1823
1824 for (i = 0; i < 512; ++i) {
1825 if (!(tbl[i] & GCR3_VALID))
1826 continue;
1827
1828 ptr = __va(tbl[i] & PAGE_MASK);
1829
1830 free_gcr3_tbl_level1(ptr);
1831 }
1832 }
1833
1834 static void free_gcr3_table(struct protection_domain *domain)
1835 {
1836 if (domain->glx == 2)
1837 free_gcr3_tbl_level2(domain->gcr3_tbl);
1838 else if (domain->glx == 1)
1839 free_gcr3_tbl_level1(domain->gcr3_tbl);
1840 else if (domain->glx != 0)
1841 BUG();
1842
1843 free_page((unsigned long)domain->gcr3_tbl);
1844 }
1845
1846 /*
1847 * Free a domain, only used if something went wrong in the
1848 * allocation path and we need to free an already allocated page table
1849 */
1850 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1851 {
1852 int i;
1853
1854 if (!dom)
1855 return;
1856
1857 del_domain_from_list(&dom->domain);
1858
1859 free_pagetable(&dom->domain);
1860
1861 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1862 if (!dom->aperture[i])
1863 continue;
1864 free_page((unsigned long)dom->aperture[i]->bitmap);
1865 kfree(dom->aperture[i]);
1866 }
1867
1868 kfree(dom);
1869 }
1870
1871 /*
1872 * Allocates a new protection domain usable for the dma_ops functions.
1873 * It also initializes the page table and the address allocator data
1874 * structures required for the dma_ops interface
1875 */
1876 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1877 {
1878 struct dma_ops_domain *dma_dom;
1879
1880 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1881 if (!dma_dom)
1882 return NULL;
1883
1884 if (protection_domain_init(&dma_dom->domain))
1885 goto free_dma_dom;
1886
1887 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1888 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1889 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1890 dma_dom->domain.priv = dma_dom;
1891 if (!dma_dom->domain.pt_root)
1892 goto free_dma_dom;
1893
1894 dma_dom->need_flush = false;
1895
1896 add_domain_to_list(&dma_dom->domain);
1897
1898 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1899 goto free_dma_dom;
1900
1901 /*
1902 * mark the first page as allocated so we never return 0 as
1903 * a valid dma-address. So we can use 0 as error value
1904 */
1905 dma_dom->aperture[0]->bitmap[0] = 1;
1906 dma_dom->next_address = 0;
1907
1908
1909 return dma_dom;
1910
1911 free_dma_dom:
1912 dma_ops_domain_free(dma_dom);
1913
1914 return NULL;
1915 }
1916
1917 /*
1918 * little helper function to check whether a given protection domain is a
1919 * dma_ops domain
1920 */
1921 static bool dma_ops_domain(struct protection_domain *domain)
1922 {
1923 return domain->flags & PD_DMA_OPS_MASK;
1924 }
1925
1926 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1927 {
1928 u64 pte_root = 0;
1929 u64 flags = 0;
1930
1931 if (domain->mode != PAGE_MODE_NONE)
1932 pte_root = virt_to_phys(domain->pt_root);
1933
1934 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1935 << DEV_ENTRY_MODE_SHIFT;
1936 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1937
1938 flags = amd_iommu_dev_table[devid].data[1];
1939
1940 if (ats)
1941 flags |= DTE_FLAG_IOTLB;
1942
1943 if (domain->flags & PD_IOMMUV2_MASK) {
1944 u64 gcr3 = __pa(domain->gcr3_tbl);
1945 u64 glx = domain->glx;
1946 u64 tmp;
1947
1948 pte_root |= DTE_FLAG_GV;
1949 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1950
1951 /* First mask out possible old values for GCR3 table */
1952 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1953 flags &= ~tmp;
1954
1955 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1956 flags &= ~tmp;
1957
1958 /* Encode GCR3 table into DTE */
1959 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1960 pte_root |= tmp;
1961
1962 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1963 flags |= tmp;
1964
1965 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1966 flags |= tmp;
1967 }
1968
1969 flags &= ~(0xffffUL);
1970 flags |= domain->id;
1971
1972 amd_iommu_dev_table[devid].data[1] = flags;
1973 amd_iommu_dev_table[devid].data[0] = pte_root;
1974 }
1975
1976 static void clear_dte_entry(u16 devid)
1977 {
1978 /* remove entry from the device table seen by the hardware */
1979 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1980 amd_iommu_dev_table[devid].data[1] = 0;
1981
1982 amd_iommu_apply_erratum_63(devid);
1983 }
1984
1985 static void do_attach(struct iommu_dev_data *dev_data,
1986 struct protection_domain *domain)
1987 {
1988 struct amd_iommu *iommu;
1989 bool ats;
1990
1991 iommu = amd_iommu_rlookup_table[dev_data->devid];
1992 ats = dev_data->ats.enabled;
1993
1994 /* Update data structures */
1995 dev_data->domain = domain;
1996 list_add(&dev_data->list, &domain->dev_list);
1997 set_dte_entry(dev_data->devid, domain, ats);
1998
1999 /* Do reference counting */
2000 domain->dev_iommu[iommu->index] += 1;
2001 domain->dev_cnt += 1;
2002
2003 /* Flush the DTE entry */
2004 device_flush_dte(dev_data);
2005 }
2006
2007 static void do_detach(struct iommu_dev_data *dev_data)
2008 {
2009 struct amd_iommu *iommu;
2010
2011 iommu = amd_iommu_rlookup_table[dev_data->devid];
2012
2013 /* decrease reference counters */
2014 dev_data->domain->dev_iommu[iommu->index] -= 1;
2015 dev_data->domain->dev_cnt -= 1;
2016
2017 /* Update data structures */
2018 dev_data->domain = NULL;
2019 list_del(&dev_data->list);
2020 clear_dte_entry(dev_data->devid);
2021
2022 /* Flush the DTE entry */
2023 device_flush_dte(dev_data);
2024 }
2025
2026 /*
2027 * If a device is not yet associated with a domain, this function does
2028 * assigns it visible for the hardware
2029 */
2030 static int __attach_device(struct iommu_dev_data *dev_data,
2031 struct protection_domain *domain)
2032 {
2033 struct iommu_dev_data *head, *entry;
2034 int ret;
2035
2036 /* lock domain */
2037 spin_lock(&domain->lock);
2038
2039 head = dev_data;
2040
2041 if (head->alias_data != NULL)
2042 head = head->alias_data;
2043
2044 /* Now we have the root of the alias group, if any */
2045
2046 ret = -EBUSY;
2047 if (head->domain != NULL)
2048 goto out_unlock;
2049
2050 /* Attach alias group root */
2051 do_attach(head, domain);
2052
2053 /* Attach other devices in the alias group */
2054 list_for_each_entry(entry, &head->alias_list, alias_list)
2055 do_attach(entry, domain);
2056
2057 ret = 0;
2058
2059 out_unlock:
2060
2061 /* ready */
2062 spin_unlock(&domain->lock);
2063
2064 return ret;
2065 }
2066
2067
2068 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2069 {
2070 pci_disable_ats(pdev);
2071 pci_disable_pri(pdev);
2072 pci_disable_pasid(pdev);
2073 }
2074
2075 /* FIXME: Change generic reset-function to do the same */
2076 static int pri_reset_while_enabled(struct pci_dev *pdev)
2077 {
2078 u16 control;
2079 int pos;
2080
2081 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2082 if (!pos)
2083 return -EINVAL;
2084
2085 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2086 control |= PCI_PRI_CTRL_RESET;
2087 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2088
2089 return 0;
2090 }
2091
2092 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2093 {
2094 bool reset_enable;
2095 int reqs, ret;
2096
2097 /* FIXME: Hardcode number of outstanding requests for now */
2098 reqs = 32;
2099 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2100 reqs = 1;
2101 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2102
2103 /* Only allow access to user-accessible pages */
2104 ret = pci_enable_pasid(pdev, 0);
2105 if (ret)
2106 goto out_err;
2107
2108 /* First reset the PRI state of the device */
2109 ret = pci_reset_pri(pdev);
2110 if (ret)
2111 goto out_err;
2112
2113 /* Enable PRI */
2114 ret = pci_enable_pri(pdev, reqs);
2115 if (ret)
2116 goto out_err;
2117
2118 if (reset_enable) {
2119 ret = pri_reset_while_enabled(pdev);
2120 if (ret)
2121 goto out_err;
2122 }
2123
2124 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2125 if (ret)
2126 goto out_err;
2127
2128 return 0;
2129
2130 out_err:
2131 pci_disable_pri(pdev);
2132 pci_disable_pasid(pdev);
2133
2134 return ret;
2135 }
2136
2137 /* FIXME: Move this to PCI code */
2138 #define PCI_PRI_TLP_OFF (1 << 15)
2139
2140 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2141 {
2142 u16 status;
2143 int pos;
2144
2145 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2146 if (!pos)
2147 return false;
2148
2149 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2150
2151 return (status & PCI_PRI_TLP_OFF) ? true : false;
2152 }
2153
2154 /*
2155 * If a device is not yet associated with a domain, this function
2156 * assigns it visible for the hardware
2157 */
2158 static int attach_device(struct device *dev,
2159 struct protection_domain *domain)
2160 {
2161 struct pci_dev *pdev = to_pci_dev(dev);
2162 struct iommu_dev_data *dev_data;
2163 unsigned long flags;
2164 int ret;
2165
2166 dev_data = get_dev_data(dev);
2167
2168 if (domain->flags & PD_IOMMUV2_MASK) {
2169 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2170 return -EINVAL;
2171
2172 if (pdev_iommuv2_enable(pdev) != 0)
2173 return -EINVAL;
2174
2175 dev_data->ats.enabled = true;
2176 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2177 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2178 } else if (amd_iommu_iotlb_sup &&
2179 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2180 dev_data->ats.enabled = true;
2181 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2182 }
2183
2184 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2185 ret = __attach_device(dev_data, domain);
2186 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2187
2188 /*
2189 * We might boot into a crash-kernel here. The crashed kernel
2190 * left the caches in the IOMMU dirty. So we have to flush
2191 * here to evict all dirty stuff.
2192 */
2193 domain_flush_tlb_pde(domain);
2194
2195 return ret;
2196 }
2197
2198 /*
2199 * Removes a device from a protection domain (unlocked)
2200 */
2201 static void __detach_device(struct iommu_dev_data *dev_data)
2202 {
2203 struct iommu_dev_data *head, *entry;
2204 struct protection_domain *domain;
2205 unsigned long flags;
2206
2207 BUG_ON(!dev_data->domain);
2208
2209 domain = dev_data->domain;
2210
2211 spin_lock_irqsave(&domain->lock, flags);
2212
2213 head = dev_data;
2214 if (head->alias_data != NULL)
2215 head = head->alias_data;
2216
2217 list_for_each_entry(entry, &head->alias_list, alias_list)
2218 do_detach(entry);
2219
2220 do_detach(head);
2221
2222 spin_unlock_irqrestore(&domain->lock, flags);
2223
2224 /*
2225 * If we run in passthrough mode the device must be assigned to the
2226 * passthrough domain if it is detached from any other domain.
2227 * Make sure we can deassign from the pt_domain itself.
2228 */
2229 if (dev_data->passthrough &&
2230 (dev_data->domain == NULL && domain != pt_domain))
2231 __attach_device(dev_data, pt_domain);
2232 }
2233
2234 /*
2235 * Removes a device from a protection domain (with devtable_lock held)
2236 */
2237 static void detach_device(struct device *dev)
2238 {
2239 struct protection_domain *domain;
2240 struct iommu_dev_data *dev_data;
2241 unsigned long flags;
2242
2243 dev_data = get_dev_data(dev);
2244 domain = dev_data->domain;
2245
2246 /* lock device table */
2247 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2248 __detach_device(dev_data);
2249 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2250
2251 if (domain->flags & PD_IOMMUV2_MASK)
2252 pdev_iommuv2_disable(to_pci_dev(dev));
2253 else if (dev_data->ats.enabled)
2254 pci_disable_ats(to_pci_dev(dev));
2255
2256 dev_data->ats.enabled = false;
2257 }
2258
2259 static int amd_iommu_add_device(struct device *dev)
2260 {
2261 struct iommu_dev_data *dev_data;
2262 struct iommu_domain *domain;
2263 struct amd_iommu *iommu;
2264 u16 devid;
2265 int ret;
2266
2267 if (!check_device(dev) || get_dev_data(dev))
2268 return 0;
2269
2270 devid = get_device_id(dev);
2271 iommu = amd_iommu_rlookup_table[devid];
2272
2273 ret = iommu_init_device(dev);
2274 if (ret) {
2275 if (ret != -ENOTSUPP)
2276 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2277 dev_name(dev));
2278
2279 iommu_ignore_device(dev);
2280 dev->archdata.dma_ops = &nommu_dma_ops;
2281 goto out;
2282 }
2283 init_iommu_group(dev);
2284
2285 dev_data = get_dev_data(dev);
2286
2287 BUG_ON(!dev_data);
2288
2289 if (dev_data->iommu_v2)
2290 iommu_request_dm_for_dev(dev);
2291
2292 /* Domains are initialized for this device - have a look what we ended up with */
2293 domain = iommu_get_domain_for_dev(dev);
2294 if (domain->type == IOMMU_DOMAIN_IDENTITY) {
2295 dev_data->passthrough = true;
2296 dev->archdata.dma_ops = &nommu_dma_ops;
2297 } else {
2298 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2299 }
2300
2301 out:
2302 iommu_completion_wait(iommu);
2303
2304 return 0;
2305 }
2306
2307 static void amd_iommu_remove_device(struct device *dev)
2308 {
2309 struct amd_iommu *iommu;
2310 u16 devid;
2311
2312 if (!check_device(dev))
2313 return;
2314
2315 devid = get_device_id(dev);
2316 iommu = amd_iommu_rlookup_table[devid];
2317
2318 iommu_uninit_device(dev);
2319 iommu_completion_wait(iommu);
2320 }
2321
2322 /*****************************************************************************
2323 *
2324 * The next functions belong to the dma_ops mapping/unmapping code.
2325 *
2326 *****************************************************************************/
2327
2328 /*
2329 * In the dma_ops path we only have the struct device. This function
2330 * finds the corresponding IOMMU, the protection domain and the
2331 * requestor id for a given device.
2332 * If the device is not yet associated with a domain this is also done
2333 * in this function.
2334 */
2335 static struct protection_domain *get_domain(struct device *dev)
2336 {
2337 struct protection_domain *domain;
2338 struct iommu_domain *io_domain;
2339
2340 if (!check_device(dev))
2341 return ERR_PTR(-EINVAL);
2342
2343 io_domain = iommu_get_domain_for_dev(dev);
2344 if (!io_domain)
2345 return NULL;
2346
2347 domain = to_pdomain(io_domain);
2348 if (!dma_ops_domain(domain))
2349 return ERR_PTR(-EBUSY);
2350
2351 return domain;
2352 }
2353
2354 static void update_device_table(struct protection_domain *domain)
2355 {
2356 struct iommu_dev_data *dev_data;
2357
2358 list_for_each_entry(dev_data, &domain->dev_list, list)
2359 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2360 }
2361
2362 static void update_domain(struct protection_domain *domain)
2363 {
2364 if (!domain->updated)
2365 return;
2366
2367 update_device_table(domain);
2368
2369 domain_flush_devices(domain);
2370 domain_flush_tlb_pde(domain);
2371
2372 domain->updated = false;
2373 }
2374
2375 /*
2376 * This function fetches the PTE for a given address in the aperture
2377 */
2378 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2379 unsigned long address)
2380 {
2381 struct aperture_range *aperture;
2382 u64 *pte, *pte_page;
2383
2384 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2385 if (!aperture)
2386 return NULL;
2387
2388 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2389 if (!pte) {
2390 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2391 GFP_ATOMIC);
2392 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2393 } else
2394 pte += PM_LEVEL_INDEX(0, address);
2395
2396 update_domain(&dom->domain);
2397
2398 return pte;
2399 }
2400
2401 /*
2402 * This is the generic map function. It maps one 4kb page at paddr to
2403 * the given address in the DMA address space for the domain.
2404 */
2405 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2406 unsigned long address,
2407 phys_addr_t paddr,
2408 int direction)
2409 {
2410 u64 *pte, __pte;
2411
2412 WARN_ON(address > dom->aperture_size);
2413
2414 paddr &= PAGE_MASK;
2415
2416 pte = dma_ops_get_pte(dom, address);
2417 if (!pte)
2418 return DMA_ERROR_CODE;
2419
2420 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2421
2422 if (direction == DMA_TO_DEVICE)
2423 __pte |= IOMMU_PTE_IR;
2424 else if (direction == DMA_FROM_DEVICE)
2425 __pte |= IOMMU_PTE_IW;
2426 else if (direction == DMA_BIDIRECTIONAL)
2427 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2428
2429 WARN_ON(*pte);
2430
2431 *pte = __pte;
2432
2433 return (dma_addr_t)address;
2434 }
2435
2436 /*
2437 * The generic unmapping function for on page in the DMA address space.
2438 */
2439 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2440 unsigned long address)
2441 {
2442 struct aperture_range *aperture;
2443 u64 *pte;
2444
2445 if (address >= dom->aperture_size)
2446 return;
2447
2448 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2449 if (!aperture)
2450 return;
2451
2452 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2453 if (!pte)
2454 return;
2455
2456 pte += PM_LEVEL_INDEX(0, address);
2457
2458 WARN_ON(!*pte);
2459
2460 *pte = 0ULL;
2461 }
2462
2463 /*
2464 * This function contains common code for mapping of a physically
2465 * contiguous memory region into DMA address space. It is used by all
2466 * mapping functions provided with this IOMMU driver.
2467 * Must be called with the domain lock held.
2468 */
2469 static dma_addr_t __map_single(struct device *dev,
2470 struct dma_ops_domain *dma_dom,
2471 phys_addr_t paddr,
2472 size_t size,
2473 int dir,
2474 bool align,
2475 u64 dma_mask)
2476 {
2477 dma_addr_t offset = paddr & ~PAGE_MASK;
2478 dma_addr_t address, start, ret;
2479 unsigned int pages;
2480 unsigned long align_mask = 0;
2481 int i;
2482
2483 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2484 paddr &= PAGE_MASK;
2485
2486 INC_STATS_COUNTER(total_map_requests);
2487
2488 if (pages > 1)
2489 INC_STATS_COUNTER(cross_page);
2490
2491 if (align)
2492 align_mask = (1UL << get_order(size)) - 1;
2493
2494 retry:
2495 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2496 dma_mask);
2497 if (unlikely(address == DMA_ERROR_CODE)) {
2498 /*
2499 * setting next_address here will let the address
2500 * allocator only scan the new allocated range in the
2501 * first run. This is a small optimization.
2502 */
2503 dma_dom->next_address = dma_dom->aperture_size;
2504
2505 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2506 goto out;
2507
2508 /*
2509 * aperture was successfully enlarged by 128 MB, try
2510 * allocation again
2511 */
2512 goto retry;
2513 }
2514
2515 start = address;
2516 for (i = 0; i < pages; ++i) {
2517 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2518 if (ret == DMA_ERROR_CODE)
2519 goto out_unmap;
2520
2521 paddr += PAGE_SIZE;
2522 start += PAGE_SIZE;
2523 }
2524 address += offset;
2525
2526 ADD_STATS_COUNTER(alloced_io_mem, size);
2527
2528 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2529 domain_flush_tlb(&dma_dom->domain);
2530 dma_dom->need_flush = false;
2531 } else if (unlikely(amd_iommu_np_cache))
2532 domain_flush_pages(&dma_dom->domain, address, size);
2533
2534 out:
2535 return address;
2536
2537 out_unmap:
2538
2539 for (--i; i >= 0; --i) {
2540 start -= PAGE_SIZE;
2541 dma_ops_domain_unmap(dma_dom, start);
2542 }
2543
2544 dma_ops_free_addresses(dma_dom, address, pages);
2545
2546 return DMA_ERROR_CODE;
2547 }
2548
2549 /*
2550 * Does the reverse of the __map_single function. Must be called with
2551 * the domain lock held too
2552 */
2553 static void __unmap_single(struct dma_ops_domain *dma_dom,
2554 dma_addr_t dma_addr,
2555 size_t size,
2556 int dir)
2557 {
2558 dma_addr_t flush_addr;
2559 dma_addr_t i, start;
2560 unsigned int pages;
2561
2562 if ((dma_addr == DMA_ERROR_CODE) ||
2563 (dma_addr + size > dma_dom->aperture_size))
2564 return;
2565
2566 flush_addr = dma_addr;
2567 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2568 dma_addr &= PAGE_MASK;
2569 start = dma_addr;
2570
2571 for (i = 0; i < pages; ++i) {
2572 dma_ops_domain_unmap(dma_dom, start);
2573 start += PAGE_SIZE;
2574 }
2575
2576 SUB_STATS_COUNTER(alloced_io_mem, size);
2577
2578 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2579
2580 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2581 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2582 dma_dom->need_flush = false;
2583 }
2584 }
2585
2586 /*
2587 * The exported map_single function for dma_ops.
2588 */
2589 static dma_addr_t map_page(struct device *dev, struct page *page,
2590 unsigned long offset, size_t size,
2591 enum dma_data_direction dir,
2592 struct dma_attrs *attrs)
2593 {
2594 unsigned long flags;
2595 struct protection_domain *domain;
2596 dma_addr_t addr;
2597 u64 dma_mask;
2598 phys_addr_t paddr = page_to_phys(page) + offset;
2599
2600 INC_STATS_COUNTER(cnt_map_single);
2601
2602 domain = get_domain(dev);
2603 if (PTR_ERR(domain) == -EINVAL)
2604 return (dma_addr_t)paddr;
2605 else if (IS_ERR(domain))
2606 return DMA_ERROR_CODE;
2607
2608 dma_mask = *dev->dma_mask;
2609
2610 spin_lock_irqsave(&domain->lock, flags);
2611
2612 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2613 dma_mask);
2614 if (addr == DMA_ERROR_CODE)
2615 goto out;
2616
2617 domain_flush_complete(domain);
2618
2619 out:
2620 spin_unlock_irqrestore(&domain->lock, flags);
2621
2622 return addr;
2623 }
2624
2625 /*
2626 * The exported unmap_single function for dma_ops.
2627 */
2628 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2629 enum dma_data_direction dir, struct dma_attrs *attrs)
2630 {
2631 unsigned long flags;
2632 struct protection_domain *domain;
2633
2634 INC_STATS_COUNTER(cnt_unmap_single);
2635
2636 domain = get_domain(dev);
2637 if (IS_ERR(domain))
2638 return;
2639
2640 spin_lock_irqsave(&domain->lock, flags);
2641
2642 __unmap_single(domain->priv, dma_addr, size, dir);
2643
2644 domain_flush_complete(domain);
2645
2646 spin_unlock_irqrestore(&domain->lock, flags);
2647 }
2648
2649 /*
2650 * The exported map_sg function for dma_ops (handles scatter-gather
2651 * lists).
2652 */
2653 static int map_sg(struct device *dev, struct scatterlist *sglist,
2654 int nelems, enum dma_data_direction dir,
2655 struct dma_attrs *attrs)
2656 {
2657 unsigned long flags;
2658 struct protection_domain *domain;
2659 int i;
2660 struct scatterlist *s;
2661 phys_addr_t paddr;
2662 int mapped_elems = 0;
2663 u64 dma_mask;
2664
2665 INC_STATS_COUNTER(cnt_map_sg);
2666
2667 domain = get_domain(dev);
2668 if (IS_ERR(domain))
2669 return 0;
2670
2671 dma_mask = *dev->dma_mask;
2672
2673 spin_lock_irqsave(&domain->lock, flags);
2674
2675 for_each_sg(sglist, s, nelems, i) {
2676 paddr = sg_phys(s);
2677
2678 s->dma_address = __map_single(dev, domain->priv,
2679 paddr, s->length, dir, false,
2680 dma_mask);
2681
2682 if (s->dma_address) {
2683 s->dma_length = s->length;
2684 mapped_elems++;
2685 } else
2686 goto unmap;
2687 }
2688
2689 domain_flush_complete(domain);
2690
2691 out:
2692 spin_unlock_irqrestore(&domain->lock, flags);
2693
2694 return mapped_elems;
2695 unmap:
2696 for_each_sg(sglist, s, mapped_elems, i) {
2697 if (s->dma_address)
2698 __unmap_single(domain->priv, s->dma_address,
2699 s->dma_length, dir);
2700 s->dma_address = s->dma_length = 0;
2701 }
2702
2703 mapped_elems = 0;
2704
2705 goto out;
2706 }
2707
2708 /*
2709 * The exported map_sg function for dma_ops (handles scatter-gather
2710 * lists).
2711 */
2712 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2713 int nelems, enum dma_data_direction dir,
2714 struct dma_attrs *attrs)
2715 {
2716 unsigned long flags;
2717 struct protection_domain *domain;
2718 struct scatterlist *s;
2719 int i;
2720
2721 INC_STATS_COUNTER(cnt_unmap_sg);
2722
2723 domain = get_domain(dev);
2724 if (IS_ERR(domain))
2725 return;
2726
2727 spin_lock_irqsave(&domain->lock, flags);
2728
2729 for_each_sg(sglist, s, nelems, i) {
2730 __unmap_single(domain->priv, s->dma_address,
2731 s->dma_length, dir);
2732 s->dma_address = s->dma_length = 0;
2733 }
2734
2735 domain_flush_complete(domain);
2736
2737 spin_unlock_irqrestore(&domain->lock, flags);
2738 }
2739
2740 /*
2741 * The exported alloc_coherent function for dma_ops.
2742 */
2743 static void *alloc_coherent(struct device *dev, size_t size,
2744 dma_addr_t *dma_addr, gfp_t flag,
2745 struct dma_attrs *attrs)
2746 {
2747 u64 dma_mask = dev->coherent_dma_mask;
2748 struct protection_domain *domain;
2749 unsigned long flags;
2750 struct page *page;
2751
2752 INC_STATS_COUNTER(cnt_alloc_coherent);
2753
2754 domain = get_domain(dev);
2755 if (PTR_ERR(domain) == -EINVAL) {
2756 page = alloc_pages(flag, get_order(size));
2757 *dma_addr = page_to_phys(page);
2758 return page_address(page);
2759 } else if (IS_ERR(domain))
2760 return NULL;
2761
2762 size = PAGE_ALIGN(size);
2763 dma_mask = dev->coherent_dma_mask;
2764 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2765 flag |= __GFP_ZERO;
2766
2767 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2768 if (!page) {
2769 if (!(flag & __GFP_WAIT))
2770 return NULL;
2771
2772 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2773 get_order(size));
2774 if (!page)
2775 return NULL;
2776 }
2777
2778 if (!dma_mask)
2779 dma_mask = *dev->dma_mask;
2780
2781 spin_lock_irqsave(&domain->lock, flags);
2782
2783 *dma_addr = __map_single(dev, domain->priv, page_to_phys(page),
2784 size, DMA_BIDIRECTIONAL, true, dma_mask);
2785
2786 if (*dma_addr == DMA_ERROR_CODE) {
2787 spin_unlock_irqrestore(&domain->lock, flags);
2788 goto out_free;
2789 }
2790
2791 domain_flush_complete(domain);
2792
2793 spin_unlock_irqrestore(&domain->lock, flags);
2794
2795 return page_address(page);
2796
2797 out_free:
2798
2799 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2800 __free_pages(page, get_order(size));
2801
2802 return NULL;
2803 }
2804
2805 /*
2806 * The exported free_coherent function for dma_ops.
2807 */
2808 static void free_coherent(struct device *dev, size_t size,
2809 void *virt_addr, dma_addr_t dma_addr,
2810 struct dma_attrs *attrs)
2811 {
2812 struct protection_domain *domain;
2813 unsigned long flags;
2814 struct page *page;
2815
2816 INC_STATS_COUNTER(cnt_free_coherent);
2817
2818 page = virt_to_page(virt_addr);
2819 size = PAGE_ALIGN(size);
2820
2821 domain = get_domain(dev);
2822 if (IS_ERR(domain))
2823 goto free_mem;
2824
2825 spin_lock_irqsave(&domain->lock, flags);
2826
2827 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2828
2829 domain_flush_complete(domain);
2830
2831 spin_unlock_irqrestore(&domain->lock, flags);
2832
2833 free_mem:
2834 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2835 __free_pages(page, get_order(size));
2836 }
2837
2838 /*
2839 * This function is called by the DMA layer to find out if we can handle a
2840 * particular device. It is part of the dma_ops.
2841 */
2842 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2843 {
2844 return check_device(dev);
2845 }
2846
2847 static struct dma_map_ops amd_iommu_dma_ops = {
2848 .alloc = alloc_coherent,
2849 .free = free_coherent,
2850 .map_page = map_page,
2851 .unmap_page = unmap_page,
2852 .map_sg = map_sg,
2853 .unmap_sg = unmap_sg,
2854 .dma_supported = amd_iommu_dma_supported,
2855 };
2856
2857 int __init amd_iommu_init_api(void)
2858 {
2859 return bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2860 }
2861
2862 int __init amd_iommu_init_dma_ops(void)
2863 {
2864 iommu_detected = 1;
2865 swiotlb = 0;
2866
2867 amd_iommu_stats_init();
2868
2869 if (amd_iommu_unmap_flush)
2870 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2871 else
2872 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2873
2874 return 0;
2875 }
2876
2877 /*****************************************************************************
2878 *
2879 * The following functions belong to the exported interface of AMD IOMMU
2880 *
2881 * This interface allows access to lower level functions of the IOMMU
2882 * like protection domain handling and assignement of devices to domains
2883 * which is not possible with the dma_ops interface.
2884 *
2885 *****************************************************************************/
2886
2887 static void cleanup_domain(struct protection_domain *domain)
2888 {
2889 struct iommu_dev_data *entry;
2890 unsigned long flags;
2891
2892 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2893
2894 while (!list_empty(&domain->dev_list)) {
2895 entry = list_first_entry(&domain->dev_list,
2896 struct iommu_dev_data, list);
2897 __detach_device(entry);
2898 }
2899
2900 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2901 }
2902
2903 static void protection_domain_free(struct protection_domain *domain)
2904 {
2905 if (!domain)
2906 return;
2907
2908 del_domain_from_list(domain);
2909
2910 if (domain->id)
2911 domain_id_free(domain->id);
2912
2913 kfree(domain);
2914 }
2915
2916 static int protection_domain_init(struct protection_domain *domain)
2917 {
2918 spin_lock_init(&domain->lock);
2919 mutex_init(&domain->api_lock);
2920 domain->id = domain_id_alloc();
2921 if (!domain->id)
2922 return -ENOMEM;
2923 INIT_LIST_HEAD(&domain->dev_list);
2924
2925 return 0;
2926 }
2927
2928 static struct protection_domain *protection_domain_alloc(void)
2929 {
2930 struct protection_domain *domain;
2931
2932 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2933 if (!domain)
2934 return NULL;
2935
2936 if (protection_domain_init(domain))
2937 goto out_err;
2938
2939 add_domain_to_list(domain);
2940
2941 return domain;
2942
2943 out_err:
2944 kfree(domain);
2945
2946 return NULL;
2947 }
2948
2949 static int alloc_passthrough_domain(void)
2950 {
2951 if (pt_domain != NULL)
2952 return 0;
2953
2954 /* allocate passthrough domain */
2955 pt_domain = protection_domain_alloc();
2956 if (!pt_domain)
2957 return -ENOMEM;
2958
2959 pt_domain->mode = PAGE_MODE_NONE;
2960
2961 return 0;
2962 }
2963
2964 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2965 {
2966 struct protection_domain *pdomain;
2967 struct dma_ops_domain *dma_domain;
2968
2969 switch (type) {
2970 case IOMMU_DOMAIN_UNMANAGED:
2971 pdomain = protection_domain_alloc();
2972 if (!pdomain)
2973 return NULL;
2974
2975 pdomain->mode = PAGE_MODE_3_LEVEL;
2976 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2977 if (!pdomain->pt_root) {
2978 protection_domain_free(pdomain);
2979 return NULL;
2980 }
2981
2982 pdomain->domain.geometry.aperture_start = 0;
2983 pdomain->domain.geometry.aperture_end = ~0ULL;
2984 pdomain->domain.geometry.force_aperture = true;
2985
2986 break;
2987 case IOMMU_DOMAIN_DMA:
2988 dma_domain = dma_ops_domain_alloc();
2989 if (!dma_domain) {
2990 pr_err("AMD-Vi: Failed to allocate\n");
2991 return NULL;
2992 }
2993 pdomain = &dma_domain->domain;
2994 break;
2995 case IOMMU_DOMAIN_IDENTITY:
2996 pdomain = protection_domain_alloc();
2997 if (!pdomain)
2998 return NULL;
2999
3000 pdomain->mode = PAGE_MODE_NONE;
3001 break;
3002 default:
3003 return NULL;
3004 }
3005
3006 return &pdomain->domain;
3007 }
3008
3009 static void amd_iommu_domain_free(struct iommu_domain *dom)
3010 {
3011 struct protection_domain *domain;
3012
3013 if (!dom)
3014 return;
3015
3016 domain = to_pdomain(dom);
3017
3018 if (domain->dev_cnt > 0)
3019 cleanup_domain(domain);
3020
3021 BUG_ON(domain->dev_cnt != 0);
3022
3023 if (domain->mode != PAGE_MODE_NONE)
3024 free_pagetable(domain);
3025
3026 if (domain->flags & PD_IOMMUV2_MASK)
3027 free_gcr3_table(domain);
3028
3029 protection_domain_free(domain);
3030 }
3031
3032 static void amd_iommu_detach_device(struct iommu_domain *dom,
3033 struct device *dev)
3034 {
3035 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3036 struct amd_iommu *iommu;
3037 u16 devid;
3038
3039 if (!check_device(dev))
3040 return;
3041
3042 devid = get_device_id(dev);
3043
3044 if (dev_data->domain != NULL)
3045 detach_device(dev);
3046
3047 iommu = amd_iommu_rlookup_table[devid];
3048 if (!iommu)
3049 return;
3050
3051 iommu_completion_wait(iommu);
3052 }
3053
3054 static int amd_iommu_attach_device(struct iommu_domain *dom,
3055 struct device *dev)
3056 {
3057 struct protection_domain *domain = to_pdomain(dom);
3058 struct iommu_dev_data *dev_data;
3059 struct amd_iommu *iommu;
3060 int ret;
3061
3062 if (!check_device(dev))
3063 return -EINVAL;
3064
3065 dev_data = dev->archdata.iommu;
3066
3067 iommu = amd_iommu_rlookup_table[dev_data->devid];
3068 if (!iommu)
3069 return -EINVAL;
3070
3071 if (dev_data->domain)
3072 detach_device(dev);
3073
3074 ret = attach_device(dev, domain);
3075
3076 iommu_completion_wait(iommu);
3077
3078 return ret;
3079 }
3080
3081 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3082 phys_addr_t paddr, size_t page_size, int iommu_prot)
3083 {
3084 struct protection_domain *domain = to_pdomain(dom);
3085 int prot = 0;
3086 int ret;
3087
3088 if (domain->mode == PAGE_MODE_NONE)
3089 return -EINVAL;
3090
3091 if (iommu_prot & IOMMU_READ)
3092 prot |= IOMMU_PROT_IR;
3093 if (iommu_prot & IOMMU_WRITE)
3094 prot |= IOMMU_PROT_IW;
3095
3096 mutex_lock(&domain->api_lock);
3097 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3098 mutex_unlock(&domain->api_lock);
3099
3100 return ret;
3101 }
3102
3103 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3104 size_t page_size)
3105 {
3106 struct protection_domain *domain = to_pdomain(dom);
3107 size_t unmap_size;
3108
3109 if (domain->mode == PAGE_MODE_NONE)
3110 return -EINVAL;
3111
3112 mutex_lock(&domain->api_lock);
3113 unmap_size = iommu_unmap_page(domain, iova, page_size);
3114 mutex_unlock(&domain->api_lock);
3115
3116 domain_flush_tlb_pde(domain);
3117
3118 return unmap_size;
3119 }
3120
3121 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3122 dma_addr_t iova)
3123 {
3124 struct protection_domain *domain = to_pdomain(dom);
3125 unsigned long offset_mask, pte_pgsize;
3126 u64 *pte, __pte;
3127
3128 if (domain->mode == PAGE_MODE_NONE)
3129 return iova;
3130
3131 pte = fetch_pte(domain, iova, &pte_pgsize);
3132
3133 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3134 return 0;
3135
3136 offset_mask = pte_pgsize - 1;
3137 __pte = *pte & PM_ADDR_MASK;
3138
3139 return (__pte & ~offset_mask) | (iova & offset_mask);
3140 }
3141
3142 static bool amd_iommu_capable(enum iommu_cap cap)
3143 {
3144 switch (cap) {
3145 case IOMMU_CAP_CACHE_COHERENCY:
3146 return true;
3147 case IOMMU_CAP_INTR_REMAP:
3148 return (irq_remapping_enabled == 1);
3149 case IOMMU_CAP_NOEXEC:
3150 return false;
3151 }
3152
3153 return false;
3154 }
3155
3156 static void amd_iommu_get_dm_regions(struct device *dev,
3157 struct list_head *head)
3158 {
3159 struct unity_map_entry *entry;
3160 u16 devid;
3161
3162 devid = get_device_id(dev);
3163
3164 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3165 struct iommu_dm_region *region;
3166
3167 if (devid < entry->devid_start || devid > entry->devid_end)
3168 continue;
3169
3170 region = kzalloc(sizeof(*region), GFP_KERNEL);
3171 if (!region) {
3172 pr_err("Out of memory allocating dm-regions for %s\n",
3173 dev_name(dev));
3174 return;
3175 }
3176
3177 region->start = entry->address_start;
3178 region->length = entry->address_end - entry->address_start;
3179 if (entry->prot & IOMMU_PROT_IR)
3180 region->prot |= IOMMU_READ;
3181 if (entry->prot & IOMMU_PROT_IW)
3182 region->prot |= IOMMU_WRITE;
3183
3184 list_add_tail(&region->list, head);
3185 }
3186 }
3187
3188 static void amd_iommu_put_dm_regions(struct device *dev,
3189 struct list_head *head)
3190 {
3191 struct iommu_dm_region *entry, *next;
3192
3193 list_for_each_entry_safe(entry, next, head, list)
3194 kfree(entry);
3195 }
3196
3197 static const struct iommu_ops amd_iommu_ops = {
3198 .capable = amd_iommu_capable,
3199 .domain_alloc = amd_iommu_domain_alloc,
3200 .domain_free = amd_iommu_domain_free,
3201 .attach_dev = amd_iommu_attach_device,
3202 .detach_dev = amd_iommu_detach_device,
3203 .map = amd_iommu_map,
3204 .unmap = amd_iommu_unmap,
3205 .map_sg = default_iommu_map_sg,
3206 .iova_to_phys = amd_iommu_iova_to_phys,
3207 .add_device = amd_iommu_add_device,
3208 .remove_device = amd_iommu_remove_device,
3209 .get_dm_regions = amd_iommu_get_dm_regions,
3210 .put_dm_regions = amd_iommu_put_dm_regions,
3211 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3212 };
3213
3214 /*****************************************************************************
3215 *
3216 * The next functions do a basic initialization of IOMMU for pass through
3217 * mode
3218 *
3219 * In passthrough mode the IOMMU is initialized and enabled but not used for
3220 * DMA-API translation.
3221 *
3222 *****************************************************************************/
3223
3224 int __init amd_iommu_init_passthrough(void)
3225 {
3226 struct iommu_dev_data *dev_data;
3227 struct pci_dev *dev = NULL;
3228 int ret;
3229
3230 ret = alloc_passthrough_domain();
3231 if (ret)
3232 return ret;
3233
3234 for_each_pci_dev(dev) {
3235 if (!check_device(&dev->dev))
3236 continue;
3237
3238 dev_data = get_dev_data(&dev->dev);
3239 dev_data->passthrough = true;
3240
3241 attach_device(&dev->dev, pt_domain);
3242 }
3243
3244 amd_iommu_stats_init();
3245
3246 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3247
3248 return 0;
3249 }
3250
3251 /* IOMMUv2 specific functions */
3252 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3253 {
3254 return atomic_notifier_chain_register(&ppr_notifier, nb);
3255 }
3256 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3257
3258 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3259 {
3260 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3261 }
3262 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3263
3264 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3265 {
3266 struct protection_domain *domain = to_pdomain(dom);
3267 unsigned long flags;
3268
3269 spin_lock_irqsave(&domain->lock, flags);
3270
3271 /* Update data structure */
3272 domain->mode = PAGE_MODE_NONE;
3273 domain->updated = true;
3274
3275 /* Make changes visible to IOMMUs */
3276 update_domain(domain);
3277
3278 /* Page-table is not visible to IOMMU anymore, so free it */
3279 free_pagetable(domain);
3280
3281 spin_unlock_irqrestore(&domain->lock, flags);
3282 }
3283 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3284
3285 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3286 {
3287 struct protection_domain *domain = to_pdomain(dom);
3288 unsigned long flags;
3289 int levels, ret;
3290
3291 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3292 return -EINVAL;
3293
3294 /* Number of GCR3 table levels required */
3295 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3296 levels += 1;
3297
3298 if (levels > amd_iommu_max_glx_val)
3299 return -EINVAL;
3300
3301 spin_lock_irqsave(&domain->lock, flags);
3302
3303 /*
3304 * Save us all sanity checks whether devices already in the
3305 * domain support IOMMUv2. Just force that the domain has no
3306 * devices attached when it is switched into IOMMUv2 mode.
3307 */
3308 ret = -EBUSY;
3309 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3310 goto out;
3311
3312 ret = -ENOMEM;
3313 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3314 if (domain->gcr3_tbl == NULL)
3315 goto out;
3316
3317 domain->glx = levels;
3318 domain->flags |= PD_IOMMUV2_MASK;
3319 domain->updated = true;
3320
3321 update_domain(domain);
3322
3323 ret = 0;
3324
3325 out:
3326 spin_unlock_irqrestore(&domain->lock, flags);
3327
3328 return ret;
3329 }
3330 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3331
3332 static int __flush_pasid(struct protection_domain *domain, int pasid,
3333 u64 address, bool size)
3334 {
3335 struct iommu_dev_data *dev_data;
3336 struct iommu_cmd cmd;
3337 int i, ret;
3338
3339 if (!(domain->flags & PD_IOMMUV2_MASK))
3340 return -EINVAL;
3341
3342 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3343
3344 /*
3345 * IOMMU TLB needs to be flushed before Device TLB to
3346 * prevent device TLB refill from IOMMU TLB
3347 */
3348 for (i = 0; i < amd_iommus_present; ++i) {
3349 if (domain->dev_iommu[i] == 0)
3350 continue;
3351
3352 ret = iommu_queue_command(amd_iommus[i], &cmd);
3353 if (ret != 0)
3354 goto out;
3355 }
3356
3357 /* Wait until IOMMU TLB flushes are complete */
3358 domain_flush_complete(domain);
3359
3360 /* Now flush device TLBs */
3361 list_for_each_entry(dev_data, &domain->dev_list, list) {
3362 struct amd_iommu *iommu;
3363 int qdep;
3364
3365 BUG_ON(!dev_data->ats.enabled);
3366
3367 qdep = dev_data->ats.qdep;
3368 iommu = amd_iommu_rlookup_table[dev_data->devid];
3369
3370 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3371 qdep, address, size);
3372
3373 ret = iommu_queue_command(iommu, &cmd);
3374 if (ret != 0)
3375 goto out;
3376 }
3377
3378 /* Wait until all device TLBs are flushed */
3379 domain_flush_complete(domain);
3380
3381 ret = 0;
3382
3383 out:
3384
3385 return ret;
3386 }
3387
3388 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3389 u64 address)
3390 {
3391 INC_STATS_COUNTER(invalidate_iotlb);
3392
3393 return __flush_pasid(domain, pasid, address, false);
3394 }
3395
3396 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3397 u64 address)
3398 {
3399 struct protection_domain *domain = to_pdomain(dom);
3400 unsigned long flags;
3401 int ret;
3402
3403 spin_lock_irqsave(&domain->lock, flags);
3404 ret = __amd_iommu_flush_page(domain, pasid, address);
3405 spin_unlock_irqrestore(&domain->lock, flags);
3406
3407 return ret;
3408 }
3409 EXPORT_SYMBOL(amd_iommu_flush_page);
3410
3411 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3412 {
3413 INC_STATS_COUNTER(invalidate_iotlb_all);
3414
3415 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3416 true);
3417 }
3418
3419 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3420 {
3421 struct protection_domain *domain = to_pdomain(dom);
3422 unsigned long flags;
3423 int ret;
3424
3425 spin_lock_irqsave(&domain->lock, flags);
3426 ret = __amd_iommu_flush_tlb(domain, pasid);
3427 spin_unlock_irqrestore(&domain->lock, flags);
3428
3429 return ret;
3430 }
3431 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3432
3433 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3434 {
3435 int index;
3436 u64 *pte;
3437
3438 while (true) {
3439
3440 index = (pasid >> (9 * level)) & 0x1ff;
3441 pte = &root[index];
3442
3443 if (level == 0)
3444 break;
3445
3446 if (!(*pte & GCR3_VALID)) {
3447 if (!alloc)
3448 return NULL;
3449
3450 root = (void *)get_zeroed_page(GFP_ATOMIC);
3451 if (root == NULL)
3452 return NULL;
3453
3454 *pte = __pa(root) | GCR3_VALID;
3455 }
3456
3457 root = __va(*pte & PAGE_MASK);
3458
3459 level -= 1;
3460 }
3461
3462 return pte;
3463 }
3464
3465 static int __set_gcr3(struct protection_domain *domain, int pasid,
3466 unsigned long cr3)
3467 {
3468 u64 *pte;
3469
3470 if (domain->mode != PAGE_MODE_NONE)
3471 return -EINVAL;
3472
3473 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3474 if (pte == NULL)
3475 return -ENOMEM;
3476
3477 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3478
3479 return __amd_iommu_flush_tlb(domain, pasid);
3480 }
3481
3482 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3483 {
3484 u64 *pte;
3485
3486 if (domain->mode != PAGE_MODE_NONE)
3487 return -EINVAL;
3488
3489 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3490 if (pte == NULL)
3491 return 0;
3492
3493 *pte = 0;
3494
3495 return __amd_iommu_flush_tlb(domain, pasid);
3496 }
3497
3498 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3499 unsigned long cr3)
3500 {
3501 struct protection_domain *domain = to_pdomain(dom);
3502 unsigned long flags;
3503 int ret;
3504
3505 spin_lock_irqsave(&domain->lock, flags);
3506 ret = __set_gcr3(domain, pasid, cr3);
3507 spin_unlock_irqrestore(&domain->lock, flags);
3508
3509 return ret;
3510 }
3511 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3512
3513 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3514 {
3515 struct protection_domain *domain = to_pdomain(dom);
3516 unsigned long flags;
3517 int ret;
3518
3519 spin_lock_irqsave(&domain->lock, flags);
3520 ret = __clear_gcr3(domain, pasid);
3521 spin_unlock_irqrestore(&domain->lock, flags);
3522
3523 return ret;
3524 }
3525 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3526
3527 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3528 int status, int tag)
3529 {
3530 struct iommu_dev_data *dev_data;
3531 struct amd_iommu *iommu;
3532 struct iommu_cmd cmd;
3533
3534 INC_STATS_COUNTER(complete_ppr);
3535
3536 dev_data = get_dev_data(&pdev->dev);
3537 iommu = amd_iommu_rlookup_table[dev_data->devid];
3538
3539 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3540 tag, dev_data->pri_tlp);
3541
3542 return iommu_queue_command(iommu, &cmd);
3543 }
3544 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3545
3546 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3547 {
3548 struct protection_domain *pdomain;
3549
3550 pdomain = get_domain(&pdev->dev);
3551 if (IS_ERR(pdomain))
3552 return NULL;
3553
3554 /* Only return IOMMUv2 domains */
3555 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3556 return NULL;
3557
3558 return &pdomain->domain;
3559 }
3560 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3561
3562 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3563 {
3564 struct iommu_dev_data *dev_data;
3565
3566 if (!amd_iommu_v2_supported())
3567 return;
3568
3569 dev_data = get_dev_data(&pdev->dev);
3570 dev_data->errata |= (1 << erratum);
3571 }
3572 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3573
3574 int amd_iommu_device_info(struct pci_dev *pdev,
3575 struct amd_iommu_device_info *info)
3576 {
3577 int max_pasids;
3578 int pos;
3579
3580 if (pdev == NULL || info == NULL)
3581 return -EINVAL;
3582
3583 if (!amd_iommu_v2_supported())
3584 return -EINVAL;
3585
3586 memset(info, 0, sizeof(*info));
3587
3588 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3589 if (pos)
3590 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3591
3592 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3593 if (pos)
3594 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3595
3596 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3597 if (pos) {
3598 int features;
3599
3600 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3601 max_pasids = min(max_pasids, (1 << 20));
3602
3603 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3604 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3605
3606 features = pci_pasid_features(pdev);
3607 if (features & PCI_PASID_CAP_EXEC)
3608 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3609 if (features & PCI_PASID_CAP_PRIV)
3610 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3611 }
3612
3613 return 0;
3614 }
3615 EXPORT_SYMBOL(amd_iommu_device_info);
3616
3617 #ifdef CONFIG_IRQ_REMAP
3618
3619 /*****************************************************************************
3620 *
3621 * Interrupt Remapping Implementation
3622 *
3623 *****************************************************************************/
3624
3625 union irte {
3626 u32 val;
3627 struct {
3628 u32 valid : 1,
3629 no_fault : 1,
3630 int_type : 3,
3631 rq_eoi : 1,
3632 dm : 1,
3633 rsvd_1 : 1,
3634 destination : 8,
3635 vector : 8,
3636 rsvd_2 : 8;
3637 } fields;
3638 };
3639
3640 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3641 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3642 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3643 #define DTE_IRQ_REMAP_ENABLE 1ULL
3644
3645 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3646 {
3647 u64 dte;
3648
3649 dte = amd_iommu_dev_table[devid].data[2];
3650 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3651 dte |= virt_to_phys(table->table);
3652 dte |= DTE_IRQ_REMAP_INTCTL;
3653 dte |= DTE_IRQ_TABLE_LEN;
3654 dte |= DTE_IRQ_REMAP_ENABLE;
3655
3656 amd_iommu_dev_table[devid].data[2] = dte;
3657 }
3658
3659 #define IRTE_ALLOCATED (~1U)
3660
3661 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3662 {
3663 struct irq_remap_table *table = NULL;
3664 struct amd_iommu *iommu;
3665 unsigned long flags;
3666 u16 alias;
3667
3668 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3669
3670 iommu = amd_iommu_rlookup_table[devid];
3671 if (!iommu)
3672 goto out_unlock;
3673
3674 table = irq_lookup_table[devid];
3675 if (table)
3676 goto out;
3677
3678 alias = amd_iommu_alias_table[devid];
3679 table = irq_lookup_table[alias];
3680 if (table) {
3681 irq_lookup_table[devid] = table;
3682 set_dte_irq_entry(devid, table);
3683 iommu_flush_dte(iommu, devid);
3684 goto out;
3685 }
3686
3687 /* Nothing there yet, allocate new irq remapping table */
3688 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3689 if (!table)
3690 goto out;
3691
3692 /* Initialize table spin-lock */
3693 spin_lock_init(&table->lock);
3694
3695 if (ioapic)
3696 /* Keep the first 32 indexes free for IOAPIC interrupts */
3697 table->min_index = 32;
3698
3699 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3700 if (!table->table) {
3701 kfree(table);
3702 table = NULL;
3703 goto out;
3704 }
3705
3706 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3707
3708 if (ioapic) {
3709 int i;
3710
3711 for (i = 0; i < 32; ++i)
3712 table->table[i] = IRTE_ALLOCATED;
3713 }
3714
3715 irq_lookup_table[devid] = table;
3716 set_dte_irq_entry(devid, table);
3717 iommu_flush_dte(iommu, devid);
3718 if (devid != alias) {
3719 irq_lookup_table[alias] = table;
3720 set_dte_irq_entry(alias, table);
3721 iommu_flush_dte(iommu, alias);
3722 }
3723
3724 out:
3725 iommu_completion_wait(iommu);
3726
3727 out_unlock:
3728 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3729
3730 return table;
3731 }
3732
3733 static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3734 {
3735 struct irq_remap_table *table;
3736 unsigned long flags;
3737 int index, c;
3738
3739 table = get_irq_table(devid, false);
3740 if (!table)
3741 return -ENODEV;
3742
3743 spin_lock_irqsave(&table->lock, flags);
3744
3745 /* Scan table for free entries */
3746 for (c = 0, index = table->min_index;
3747 index < MAX_IRQS_PER_TABLE;
3748 ++index) {
3749 if (table->table[index] == 0)
3750 c += 1;
3751 else
3752 c = 0;
3753
3754 if (c == count) {
3755 struct irq_2_irte *irte_info;
3756
3757 for (; c != 0; --c)
3758 table->table[index - c + 1] = IRTE_ALLOCATED;
3759
3760 index -= count - 1;
3761
3762 cfg->remapped = 1;
3763 irte_info = &cfg->irq_2_irte;
3764 irte_info->devid = devid;
3765 irte_info->index = index;
3766
3767 goto out;
3768 }
3769 }
3770
3771 index = -ENOSPC;
3772
3773 out:
3774 spin_unlock_irqrestore(&table->lock, flags);
3775
3776 return index;
3777 }
3778
3779 static int get_irte(u16 devid, int index, union irte *irte)
3780 {
3781 struct irq_remap_table *table;
3782 unsigned long flags;
3783
3784 table = get_irq_table(devid, false);
3785 if (!table)
3786 return -ENOMEM;
3787
3788 spin_lock_irqsave(&table->lock, flags);
3789 irte->val = table->table[index];
3790 spin_unlock_irqrestore(&table->lock, flags);
3791
3792 return 0;
3793 }
3794
3795 static int modify_irte(u16 devid, int index, union irte irte)
3796 {
3797 struct irq_remap_table *table;
3798 struct amd_iommu *iommu;
3799 unsigned long flags;
3800
3801 iommu = amd_iommu_rlookup_table[devid];
3802 if (iommu == NULL)
3803 return -EINVAL;
3804
3805 table = get_irq_table(devid, false);
3806 if (!table)
3807 return -ENOMEM;
3808
3809 spin_lock_irqsave(&table->lock, flags);
3810 table->table[index] = irte.val;
3811 spin_unlock_irqrestore(&table->lock, flags);
3812
3813 iommu_flush_irt(iommu, devid);
3814 iommu_completion_wait(iommu);
3815
3816 return 0;
3817 }
3818
3819 static void free_irte(u16 devid, int index)
3820 {
3821 struct irq_remap_table *table;
3822 struct amd_iommu *iommu;
3823 unsigned long flags;
3824
3825 iommu = amd_iommu_rlookup_table[devid];
3826 if (iommu == NULL)
3827 return;
3828
3829 table = get_irq_table(devid, false);
3830 if (!table)
3831 return;
3832
3833 spin_lock_irqsave(&table->lock, flags);
3834 table->table[index] = 0;
3835 spin_unlock_irqrestore(&table->lock, flags);
3836
3837 iommu_flush_irt(iommu, devid);
3838 iommu_completion_wait(iommu);
3839 }
3840
3841 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
3842 unsigned int destination, int vector,
3843 struct io_apic_irq_attr *attr)
3844 {
3845 struct irq_remap_table *table;
3846 struct irq_2_irte *irte_info;
3847 struct irq_cfg *cfg;
3848 union irte irte;
3849 int ioapic_id;
3850 int index;
3851 int devid;
3852 int ret;
3853
3854 cfg = irq_cfg(irq);
3855 if (!cfg)
3856 return -EINVAL;
3857
3858 irte_info = &cfg->irq_2_irte;
3859 ioapic_id = mpc_ioapic_id(attr->ioapic);
3860 devid = get_ioapic_devid(ioapic_id);
3861
3862 if (devid < 0)
3863 return devid;
3864
3865 table = get_irq_table(devid, true);
3866 if (table == NULL)
3867 return -ENOMEM;
3868
3869 index = attr->ioapic_pin;
3870
3871 /* Setup IRQ remapping info */
3872 cfg->remapped = 1;
3873 irte_info->devid = devid;
3874 irte_info->index = index;
3875
3876 /* Setup IRTE for IOMMU */
3877 irte.val = 0;
3878 irte.fields.vector = vector;
3879 irte.fields.int_type = apic->irq_delivery_mode;
3880 irte.fields.destination = destination;
3881 irte.fields.dm = apic->irq_dest_mode;
3882 irte.fields.valid = 1;
3883
3884 ret = modify_irte(devid, index, irte);
3885 if (ret)
3886 return ret;
3887
3888 /* Setup IOAPIC entry */
3889 memset(entry, 0, sizeof(*entry));
3890
3891 entry->vector = index;
3892 entry->mask = 0;
3893 entry->trigger = attr->trigger;
3894 entry->polarity = attr->polarity;
3895
3896 /*
3897 * Mask level triggered irqs.
3898 */
3899 if (attr->trigger)
3900 entry->mask = 1;
3901
3902 return 0;
3903 }
3904
3905 static int set_affinity(struct irq_data *data, const struct cpumask *mask,
3906 bool force)
3907 {
3908 struct irq_2_irte *irte_info;
3909 unsigned int dest, irq;
3910 struct irq_cfg *cfg;
3911 union irte irte;
3912 int err;
3913
3914 if (!config_enabled(CONFIG_SMP))
3915 return -1;
3916
3917 cfg = irqd_cfg(data);
3918 irq = data->irq;
3919 irte_info = &cfg->irq_2_irte;
3920
3921 if (!cpumask_intersects(mask, cpu_online_mask))
3922 return -EINVAL;
3923
3924 if (get_irte(irte_info->devid, irte_info->index, &irte))
3925 return -EBUSY;
3926
3927 if (assign_irq_vector(irq, cfg, mask))
3928 return -EBUSY;
3929
3930 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
3931 if (err) {
3932 if (assign_irq_vector(irq, cfg, data->affinity))
3933 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
3934 return err;
3935 }
3936
3937 irte.fields.vector = cfg->vector;
3938 irte.fields.destination = dest;
3939
3940 modify_irte(irte_info->devid, irte_info->index, irte);
3941
3942 if (cfg->move_in_progress)
3943 send_cleanup_vector(cfg);
3944
3945 cpumask_copy(data->affinity, mask);
3946
3947 return 0;
3948 }
3949
3950 static int free_irq(int irq)
3951 {
3952 struct irq_2_irte *irte_info;
3953 struct irq_cfg *cfg;
3954
3955 cfg = irq_cfg(irq);
3956 if (!cfg)
3957 return -EINVAL;
3958
3959 irte_info = &cfg->irq_2_irte;
3960
3961 free_irte(irte_info->devid, irte_info->index);
3962
3963 return 0;
3964 }
3965
3966 static void compose_msi_msg(struct pci_dev *pdev,
3967 unsigned int irq, unsigned int dest,
3968 struct msi_msg *msg, u8 hpet_id)
3969 {
3970 struct irq_2_irte *irte_info;
3971 struct irq_cfg *cfg;
3972 union irte irte;
3973
3974 cfg = irq_cfg(irq);
3975 if (!cfg)
3976 return;
3977
3978 irte_info = &cfg->irq_2_irte;
3979
3980 irte.val = 0;
3981 irte.fields.vector = cfg->vector;
3982 irte.fields.int_type = apic->irq_delivery_mode;
3983 irte.fields.destination = dest;
3984 irte.fields.dm = apic->irq_dest_mode;
3985 irte.fields.valid = 1;
3986
3987 modify_irte(irte_info->devid, irte_info->index, irte);
3988
3989 msg->address_hi = MSI_ADDR_BASE_HI;
3990 msg->address_lo = MSI_ADDR_BASE_LO;
3991 msg->data = irte_info->index;
3992 }
3993
3994 static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
3995 {
3996 struct irq_cfg *cfg;
3997 int index;
3998 u16 devid;
3999
4000 if (!pdev)
4001 return -EINVAL;
4002
4003 cfg = irq_cfg(irq);
4004 if (!cfg)
4005 return -EINVAL;
4006
4007 devid = get_device_id(&pdev->dev);
4008 index = alloc_irq_index(cfg, devid, nvec);
4009
4010 return index < 0 ? MAX_IRQS_PER_TABLE : index;
4011 }
4012
4013 static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4014 int index, int offset)
4015 {
4016 struct irq_2_irte *irte_info;
4017 struct irq_cfg *cfg;
4018 u16 devid;
4019
4020 if (!pdev)
4021 return -EINVAL;
4022
4023 cfg = irq_cfg(irq);
4024 if (!cfg)
4025 return -EINVAL;
4026
4027 if (index >= MAX_IRQS_PER_TABLE)
4028 return 0;
4029
4030 devid = get_device_id(&pdev->dev);
4031 irte_info = &cfg->irq_2_irte;
4032
4033 cfg->remapped = 1;
4034 irte_info->devid = devid;
4035 irte_info->index = index + offset;
4036
4037 return 0;
4038 }
4039
4040 static int alloc_hpet_msi(unsigned int irq, unsigned int id)
4041 {
4042 struct irq_2_irte *irte_info;
4043 struct irq_cfg *cfg;
4044 int index, devid;
4045
4046 cfg = irq_cfg(irq);
4047 if (!cfg)
4048 return -EINVAL;
4049
4050 irte_info = &cfg->irq_2_irte;
4051 devid = get_hpet_devid(id);
4052 if (devid < 0)
4053 return devid;
4054
4055 index = alloc_irq_index(cfg, devid, 1);
4056 if (index < 0)
4057 return index;
4058
4059 cfg->remapped = 1;
4060 irte_info->devid = devid;
4061 irte_info->index = index;
4062
4063 return 0;
4064 }
4065
4066 struct irq_remap_ops amd_iommu_irq_ops = {
4067 .prepare = amd_iommu_prepare,
4068 .enable = amd_iommu_enable,
4069 .disable = amd_iommu_disable,
4070 .reenable = amd_iommu_reenable,
4071 .enable_faulting = amd_iommu_enable_faulting,
4072 .setup_ioapic_entry = setup_ioapic_entry,
4073 .set_affinity = set_affinity,
4074 .free_irq = free_irq,
4075 .compose_msi_msg = compose_msi_msg,
4076 .msi_alloc_irq = msi_alloc_irq,
4077 .msi_setup_irq = msi_setup_irq,
4078 .alloc_hpet_msi = alloc_hpet_msi,
4079 };
4080 #endif
Linux kernel - Deliverables
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