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iommu/amd: Handle errors returned from iommu_init_device
[deliverable/linux.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <linux/dma-contiguous.h>
37 #include <asm/irq_remapping.h>
38 #include <asm/io_apic.h>
39 #include <asm/apic.h>
40 #include <asm/hw_irq.h>
41 #include <asm/msidef.h>
42 #include <asm/proto.h>
43 #include <asm/iommu.h>
44 #include <asm/gart.h>
45 #include <asm/dma.h>
46
47 #include "amd_iommu_proto.h"
48 #include "amd_iommu_types.h"
49 #include "irq_remapping.h"
50
51 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
52
53 #define LOOP_TIMEOUT 100000
54
55 /*
56 * This bitmap is used to advertise the page sizes our hardware support
57 * to the IOMMU core, which will then use this information to split
58 * physically contiguous memory regions it is mapping into page sizes
59 * that we support.
60 *
61 * 512GB Pages are not supported due to a hardware bug
62 */
63 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
64
65 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
66
67 /* List of all available dev_data structures */
68 static LIST_HEAD(dev_data_list);
69 static DEFINE_SPINLOCK(dev_data_list_lock);
70
71 LIST_HEAD(ioapic_map);
72 LIST_HEAD(hpet_map);
73
74 /*
75 * Domain for untranslated devices - only allocated
76 * if iommu=pt passed on kernel cmd line.
77 */
78 static struct protection_domain *pt_domain;
79
80 static const struct iommu_ops amd_iommu_ops;
81
82 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
83 int amd_iommu_max_glx_val = -1;
84
85 static struct dma_map_ops amd_iommu_dma_ops;
86
87 /*
88 * This struct contains device specific data for the IOMMU
89 */
90 struct iommu_dev_data {
91 struct list_head list; /* For domain->dev_list */
92 struct list_head dev_data_list; /* For global dev_data_list */
93 struct list_head alias_list; /* Link alias-groups together */
94 struct iommu_dev_data *alias_data;/* The alias dev_data */
95 struct protection_domain *domain; /* Domain the device is bound to */
96 u16 devid; /* PCI Device ID */
97 bool iommu_v2; /* Device can make use of IOMMUv2 */
98 bool passthrough; /* Default for device is pt_domain */
99 struct {
100 bool enabled;
101 int qdep;
102 } ats; /* ATS state */
103 bool pri_tlp; /* PASID TLB required for
104 PPR completions */
105 u32 errata; /* Bitmap for errata to apply */
106 };
107
108 /*
109 * general struct to manage commands send to an IOMMU
110 */
111 struct iommu_cmd {
112 u32 data[4];
113 };
114
115 struct kmem_cache *amd_iommu_irq_cache;
116
117 static void update_domain(struct protection_domain *domain);
118 static int alloc_passthrough_domain(void);
119
120 /****************************************************************************
121 *
122 * Helper functions
123 *
124 ****************************************************************************/
125
126 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
127 {
128 return container_of(dom, struct protection_domain, domain);
129 }
130
131 static struct iommu_dev_data *alloc_dev_data(u16 devid)
132 {
133 struct iommu_dev_data *dev_data;
134 unsigned long flags;
135
136 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
137 if (!dev_data)
138 return NULL;
139
140 INIT_LIST_HEAD(&dev_data->alias_list);
141
142 dev_data->devid = devid;
143
144 spin_lock_irqsave(&dev_data_list_lock, flags);
145 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
146 spin_unlock_irqrestore(&dev_data_list_lock, flags);
147
148 return dev_data;
149 }
150
151 static void free_dev_data(struct iommu_dev_data *dev_data)
152 {
153 unsigned long flags;
154
155 spin_lock_irqsave(&dev_data_list_lock, flags);
156 list_del(&dev_data->dev_data_list);
157 spin_unlock_irqrestore(&dev_data_list_lock, flags);
158
159 kfree(dev_data);
160 }
161
162 static struct iommu_dev_data *search_dev_data(u16 devid)
163 {
164 struct iommu_dev_data *dev_data;
165 unsigned long flags;
166
167 spin_lock_irqsave(&dev_data_list_lock, flags);
168 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
169 if (dev_data->devid == devid)
170 goto out_unlock;
171 }
172
173 dev_data = NULL;
174
175 out_unlock:
176 spin_unlock_irqrestore(&dev_data_list_lock, flags);
177
178 return dev_data;
179 }
180
181 static struct iommu_dev_data *find_dev_data(u16 devid)
182 {
183 struct iommu_dev_data *dev_data;
184
185 dev_data = search_dev_data(devid);
186
187 if (dev_data == NULL)
188 dev_data = alloc_dev_data(devid);
189
190 return dev_data;
191 }
192
193 static inline u16 get_device_id(struct device *dev)
194 {
195 struct pci_dev *pdev = to_pci_dev(dev);
196
197 return PCI_DEVID(pdev->bus->number, pdev->devfn);
198 }
199
200 static struct iommu_dev_data *get_dev_data(struct device *dev)
201 {
202 return dev->archdata.iommu;
203 }
204
205 static bool pci_iommuv2_capable(struct pci_dev *pdev)
206 {
207 static const int caps[] = {
208 PCI_EXT_CAP_ID_ATS,
209 PCI_EXT_CAP_ID_PRI,
210 PCI_EXT_CAP_ID_PASID,
211 };
212 int i, pos;
213
214 for (i = 0; i < 3; ++i) {
215 pos = pci_find_ext_capability(pdev, caps[i]);
216 if (pos == 0)
217 return false;
218 }
219
220 return true;
221 }
222
223 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
224 {
225 struct iommu_dev_data *dev_data;
226
227 dev_data = get_dev_data(&pdev->dev);
228
229 return dev_data->errata & (1 << erratum) ? true : false;
230 }
231
232 /*
233 * This function actually applies the mapping to the page table of the
234 * dma_ops domain.
235 */
236 static void alloc_unity_mapping(struct dma_ops_domain *dma_dom,
237 struct unity_map_entry *e)
238 {
239 u64 addr;
240
241 for (addr = e->address_start; addr < e->address_end;
242 addr += PAGE_SIZE) {
243 if (addr < dma_dom->aperture_size)
244 __set_bit(addr >> PAGE_SHIFT,
245 dma_dom->aperture[0]->bitmap);
246 }
247 }
248
249 /*
250 * Inits the unity mappings required for a specific device
251 */
252 static void init_unity_mappings_for_device(struct device *dev,
253 struct dma_ops_domain *dma_dom)
254 {
255 struct unity_map_entry *e;
256 u16 devid;
257
258 devid = get_device_id(dev);
259
260 list_for_each_entry(e, &amd_iommu_unity_map, list) {
261 if (!(devid >= e->devid_start && devid <= e->devid_end))
262 continue;
263 alloc_unity_mapping(dma_dom, e);
264 }
265 }
266
267 /*
268 * This function checks if the driver got a valid device from the caller to
269 * avoid dereferencing invalid pointers.
270 */
271 static bool check_device(struct device *dev)
272 {
273 u16 devid;
274
275 if (!dev || !dev->dma_mask)
276 return false;
277
278 /* No PCI device */
279 if (!dev_is_pci(dev))
280 return false;
281
282 devid = get_device_id(dev);
283
284 /* Out of our scope? */
285 if (devid > amd_iommu_last_bdf)
286 return false;
287
288 if (amd_iommu_rlookup_table[devid] == NULL)
289 return false;
290
291 return true;
292 }
293
294 static void init_iommu_group(struct device *dev)
295 {
296 struct dma_ops_domain *dma_domain;
297 struct iommu_domain *domain;
298 struct iommu_group *group;
299
300 group = iommu_group_get_for_dev(dev);
301 if (IS_ERR(group))
302 return;
303
304 domain = iommu_group_default_domain(group);
305 if (!domain)
306 goto out;
307
308 dma_domain = to_pdomain(domain)->priv;
309
310 init_unity_mappings_for_device(dev, dma_domain);
311 out:
312 iommu_group_put(group);
313 }
314
315 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
316 {
317 *(u16 *)data = alias;
318 return 0;
319 }
320
321 static u16 get_alias(struct device *dev)
322 {
323 struct pci_dev *pdev = to_pci_dev(dev);
324 u16 devid, ivrs_alias, pci_alias;
325
326 devid = get_device_id(dev);
327 ivrs_alias = amd_iommu_alias_table[devid];
328 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
329
330 if (ivrs_alias == pci_alias)
331 return ivrs_alias;
332
333 /*
334 * DMA alias showdown
335 *
336 * The IVRS is fairly reliable in telling us about aliases, but it
337 * can't know about every screwy device. If we don't have an IVRS
338 * reported alias, use the PCI reported alias. In that case we may
339 * still need to initialize the rlookup and dev_table entries if the
340 * alias is to a non-existent device.
341 */
342 if (ivrs_alias == devid) {
343 if (!amd_iommu_rlookup_table[pci_alias]) {
344 amd_iommu_rlookup_table[pci_alias] =
345 amd_iommu_rlookup_table[devid];
346 memcpy(amd_iommu_dev_table[pci_alias].data,
347 amd_iommu_dev_table[devid].data,
348 sizeof(amd_iommu_dev_table[pci_alias].data));
349 }
350
351 return pci_alias;
352 }
353
354 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
355 "for device %s[%04x:%04x], kernel reported alias "
356 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
357 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
358 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
359 PCI_FUNC(pci_alias));
360
361 /*
362 * If we don't have a PCI DMA alias and the IVRS alias is on the same
363 * bus, then the IVRS table may know about a quirk that we don't.
364 */
365 if (pci_alias == devid &&
366 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
367 pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
368 pdev->dma_alias_devfn = ivrs_alias & 0xff;
369 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
370 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
371 dev_name(dev));
372 }
373
374 return ivrs_alias;
375 }
376
377 static int iommu_init_device(struct device *dev)
378 {
379 struct pci_dev *pdev = to_pci_dev(dev);
380 struct iommu_dev_data *dev_data;
381 u16 alias;
382
383 if (dev->archdata.iommu)
384 return 0;
385
386 dev_data = find_dev_data(get_device_id(dev));
387 if (!dev_data)
388 return -ENOMEM;
389
390 alias = get_alias(dev);
391
392 if (alias != dev_data->devid) {
393 struct iommu_dev_data *alias_data;
394
395 alias_data = find_dev_data(alias);
396 if (alias_data == NULL) {
397 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
398 dev_name(dev));
399 free_dev_data(dev_data);
400 return -ENOTSUPP;
401 }
402 dev_data->alias_data = alias_data;
403
404 /* Add device to the alias_list */
405 list_add(&dev_data->alias_list, &alias_data->alias_list);
406 }
407
408 if (pci_iommuv2_capable(pdev)) {
409 struct amd_iommu *iommu;
410
411 iommu = amd_iommu_rlookup_table[dev_data->devid];
412 dev_data->iommu_v2 = iommu->is_iommu_v2;
413 }
414
415 dev->archdata.iommu = dev_data;
416
417 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
418 dev);
419
420 return 0;
421 }
422
423 static void iommu_ignore_device(struct device *dev)
424 {
425 u16 devid, alias;
426
427 devid = get_device_id(dev);
428 alias = amd_iommu_alias_table[devid];
429
430 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
431 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
432
433 amd_iommu_rlookup_table[devid] = NULL;
434 amd_iommu_rlookup_table[alias] = NULL;
435 }
436
437 static void iommu_uninit_device(struct device *dev)
438 {
439 struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev));
440
441 if (!dev_data)
442 return;
443
444 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
445 dev);
446
447 iommu_group_remove_device(dev);
448
449 /* Unlink from alias, it may change if another device is re-plugged */
450 dev_data->alias_data = NULL;
451
452 /* Remove dma-ops */
453 dev->archdata.dma_ops = NULL;
454
455 /*
456 * We keep dev_data around for unplugged devices and reuse it when the
457 * device is re-plugged - not doing so would introduce a ton of races.
458 */
459 }
460
461 #ifdef CONFIG_AMD_IOMMU_STATS
462
463 /*
464 * Initialization code for statistics collection
465 */
466
467 DECLARE_STATS_COUNTER(compl_wait);
468 DECLARE_STATS_COUNTER(cnt_map_single);
469 DECLARE_STATS_COUNTER(cnt_unmap_single);
470 DECLARE_STATS_COUNTER(cnt_map_sg);
471 DECLARE_STATS_COUNTER(cnt_unmap_sg);
472 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
473 DECLARE_STATS_COUNTER(cnt_free_coherent);
474 DECLARE_STATS_COUNTER(cross_page);
475 DECLARE_STATS_COUNTER(domain_flush_single);
476 DECLARE_STATS_COUNTER(domain_flush_all);
477 DECLARE_STATS_COUNTER(alloced_io_mem);
478 DECLARE_STATS_COUNTER(total_map_requests);
479 DECLARE_STATS_COUNTER(complete_ppr);
480 DECLARE_STATS_COUNTER(invalidate_iotlb);
481 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
482 DECLARE_STATS_COUNTER(pri_requests);
483
484 static struct dentry *stats_dir;
485 static struct dentry *de_fflush;
486
487 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
488 {
489 if (stats_dir == NULL)
490 return;
491
492 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
493 &cnt->value);
494 }
495
496 static void amd_iommu_stats_init(void)
497 {
498 stats_dir = debugfs_create_dir("amd-iommu", NULL);
499 if (stats_dir == NULL)
500 return;
501
502 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
503 &amd_iommu_unmap_flush);
504
505 amd_iommu_stats_add(&compl_wait);
506 amd_iommu_stats_add(&cnt_map_single);
507 amd_iommu_stats_add(&cnt_unmap_single);
508 amd_iommu_stats_add(&cnt_map_sg);
509 amd_iommu_stats_add(&cnt_unmap_sg);
510 amd_iommu_stats_add(&cnt_alloc_coherent);
511 amd_iommu_stats_add(&cnt_free_coherent);
512 amd_iommu_stats_add(&cross_page);
513 amd_iommu_stats_add(&domain_flush_single);
514 amd_iommu_stats_add(&domain_flush_all);
515 amd_iommu_stats_add(&alloced_io_mem);
516 amd_iommu_stats_add(&total_map_requests);
517 amd_iommu_stats_add(&complete_ppr);
518 amd_iommu_stats_add(&invalidate_iotlb);
519 amd_iommu_stats_add(&invalidate_iotlb_all);
520 amd_iommu_stats_add(&pri_requests);
521 }
522
523 #endif
524
525 /****************************************************************************
526 *
527 * Interrupt handling functions
528 *
529 ****************************************************************************/
530
531 static void dump_dte_entry(u16 devid)
532 {
533 int i;
534
535 for (i = 0; i < 4; ++i)
536 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
537 amd_iommu_dev_table[devid].data[i]);
538 }
539
540 static void dump_command(unsigned long phys_addr)
541 {
542 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
543 int i;
544
545 for (i = 0; i < 4; ++i)
546 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
547 }
548
549 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
550 {
551 int type, devid, domid, flags;
552 volatile u32 *event = __evt;
553 int count = 0;
554 u64 address;
555
556 retry:
557 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
558 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
559 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
560 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
561 address = (u64)(((u64)event[3]) << 32) | event[2];
562
563 if (type == 0) {
564 /* Did we hit the erratum? */
565 if (++count == LOOP_TIMEOUT) {
566 pr_err("AMD-Vi: No event written to event log\n");
567 return;
568 }
569 udelay(1);
570 goto retry;
571 }
572
573 printk(KERN_ERR "AMD-Vi: Event logged [");
574
575 switch (type) {
576 case EVENT_TYPE_ILL_DEV:
577 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
578 "address=0x%016llx flags=0x%04x]\n",
579 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
580 address, flags);
581 dump_dte_entry(devid);
582 break;
583 case EVENT_TYPE_IO_FAULT:
584 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
585 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
586 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
587 domid, address, flags);
588 break;
589 case EVENT_TYPE_DEV_TAB_ERR:
590 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
591 "address=0x%016llx flags=0x%04x]\n",
592 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
593 address, flags);
594 break;
595 case EVENT_TYPE_PAGE_TAB_ERR:
596 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
597 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
598 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
599 domid, address, flags);
600 break;
601 case EVENT_TYPE_ILL_CMD:
602 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
603 dump_command(address);
604 break;
605 case EVENT_TYPE_CMD_HARD_ERR:
606 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
607 "flags=0x%04x]\n", address, flags);
608 break;
609 case EVENT_TYPE_IOTLB_INV_TO:
610 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
611 "address=0x%016llx]\n",
612 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
613 address);
614 break;
615 case EVENT_TYPE_INV_DEV_REQ:
616 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
617 "address=0x%016llx flags=0x%04x]\n",
618 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
619 address, flags);
620 break;
621 default:
622 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
623 }
624
625 memset(__evt, 0, 4 * sizeof(u32));
626 }
627
628 static void iommu_poll_events(struct amd_iommu *iommu)
629 {
630 u32 head, tail;
631
632 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
633 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
634
635 while (head != tail) {
636 iommu_print_event(iommu, iommu->evt_buf + head);
637 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
638 }
639
640 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
641 }
642
643 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
644 {
645 struct amd_iommu_fault fault;
646
647 INC_STATS_COUNTER(pri_requests);
648
649 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
650 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
651 return;
652 }
653
654 fault.address = raw[1];
655 fault.pasid = PPR_PASID(raw[0]);
656 fault.device_id = PPR_DEVID(raw[0]);
657 fault.tag = PPR_TAG(raw[0]);
658 fault.flags = PPR_FLAGS(raw[0]);
659
660 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
661 }
662
663 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
664 {
665 u32 head, tail;
666
667 if (iommu->ppr_log == NULL)
668 return;
669
670 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
671 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
672
673 while (head != tail) {
674 volatile u64 *raw;
675 u64 entry[2];
676 int i;
677
678 raw = (u64 *)(iommu->ppr_log + head);
679
680 /*
681 * Hardware bug: Interrupt may arrive before the entry is
682 * written to memory. If this happens we need to wait for the
683 * entry to arrive.
684 */
685 for (i = 0; i < LOOP_TIMEOUT; ++i) {
686 if (PPR_REQ_TYPE(raw[0]) != 0)
687 break;
688 udelay(1);
689 }
690
691 /* Avoid memcpy function-call overhead */
692 entry[0] = raw[0];
693 entry[1] = raw[1];
694
695 /*
696 * To detect the hardware bug we need to clear the entry
697 * back to zero.
698 */
699 raw[0] = raw[1] = 0UL;
700
701 /* Update head pointer of hardware ring-buffer */
702 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
703 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
704
705 /* Handle PPR entry */
706 iommu_handle_ppr_entry(iommu, entry);
707
708 /* Refresh ring-buffer information */
709 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
710 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
711 }
712 }
713
714 irqreturn_t amd_iommu_int_thread(int irq, void *data)
715 {
716 struct amd_iommu *iommu = (struct amd_iommu *) data;
717 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
718
719 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
720 /* Enable EVT and PPR interrupts again */
721 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
722 iommu->mmio_base + MMIO_STATUS_OFFSET);
723
724 if (status & MMIO_STATUS_EVT_INT_MASK) {
725 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
726 iommu_poll_events(iommu);
727 }
728
729 if (status & MMIO_STATUS_PPR_INT_MASK) {
730 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
731 iommu_poll_ppr_log(iommu);
732 }
733
734 /*
735 * Hardware bug: ERBT1312
736 * When re-enabling interrupt (by writing 1
737 * to clear the bit), the hardware might also try to set
738 * the interrupt bit in the event status register.
739 * In this scenario, the bit will be set, and disable
740 * subsequent interrupts.
741 *
742 * Workaround: The IOMMU driver should read back the
743 * status register and check if the interrupt bits are cleared.
744 * If not, driver will need to go through the interrupt handler
745 * again and re-clear the bits
746 */
747 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
748 }
749 return IRQ_HANDLED;
750 }
751
752 irqreturn_t amd_iommu_int_handler(int irq, void *data)
753 {
754 return IRQ_WAKE_THREAD;
755 }
756
757 /****************************************************************************
758 *
759 * IOMMU command queuing functions
760 *
761 ****************************************************************************/
762
763 static int wait_on_sem(volatile u64 *sem)
764 {
765 int i = 0;
766
767 while (*sem == 0 && i < LOOP_TIMEOUT) {
768 udelay(1);
769 i += 1;
770 }
771
772 if (i == LOOP_TIMEOUT) {
773 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
774 return -EIO;
775 }
776
777 return 0;
778 }
779
780 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
781 struct iommu_cmd *cmd,
782 u32 tail)
783 {
784 u8 *target;
785
786 target = iommu->cmd_buf + tail;
787 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
788
789 /* Copy command to buffer */
790 memcpy(target, cmd, sizeof(*cmd));
791
792 /* Tell the IOMMU about it */
793 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
794 }
795
796 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
797 {
798 WARN_ON(address & 0x7ULL);
799
800 memset(cmd, 0, sizeof(*cmd));
801 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
802 cmd->data[1] = upper_32_bits(__pa(address));
803 cmd->data[2] = 1;
804 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
805 }
806
807 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
808 {
809 memset(cmd, 0, sizeof(*cmd));
810 cmd->data[0] = devid;
811 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
812 }
813
814 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
815 size_t size, u16 domid, int pde)
816 {
817 u64 pages;
818 bool s;
819
820 pages = iommu_num_pages(address, size, PAGE_SIZE);
821 s = false;
822
823 if (pages > 1) {
824 /*
825 * If we have to flush more than one page, flush all
826 * TLB entries for this domain
827 */
828 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
829 s = true;
830 }
831
832 address &= PAGE_MASK;
833
834 memset(cmd, 0, sizeof(*cmd));
835 cmd->data[1] |= domid;
836 cmd->data[2] = lower_32_bits(address);
837 cmd->data[3] = upper_32_bits(address);
838 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
839 if (s) /* size bit - we flush more than one 4kb page */
840 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
841 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
842 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
843 }
844
845 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
846 u64 address, size_t size)
847 {
848 u64 pages;
849 bool s;
850
851 pages = iommu_num_pages(address, size, PAGE_SIZE);
852 s = false;
853
854 if (pages > 1) {
855 /*
856 * If we have to flush more than one page, flush all
857 * TLB entries for this domain
858 */
859 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
860 s = true;
861 }
862
863 address &= PAGE_MASK;
864
865 memset(cmd, 0, sizeof(*cmd));
866 cmd->data[0] = devid;
867 cmd->data[0] |= (qdep & 0xff) << 24;
868 cmd->data[1] = devid;
869 cmd->data[2] = lower_32_bits(address);
870 cmd->data[3] = upper_32_bits(address);
871 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
872 if (s)
873 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
874 }
875
876 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
877 u64 address, bool size)
878 {
879 memset(cmd, 0, sizeof(*cmd));
880
881 address &= ~(0xfffULL);
882
883 cmd->data[0] = pasid;
884 cmd->data[1] = domid;
885 cmd->data[2] = lower_32_bits(address);
886 cmd->data[3] = upper_32_bits(address);
887 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
888 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
889 if (size)
890 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
891 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
892 }
893
894 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
895 int qdep, u64 address, bool size)
896 {
897 memset(cmd, 0, sizeof(*cmd));
898
899 address &= ~(0xfffULL);
900
901 cmd->data[0] = devid;
902 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
903 cmd->data[0] |= (qdep & 0xff) << 24;
904 cmd->data[1] = devid;
905 cmd->data[1] |= (pasid & 0xff) << 16;
906 cmd->data[2] = lower_32_bits(address);
907 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
908 cmd->data[3] = upper_32_bits(address);
909 if (size)
910 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
911 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
912 }
913
914 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
915 int status, int tag, bool gn)
916 {
917 memset(cmd, 0, sizeof(*cmd));
918
919 cmd->data[0] = devid;
920 if (gn) {
921 cmd->data[1] = pasid;
922 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
923 }
924 cmd->data[3] = tag & 0x1ff;
925 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
926
927 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
928 }
929
930 static void build_inv_all(struct iommu_cmd *cmd)
931 {
932 memset(cmd, 0, sizeof(*cmd));
933 CMD_SET_TYPE(cmd, CMD_INV_ALL);
934 }
935
936 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
937 {
938 memset(cmd, 0, sizeof(*cmd));
939 cmd->data[0] = devid;
940 CMD_SET_TYPE(cmd, CMD_INV_IRT);
941 }
942
943 /*
944 * Writes the command to the IOMMUs command buffer and informs the
945 * hardware about the new command.
946 */
947 static int iommu_queue_command_sync(struct amd_iommu *iommu,
948 struct iommu_cmd *cmd,
949 bool sync)
950 {
951 u32 left, tail, head, next_tail;
952 unsigned long flags;
953
954 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
955
956 again:
957 spin_lock_irqsave(&iommu->lock, flags);
958
959 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
960 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
961 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
962 left = (head - next_tail) % iommu->cmd_buf_size;
963
964 if (left <= 2) {
965 struct iommu_cmd sync_cmd;
966 volatile u64 sem = 0;
967 int ret;
968
969 build_completion_wait(&sync_cmd, (u64)&sem);
970 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
971
972 spin_unlock_irqrestore(&iommu->lock, flags);
973
974 if ((ret = wait_on_sem(&sem)) != 0)
975 return ret;
976
977 goto again;
978 }
979
980 copy_cmd_to_buffer(iommu, cmd, tail);
981
982 /* We need to sync now to make sure all commands are processed */
983 iommu->need_sync = sync;
984
985 spin_unlock_irqrestore(&iommu->lock, flags);
986
987 return 0;
988 }
989
990 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
991 {
992 return iommu_queue_command_sync(iommu, cmd, true);
993 }
994
995 /*
996 * This function queues a completion wait command into the command
997 * buffer of an IOMMU
998 */
999 static int iommu_completion_wait(struct amd_iommu *iommu)
1000 {
1001 struct iommu_cmd cmd;
1002 volatile u64 sem = 0;
1003 int ret;
1004
1005 if (!iommu->need_sync)
1006 return 0;
1007
1008 build_completion_wait(&cmd, (u64)&sem);
1009
1010 ret = iommu_queue_command_sync(iommu, &cmd, false);
1011 if (ret)
1012 return ret;
1013
1014 return wait_on_sem(&sem);
1015 }
1016
1017 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1018 {
1019 struct iommu_cmd cmd;
1020
1021 build_inv_dte(&cmd, devid);
1022
1023 return iommu_queue_command(iommu, &cmd);
1024 }
1025
1026 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1027 {
1028 u32 devid;
1029
1030 for (devid = 0; devid <= 0xffff; ++devid)
1031 iommu_flush_dte(iommu, devid);
1032
1033 iommu_completion_wait(iommu);
1034 }
1035
1036 /*
1037 * This function uses heavy locking and may disable irqs for some time. But
1038 * this is no issue because it is only called during resume.
1039 */
1040 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1041 {
1042 u32 dom_id;
1043
1044 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1045 struct iommu_cmd cmd;
1046 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1047 dom_id, 1);
1048 iommu_queue_command(iommu, &cmd);
1049 }
1050
1051 iommu_completion_wait(iommu);
1052 }
1053
1054 static void iommu_flush_all(struct amd_iommu *iommu)
1055 {
1056 struct iommu_cmd cmd;
1057
1058 build_inv_all(&cmd);
1059
1060 iommu_queue_command(iommu, &cmd);
1061 iommu_completion_wait(iommu);
1062 }
1063
1064 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1065 {
1066 struct iommu_cmd cmd;
1067
1068 build_inv_irt(&cmd, devid);
1069
1070 iommu_queue_command(iommu, &cmd);
1071 }
1072
1073 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1074 {
1075 u32 devid;
1076
1077 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1078 iommu_flush_irt(iommu, devid);
1079
1080 iommu_completion_wait(iommu);
1081 }
1082
1083 void iommu_flush_all_caches(struct amd_iommu *iommu)
1084 {
1085 if (iommu_feature(iommu, FEATURE_IA)) {
1086 iommu_flush_all(iommu);
1087 } else {
1088 iommu_flush_dte_all(iommu);
1089 iommu_flush_irt_all(iommu);
1090 iommu_flush_tlb_all(iommu);
1091 }
1092 }
1093
1094 /*
1095 * Command send function for flushing on-device TLB
1096 */
1097 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1098 u64 address, size_t size)
1099 {
1100 struct amd_iommu *iommu;
1101 struct iommu_cmd cmd;
1102 int qdep;
1103
1104 qdep = dev_data->ats.qdep;
1105 iommu = amd_iommu_rlookup_table[dev_data->devid];
1106
1107 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1108
1109 return iommu_queue_command(iommu, &cmd);
1110 }
1111
1112 /*
1113 * Command send function for invalidating a device table entry
1114 */
1115 static int device_flush_dte(struct iommu_dev_data *dev_data)
1116 {
1117 struct amd_iommu *iommu;
1118 int ret;
1119
1120 iommu = amd_iommu_rlookup_table[dev_data->devid];
1121
1122 ret = iommu_flush_dte(iommu, dev_data->devid);
1123 if (ret)
1124 return ret;
1125
1126 if (dev_data->ats.enabled)
1127 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1128
1129 return ret;
1130 }
1131
1132 /*
1133 * TLB invalidation function which is called from the mapping functions.
1134 * It invalidates a single PTE if the range to flush is within a single
1135 * page. Otherwise it flushes the whole TLB of the IOMMU.
1136 */
1137 static void __domain_flush_pages(struct protection_domain *domain,
1138 u64 address, size_t size, int pde)
1139 {
1140 struct iommu_dev_data *dev_data;
1141 struct iommu_cmd cmd;
1142 int ret = 0, i;
1143
1144 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1145
1146 for (i = 0; i < amd_iommus_present; ++i) {
1147 if (!domain->dev_iommu[i])
1148 continue;
1149
1150 /*
1151 * Devices of this domain are behind this IOMMU
1152 * We need a TLB flush
1153 */
1154 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1155 }
1156
1157 list_for_each_entry(dev_data, &domain->dev_list, list) {
1158
1159 if (!dev_data->ats.enabled)
1160 continue;
1161
1162 ret |= device_flush_iotlb(dev_data, address, size);
1163 }
1164
1165 WARN_ON(ret);
1166 }
1167
1168 static void domain_flush_pages(struct protection_domain *domain,
1169 u64 address, size_t size)
1170 {
1171 __domain_flush_pages(domain, address, size, 0);
1172 }
1173
1174 /* Flush the whole IO/TLB for a given protection domain */
1175 static void domain_flush_tlb(struct protection_domain *domain)
1176 {
1177 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1178 }
1179
1180 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1181 static void domain_flush_tlb_pde(struct protection_domain *domain)
1182 {
1183 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1184 }
1185
1186 static void domain_flush_complete(struct protection_domain *domain)
1187 {
1188 int i;
1189
1190 for (i = 0; i < amd_iommus_present; ++i) {
1191 if (!domain->dev_iommu[i])
1192 continue;
1193
1194 /*
1195 * Devices of this domain are behind this IOMMU
1196 * We need to wait for completion of all commands.
1197 */
1198 iommu_completion_wait(amd_iommus[i]);
1199 }
1200 }
1201
1202
1203 /*
1204 * This function flushes the DTEs for all devices in domain
1205 */
1206 static void domain_flush_devices(struct protection_domain *domain)
1207 {
1208 struct iommu_dev_data *dev_data;
1209
1210 list_for_each_entry(dev_data, &domain->dev_list, list)
1211 device_flush_dte(dev_data);
1212 }
1213
1214 /****************************************************************************
1215 *
1216 * The functions below are used the create the page table mappings for
1217 * unity mapped regions.
1218 *
1219 ****************************************************************************/
1220
1221 /*
1222 * This function is used to add another level to an IO page table. Adding
1223 * another level increases the size of the address space by 9 bits to a size up
1224 * to 64 bits.
1225 */
1226 static bool increase_address_space(struct protection_domain *domain,
1227 gfp_t gfp)
1228 {
1229 u64 *pte;
1230
1231 if (domain->mode == PAGE_MODE_6_LEVEL)
1232 /* address space already 64 bit large */
1233 return false;
1234
1235 pte = (void *)get_zeroed_page(gfp);
1236 if (!pte)
1237 return false;
1238
1239 *pte = PM_LEVEL_PDE(domain->mode,
1240 virt_to_phys(domain->pt_root));
1241 domain->pt_root = pte;
1242 domain->mode += 1;
1243 domain->updated = true;
1244
1245 return true;
1246 }
1247
1248 static u64 *alloc_pte(struct protection_domain *domain,
1249 unsigned long address,
1250 unsigned long page_size,
1251 u64 **pte_page,
1252 gfp_t gfp)
1253 {
1254 int level, end_lvl;
1255 u64 *pte, *page;
1256
1257 BUG_ON(!is_power_of_2(page_size));
1258
1259 while (address > PM_LEVEL_SIZE(domain->mode))
1260 increase_address_space(domain, gfp);
1261
1262 level = domain->mode - 1;
1263 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1264 address = PAGE_SIZE_ALIGN(address, page_size);
1265 end_lvl = PAGE_SIZE_LEVEL(page_size);
1266
1267 while (level > end_lvl) {
1268 if (!IOMMU_PTE_PRESENT(*pte)) {
1269 page = (u64 *)get_zeroed_page(gfp);
1270 if (!page)
1271 return NULL;
1272 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1273 }
1274
1275 /* No level skipping support yet */
1276 if (PM_PTE_LEVEL(*pte) != level)
1277 return NULL;
1278
1279 level -= 1;
1280
1281 pte = IOMMU_PTE_PAGE(*pte);
1282
1283 if (pte_page && level == end_lvl)
1284 *pte_page = pte;
1285
1286 pte = &pte[PM_LEVEL_INDEX(level, address)];
1287 }
1288
1289 return pte;
1290 }
1291
1292 /*
1293 * This function checks if there is a PTE for a given dma address. If
1294 * there is one, it returns the pointer to it.
1295 */
1296 static u64 *fetch_pte(struct protection_domain *domain,
1297 unsigned long address,
1298 unsigned long *page_size)
1299 {
1300 int level;
1301 u64 *pte;
1302
1303 if (address > PM_LEVEL_SIZE(domain->mode))
1304 return NULL;
1305
1306 level = domain->mode - 1;
1307 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1308 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1309
1310 while (level > 0) {
1311
1312 /* Not Present */
1313 if (!IOMMU_PTE_PRESENT(*pte))
1314 return NULL;
1315
1316 /* Large PTE */
1317 if (PM_PTE_LEVEL(*pte) == 7 ||
1318 PM_PTE_LEVEL(*pte) == 0)
1319 break;
1320
1321 /* No level skipping support yet */
1322 if (PM_PTE_LEVEL(*pte) != level)
1323 return NULL;
1324
1325 level -= 1;
1326
1327 /* Walk to the next level */
1328 pte = IOMMU_PTE_PAGE(*pte);
1329 pte = &pte[PM_LEVEL_INDEX(level, address)];
1330 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1331 }
1332
1333 if (PM_PTE_LEVEL(*pte) == 0x07) {
1334 unsigned long pte_mask;
1335
1336 /*
1337 * If we have a series of large PTEs, make
1338 * sure to return a pointer to the first one.
1339 */
1340 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1341 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1342 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1343 }
1344
1345 return pte;
1346 }
1347
1348 /*
1349 * Generic mapping functions. It maps a physical address into a DMA
1350 * address space. It allocates the page table pages if necessary.
1351 * In the future it can be extended to a generic mapping function
1352 * supporting all features of AMD IOMMU page tables like level skipping
1353 * and full 64 bit address spaces.
1354 */
1355 static int iommu_map_page(struct protection_domain *dom,
1356 unsigned long bus_addr,
1357 unsigned long phys_addr,
1358 int prot,
1359 unsigned long page_size)
1360 {
1361 u64 __pte, *pte;
1362 int i, count;
1363
1364 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1365 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1366
1367 if (!(prot & IOMMU_PROT_MASK))
1368 return -EINVAL;
1369
1370 count = PAGE_SIZE_PTE_COUNT(page_size);
1371 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1372
1373 if (!pte)
1374 return -ENOMEM;
1375
1376 for (i = 0; i < count; ++i)
1377 if (IOMMU_PTE_PRESENT(pte[i]))
1378 return -EBUSY;
1379
1380 if (count > 1) {
1381 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1382 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1383 } else
1384 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1385
1386 if (prot & IOMMU_PROT_IR)
1387 __pte |= IOMMU_PTE_IR;
1388 if (prot & IOMMU_PROT_IW)
1389 __pte |= IOMMU_PTE_IW;
1390
1391 for (i = 0; i < count; ++i)
1392 pte[i] = __pte;
1393
1394 update_domain(dom);
1395
1396 return 0;
1397 }
1398
1399 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1400 unsigned long bus_addr,
1401 unsigned long page_size)
1402 {
1403 unsigned long long unmapped;
1404 unsigned long unmap_size;
1405 u64 *pte;
1406
1407 BUG_ON(!is_power_of_2(page_size));
1408
1409 unmapped = 0;
1410
1411 while (unmapped < page_size) {
1412
1413 pte = fetch_pte(dom, bus_addr, &unmap_size);
1414
1415 if (pte) {
1416 int i, count;
1417
1418 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1419 for (i = 0; i < count; i++)
1420 pte[i] = 0ULL;
1421 }
1422
1423 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1424 unmapped += unmap_size;
1425 }
1426
1427 BUG_ON(unmapped && !is_power_of_2(unmapped));
1428
1429 return unmapped;
1430 }
1431
1432 /****************************************************************************
1433 *
1434 * The next functions belong to the address allocator for the dma_ops
1435 * interface functions. They work like the allocators in the other IOMMU
1436 * drivers. Its basically a bitmap which marks the allocated pages in
1437 * the aperture. Maybe it could be enhanced in the future to a more
1438 * efficient allocator.
1439 *
1440 ****************************************************************************/
1441
1442 /*
1443 * The address allocator core functions.
1444 *
1445 * called with domain->lock held
1446 */
1447
1448 /*
1449 * Used to reserve address ranges in the aperture (e.g. for exclusion
1450 * ranges.
1451 */
1452 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1453 unsigned long start_page,
1454 unsigned int pages)
1455 {
1456 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1457
1458 if (start_page + pages > last_page)
1459 pages = last_page - start_page;
1460
1461 for (i = start_page; i < start_page + pages; ++i) {
1462 int index = i / APERTURE_RANGE_PAGES;
1463 int page = i % APERTURE_RANGE_PAGES;
1464 __set_bit(page, dom->aperture[index]->bitmap);
1465 }
1466 }
1467
1468 /*
1469 * This function is used to add a new aperture range to an existing
1470 * aperture in case of dma_ops domain allocation or address allocation
1471 * failure.
1472 */
1473 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1474 bool populate, gfp_t gfp)
1475 {
1476 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1477 struct amd_iommu *iommu;
1478 unsigned long i, old_size, pte_pgsize;
1479
1480 #ifdef CONFIG_IOMMU_STRESS
1481 populate = false;
1482 #endif
1483
1484 if (index >= APERTURE_MAX_RANGES)
1485 return -ENOMEM;
1486
1487 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1488 if (!dma_dom->aperture[index])
1489 return -ENOMEM;
1490
1491 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1492 if (!dma_dom->aperture[index]->bitmap)
1493 goto out_free;
1494
1495 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1496
1497 if (populate) {
1498 unsigned long address = dma_dom->aperture_size;
1499 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1500 u64 *pte, *pte_page;
1501
1502 for (i = 0; i < num_ptes; ++i) {
1503 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1504 &pte_page, gfp);
1505 if (!pte)
1506 goto out_free;
1507
1508 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1509
1510 address += APERTURE_RANGE_SIZE / 64;
1511 }
1512 }
1513
1514 old_size = dma_dom->aperture_size;
1515 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1516
1517 /* Reserve address range used for MSI messages */
1518 if (old_size < MSI_ADDR_BASE_LO &&
1519 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1520 unsigned long spage;
1521 int pages;
1522
1523 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1524 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1525
1526 dma_ops_reserve_addresses(dma_dom, spage, pages);
1527 }
1528
1529 /* Initialize the exclusion range if necessary */
1530 for_each_iommu(iommu) {
1531 if (iommu->exclusion_start &&
1532 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1533 && iommu->exclusion_start < dma_dom->aperture_size) {
1534 unsigned long startpage;
1535 int pages = iommu_num_pages(iommu->exclusion_start,
1536 iommu->exclusion_length,
1537 PAGE_SIZE);
1538 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1539 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1540 }
1541 }
1542
1543 /*
1544 * Check for areas already mapped as present in the new aperture
1545 * range and mark those pages as reserved in the allocator. Such
1546 * mappings may already exist as a result of requested unity
1547 * mappings for devices.
1548 */
1549 for (i = dma_dom->aperture[index]->offset;
1550 i < dma_dom->aperture_size;
1551 i += pte_pgsize) {
1552 u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize);
1553 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1554 continue;
1555
1556 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT,
1557 pte_pgsize >> 12);
1558 }
1559
1560 update_domain(&dma_dom->domain);
1561
1562 return 0;
1563
1564 out_free:
1565 update_domain(&dma_dom->domain);
1566
1567 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1568
1569 kfree(dma_dom->aperture[index]);
1570 dma_dom->aperture[index] = NULL;
1571
1572 return -ENOMEM;
1573 }
1574
1575 static unsigned long dma_ops_area_alloc(struct device *dev,
1576 struct dma_ops_domain *dom,
1577 unsigned int pages,
1578 unsigned long align_mask,
1579 u64 dma_mask,
1580 unsigned long start)
1581 {
1582 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1583 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1584 int i = start >> APERTURE_RANGE_SHIFT;
1585 unsigned long boundary_size;
1586 unsigned long address = -1;
1587 unsigned long limit;
1588
1589 next_bit >>= PAGE_SHIFT;
1590
1591 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1592 PAGE_SIZE) >> PAGE_SHIFT;
1593
1594 for (;i < max_index; ++i) {
1595 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1596
1597 if (dom->aperture[i]->offset >= dma_mask)
1598 break;
1599
1600 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1601 dma_mask >> PAGE_SHIFT);
1602
1603 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1604 limit, next_bit, pages, 0,
1605 boundary_size, align_mask);
1606 if (address != -1) {
1607 address = dom->aperture[i]->offset +
1608 (address << PAGE_SHIFT);
1609 dom->next_address = address + (pages << PAGE_SHIFT);
1610 break;
1611 }
1612
1613 next_bit = 0;
1614 }
1615
1616 return address;
1617 }
1618
1619 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1620 struct dma_ops_domain *dom,
1621 unsigned int pages,
1622 unsigned long align_mask,
1623 u64 dma_mask)
1624 {
1625 unsigned long address;
1626
1627 #ifdef CONFIG_IOMMU_STRESS
1628 dom->next_address = 0;
1629 dom->need_flush = true;
1630 #endif
1631
1632 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1633 dma_mask, dom->next_address);
1634
1635 if (address == -1) {
1636 dom->next_address = 0;
1637 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1638 dma_mask, 0);
1639 dom->need_flush = true;
1640 }
1641
1642 if (unlikely(address == -1))
1643 address = DMA_ERROR_CODE;
1644
1645 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1646
1647 return address;
1648 }
1649
1650 /*
1651 * The address free function.
1652 *
1653 * called with domain->lock held
1654 */
1655 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1656 unsigned long address,
1657 unsigned int pages)
1658 {
1659 unsigned i = address >> APERTURE_RANGE_SHIFT;
1660 struct aperture_range *range = dom->aperture[i];
1661
1662 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1663
1664 #ifdef CONFIG_IOMMU_STRESS
1665 if (i < 4)
1666 return;
1667 #endif
1668
1669 if (address >= dom->next_address)
1670 dom->need_flush = true;
1671
1672 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1673
1674 bitmap_clear(range->bitmap, address, pages);
1675
1676 }
1677
1678 /****************************************************************************
1679 *
1680 * The next functions belong to the domain allocation. A domain is
1681 * allocated for every IOMMU as the default domain. If device isolation
1682 * is enabled, every device get its own domain. The most important thing
1683 * about domains is the page table mapping the DMA address space they
1684 * contain.
1685 *
1686 ****************************************************************************/
1687
1688 /*
1689 * This function adds a protection domain to the global protection domain list
1690 */
1691 static void add_domain_to_list(struct protection_domain *domain)
1692 {
1693 unsigned long flags;
1694
1695 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1696 list_add(&domain->list, &amd_iommu_pd_list);
1697 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1698 }
1699
1700 /*
1701 * This function removes a protection domain to the global
1702 * protection domain list
1703 */
1704 static void del_domain_from_list(struct protection_domain *domain)
1705 {
1706 unsigned long flags;
1707
1708 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1709 list_del(&domain->list);
1710 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1711 }
1712
1713 static u16 domain_id_alloc(void)
1714 {
1715 unsigned long flags;
1716 int id;
1717
1718 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1719 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1720 BUG_ON(id == 0);
1721 if (id > 0 && id < MAX_DOMAIN_ID)
1722 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1723 else
1724 id = 0;
1725 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1726
1727 return id;
1728 }
1729
1730 static void domain_id_free(int id)
1731 {
1732 unsigned long flags;
1733
1734 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1735 if (id > 0 && id < MAX_DOMAIN_ID)
1736 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1737 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1738 }
1739
1740 #define DEFINE_FREE_PT_FN(LVL, FN) \
1741 static void free_pt_##LVL (unsigned long __pt) \
1742 { \
1743 unsigned long p; \
1744 u64 *pt; \
1745 int i; \
1746 \
1747 pt = (u64 *)__pt; \
1748 \
1749 for (i = 0; i < 512; ++i) { \
1750 if (!IOMMU_PTE_PRESENT(pt[i])) \
1751 continue; \
1752 \
1753 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1754 FN(p); \
1755 } \
1756 free_page((unsigned long)pt); \
1757 }
1758
1759 DEFINE_FREE_PT_FN(l2, free_page)
1760 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1761 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1762 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1763 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1764
1765 static void free_pagetable(struct protection_domain *domain)
1766 {
1767 unsigned long root = (unsigned long)domain->pt_root;
1768
1769 switch (domain->mode) {
1770 case PAGE_MODE_NONE:
1771 break;
1772 case PAGE_MODE_1_LEVEL:
1773 free_page(root);
1774 break;
1775 case PAGE_MODE_2_LEVEL:
1776 free_pt_l2(root);
1777 break;
1778 case PAGE_MODE_3_LEVEL:
1779 free_pt_l3(root);
1780 break;
1781 case PAGE_MODE_4_LEVEL:
1782 free_pt_l4(root);
1783 break;
1784 case PAGE_MODE_5_LEVEL:
1785 free_pt_l5(root);
1786 break;
1787 case PAGE_MODE_6_LEVEL:
1788 free_pt_l6(root);
1789 break;
1790 default:
1791 BUG();
1792 }
1793 }
1794
1795 static void free_gcr3_tbl_level1(u64 *tbl)
1796 {
1797 u64 *ptr;
1798 int i;
1799
1800 for (i = 0; i < 512; ++i) {
1801 if (!(tbl[i] & GCR3_VALID))
1802 continue;
1803
1804 ptr = __va(tbl[i] & PAGE_MASK);
1805
1806 free_page((unsigned long)ptr);
1807 }
1808 }
1809
1810 static void free_gcr3_tbl_level2(u64 *tbl)
1811 {
1812 u64 *ptr;
1813 int i;
1814
1815 for (i = 0; i < 512; ++i) {
1816 if (!(tbl[i] & GCR3_VALID))
1817 continue;
1818
1819 ptr = __va(tbl[i] & PAGE_MASK);
1820
1821 free_gcr3_tbl_level1(ptr);
1822 }
1823 }
1824
1825 static void free_gcr3_table(struct protection_domain *domain)
1826 {
1827 if (domain->glx == 2)
1828 free_gcr3_tbl_level2(domain->gcr3_tbl);
1829 else if (domain->glx == 1)
1830 free_gcr3_tbl_level1(domain->gcr3_tbl);
1831 else if (domain->glx != 0)
1832 BUG();
1833
1834 free_page((unsigned long)domain->gcr3_tbl);
1835 }
1836
1837 /*
1838 * Free a domain, only used if something went wrong in the
1839 * allocation path and we need to free an already allocated page table
1840 */
1841 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1842 {
1843 int i;
1844
1845 if (!dom)
1846 return;
1847
1848 del_domain_from_list(&dom->domain);
1849
1850 free_pagetable(&dom->domain);
1851
1852 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1853 if (!dom->aperture[i])
1854 continue;
1855 free_page((unsigned long)dom->aperture[i]->bitmap);
1856 kfree(dom->aperture[i]);
1857 }
1858
1859 kfree(dom);
1860 }
1861
1862 /*
1863 * Allocates a new protection domain usable for the dma_ops functions.
1864 * It also initializes the page table and the address allocator data
1865 * structures required for the dma_ops interface
1866 */
1867 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1868 {
1869 struct dma_ops_domain *dma_dom;
1870
1871 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1872 if (!dma_dom)
1873 return NULL;
1874
1875 spin_lock_init(&dma_dom->domain.lock);
1876
1877 dma_dom->domain.id = domain_id_alloc();
1878 if (dma_dom->domain.id == 0)
1879 goto free_dma_dom;
1880 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1881 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1882 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1883 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1884 dma_dom->domain.priv = dma_dom;
1885 if (!dma_dom->domain.pt_root)
1886 goto free_dma_dom;
1887
1888 dma_dom->need_flush = false;
1889
1890 add_domain_to_list(&dma_dom->domain);
1891
1892 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1893 goto free_dma_dom;
1894
1895 /*
1896 * mark the first page as allocated so we never return 0 as
1897 * a valid dma-address. So we can use 0 as error value
1898 */
1899 dma_dom->aperture[0]->bitmap[0] = 1;
1900 dma_dom->next_address = 0;
1901
1902
1903 return dma_dom;
1904
1905 free_dma_dom:
1906 dma_ops_domain_free(dma_dom);
1907
1908 return NULL;
1909 }
1910
1911 /*
1912 * little helper function to check whether a given protection domain is a
1913 * dma_ops domain
1914 */
1915 static bool dma_ops_domain(struct protection_domain *domain)
1916 {
1917 return domain->flags & PD_DMA_OPS_MASK;
1918 }
1919
1920 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1921 {
1922 u64 pte_root = 0;
1923 u64 flags = 0;
1924
1925 if (domain->mode != PAGE_MODE_NONE)
1926 pte_root = virt_to_phys(domain->pt_root);
1927
1928 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1929 << DEV_ENTRY_MODE_SHIFT;
1930 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1931
1932 flags = amd_iommu_dev_table[devid].data[1];
1933
1934 if (ats)
1935 flags |= DTE_FLAG_IOTLB;
1936
1937 if (domain->flags & PD_IOMMUV2_MASK) {
1938 u64 gcr3 = __pa(domain->gcr3_tbl);
1939 u64 glx = domain->glx;
1940 u64 tmp;
1941
1942 pte_root |= DTE_FLAG_GV;
1943 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1944
1945 /* First mask out possible old values for GCR3 table */
1946 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1947 flags &= ~tmp;
1948
1949 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1950 flags &= ~tmp;
1951
1952 /* Encode GCR3 table into DTE */
1953 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1954 pte_root |= tmp;
1955
1956 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1957 flags |= tmp;
1958
1959 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1960 flags |= tmp;
1961 }
1962
1963 flags &= ~(0xffffUL);
1964 flags |= domain->id;
1965
1966 amd_iommu_dev_table[devid].data[1] = flags;
1967 amd_iommu_dev_table[devid].data[0] = pte_root;
1968 }
1969
1970 static void clear_dte_entry(u16 devid)
1971 {
1972 /* remove entry from the device table seen by the hardware */
1973 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1974 amd_iommu_dev_table[devid].data[1] = 0;
1975
1976 amd_iommu_apply_erratum_63(devid);
1977 }
1978
1979 static void do_attach(struct iommu_dev_data *dev_data,
1980 struct protection_domain *domain)
1981 {
1982 struct amd_iommu *iommu;
1983 bool ats;
1984
1985 iommu = amd_iommu_rlookup_table[dev_data->devid];
1986 ats = dev_data->ats.enabled;
1987
1988 /* Update data structures */
1989 dev_data->domain = domain;
1990 list_add(&dev_data->list, &domain->dev_list);
1991 set_dte_entry(dev_data->devid, domain, ats);
1992
1993 /* Do reference counting */
1994 domain->dev_iommu[iommu->index] += 1;
1995 domain->dev_cnt += 1;
1996
1997 /* Flush the DTE entry */
1998 device_flush_dte(dev_data);
1999 }
2000
2001 static void do_detach(struct iommu_dev_data *dev_data)
2002 {
2003 struct amd_iommu *iommu;
2004
2005 iommu = amd_iommu_rlookup_table[dev_data->devid];
2006
2007 /* decrease reference counters */
2008 dev_data->domain->dev_iommu[iommu->index] -= 1;
2009 dev_data->domain->dev_cnt -= 1;
2010
2011 /* Update data structures */
2012 dev_data->domain = NULL;
2013 list_del(&dev_data->list);
2014 clear_dte_entry(dev_data->devid);
2015
2016 /* Flush the DTE entry */
2017 device_flush_dte(dev_data);
2018 }
2019
2020 /*
2021 * If a device is not yet associated with a domain, this function does
2022 * assigns it visible for the hardware
2023 */
2024 static int __attach_device(struct iommu_dev_data *dev_data,
2025 struct protection_domain *domain)
2026 {
2027 struct iommu_dev_data *head, *entry;
2028 int ret;
2029
2030 /* lock domain */
2031 spin_lock(&domain->lock);
2032
2033 head = dev_data;
2034
2035 if (head->alias_data != NULL)
2036 head = head->alias_data;
2037
2038 /* Now we have the root of the alias group, if any */
2039
2040 ret = -EBUSY;
2041 if (head->domain != NULL)
2042 goto out_unlock;
2043
2044 /* Attach alias group root */
2045 do_attach(head, domain);
2046
2047 /* Attach other devices in the alias group */
2048 list_for_each_entry(entry, &head->alias_list, alias_list)
2049 do_attach(entry, domain);
2050
2051 ret = 0;
2052
2053 out_unlock:
2054
2055 /* ready */
2056 spin_unlock(&domain->lock);
2057
2058 return ret;
2059 }
2060
2061
2062 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2063 {
2064 pci_disable_ats(pdev);
2065 pci_disable_pri(pdev);
2066 pci_disable_pasid(pdev);
2067 }
2068
2069 /* FIXME: Change generic reset-function to do the same */
2070 static int pri_reset_while_enabled(struct pci_dev *pdev)
2071 {
2072 u16 control;
2073 int pos;
2074
2075 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2076 if (!pos)
2077 return -EINVAL;
2078
2079 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2080 control |= PCI_PRI_CTRL_RESET;
2081 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2082
2083 return 0;
2084 }
2085
2086 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2087 {
2088 bool reset_enable;
2089 int reqs, ret;
2090
2091 /* FIXME: Hardcode number of outstanding requests for now */
2092 reqs = 32;
2093 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2094 reqs = 1;
2095 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2096
2097 /* Only allow access to user-accessible pages */
2098 ret = pci_enable_pasid(pdev, 0);
2099 if (ret)
2100 goto out_err;
2101
2102 /* First reset the PRI state of the device */
2103 ret = pci_reset_pri(pdev);
2104 if (ret)
2105 goto out_err;
2106
2107 /* Enable PRI */
2108 ret = pci_enable_pri(pdev, reqs);
2109 if (ret)
2110 goto out_err;
2111
2112 if (reset_enable) {
2113 ret = pri_reset_while_enabled(pdev);
2114 if (ret)
2115 goto out_err;
2116 }
2117
2118 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2119 if (ret)
2120 goto out_err;
2121
2122 return 0;
2123
2124 out_err:
2125 pci_disable_pri(pdev);
2126 pci_disable_pasid(pdev);
2127
2128 return ret;
2129 }
2130
2131 /* FIXME: Move this to PCI code */
2132 #define PCI_PRI_TLP_OFF (1 << 15)
2133
2134 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2135 {
2136 u16 status;
2137 int pos;
2138
2139 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2140 if (!pos)
2141 return false;
2142
2143 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2144
2145 return (status & PCI_PRI_TLP_OFF) ? true : false;
2146 }
2147
2148 /*
2149 * If a device is not yet associated with a domain, this function
2150 * assigns it visible for the hardware
2151 */
2152 static int attach_device(struct device *dev,
2153 struct protection_domain *domain)
2154 {
2155 struct pci_dev *pdev = to_pci_dev(dev);
2156 struct iommu_dev_data *dev_data;
2157 unsigned long flags;
2158 int ret;
2159
2160 dev_data = get_dev_data(dev);
2161
2162 if (domain->flags & PD_IOMMUV2_MASK) {
2163 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2164 return -EINVAL;
2165
2166 if (pdev_iommuv2_enable(pdev) != 0)
2167 return -EINVAL;
2168
2169 dev_data->ats.enabled = true;
2170 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2171 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2172 } else if (amd_iommu_iotlb_sup &&
2173 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2174 dev_data->ats.enabled = true;
2175 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2176 }
2177
2178 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2179 ret = __attach_device(dev_data, domain);
2180 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2181
2182 /*
2183 * We might boot into a crash-kernel here. The crashed kernel
2184 * left the caches in the IOMMU dirty. So we have to flush
2185 * here to evict all dirty stuff.
2186 */
2187 domain_flush_tlb_pde(domain);
2188
2189 return ret;
2190 }
2191
2192 /*
2193 * Removes a device from a protection domain (unlocked)
2194 */
2195 static void __detach_device(struct iommu_dev_data *dev_data)
2196 {
2197 struct iommu_dev_data *head, *entry;
2198 struct protection_domain *domain;
2199 unsigned long flags;
2200
2201 BUG_ON(!dev_data->domain);
2202
2203 domain = dev_data->domain;
2204
2205 spin_lock_irqsave(&domain->lock, flags);
2206
2207 head = dev_data;
2208 if (head->alias_data != NULL)
2209 head = head->alias_data;
2210
2211 list_for_each_entry(entry, &head->alias_list, alias_list)
2212 do_detach(entry);
2213
2214 do_detach(head);
2215
2216 spin_unlock_irqrestore(&domain->lock, flags);
2217
2218 /*
2219 * If we run in passthrough mode the device must be assigned to the
2220 * passthrough domain if it is detached from any other domain.
2221 * Make sure we can deassign from the pt_domain itself.
2222 */
2223 if (dev_data->passthrough &&
2224 (dev_data->domain == NULL && domain != pt_domain))
2225 __attach_device(dev_data, pt_domain);
2226 }
2227
2228 /*
2229 * Removes a device from a protection domain (with devtable_lock held)
2230 */
2231 static void detach_device(struct device *dev)
2232 {
2233 struct protection_domain *domain;
2234 struct iommu_dev_data *dev_data;
2235 unsigned long flags;
2236
2237 dev_data = get_dev_data(dev);
2238 domain = dev_data->domain;
2239
2240 /* lock device table */
2241 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2242 __detach_device(dev_data);
2243 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2244
2245 if (domain->flags & PD_IOMMUV2_MASK)
2246 pdev_iommuv2_disable(to_pci_dev(dev));
2247 else if (dev_data->ats.enabled)
2248 pci_disable_ats(to_pci_dev(dev));
2249
2250 dev_data->ats.enabled = false;
2251 }
2252
2253 static int amd_iommu_add_device(struct device *dev)
2254 {
2255 struct iommu_dev_data *dev_data;
2256 struct iommu_domain *domain;
2257 struct amd_iommu *iommu;
2258 u16 devid;
2259 int ret;
2260
2261 if (!check_device(dev) || get_dev_data(dev))
2262 return 0;
2263
2264 devid = get_device_id(dev);
2265 iommu = amd_iommu_rlookup_table[devid];
2266
2267 ret = iommu_init_device(dev);
2268 if (ret) {
2269 if (ret != -ENOTSUPP)
2270 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2271 dev_name(dev));
2272
2273 iommu_ignore_device(dev);
2274 dev->archdata.dma_ops = &nommu_dma_ops;
2275 goto out;
2276 }
2277 init_iommu_group(dev);
2278
2279 dev_data = get_dev_data(dev);
2280
2281 BUG_ON(!dev_data);
2282
2283 if (dev_data->iommu_v2)
2284 iommu_request_dm_for_dev(dev);
2285
2286 /* Domains are initialized for this device - have a look what we ended up with */
2287 domain = iommu_get_domain_for_dev(dev);
2288 if (domain->type == IOMMU_DOMAIN_IDENTITY) {
2289 dev_data->passthrough = true;
2290 dev->archdata.dma_ops = &nommu_dma_ops;
2291 } else {
2292 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2293 }
2294
2295 out:
2296 iommu_completion_wait(iommu);
2297
2298 return 0;
2299 }
2300
2301 static void amd_iommu_remove_device(struct device *dev)
2302 {
2303 struct amd_iommu *iommu;
2304 u16 devid;
2305
2306 if (!check_device(dev))
2307 return;
2308
2309 devid = get_device_id(dev);
2310 iommu = amd_iommu_rlookup_table[devid];
2311
2312 iommu_uninit_device(dev);
2313 iommu_completion_wait(iommu);
2314 }
2315
2316 /*****************************************************************************
2317 *
2318 * The next functions belong to the dma_ops mapping/unmapping code.
2319 *
2320 *****************************************************************************/
2321
2322 /*
2323 * In the dma_ops path we only have the struct device. This function
2324 * finds the corresponding IOMMU, the protection domain and the
2325 * requestor id for a given device.
2326 * If the device is not yet associated with a domain this is also done
2327 * in this function.
2328 */
2329 static struct protection_domain *get_domain(struct device *dev)
2330 {
2331 struct protection_domain *domain;
2332 struct iommu_domain *io_domain;
2333
2334 if (!check_device(dev))
2335 return ERR_PTR(-EINVAL);
2336
2337 io_domain = iommu_get_domain_for_dev(dev);
2338 if (!io_domain)
2339 return NULL;
2340
2341 domain = to_pdomain(io_domain);
2342 if (!dma_ops_domain(domain))
2343 return ERR_PTR(-EBUSY);
2344
2345 return domain;
2346 }
2347
2348 static void update_device_table(struct protection_domain *domain)
2349 {
2350 struct iommu_dev_data *dev_data;
2351
2352 list_for_each_entry(dev_data, &domain->dev_list, list)
2353 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2354 }
2355
2356 static void update_domain(struct protection_domain *domain)
2357 {
2358 if (!domain->updated)
2359 return;
2360
2361 update_device_table(domain);
2362
2363 domain_flush_devices(domain);
2364 domain_flush_tlb_pde(domain);
2365
2366 domain->updated = false;
2367 }
2368
2369 /*
2370 * This function fetches the PTE for a given address in the aperture
2371 */
2372 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2373 unsigned long address)
2374 {
2375 struct aperture_range *aperture;
2376 u64 *pte, *pte_page;
2377
2378 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2379 if (!aperture)
2380 return NULL;
2381
2382 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2383 if (!pte) {
2384 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2385 GFP_ATOMIC);
2386 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2387 } else
2388 pte += PM_LEVEL_INDEX(0, address);
2389
2390 update_domain(&dom->domain);
2391
2392 return pte;
2393 }
2394
2395 /*
2396 * This is the generic map function. It maps one 4kb page at paddr to
2397 * the given address in the DMA address space for the domain.
2398 */
2399 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2400 unsigned long address,
2401 phys_addr_t paddr,
2402 int direction)
2403 {
2404 u64 *pte, __pte;
2405
2406 WARN_ON(address > dom->aperture_size);
2407
2408 paddr &= PAGE_MASK;
2409
2410 pte = dma_ops_get_pte(dom, address);
2411 if (!pte)
2412 return DMA_ERROR_CODE;
2413
2414 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2415
2416 if (direction == DMA_TO_DEVICE)
2417 __pte |= IOMMU_PTE_IR;
2418 else if (direction == DMA_FROM_DEVICE)
2419 __pte |= IOMMU_PTE_IW;
2420 else if (direction == DMA_BIDIRECTIONAL)
2421 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2422
2423 WARN_ON(*pte);
2424
2425 *pte = __pte;
2426
2427 return (dma_addr_t)address;
2428 }
2429
2430 /*
2431 * The generic unmapping function for on page in the DMA address space.
2432 */
2433 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2434 unsigned long address)
2435 {
2436 struct aperture_range *aperture;
2437 u64 *pte;
2438
2439 if (address >= dom->aperture_size)
2440 return;
2441
2442 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2443 if (!aperture)
2444 return;
2445
2446 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2447 if (!pte)
2448 return;
2449
2450 pte += PM_LEVEL_INDEX(0, address);
2451
2452 WARN_ON(!*pte);
2453
2454 *pte = 0ULL;
2455 }
2456
2457 /*
2458 * This function contains common code for mapping of a physically
2459 * contiguous memory region into DMA address space. It is used by all
2460 * mapping functions provided with this IOMMU driver.
2461 * Must be called with the domain lock held.
2462 */
2463 static dma_addr_t __map_single(struct device *dev,
2464 struct dma_ops_domain *dma_dom,
2465 phys_addr_t paddr,
2466 size_t size,
2467 int dir,
2468 bool align,
2469 u64 dma_mask)
2470 {
2471 dma_addr_t offset = paddr & ~PAGE_MASK;
2472 dma_addr_t address, start, ret;
2473 unsigned int pages;
2474 unsigned long align_mask = 0;
2475 int i;
2476
2477 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2478 paddr &= PAGE_MASK;
2479
2480 INC_STATS_COUNTER(total_map_requests);
2481
2482 if (pages > 1)
2483 INC_STATS_COUNTER(cross_page);
2484
2485 if (align)
2486 align_mask = (1UL << get_order(size)) - 1;
2487
2488 retry:
2489 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2490 dma_mask);
2491 if (unlikely(address == DMA_ERROR_CODE)) {
2492 /*
2493 * setting next_address here will let the address
2494 * allocator only scan the new allocated range in the
2495 * first run. This is a small optimization.
2496 */
2497 dma_dom->next_address = dma_dom->aperture_size;
2498
2499 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2500 goto out;
2501
2502 /*
2503 * aperture was successfully enlarged by 128 MB, try
2504 * allocation again
2505 */
2506 goto retry;
2507 }
2508
2509 start = address;
2510 for (i = 0; i < pages; ++i) {
2511 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2512 if (ret == DMA_ERROR_CODE)
2513 goto out_unmap;
2514
2515 paddr += PAGE_SIZE;
2516 start += PAGE_SIZE;
2517 }
2518 address += offset;
2519
2520 ADD_STATS_COUNTER(alloced_io_mem, size);
2521
2522 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2523 domain_flush_tlb(&dma_dom->domain);
2524 dma_dom->need_flush = false;
2525 } else if (unlikely(amd_iommu_np_cache))
2526 domain_flush_pages(&dma_dom->domain, address, size);
2527
2528 out:
2529 return address;
2530
2531 out_unmap:
2532
2533 for (--i; i >= 0; --i) {
2534 start -= PAGE_SIZE;
2535 dma_ops_domain_unmap(dma_dom, start);
2536 }
2537
2538 dma_ops_free_addresses(dma_dom, address, pages);
2539
2540 return DMA_ERROR_CODE;
2541 }
2542
2543 /*
2544 * Does the reverse of the __map_single function. Must be called with
2545 * the domain lock held too
2546 */
2547 static void __unmap_single(struct dma_ops_domain *dma_dom,
2548 dma_addr_t dma_addr,
2549 size_t size,
2550 int dir)
2551 {
2552 dma_addr_t flush_addr;
2553 dma_addr_t i, start;
2554 unsigned int pages;
2555
2556 if ((dma_addr == DMA_ERROR_CODE) ||
2557 (dma_addr + size > dma_dom->aperture_size))
2558 return;
2559
2560 flush_addr = dma_addr;
2561 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2562 dma_addr &= PAGE_MASK;
2563 start = dma_addr;
2564
2565 for (i = 0; i < pages; ++i) {
2566 dma_ops_domain_unmap(dma_dom, start);
2567 start += PAGE_SIZE;
2568 }
2569
2570 SUB_STATS_COUNTER(alloced_io_mem, size);
2571
2572 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2573
2574 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2575 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2576 dma_dom->need_flush = false;
2577 }
2578 }
2579
2580 /*
2581 * The exported map_single function for dma_ops.
2582 */
2583 static dma_addr_t map_page(struct device *dev, struct page *page,
2584 unsigned long offset, size_t size,
2585 enum dma_data_direction dir,
2586 struct dma_attrs *attrs)
2587 {
2588 unsigned long flags;
2589 struct protection_domain *domain;
2590 dma_addr_t addr;
2591 u64 dma_mask;
2592 phys_addr_t paddr = page_to_phys(page) + offset;
2593
2594 INC_STATS_COUNTER(cnt_map_single);
2595
2596 domain = get_domain(dev);
2597 if (PTR_ERR(domain) == -EINVAL)
2598 return (dma_addr_t)paddr;
2599 else if (IS_ERR(domain))
2600 return DMA_ERROR_CODE;
2601
2602 dma_mask = *dev->dma_mask;
2603
2604 spin_lock_irqsave(&domain->lock, flags);
2605
2606 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2607 dma_mask);
2608 if (addr == DMA_ERROR_CODE)
2609 goto out;
2610
2611 domain_flush_complete(domain);
2612
2613 out:
2614 spin_unlock_irqrestore(&domain->lock, flags);
2615
2616 return addr;
2617 }
2618
2619 /*
2620 * The exported unmap_single function for dma_ops.
2621 */
2622 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2623 enum dma_data_direction dir, struct dma_attrs *attrs)
2624 {
2625 unsigned long flags;
2626 struct protection_domain *domain;
2627
2628 INC_STATS_COUNTER(cnt_unmap_single);
2629
2630 domain = get_domain(dev);
2631 if (IS_ERR(domain))
2632 return;
2633
2634 spin_lock_irqsave(&domain->lock, flags);
2635
2636 __unmap_single(domain->priv, dma_addr, size, dir);
2637
2638 domain_flush_complete(domain);
2639
2640 spin_unlock_irqrestore(&domain->lock, flags);
2641 }
2642
2643 /*
2644 * The exported map_sg function for dma_ops (handles scatter-gather
2645 * lists).
2646 */
2647 static int map_sg(struct device *dev, struct scatterlist *sglist,
2648 int nelems, enum dma_data_direction dir,
2649 struct dma_attrs *attrs)
2650 {
2651 unsigned long flags;
2652 struct protection_domain *domain;
2653 int i;
2654 struct scatterlist *s;
2655 phys_addr_t paddr;
2656 int mapped_elems = 0;
2657 u64 dma_mask;
2658
2659 INC_STATS_COUNTER(cnt_map_sg);
2660
2661 domain = get_domain(dev);
2662 if (IS_ERR(domain))
2663 return 0;
2664
2665 dma_mask = *dev->dma_mask;
2666
2667 spin_lock_irqsave(&domain->lock, flags);
2668
2669 for_each_sg(sglist, s, nelems, i) {
2670 paddr = sg_phys(s);
2671
2672 s->dma_address = __map_single(dev, domain->priv,
2673 paddr, s->length, dir, false,
2674 dma_mask);
2675
2676 if (s->dma_address) {
2677 s->dma_length = s->length;
2678 mapped_elems++;
2679 } else
2680 goto unmap;
2681 }
2682
2683 domain_flush_complete(domain);
2684
2685 out:
2686 spin_unlock_irqrestore(&domain->lock, flags);
2687
2688 return mapped_elems;
2689 unmap:
2690 for_each_sg(sglist, s, mapped_elems, i) {
2691 if (s->dma_address)
2692 __unmap_single(domain->priv, s->dma_address,
2693 s->dma_length, dir);
2694 s->dma_address = s->dma_length = 0;
2695 }
2696
2697 mapped_elems = 0;
2698
2699 goto out;
2700 }
2701
2702 /*
2703 * The exported map_sg function for dma_ops (handles scatter-gather
2704 * lists).
2705 */
2706 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2707 int nelems, enum dma_data_direction dir,
2708 struct dma_attrs *attrs)
2709 {
2710 unsigned long flags;
2711 struct protection_domain *domain;
2712 struct scatterlist *s;
2713 int i;
2714
2715 INC_STATS_COUNTER(cnt_unmap_sg);
2716
2717 domain = get_domain(dev);
2718 if (IS_ERR(domain))
2719 return;
2720
2721 spin_lock_irqsave(&domain->lock, flags);
2722
2723 for_each_sg(sglist, s, nelems, i) {
2724 __unmap_single(domain->priv, s->dma_address,
2725 s->dma_length, dir);
2726 s->dma_address = s->dma_length = 0;
2727 }
2728
2729 domain_flush_complete(domain);
2730
2731 spin_unlock_irqrestore(&domain->lock, flags);
2732 }
2733
2734 /*
2735 * The exported alloc_coherent function for dma_ops.
2736 */
2737 static void *alloc_coherent(struct device *dev, size_t size,
2738 dma_addr_t *dma_addr, gfp_t flag,
2739 struct dma_attrs *attrs)
2740 {
2741 u64 dma_mask = dev->coherent_dma_mask;
2742 struct protection_domain *domain;
2743 unsigned long flags;
2744 struct page *page;
2745
2746 INC_STATS_COUNTER(cnt_alloc_coherent);
2747
2748 domain = get_domain(dev);
2749 if (PTR_ERR(domain) == -EINVAL) {
2750 page = alloc_pages(flag, get_order(size));
2751 *dma_addr = page_to_phys(page);
2752 return page_address(page);
2753 } else if (IS_ERR(domain))
2754 return NULL;
2755
2756 size = PAGE_ALIGN(size);
2757 dma_mask = dev->coherent_dma_mask;
2758 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2759
2760 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2761 if (!page) {
2762 if (!(flag & __GFP_WAIT))
2763 return NULL;
2764
2765 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2766 get_order(size));
2767 if (!page)
2768 return NULL;
2769 }
2770
2771 if (!dma_mask)
2772 dma_mask = *dev->dma_mask;
2773
2774 spin_lock_irqsave(&domain->lock, flags);
2775
2776 *dma_addr = __map_single(dev, domain->priv, page_to_phys(page),
2777 size, DMA_BIDIRECTIONAL, true, dma_mask);
2778
2779 if (*dma_addr == DMA_ERROR_CODE) {
2780 spin_unlock_irqrestore(&domain->lock, flags);
2781 goto out_free;
2782 }
2783
2784 domain_flush_complete(domain);
2785
2786 spin_unlock_irqrestore(&domain->lock, flags);
2787
2788 return page_address(page);
2789
2790 out_free:
2791
2792 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2793 __free_pages(page, get_order(size));
2794
2795 return NULL;
2796 }
2797
2798 /*
2799 * The exported free_coherent function for dma_ops.
2800 */
2801 static void free_coherent(struct device *dev, size_t size,
2802 void *virt_addr, dma_addr_t dma_addr,
2803 struct dma_attrs *attrs)
2804 {
2805 struct protection_domain *domain;
2806 unsigned long flags;
2807 struct page *page;
2808
2809 INC_STATS_COUNTER(cnt_free_coherent);
2810
2811 page = virt_to_page(virt_addr);
2812 size = PAGE_ALIGN(size);
2813
2814 domain = get_domain(dev);
2815 if (IS_ERR(domain))
2816 goto free_mem;
2817
2818 spin_lock_irqsave(&domain->lock, flags);
2819
2820 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2821
2822 domain_flush_complete(domain);
2823
2824 spin_unlock_irqrestore(&domain->lock, flags);
2825
2826 free_mem:
2827 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2828 __free_pages(page, get_order(size));
2829 }
2830
2831 /*
2832 * This function is called by the DMA layer to find out if we can handle a
2833 * particular device. It is part of the dma_ops.
2834 */
2835 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2836 {
2837 return check_device(dev);
2838 }
2839
2840 static struct dma_map_ops amd_iommu_dma_ops = {
2841 .alloc = alloc_coherent,
2842 .free = free_coherent,
2843 .map_page = map_page,
2844 .unmap_page = unmap_page,
2845 .map_sg = map_sg,
2846 .unmap_sg = unmap_sg,
2847 .dma_supported = amd_iommu_dma_supported,
2848 };
2849
2850 int __init amd_iommu_init_api(void)
2851 {
2852 return bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2853 }
2854
2855 int __init amd_iommu_init_dma_ops(void)
2856 {
2857 iommu_detected = 1;
2858 swiotlb = 0;
2859
2860 amd_iommu_stats_init();
2861
2862 if (amd_iommu_unmap_flush)
2863 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2864 else
2865 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2866
2867 return 0;
2868 }
2869
2870 /*****************************************************************************
2871 *
2872 * The following functions belong to the exported interface of AMD IOMMU
2873 *
2874 * This interface allows access to lower level functions of the IOMMU
2875 * like protection domain handling and assignement of devices to domains
2876 * which is not possible with the dma_ops interface.
2877 *
2878 *****************************************************************************/
2879
2880 static void cleanup_domain(struct protection_domain *domain)
2881 {
2882 struct iommu_dev_data *entry;
2883 unsigned long flags;
2884
2885 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2886
2887 while (!list_empty(&domain->dev_list)) {
2888 entry = list_first_entry(&domain->dev_list,
2889 struct iommu_dev_data, list);
2890 __detach_device(entry);
2891 }
2892
2893 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2894 }
2895
2896 static void protection_domain_free(struct protection_domain *domain)
2897 {
2898 if (!domain)
2899 return;
2900
2901 del_domain_from_list(domain);
2902
2903 if (domain->id)
2904 domain_id_free(domain->id);
2905
2906 kfree(domain);
2907 }
2908
2909 static struct protection_domain *protection_domain_alloc(void)
2910 {
2911 struct protection_domain *domain;
2912
2913 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2914 if (!domain)
2915 return NULL;
2916
2917 spin_lock_init(&domain->lock);
2918 mutex_init(&domain->api_lock);
2919 domain->id = domain_id_alloc();
2920 if (!domain->id)
2921 goto out_err;
2922 INIT_LIST_HEAD(&domain->dev_list);
2923
2924 add_domain_to_list(domain);
2925
2926 return domain;
2927
2928 out_err:
2929 kfree(domain);
2930
2931 return NULL;
2932 }
2933
2934 static int alloc_passthrough_domain(void)
2935 {
2936 if (pt_domain != NULL)
2937 return 0;
2938
2939 /* allocate passthrough domain */
2940 pt_domain = protection_domain_alloc();
2941 if (!pt_domain)
2942 return -ENOMEM;
2943
2944 pt_domain->mode = PAGE_MODE_NONE;
2945
2946 return 0;
2947 }
2948
2949 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2950 {
2951 struct protection_domain *pdomain;
2952 struct dma_ops_domain *dma_domain;
2953
2954 switch (type) {
2955 case IOMMU_DOMAIN_UNMANAGED:
2956 pdomain = protection_domain_alloc();
2957 if (!pdomain)
2958 return NULL;
2959
2960 pdomain->mode = PAGE_MODE_3_LEVEL;
2961 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2962 if (!pdomain->pt_root) {
2963 protection_domain_free(pdomain);
2964 return NULL;
2965 }
2966
2967 pdomain->domain.geometry.aperture_start = 0;
2968 pdomain->domain.geometry.aperture_end = ~0ULL;
2969 pdomain->domain.geometry.force_aperture = true;
2970
2971 break;
2972 case IOMMU_DOMAIN_DMA:
2973 dma_domain = dma_ops_domain_alloc();
2974 if (!dma_domain) {
2975 pr_err("AMD-Vi: Failed to allocate\n");
2976 return NULL;
2977 }
2978 pdomain = &dma_domain->domain;
2979 break;
2980 case IOMMU_DOMAIN_IDENTITY:
2981 pdomain = protection_domain_alloc();
2982 if (!pdomain)
2983 return NULL;
2984
2985 pdomain->mode = PAGE_MODE_NONE;
2986 break;
2987 default:
2988 return NULL;
2989 }
2990
2991 return &pdomain->domain;
2992 }
2993
2994 static void amd_iommu_domain_free(struct iommu_domain *dom)
2995 {
2996 struct protection_domain *domain;
2997
2998 if (!dom)
2999 return;
3000
3001 domain = to_pdomain(dom);
3002
3003 if (domain->dev_cnt > 0)
3004 cleanup_domain(domain);
3005
3006 BUG_ON(domain->dev_cnt != 0);
3007
3008 if (domain->mode != PAGE_MODE_NONE)
3009 free_pagetable(domain);
3010
3011 if (domain->flags & PD_IOMMUV2_MASK)
3012 free_gcr3_table(domain);
3013
3014 protection_domain_free(domain);
3015 }
3016
3017 static void amd_iommu_detach_device(struct iommu_domain *dom,
3018 struct device *dev)
3019 {
3020 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3021 struct amd_iommu *iommu;
3022 u16 devid;
3023
3024 if (!check_device(dev))
3025 return;
3026
3027 devid = get_device_id(dev);
3028
3029 if (dev_data->domain != NULL)
3030 detach_device(dev);
3031
3032 iommu = amd_iommu_rlookup_table[devid];
3033 if (!iommu)
3034 return;
3035
3036 iommu_completion_wait(iommu);
3037 }
3038
3039 static int amd_iommu_attach_device(struct iommu_domain *dom,
3040 struct device *dev)
3041 {
3042 struct protection_domain *domain = to_pdomain(dom);
3043 struct iommu_dev_data *dev_data;
3044 struct amd_iommu *iommu;
3045 int ret;
3046
3047 if (!check_device(dev))
3048 return -EINVAL;
3049
3050 dev_data = dev->archdata.iommu;
3051
3052 iommu = amd_iommu_rlookup_table[dev_data->devid];
3053 if (!iommu)
3054 return -EINVAL;
3055
3056 if (dev_data->domain)
3057 detach_device(dev);
3058
3059 ret = attach_device(dev, domain);
3060
3061 iommu_completion_wait(iommu);
3062
3063 return ret;
3064 }
3065
3066 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3067 phys_addr_t paddr, size_t page_size, int iommu_prot)
3068 {
3069 struct protection_domain *domain = to_pdomain(dom);
3070 int prot = 0;
3071 int ret;
3072
3073 if (domain->mode == PAGE_MODE_NONE)
3074 return -EINVAL;
3075
3076 if (iommu_prot & IOMMU_READ)
3077 prot |= IOMMU_PROT_IR;
3078 if (iommu_prot & IOMMU_WRITE)
3079 prot |= IOMMU_PROT_IW;
3080
3081 mutex_lock(&domain->api_lock);
3082 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3083 mutex_unlock(&domain->api_lock);
3084
3085 return ret;
3086 }
3087
3088 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3089 size_t page_size)
3090 {
3091 struct protection_domain *domain = to_pdomain(dom);
3092 size_t unmap_size;
3093
3094 if (domain->mode == PAGE_MODE_NONE)
3095 return -EINVAL;
3096
3097 mutex_lock(&domain->api_lock);
3098 unmap_size = iommu_unmap_page(domain, iova, page_size);
3099 mutex_unlock(&domain->api_lock);
3100
3101 domain_flush_tlb_pde(domain);
3102
3103 return unmap_size;
3104 }
3105
3106 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3107 dma_addr_t iova)
3108 {
3109 struct protection_domain *domain = to_pdomain(dom);
3110 unsigned long offset_mask, pte_pgsize;
3111 u64 *pte, __pte;
3112
3113 if (domain->mode == PAGE_MODE_NONE)
3114 return iova;
3115
3116 pte = fetch_pte(domain, iova, &pte_pgsize);
3117
3118 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3119 return 0;
3120
3121 offset_mask = pte_pgsize - 1;
3122 __pte = *pte & PM_ADDR_MASK;
3123
3124 return (__pte & ~offset_mask) | (iova & offset_mask);
3125 }
3126
3127 static bool amd_iommu_capable(enum iommu_cap cap)
3128 {
3129 switch (cap) {
3130 case IOMMU_CAP_CACHE_COHERENCY:
3131 return true;
3132 case IOMMU_CAP_INTR_REMAP:
3133 return (irq_remapping_enabled == 1);
3134 case IOMMU_CAP_NOEXEC:
3135 return false;
3136 }
3137
3138 return false;
3139 }
3140
3141 static void amd_iommu_get_dm_regions(struct device *dev,
3142 struct list_head *head)
3143 {
3144 struct unity_map_entry *entry;
3145 u16 devid;
3146
3147 devid = get_device_id(dev);
3148
3149 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3150 struct iommu_dm_region *region;
3151
3152 if (devid < entry->devid_start || devid > entry->devid_end)
3153 continue;
3154
3155 region = kzalloc(sizeof(*region), GFP_KERNEL);
3156 if (!region) {
3157 pr_err("Out of memory allocating dm-regions for %s\n",
3158 dev_name(dev));
3159 return;
3160 }
3161
3162 region->start = entry->address_start;
3163 region->length = entry->address_end - entry->address_start;
3164 if (entry->prot & IOMMU_PROT_IR)
3165 region->prot |= IOMMU_READ;
3166 if (entry->prot & IOMMU_PROT_IW)
3167 region->prot |= IOMMU_WRITE;
3168
3169 list_add_tail(&region->list, head);
3170 }
3171 }
3172
3173 static void amd_iommu_put_dm_regions(struct device *dev,
3174 struct list_head *head)
3175 {
3176 struct iommu_dm_region *entry, *next;
3177
3178 list_for_each_entry_safe(entry, next, head, list)
3179 kfree(entry);
3180 }
3181
3182 static const struct iommu_ops amd_iommu_ops = {
3183 .capable = amd_iommu_capable,
3184 .domain_alloc = amd_iommu_domain_alloc,
3185 .domain_free = amd_iommu_domain_free,
3186 .attach_dev = amd_iommu_attach_device,
3187 .detach_dev = amd_iommu_detach_device,
3188 .map = amd_iommu_map,
3189 .unmap = amd_iommu_unmap,
3190 .map_sg = default_iommu_map_sg,
3191 .iova_to_phys = amd_iommu_iova_to_phys,
3192 .add_device = amd_iommu_add_device,
3193 .remove_device = amd_iommu_remove_device,
3194 .get_dm_regions = amd_iommu_get_dm_regions,
3195 .put_dm_regions = amd_iommu_put_dm_regions,
3196 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3197 };
3198
3199 /*****************************************************************************
3200 *
3201 * The next functions do a basic initialization of IOMMU for pass through
3202 * mode
3203 *
3204 * In passthrough mode the IOMMU is initialized and enabled but not used for
3205 * DMA-API translation.
3206 *
3207 *****************************************************************************/
3208
3209 int __init amd_iommu_init_passthrough(void)
3210 {
3211 struct iommu_dev_data *dev_data;
3212 struct pci_dev *dev = NULL;
3213 int ret;
3214
3215 ret = alloc_passthrough_domain();
3216 if (ret)
3217 return ret;
3218
3219 for_each_pci_dev(dev) {
3220 if (!check_device(&dev->dev))
3221 continue;
3222
3223 dev_data = get_dev_data(&dev->dev);
3224 dev_data->passthrough = true;
3225
3226 attach_device(&dev->dev, pt_domain);
3227 }
3228
3229 amd_iommu_stats_init();
3230
3231 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3232
3233 return 0;
3234 }
3235
3236 /* IOMMUv2 specific functions */
3237 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3238 {
3239 return atomic_notifier_chain_register(&ppr_notifier, nb);
3240 }
3241 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3242
3243 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3244 {
3245 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3246 }
3247 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3248
3249 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3250 {
3251 struct protection_domain *domain = to_pdomain(dom);
3252 unsigned long flags;
3253
3254 spin_lock_irqsave(&domain->lock, flags);
3255
3256 /* Update data structure */
3257 domain->mode = PAGE_MODE_NONE;
3258 domain->updated = true;
3259
3260 /* Make changes visible to IOMMUs */
3261 update_domain(domain);
3262
3263 /* Page-table is not visible to IOMMU anymore, so free it */
3264 free_pagetable(domain);
3265
3266 spin_unlock_irqrestore(&domain->lock, flags);
3267 }
3268 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3269
3270 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3271 {
3272 struct protection_domain *domain = to_pdomain(dom);
3273 unsigned long flags;
3274 int levels, ret;
3275
3276 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3277 return -EINVAL;
3278
3279 /* Number of GCR3 table levels required */
3280 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3281 levels += 1;
3282
3283 if (levels > amd_iommu_max_glx_val)
3284 return -EINVAL;
3285
3286 spin_lock_irqsave(&domain->lock, flags);
3287
3288 /*
3289 * Save us all sanity checks whether devices already in the
3290 * domain support IOMMUv2. Just force that the domain has no
3291 * devices attached when it is switched into IOMMUv2 mode.
3292 */
3293 ret = -EBUSY;
3294 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3295 goto out;
3296
3297 ret = -ENOMEM;
3298 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3299 if (domain->gcr3_tbl == NULL)
3300 goto out;
3301
3302 domain->glx = levels;
3303 domain->flags |= PD_IOMMUV2_MASK;
3304 domain->updated = true;
3305
3306 update_domain(domain);
3307
3308 ret = 0;
3309
3310 out:
3311 spin_unlock_irqrestore(&domain->lock, flags);
3312
3313 return ret;
3314 }
3315 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3316
3317 static int __flush_pasid(struct protection_domain *domain, int pasid,
3318 u64 address, bool size)
3319 {
3320 struct iommu_dev_data *dev_data;
3321 struct iommu_cmd cmd;
3322 int i, ret;
3323
3324 if (!(domain->flags & PD_IOMMUV2_MASK))
3325 return -EINVAL;
3326
3327 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3328
3329 /*
3330 * IOMMU TLB needs to be flushed before Device TLB to
3331 * prevent device TLB refill from IOMMU TLB
3332 */
3333 for (i = 0; i < amd_iommus_present; ++i) {
3334 if (domain->dev_iommu[i] == 0)
3335 continue;
3336
3337 ret = iommu_queue_command(amd_iommus[i], &cmd);
3338 if (ret != 0)
3339 goto out;
3340 }
3341
3342 /* Wait until IOMMU TLB flushes are complete */
3343 domain_flush_complete(domain);
3344
3345 /* Now flush device TLBs */
3346 list_for_each_entry(dev_data, &domain->dev_list, list) {
3347 struct amd_iommu *iommu;
3348 int qdep;
3349
3350 BUG_ON(!dev_data->ats.enabled);
3351
3352 qdep = dev_data->ats.qdep;
3353 iommu = amd_iommu_rlookup_table[dev_data->devid];
3354
3355 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3356 qdep, address, size);
3357
3358 ret = iommu_queue_command(iommu, &cmd);
3359 if (ret != 0)
3360 goto out;
3361 }
3362
3363 /* Wait until all device TLBs are flushed */
3364 domain_flush_complete(domain);
3365
3366 ret = 0;
3367
3368 out:
3369
3370 return ret;
3371 }
3372
3373 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3374 u64 address)
3375 {
3376 INC_STATS_COUNTER(invalidate_iotlb);
3377
3378 return __flush_pasid(domain, pasid, address, false);
3379 }
3380
3381 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3382 u64 address)
3383 {
3384 struct protection_domain *domain = to_pdomain(dom);
3385 unsigned long flags;
3386 int ret;
3387
3388 spin_lock_irqsave(&domain->lock, flags);
3389 ret = __amd_iommu_flush_page(domain, pasid, address);
3390 spin_unlock_irqrestore(&domain->lock, flags);
3391
3392 return ret;
3393 }
3394 EXPORT_SYMBOL(amd_iommu_flush_page);
3395
3396 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3397 {
3398 INC_STATS_COUNTER(invalidate_iotlb_all);
3399
3400 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3401 true);
3402 }
3403
3404 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3405 {
3406 struct protection_domain *domain = to_pdomain(dom);
3407 unsigned long flags;
3408 int ret;
3409
3410 spin_lock_irqsave(&domain->lock, flags);
3411 ret = __amd_iommu_flush_tlb(domain, pasid);
3412 spin_unlock_irqrestore(&domain->lock, flags);
3413
3414 return ret;
3415 }
3416 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3417
3418 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3419 {
3420 int index;
3421 u64 *pte;
3422
3423 while (true) {
3424
3425 index = (pasid >> (9 * level)) & 0x1ff;
3426 pte = &root[index];
3427
3428 if (level == 0)
3429 break;
3430
3431 if (!(*pte & GCR3_VALID)) {
3432 if (!alloc)
3433 return NULL;
3434
3435 root = (void *)get_zeroed_page(GFP_ATOMIC);
3436 if (root == NULL)
3437 return NULL;
3438
3439 *pte = __pa(root) | GCR3_VALID;
3440 }
3441
3442 root = __va(*pte & PAGE_MASK);
3443
3444 level -= 1;
3445 }
3446
3447 return pte;
3448 }
3449
3450 static int __set_gcr3(struct protection_domain *domain, int pasid,
3451 unsigned long cr3)
3452 {
3453 u64 *pte;
3454
3455 if (domain->mode != PAGE_MODE_NONE)
3456 return -EINVAL;
3457
3458 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3459 if (pte == NULL)
3460 return -ENOMEM;
3461
3462 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3463
3464 return __amd_iommu_flush_tlb(domain, pasid);
3465 }
3466
3467 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3468 {
3469 u64 *pte;
3470
3471 if (domain->mode != PAGE_MODE_NONE)
3472 return -EINVAL;
3473
3474 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3475 if (pte == NULL)
3476 return 0;
3477
3478 *pte = 0;
3479
3480 return __amd_iommu_flush_tlb(domain, pasid);
3481 }
3482
3483 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3484 unsigned long cr3)
3485 {
3486 struct protection_domain *domain = to_pdomain(dom);
3487 unsigned long flags;
3488 int ret;
3489
3490 spin_lock_irqsave(&domain->lock, flags);
3491 ret = __set_gcr3(domain, pasid, cr3);
3492 spin_unlock_irqrestore(&domain->lock, flags);
3493
3494 return ret;
3495 }
3496 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3497
3498 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3499 {
3500 struct protection_domain *domain = to_pdomain(dom);
3501 unsigned long flags;
3502 int ret;
3503
3504 spin_lock_irqsave(&domain->lock, flags);
3505 ret = __clear_gcr3(domain, pasid);
3506 spin_unlock_irqrestore(&domain->lock, flags);
3507
3508 return ret;
3509 }
3510 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3511
3512 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3513 int status, int tag)
3514 {
3515 struct iommu_dev_data *dev_data;
3516 struct amd_iommu *iommu;
3517 struct iommu_cmd cmd;
3518
3519 INC_STATS_COUNTER(complete_ppr);
3520
3521 dev_data = get_dev_data(&pdev->dev);
3522 iommu = amd_iommu_rlookup_table[dev_data->devid];
3523
3524 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3525 tag, dev_data->pri_tlp);
3526
3527 return iommu_queue_command(iommu, &cmd);
3528 }
3529 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3530
3531 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3532 {
3533 struct protection_domain *pdomain;
3534
3535 pdomain = get_domain(&pdev->dev);
3536 if (IS_ERR(pdomain))
3537 return NULL;
3538
3539 /* Only return IOMMUv2 domains */
3540 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3541 return NULL;
3542
3543 return &pdomain->domain;
3544 }
3545 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3546
3547 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3548 {
3549 struct iommu_dev_data *dev_data;
3550
3551 if (!amd_iommu_v2_supported())
3552 return;
3553
3554 dev_data = get_dev_data(&pdev->dev);
3555 dev_data->errata |= (1 << erratum);
3556 }
3557 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3558
3559 int amd_iommu_device_info(struct pci_dev *pdev,
3560 struct amd_iommu_device_info *info)
3561 {
3562 int max_pasids;
3563 int pos;
3564
3565 if (pdev == NULL || info == NULL)
3566 return -EINVAL;
3567
3568 if (!amd_iommu_v2_supported())
3569 return -EINVAL;
3570
3571 memset(info, 0, sizeof(*info));
3572
3573 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3574 if (pos)
3575 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3576
3577 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3578 if (pos)
3579 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3580
3581 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3582 if (pos) {
3583 int features;
3584
3585 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3586 max_pasids = min(max_pasids, (1 << 20));
3587
3588 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3589 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3590
3591 features = pci_pasid_features(pdev);
3592 if (features & PCI_PASID_CAP_EXEC)
3593 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3594 if (features & PCI_PASID_CAP_PRIV)
3595 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3596 }
3597
3598 return 0;
3599 }
3600 EXPORT_SYMBOL(amd_iommu_device_info);
3601
3602 #ifdef CONFIG_IRQ_REMAP
3603
3604 /*****************************************************************************
3605 *
3606 * Interrupt Remapping Implementation
3607 *
3608 *****************************************************************************/
3609
3610 union irte {
3611 u32 val;
3612 struct {
3613 u32 valid : 1,
3614 no_fault : 1,
3615 int_type : 3,
3616 rq_eoi : 1,
3617 dm : 1,
3618 rsvd_1 : 1,
3619 destination : 8,
3620 vector : 8,
3621 rsvd_2 : 8;
3622 } fields;
3623 };
3624
3625 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3626 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3627 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3628 #define DTE_IRQ_REMAP_ENABLE 1ULL
3629
3630 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3631 {
3632 u64 dte;
3633
3634 dte = amd_iommu_dev_table[devid].data[2];
3635 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3636 dte |= virt_to_phys(table->table);
3637 dte |= DTE_IRQ_REMAP_INTCTL;
3638 dte |= DTE_IRQ_TABLE_LEN;
3639 dte |= DTE_IRQ_REMAP_ENABLE;
3640
3641 amd_iommu_dev_table[devid].data[2] = dte;
3642 }
3643
3644 #define IRTE_ALLOCATED (~1U)
3645
3646 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3647 {
3648 struct irq_remap_table *table = NULL;
3649 struct amd_iommu *iommu;
3650 unsigned long flags;
3651 u16 alias;
3652
3653 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3654
3655 iommu = amd_iommu_rlookup_table[devid];
3656 if (!iommu)
3657 goto out_unlock;
3658
3659 table = irq_lookup_table[devid];
3660 if (table)
3661 goto out;
3662
3663 alias = amd_iommu_alias_table[devid];
3664 table = irq_lookup_table[alias];
3665 if (table) {
3666 irq_lookup_table[devid] = table;
3667 set_dte_irq_entry(devid, table);
3668 iommu_flush_dte(iommu, devid);
3669 goto out;
3670 }
3671
3672 /* Nothing there yet, allocate new irq remapping table */
3673 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3674 if (!table)
3675 goto out;
3676
3677 /* Initialize table spin-lock */
3678 spin_lock_init(&table->lock);
3679
3680 if (ioapic)
3681 /* Keep the first 32 indexes free for IOAPIC interrupts */
3682 table->min_index = 32;
3683
3684 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3685 if (!table->table) {
3686 kfree(table);
3687 table = NULL;
3688 goto out;
3689 }
3690
3691 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3692
3693 if (ioapic) {
3694 int i;
3695
3696 for (i = 0; i < 32; ++i)
3697 table->table[i] = IRTE_ALLOCATED;
3698 }
3699
3700 irq_lookup_table[devid] = table;
3701 set_dte_irq_entry(devid, table);
3702 iommu_flush_dte(iommu, devid);
3703 if (devid != alias) {
3704 irq_lookup_table[alias] = table;
3705 set_dte_irq_entry(alias, table);
3706 iommu_flush_dte(iommu, alias);
3707 }
3708
3709 out:
3710 iommu_completion_wait(iommu);
3711
3712 out_unlock:
3713 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3714
3715 return table;
3716 }
3717
3718 static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3719 {
3720 struct irq_remap_table *table;
3721 unsigned long flags;
3722 int index, c;
3723
3724 table = get_irq_table(devid, false);
3725 if (!table)
3726 return -ENODEV;
3727
3728 spin_lock_irqsave(&table->lock, flags);
3729
3730 /* Scan table for free entries */
3731 for (c = 0, index = table->min_index;
3732 index < MAX_IRQS_PER_TABLE;
3733 ++index) {
3734 if (table->table[index] == 0)
3735 c += 1;
3736 else
3737 c = 0;
3738
3739 if (c == count) {
3740 struct irq_2_irte *irte_info;
3741
3742 for (; c != 0; --c)
3743 table->table[index - c + 1] = IRTE_ALLOCATED;
3744
3745 index -= count - 1;
3746
3747 cfg->remapped = 1;
3748 irte_info = &cfg->irq_2_irte;
3749 irte_info->devid = devid;
3750 irte_info->index = index;
3751
3752 goto out;
3753 }
3754 }
3755
3756 index = -ENOSPC;
3757
3758 out:
3759 spin_unlock_irqrestore(&table->lock, flags);
3760
3761 return index;
3762 }
3763
3764 static int get_irte(u16 devid, int index, union irte *irte)
3765 {
3766 struct irq_remap_table *table;
3767 unsigned long flags;
3768
3769 table = get_irq_table(devid, false);
3770 if (!table)
3771 return -ENOMEM;
3772
3773 spin_lock_irqsave(&table->lock, flags);
3774 irte->val = table->table[index];
3775 spin_unlock_irqrestore(&table->lock, flags);
3776
3777 return 0;
3778 }
3779
3780 static int modify_irte(u16 devid, int index, union irte irte)
3781 {
3782 struct irq_remap_table *table;
3783 struct amd_iommu *iommu;
3784 unsigned long flags;
3785
3786 iommu = amd_iommu_rlookup_table[devid];
3787 if (iommu == NULL)
3788 return -EINVAL;
3789
3790 table = get_irq_table(devid, false);
3791 if (!table)
3792 return -ENOMEM;
3793
3794 spin_lock_irqsave(&table->lock, flags);
3795 table->table[index] = irte.val;
3796 spin_unlock_irqrestore(&table->lock, flags);
3797
3798 iommu_flush_irt(iommu, devid);
3799 iommu_completion_wait(iommu);
3800
3801 return 0;
3802 }
3803
3804 static void free_irte(u16 devid, int index)
3805 {
3806 struct irq_remap_table *table;
3807 struct amd_iommu *iommu;
3808 unsigned long flags;
3809
3810 iommu = amd_iommu_rlookup_table[devid];
3811 if (iommu == NULL)
3812 return;
3813
3814 table = get_irq_table(devid, false);
3815 if (!table)
3816 return;
3817
3818 spin_lock_irqsave(&table->lock, flags);
3819 table->table[index] = 0;
3820 spin_unlock_irqrestore(&table->lock, flags);
3821
3822 iommu_flush_irt(iommu, devid);
3823 iommu_completion_wait(iommu);
3824 }
3825
3826 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
3827 unsigned int destination, int vector,
3828 struct io_apic_irq_attr *attr)
3829 {
3830 struct irq_remap_table *table;
3831 struct irq_2_irte *irte_info;
3832 struct irq_cfg *cfg;
3833 union irte irte;
3834 int ioapic_id;
3835 int index;
3836 int devid;
3837 int ret;
3838
3839 cfg = irq_cfg(irq);
3840 if (!cfg)
3841 return -EINVAL;
3842
3843 irte_info = &cfg->irq_2_irte;
3844 ioapic_id = mpc_ioapic_id(attr->ioapic);
3845 devid = get_ioapic_devid(ioapic_id);
3846
3847 if (devid < 0)
3848 return devid;
3849
3850 table = get_irq_table(devid, true);
3851 if (table == NULL)
3852 return -ENOMEM;
3853
3854 index = attr->ioapic_pin;
3855
3856 /* Setup IRQ remapping info */
3857 cfg->remapped = 1;
3858 irte_info->devid = devid;
3859 irte_info->index = index;
3860
3861 /* Setup IRTE for IOMMU */
3862 irte.val = 0;
3863 irte.fields.vector = vector;
3864 irte.fields.int_type = apic->irq_delivery_mode;
3865 irte.fields.destination = destination;
3866 irte.fields.dm = apic->irq_dest_mode;
3867 irte.fields.valid = 1;
3868
3869 ret = modify_irte(devid, index, irte);
3870 if (ret)
3871 return ret;
3872
3873 /* Setup IOAPIC entry */
3874 memset(entry, 0, sizeof(*entry));
3875
3876 entry->vector = index;
3877 entry->mask = 0;
3878 entry->trigger = attr->trigger;
3879 entry->polarity = attr->polarity;
3880
3881 /*
3882 * Mask level triggered irqs.
3883 */
3884 if (attr->trigger)
3885 entry->mask = 1;
3886
3887 return 0;
3888 }
3889
3890 static int set_affinity(struct irq_data *data, const struct cpumask *mask,
3891 bool force)
3892 {
3893 struct irq_2_irte *irte_info;
3894 unsigned int dest, irq;
3895 struct irq_cfg *cfg;
3896 union irte irte;
3897 int err;
3898
3899 if (!config_enabled(CONFIG_SMP))
3900 return -1;
3901
3902 cfg = irqd_cfg(data);
3903 irq = data->irq;
3904 irte_info = &cfg->irq_2_irte;
3905
3906 if (!cpumask_intersects(mask, cpu_online_mask))
3907 return -EINVAL;
3908
3909 if (get_irte(irte_info->devid, irte_info->index, &irte))
3910 return -EBUSY;
3911
3912 if (assign_irq_vector(irq, cfg, mask))
3913 return -EBUSY;
3914
3915 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
3916 if (err) {
3917 if (assign_irq_vector(irq, cfg, data->affinity))
3918 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
3919 return err;
3920 }
3921
3922 irte.fields.vector = cfg->vector;
3923 irte.fields.destination = dest;
3924
3925 modify_irte(irte_info->devid, irte_info->index, irte);
3926
3927 if (cfg->move_in_progress)
3928 send_cleanup_vector(cfg);
3929
3930 cpumask_copy(data->affinity, mask);
3931
3932 return 0;
3933 }
3934
3935 static int free_irq(int irq)
3936 {
3937 struct irq_2_irte *irte_info;
3938 struct irq_cfg *cfg;
3939
3940 cfg = irq_cfg(irq);
3941 if (!cfg)
3942 return -EINVAL;
3943
3944 irte_info = &cfg->irq_2_irte;
3945
3946 free_irte(irte_info->devid, irte_info->index);
3947
3948 return 0;
3949 }
3950
3951 static void compose_msi_msg(struct pci_dev *pdev,
3952 unsigned int irq, unsigned int dest,
3953 struct msi_msg *msg, u8 hpet_id)
3954 {
3955 struct irq_2_irte *irte_info;
3956 struct irq_cfg *cfg;
3957 union irte irte;
3958
3959 cfg = irq_cfg(irq);
3960 if (!cfg)
3961 return;
3962
3963 irte_info = &cfg->irq_2_irte;
3964
3965 irte.val = 0;
3966 irte.fields.vector = cfg->vector;
3967 irte.fields.int_type = apic->irq_delivery_mode;
3968 irte.fields.destination = dest;
3969 irte.fields.dm = apic->irq_dest_mode;
3970 irte.fields.valid = 1;
3971
3972 modify_irte(irte_info->devid, irte_info->index, irte);
3973
3974 msg->address_hi = MSI_ADDR_BASE_HI;
3975 msg->address_lo = MSI_ADDR_BASE_LO;
3976 msg->data = irte_info->index;
3977 }
3978
3979 static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
3980 {
3981 struct irq_cfg *cfg;
3982 int index;
3983 u16 devid;
3984
3985 if (!pdev)
3986 return -EINVAL;
3987
3988 cfg = irq_cfg(irq);
3989 if (!cfg)
3990 return -EINVAL;
3991
3992 devid = get_device_id(&pdev->dev);
3993 index = alloc_irq_index(cfg, devid, nvec);
3994
3995 return index < 0 ? MAX_IRQS_PER_TABLE : index;
3996 }
3997
3998 static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
3999 int index, int offset)
4000 {
4001 struct irq_2_irte *irte_info;
4002 struct irq_cfg *cfg;
4003 u16 devid;
4004
4005 if (!pdev)
4006 return -EINVAL;
4007
4008 cfg = irq_cfg(irq);
4009 if (!cfg)
4010 return -EINVAL;
4011
4012 if (index >= MAX_IRQS_PER_TABLE)
4013 return 0;
4014
4015 devid = get_device_id(&pdev->dev);
4016 irte_info = &cfg->irq_2_irte;
4017
4018 cfg->remapped = 1;
4019 irte_info->devid = devid;
4020 irte_info->index = index + offset;
4021
4022 return 0;
4023 }
4024
4025 static int alloc_hpet_msi(unsigned int irq, unsigned int id)
4026 {
4027 struct irq_2_irte *irte_info;
4028 struct irq_cfg *cfg;
4029 int index, devid;
4030
4031 cfg = irq_cfg(irq);
4032 if (!cfg)
4033 return -EINVAL;
4034
4035 irte_info = &cfg->irq_2_irte;
4036 devid = get_hpet_devid(id);
4037 if (devid < 0)
4038 return devid;
4039
4040 index = alloc_irq_index(cfg, devid, 1);
4041 if (index < 0)
4042 return index;
4043
4044 cfg->remapped = 1;
4045 irte_info->devid = devid;
4046 irte_info->index = index;
4047
4048 return 0;
4049 }
4050
4051 struct irq_remap_ops amd_iommu_irq_ops = {
4052 .prepare = amd_iommu_prepare,
4053 .enable = amd_iommu_enable,
4054 .disable = amd_iommu_disable,
4055 .reenable = amd_iommu_reenable,
4056 .enable_faulting = amd_iommu_enable_faulting,
4057 .setup_ioapic_entry = setup_ioapic_entry,
4058 .set_affinity = set_affinity,
4059 .free_irq = free_irq,
4060 .compose_msi_msg = compose_msi_msg,
4061 .msi_alloc_irq = msi_alloc_irq,
4062 .msi_setup_irq = msi_setup_irq,
4063 .alloc_hpet_msi = alloc_hpet_msi,
4064 };
4065 #endif
Linux kernel - Deliverables
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