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Merge tag 'omap-for-v4.5/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <linux/dma-contiguous.h>
37 #include <linux/irqdomain.h>
38 #include <linux/percpu.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/io_apic.h>
41 #include <asm/apic.h>
42 #include <asm/hw_irq.h>
43 #include <asm/msidef.h>
44 #include <asm/proto.h>
45 #include <asm/iommu.h>
46 #include <asm/gart.h>
47 #include <asm/dma.h>
48
49 #include "amd_iommu_proto.h"
50 #include "amd_iommu_types.h"
51 #include "irq_remapping.h"
52
53 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
54
55 #define LOOP_TIMEOUT 100000
56
57 /*
58 * This bitmap is used to advertise the page sizes our hardware support
59 * to the IOMMU core, which will then use this information to split
60 * physically contiguous memory regions it is mapping into page sizes
61 * that we support.
62 *
63 * 512GB Pages are not supported due to a hardware bug
64 */
65 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
66
67 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
68
69 /* List of all available dev_data structures */
70 static LIST_HEAD(dev_data_list);
71 static DEFINE_SPINLOCK(dev_data_list_lock);
72
73 LIST_HEAD(ioapic_map);
74 LIST_HEAD(hpet_map);
75
76 /*
77 * Domain for untranslated devices - only allocated
78 * if iommu=pt passed on kernel cmd line.
79 */
80 static const struct iommu_ops amd_iommu_ops;
81
82 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
83 int amd_iommu_max_glx_val = -1;
84
85 static struct dma_map_ops amd_iommu_dma_ops;
86
87 /*
88 * This struct contains device specific data for the IOMMU
89 */
90 struct iommu_dev_data {
91 struct list_head list; /* For domain->dev_list */
92 struct list_head dev_data_list; /* For global dev_data_list */
93 struct protection_domain *domain; /* Domain the device is bound to */
94 u16 devid; /* PCI Device ID */
95 bool iommu_v2; /* Device can make use of IOMMUv2 */
96 bool passthrough; /* Device is identity mapped */
97 struct {
98 bool enabled;
99 int qdep;
100 } ats; /* ATS state */
101 bool pri_tlp; /* PASID TLB required for
102 PPR completions */
103 u32 errata; /* Bitmap for errata to apply */
104 };
105
106 /*
107 * general struct to manage commands send to an IOMMU
108 */
109 struct iommu_cmd {
110 u32 data[4];
111 };
112
113 struct kmem_cache *amd_iommu_irq_cache;
114
115 static void update_domain(struct protection_domain *domain);
116 static int protection_domain_init(struct protection_domain *domain);
117
118 /*
119 * For dynamic growth the aperture size is split into ranges of 128MB of
120 * DMA address space each. This struct represents one such range.
121 */
122 struct aperture_range {
123
124 spinlock_t bitmap_lock;
125
126 /* address allocation bitmap */
127 unsigned long *bitmap;
128 unsigned long offset;
129 unsigned long next_bit;
130
131 /*
132 * Array of PTE pages for the aperture. In this array we save all the
133 * leaf pages of the domain page table used for the aperture. This way
134 * we don't need to walk the page table to find a specific PTE. We can
135 * just calculate its address in constant time.
136 */
137 u64 *pte_pages[64];
138 };
139
140 /*
141 * Data container for a dma_ops specific protection domain
142 */
143 struct dma_ops_domain {
144 /* generic protection domain information */
145 struct protection_domain domain;
146
147 /* size of the aperture for the mappings */
148 unsigned long aperture_size;
149
150 /* aperture index we start searching for free addresses */
151 u32 __percpu *next_index;
152
153 /* address space relevant data */
154 struct aperture_range *aperture[APERTURE_MAX_RANGES];
155 };
156
157 /****************************************************************************
158 *
159 * Helper functions
160 *
161 ****************************************************************************/
162
163 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
164 {
165 return container_of(dom, struct protection_domain, domain);
166 }
167
168 static struct iommu_dev_data *alloc_dev_data(u16 devid)
169 {
170 struct iommu_dev_data *dev_data;
171 unsigned long flags;
172
173 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
174 if (!dev_data)
175 return NULL;
176
177 dev_data->devid = devid;
178
179 spin_lock_irqsave(&dev_data_list_lock, flags);
180 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
181 spin_unlock_irqrestore(&dev_data_list_lock, flags);
182
183 return dev_data;
184 }
185
186 static struct iommu_dev_data *search_dev_data(u16 devid)
187 {
188 struct iommu_dev_data *dev_data;
189 unsigned long flags;
190
191 spin_lock_irqsave(&dev_data_list_lock, flags);
192 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
193 if (dev_data->devid == devid)
194 goto out_unlock;
195 }
196
197 dev_data = NULL;
198
199 out_unlock:
200 spin_unlock_irqrestore(&dev_data_list_lock, flags);
201
202 return dev_data;
203 }
204
205 static struct iommu_dev_data *find_dev_data(u16 devid)
206 {
207 struct iommu_dev_data *dev_data;
208
209 dev_data = search_dev_data(devid);
210
211 if (dev_data == NULL)
212 dev_data = alloc_dev_data(devid);
213
214 return dev_data;
215 }
216
217 static inline u16 get_device_id(struct device *dev)
218 {
219 struct pci_dev *pdev = to_pci_dev(dev);
220
221 return PCI_DEVID(pdev->bus->number, pdev->devfn);
222 }
223
224 static struct iommu_dev_data *get_dev_data(struct device *dev)
225 {
226 return dev->archdata.iommu;
227 }
228
229 static bool pci_iommuv2_capable(struct pci_dev *pdev)
230 {
231 static const int caps[] = {
232 PCI_EXT_CAP_ID_ATS,
233 PCI_EXT_CAP_ID_PRI,
234 PCI_EXT_CAP_ID_PASID,
235 };
236 int i, pos;
237
238 for (i = 0; i < 3; ++i) {
239 pos = pci_find_ext_capability(pdev, caps[i]);
240 if (pos == 0)
241 return false;
242 }
243
244 return true;
245 }
246
247 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
248 {
249 struct iommu_dev_data *dev_data;
250
251 dev_data = get_dev_data(&pdev->dev);
252
253 return dev_data->errata & (1 << erratum) ? true : false;
254 }
255
256 /*
257 * This function actually applies the mapping to the page table of the
258 * dma_ops domain.
259 */
260 static void alloc_unity_mapping(struct dma_ops_domain *dma_dom,
261 struct unity_map_entry *e)
262 {
263 u64 addr;
264
265 for (addr = e->address_start; addr < e->address_end;
266 addr += PAGE_SIZE) {
267 if (addr < dma_dom->aperture_size)
268 __set_bit(addr >> PAGE_SHIFT,
269 dma_dom->aperture[0]->bitmap);
270 }
271 }
272
273 /*
274 * Inits the unity mappings required for a specific device
275 */
276 static void init_unity_mappings_for_device(struct device *dev,
277 struct dma_ops_domain *dma_dom)
278 {
279 struct unity_map_entry *e;
280 u16 devid;
281
282 devid = get_device_id(dev);
283
284 list_for_each_entry(e, &amd_iommu_unity_map, list) {
285 if (!(devid >= e->devid_start && devid <= e->devid_end))
286 continue;
287 alloc_unity_mapping(dma_dom, e);
288 }
289 }
290
291 /*
292 * This function checks if the driver got a valid device from the caller to
293 * avoid dereferencing invalid pointers.
294 */
295 static bool check_device(struct device *dev)
296 {
297 u16 devid;
298
299 if (!dev || !dev->dma_mask)
300 return false;
301
302 /* No PCI device */
303 if (!dev_is_pci(dev))
304 return false;
305
306 devid = get_device_id(dev);
307
308 /* Out of our scope? */
309 if (devid > amd_iommu_last_bdf)
310 return false;
311
312 if (amd_iommu_rlookup_table[devid] == NULL)
313 return false;
314
315 return true;
316 }
317
318 static void init_iommu_group(struct device *dev)
319 {
320 struct dma_ops_domain *dma_domain;
321 struct iommu_domain *domain;
322 struct iommu_group *group;
323
324 group = iommu_group_get_for_dev(dev);
325 if (IS_ERR(group))
326 return;
327
328 domain = iommu_group_default_domain(group);
329 if (!domain)
330 goto out;
331
332 dma_domain = to_pdomain(domain)->priv;
333
334 init_unity_mappings_for_device(dev, dma_domain);
335 out:
336 iommu_group_put(group);
337 }
338
339 static int iommu_init_device(struct device *dev)
340 {
341 struct pci_dev *pdev = to_pci_dev(dev);
342 struct iommu_dev_data *dev_data;
343
344 if (dev->archdata.iommu)
345 return 0;
346
347 dev_data = find_dev_data(get_device_id(dev));
348 if (!dev_data)
349 return -ENOMEM;
350
351 if (pci_iommuv2_capable(pdev)) {
352 struct amd_iommu *iommu;
353
354 iommu = amd_iommu_rlookup_table[dev_data->devid];
355 dev_data->iommu_v2 = iommu->is_iommu_v2;
356 }
357
358 dev->archdata.iommu = dev_data;
359
360 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
361 dev);
362
363 return 0;
364 }
365
366 static void iommu_ignore_device(struct device *dev)
367 {
368 u16 devid, alias;
369
370 devid = get_device_id(dev);
371 alias = amd_iommu_alias_table[devid];
372
373 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
374 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
375
376 amd_iommu_rlookup_table[devid] = NULL;
377 amd_iommu_rlookup_table[alias] = NULL;
378 }
379
380 static void iommu_uninit_device(struct device *dev)
381 {
382 struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev));
383
384 if (!dev_data)
385 return;
386
387 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
388 dev);
389
390 iommu_group_remove_device(dev);
391
392 /* Remove dma-ops */
393 dev->archdata.dma_ops = NULL;
394
395 /*
396 * We keep dev_data around for unplugged devices and reuse it when the
397 * device is re-plugged - not doing so would introduce a ton of races.
398 */
399 }
400
401 #ifdef CONFIG_AMD_IOMMU_STATS
402
403 /*
404 * Initialization code for statistics collection
405 */
406
407 DECLARE_STATS_COUNTER(compl_wait);
408 DECLARE_STATS_COUNTER(cnt_map_single);
409 DECLARE_STATS_COUNTER(cnt_unmap_single);
410 DECLARE_STATS_COUNTER(cnt_map_sg);
411 DECLARE_STATS_COUNTER(cnt_unmap_sg);
412 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
413 DECLARE_STATS_COUNTER(cnt_free_coherent);
414 DECLARE_STATS_COUNTER(cross_page);
415 DECLARE_STATS_COUNTER(domain_flush_single);
416 DECLARE_STATS_COUNTER(domain_flush_all);
417 DECLARE_STATS_COUNTER(alloced_io_mem);
418 DECLARE_STATS_COUNTER(total_map_requests);
419 DECLARE_STATS_COUNTER(complete_ppr);
420 DECLARE_STATS_COUNTER(invalidate_iotlb);
421 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
422 DECLARE_STATS_COUNTER(pri_requests);
423
424 static struct dentry *stats_dir;
425 static struct dentry *de_fflush;
426
427 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
428 {
429 if (stats_dir == NULL)
430 return;
431
432 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
433 &cnt->value);
434 }
435
436 static void amd_iommu_stats_init(void)
437 {
438 stats_dir = debugfs_create_dir("amd-iommu", NULL);
439 if (stats_dir == NULL)
440 return;
441
442 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
443 &amd_iommu_unmap_flush);
444
445 amd_iommu_stats_add(&compl_wait);
446 amd_iommu_stats_add(&cnt_map_single);
447 amd_iommu_stats_add(&cnt_unmap_single);
448 amd_iommu_stats_add(&cnt_map_sg);
449 amd_iommu_stats_add(&cnt_unmap_sg);
450 amd_iommu_stats_add(&cnt_alloc_coherent);
451 amd_iommu_stats_add(&cnt_free_coherent);
452 amd_iommu_stats_add(&cross_page);
453 amd_iommu_stats_add(&domain_flush_single);
454 amd_iommu_stats_add(&domain_flush_all);
455 amd_iommu_stats_add(&alloced_io_mem);
456 amd_iommu_stats_add(&total_map_requests);
457 amd_iommu_stats_add(&complete_ppr);
458 amd_iommu_stats_add(&invalidate_iotlb);
459 amd_iommu_stats_add(&invalidate_iotlb_all);
460 amd_iommu_stats_add(&pri_requests);
461 }
462
463 #endif
464
465 /****************************************************************************
466 *
467 * Interrupt handling functions
468 *
469 ****************************************************************************/
470
471 static void dump_dte_entry(u16 devid)
472 {
473 int i;
474
475 for (i = 0; i < 4; ++i)
476 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
477 amd_iommu_dev_table[devid].data[i]);
478 }
479
480 static void dump_command(unsigned long phys_addr)
481 {
482 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
483 int i;
484
485 for (i = 0; i < 4; ++i)
486 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
487 }
488
489 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
490 {
491 int type, devid, domid, flags;
492 volatile u32 *event = __evt;
493 int count = 0;
494 u64 address;
495
496 retry:
497 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
498 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
499 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
500 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
501 address = (u64)(((u64)event[3]) << 32) | event[2];
502
503 if (type == 0) {
504 /* Did we hit the erratum? */
505 if (++count == LOOP_TIMEOUT) {
506 pr_err("AMD-Vi: No event written to event log\n");
507 return;
508 }
509 udelay(1);
510 goto retry;
511 }
512
513 printk(KERN_ERR "AMD-Vi: Event logged [");
514
515 switch (type) {
516 case EVENT_TYPE_ILL_DEV:
517 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
518 "address=0x%016llx flags=0x%04x]\n",
519 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
520 address, flags);
521 dump_dte_entry(devid);
522 break;
523 case EVENT_TYPE_IO_FAULT:
524 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
525 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
526 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
527 domid, address, flags);
528 break;
529 case EVENT_TYPE_DEV_TAB_ERR:
530 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
531 "address=0x%016llx flags=0x%04x]\n",
532 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
533 address, flags);
534 break;
535 case EVENT_TYPE_PAGE_TAB_ERR:
536 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
537 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
538 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
539 domid, address, flags);
540 break;
541 case EVENT_TYPE_ILL_CMD:
542 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
543 dump_command(address);
544 break;
545 case EVENT_TYPE_CMD_HARD_ERR:
546 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
547 "flags=0x%04x]\n", address, flags);
548 break;
549 case EVENT_TYPE_IOTLB_INV_TO:
550 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
551 "address=0x%016llx]\n",
552 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
553 address);
554 break;
555 case EVENT_TYPE_INV_DEV_REQ:
556 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
557 "address=0x%016llx flags=0x%04x]\n",
558 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
559 address, flags);
560 break;
561 default:
562 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
563 }
564
565 memset(__evt, 0, 4 * sizeof(u32));
566 }
567
568 static void iommu_poll_events(struct amd_iommu *iommu)
569 {
570 u32 head, tail;
571
572 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
573 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
574
575 while (head != tail) {
576 iommu_print_event(iommu, iommu->evt_buf + head);
577 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
578 }
579
580 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
581 }
582
583 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
584 {
585 struct amd_iommu_fault fault;
586
587 INC_STATS_COUNTER(pri_requests);
588
589 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
590 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
591 return;
592 }
593
594 fault.address = raw[1];
595 fault.pasid = PPR_PASID(raw[0]);
596 fault.device_id = PPR_DEVID(raw[0]);
597 fault.tag = PPR_TAG(raw[0]);
598 fault.flags = PPR_FLAGS(raw[0]);
599
600 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
601 }
602
603 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
604 {
605 u32 head, tail;
606
607 if (iommu->ppr_log == NULL)
608 return;
609
610 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
611 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
612
613 while (head != tail) {
614 volatile u64 *raw;
615 u64 entry[2];
616 int i;
617
618 raw = (u64 *)(iommu->ppr_log + head);
619
620 /*
621 * Hardware bug: Interrupt may arrive before the entry is
622 * written to memory. If this happens we need to wait for the
623 * entry to arrive.
624 */
625 for (i = 0; i < LOOP_TIMEOUT; ++i) {
626 if (PPR_REQ_TYPE(raw[0]) != 0)
627 break;
628 udelay(1);
629 }
630
631 /* Avoid memcpy function-call overhead */
632 entry[0] = raw[0];
633 entry[1] = raw[1];
634
635 /*
636 * To detect the hardware bug we need to clear the entry
637 * back to zero.
638 */
639 raw[0] = raw[1] = 0UL;
640
641 /* Update head pointer of hardware ring-buffer */
642 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
643 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
644
645 /* Handle PPR entry */
646 iommu_handle_ppr_entry(iommu, entry);
647
648 /* Refresh ring-buffer information */
649 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
650 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
651 }
652 }
653
654 irqreturn_t amd_iommu_int_thread(int irq, void *data)
655 {
656 struct amd_iommu *iommu = (struct amd_iommu *) data;
657 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
658
659 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
660 /* Enable EVT and PPR interrupts again */
661 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
662 iommu->mmio_base + MMIO_STATUS_OFFSET);
663
664 if (status & MMIO_STATUS_EVT_INT_MASK) {
665 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
666 iommu_poll_events(iommu);
667 }
668
669 if (status & MMIO_STATUS_PPR_INT_MASK) {
670 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
671 iommu_poll_ppr_log(iommu);
672 }
673
674 /*
675 * Hardware bug: ERBT1312
676 * When re-enabling interrupt (by writing 1
677 * to clear the bit), the hardware might also try to set
678 * the interrupt bit in the event status register.
679 * In this scenario, the bit will be set, and disable
680 * subsequent interrupts.
681 *
682 * Workaround: The IOMMU driver should read back the
683 * status register and check if the interrupt bits are cleared.
684 * If not, driver will need to go through the interrupt handler
685 * again and re-clear the bits
686 */
687 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
688 }
689 return IRQ_HANDLED;
690 }
691
692 irqreturn_t amd_iommu_int_handler(int irq, void *data)
693 {
694 return IRQ_WAKE_THREAD;
695 }
696
697 /****************************************************************************
698 *
699 * IOMMU command queuing functions
700 *
701 ****************************************************************************/
702
703 static int wait_on_sem(volatile u64 *sem)
704 {
705 int i = 0;
706
707 while (*sem == 0 && i < LOOP_TIMEOUT) {
708 udelay(1);
709 i += 1;
710 }
711
712 if (i == LOOP_TIMEOUT) {
713 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
714 return -EIO;
715 }
716
717 return 0;
718 }
719
720 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
721 struct iommu_cmd *cmd,
722 u32 tail)
723 {
724 u8 *target;
725
726 target = iommu->cmd_buf + tail;
727 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
728
729 /* Copy command to buffer */
730 memcpy(target, cmd, sizeof(*cmd));
731
732 /* Tell the IOMMU about it */
733 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
734 }
735
736 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
737 {
738 WARN_ON(address & 0x7ULL);
739
740 memset(cmd, 0, sizeof(*cmd));
741 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
742 cmd->data[1] = upper_32_bits(__pa(address));
743 cmd->data[2] = 1;
744 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
745 }
746
747 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
748 {
749 memset(cmd, 0, sizeof(*cmd));
750 cmd->data[0] = devid;
751 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
752 }
753
754 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
755 size_t size, u16 domid, int pde)
756 {
757 u64 pages;
758 bool s;
759
760 pages = iommu_num_pages(address, size, PAGE_SIZE);
761 s = false;
762
763 if (pages > 1) {
764 /*
765 * If we have to flush more than one page, flush all
766 * TLB entries for this domain
767 */
768 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
769 s = true;
770 }
771
772 address &= PAGE_MASK;
773
774 memset(cmd, 0, sizeof(*cmd));
775 cmd->data[1] |= domid;
776 cmd->data[2] = lower_32_bits(address);
777 cmd->data[3] = upper_32_bits(address);
778 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
779 if (s) /* size bit - we flush more than one 4kb page */
780 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
781 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
782 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
783 }
784
785 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
786 u64 address, size_t size)
787 {
788 u64 pages;
789 bool s;
790
791 pages = iommu_num_pages(address, size, PAGE_SIZE);
792 s = false;
793
794 if (pages > 1) {
795 /*
796 * If we have to flush more than one page, flush all
797 * TLB entries for this domain
798 */
799 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
800 s = true;
801 }
802
803 address &= PAGE_MASK;
804
805 memset(cmd, 0, sizeof(*cmd));
806 cmd->data[0] = devid;
807 cmd->data[0] |= (qdep & 0xff) << 24;
808 cmd->data[1] = devid;
809 cmd->data[2] = lower_32_bits(address);
810 cmd->data[3] = upper_32_bits(address);
811 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
812 if (s)
813 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
814 }
815
816 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
817 u64 address, bool size)
818 {
819 memset(cmd, 0, sizeof(*cmd));
820
821 address &= ~(0xfffULL);
822
823 cmd->data[0] = pasid;
824 cmd->data[1] = domid;
825 cmd->data[2] = lower_32_bits(address);
826 cmd->data[3] = upper_32_bits(address);
827 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
828 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
829 if (size)
830 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
831 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
832 }
833
834 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
835 int qdep, u64 address, bool size)
836 {
837 memset(cmd, 0, sizeof(*cmd));
838
839 address &= ~(0xfffULL);
840
841 cmd->data[0] = devid;
842 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
843 cmd->data[0] |= (qdep & 0xff) << 24;
844 cmd->data[1] = devid;
845 cmd->data[1] |= (pasid & 0xff) << 16;
846 cmd->data[2] = lower_32_bits(address);
847 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
848 cmd->data[3] = upper_32_bits(address);
849 if (size)
850 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
851 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
852 }
853
854 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
855 int status, int tag, bool gn)
856 {
857 memset(cmd, 0, sizeof(*cmd));
858
859 cmd->data[0] = devid;
860 if (gn) {
861 cmd->data[1] = pasid;
862 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
863 }
864 cmd->data[3] = tag & 0x1ff;
865 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
866
867 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
868 }
869
870 static void build_inv_all(struct iommu_cmd *cmd)
871 {
872 memset(cmd, 0, sizeof(*cmd));
873 CMD_SET_TYPE(cmd, CMD_INV_ALL);
874 }
875
876 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
877 {
878 memset(cmd, 0, sizeof(*cmd));
879 cmd->data[0] = devid;
880 CMD_SET_TYPE(cmd, CMD_INV_IRT);
881 }
882
883 /*
884 * Writes the command to the IOMMUs command buffer and informs the
885 * hardware about the new command.
886 */
887 static int iommu_queue_command_sync(struct amd_iommu *iommu,
888 struct iommu_cmd *cmd,
889 bool sync)
890 {
891 u32 left, tail, head, next_tail;
892 unsigned long flags;
893
894 again:
895 spin_lock_irqsave(&iommu->lock, flags);
896
897 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
898 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
899 next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
900 left = (head - next_tail) % CMD_BUFFER_SIZE;
901
902 if (left <= 2) {
903 struct iommu_cmd sync_cmd;
904 volatile u64 sem = 0;
905 int ret;
906
907 build_completion_wait(&sync_cmd, (u64)&sem);
908 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
909
910 spin_unlock_irqrestore(&iommu->lock, flags);
911
912 if ((ret = wait_on_sem(&sem)) != 0)
913 return ret;
914
915 goto again;
916 }
917
918 copy_cmd_to_buffer(iommu, cmd, tail);
919
920 /* We need to sync now to make sure all commands are processed */
921 iommu->need_sync = sync;
922
923 spin_unlock_irqrestore(&iommu->lock, flags);
924
925 return 0;
926 }
927
928 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
929 {
930 return iommu_queue_command_sync(iommu, cmd, true);
931 }
932
933 /*
934 * This function queues a completion wait command into the command
935 * buffer of an IOMMU
936 */
937 static int iommu_completion_wait(struct amd_iommu *iommu)
938 {
939 struct iommu_cmd cmd;
940 volatile u64 sem = 0;
941 int ret;
942
943 if (!iommu->need_sync)
944 return 0;
945
946 build_completion_wait(&cmd, (u64)&sem);
947
948 ret = iommu_queue_command_sync(iommu, &cmd, false);
949 if (ret)
950 return ret;
951
952 return wait_on_sem(&sem);
953 }
954
955 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
956 {
957 struct iommu_cmd cmd;
958
959 build_inv_dte(&cmd, devid);
960
961 return iommu_queue_command(iommu, &cmd);
962 }
963
964 static void iommu_flush_dte_all(struct amd_iommu *iommu)
965 {
966 u32 devid;
967
968 for (devid = 0; devid <= 0xffff; ++devid)
969 iommu_flush_dte(iommu, devid);
970
971 iommu_completion_wait(iommu);
972 }
973
974 /*
975 * This function uses heavy locking and may disable irqs for some time. But
976 * this is no issue because it is only called during resume.
977 */
978 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
979 {
980 u32 dom_id;
981
982 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
983 struct iommu_cmd cmd;
984 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
985 dom_id, 1);
986 iommu_queue_command(iommu, &cmd);
987 }
988
989 iommu_completion_wait(iommu);
990 }
991
992 static void iommu_flush_all(struct amd_iommu *iommu)
993 {
994 struct iommu_cmd cmd;
995
996 build_inv_all(&cmd);
997
998 iommu_queue_command(iommu, &cmd);
999 iommu_completion_wait(iommu);
1000 }
1001
1002 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1003 {
1004 struct iommu_cmd cmd;
1005
1006 build_inv_irt(&cmd, devid);
1007
1008 iommu_queue_command(iommu, &cmd);
1009 }
1010
1011 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1012 {
1013 u32 devid;
1014
1015 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1016 iommu_flush_irt(iommu, devid);
1017
1018 iommu_completion_wait(iommu);
1019 }
1020
1021 void iommu_flush_all_caches(struct amd_iommu *iommu)
1022 {
1023 if (iommu_feature(iommu, FEATURE_IA)) {
1024 iommu_flush_all(iommu);
1025 } else {
1026 iommu_flush_dte_all(iommu);
1027 iommu_flush_irt_all(iommu);
1028 iommu_flush_tlb_all(iommu);
1029 }
1030 }
1031
1032 /*
1033 * Command send function for flushing on-device TLB
1034 */
1035 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1036 u64 address, size_t size)
1037 {
1038 struct amd_iommu *iommu;
1039 struct iommu_cmd cmd;
1040 int qdep;
1041
1042 qdep = dev_data->ats.qdep;
1043 iommu = amd_iommu_rlookup_table[dev_data->devid];
1044
1045 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1046
1047 return iommu_queue_command(iommu, &cmd);
1048 }
1049
1050 /*
1051 * Command send function for invalidating a device table entry
1052 */
1053 static int device_flush_dte(struct iommu_dev_data *dev_data)
1054 {
1055 struct amd_iommu *iommu;
1056 u16 alias;
1057 int ret;
1058
1059 iommu = amd_iommu_rlookup_table[dev_data->devid];
1060 alias = amd_iommu_alias_table[dev_data->devid];
1061
1062 ret = iommu_flush_dte(iommu, dev_data->devid);
1063 if (!ret && alias != dev_data->devid)
1064 ret = iommu_flush_dte(iommu, alias);
1065 if (ret)
1066 return ret;
1067
1068 if (dev_data->ats.enabled)
1069 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1070
1071 return ret;
1072 }
1073
1074 /*
1075 * TLB invalidation function which is called from the mapping functions.
1076 * It invalidates a single PTE if the range to flush is within a single
1077 * page. Otherwise it flushes the whole TLB of the IOMMU.
1078 */
1079 static void __domain_flush_pages(struct protection_domain *domain,
1080 u64 address, size_t size, int pde)
1081 {
1082 struct iommu_dev_data *dev_data;
1083 struct iommu_cmd cmd;
1084 int ret = 0, i;
1085
1086 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1087
1088 for (i = 0; i < amd_iommus_present; ++i) {
1089 if (!domain->dev_iommu[i])
1090 continue;
1091
1092 /*
1093 * Devices of this domain are behind this IOMMU
1094 * We need a TLB flush
1095 */
1096 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1097 }
1098
1099 list_for_each_entry(dev_data, &domain->dev_list, list) {
1100
1101 if (!dev_data->ats.enabled)
1102 continue;
1103
1104 ret |= device_flush_iotlb(dev_data, address, size);
1105 }
1106
1107 WARN_ON(ret);
1108 }
1109
1110 static void domain_flush_pages(struct protection_domain *domain,
1111 u64 address, size_t size)
1112 {
1113 __domain_flush_pages(domain, address, size, 0);
1114 }
1115
1116 /* Flush the whole IO/TLB for a given protection domain */
1117 static void domain_flush_tlb(struct protection_domain *domain)
1118 {
1119 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1120 }
1121
1122 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1123 static void domain_flush_tlb_pde(struct protection_domain *domain)
1124 {
1125 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1126 }
1127
1128 static void domain_flush_complete(struct protection_domain *domain)
1129 {
1130 int i;
1131
1132 for (i = 0; i < amd_iommus_present; ++i) {
1133 if (!domain->dev_iommu[i])
1134 continue;
1135
1136 /*
1137 * Devices of this domain are behind this IOMMU
1138 * We need to wait for completion of all commands.
1139 */
1140 iommu_completion_wait(amd_iommus[i]);
1141 }
1142 }
1143
1144
1145 /*
1146 * This function flushes the DTEs for all devices in domain
1147 */
1148 static void domain_flush_devices(struct protection_domain *domain)
1149 {
1150 struct iommu_dev_data *dev_data;
1151
1152 list_for_each_entry(dev_data, &domain->dev_list, list)
1153 device_flush_dte(dev_data);
1154 }
1155
1156 /****************************************************************************
1157 *
1158 * The functions below are used the create the page table mappings for
1159 * unity mapped regions.
1160 *
1161 ****************************************************************************/
1162
1163 /*
1164 * This function is used to add another level to an IO page table. Adding
1165 * another level increases the size of the address space by 9 bits to a size up
1166 * to 64 bits.
1167 */
1168 static bool increase_address_space(struct protection_domain *domain,
1169 gfp_t gfp)
1170 {
1171 u64 *pte;
1172
1173 if (domain->mode == PAGE_MODE_6_LEVEL)
1174 /* address space already 64 bit large */
1175 return false;
1176
1177 pte = (void *)get_zeroed_page(gfp);
1178 if (!pte)
1179 return false;
1180
1181 *pte = PM_LEVEL_PDE(domain->mode,
1182 virt_to_phys(domain->pt_root));
1183 domain->pt_root = pte;
1184 domain->mode += 1;
1185 domain->updated = true;
1186
1187 return true;
1188 }
1189
1190 static u64 *alloc_pte(struct protection_domain *domain,
1191 unsigned long address,
1192 unsigned long page_size,
1193 u64 **pte_page,
1194 gfp_t gfp)
1195 {
1196 int level, end_lvl;
1197 u64 *pte, *page;
1198
1199 BUG_ON(!is_power_of_2(page_size));
1200
1201 while (address > PM_LEVEL_SIZE(domain->mode))
1202 increase_address_space(domain, gfp);
1203
1204 level = domain->mode - 1;
1205 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1206 address = PAGE_SIZE_ALIGN(address, page_size);
1207 end_lvl = PAGE_SIZE_LEVEL(page_size);
1208
1209 while (level > end_lvl) {
1210 u64 __pte, __npte;
1211
1212 __pte = *pte;
1213
1214 if (!IOMMU_PTE_PRESENT(__pte)) {
1215 page = (u64 *)get_zeroed_page(gfp);
1216 if (!page)
1217 return NULL;
1218
1219 __npte = PM_LEVEL_PDE(level, virt_to_phys(page));
1220
1221 if (cmpxchg64(pte, __pte, __npte)) {
1222 free_page((unsigned long)page);
1223 continue;
1224 }
1225 }
1226
1227 /* No level skipping support yet */
1228 if (PM_PTE_LEVEL(*pte) != level)
1229 return NULL;
1230
1231 level -= 1;
1232
1233 pte = IOMMU_PTE_PAGE(*pte);
1234
1235 if (pte_page && level == end_lvl)
1236 *pte_page = pte;
1237
1238 pte = &pte[PM_LEVEL_INDEX(level, address)];
1239 }
1240
1241 return pte;
1242 }
1243
1244 /*
1245 * This function checks if there is a PTE for a given dma address. If
1246 * there is one, it returns the pointer to it.
1247 */
1248 static u64 *fetch_pte(struct protection_domain *domain,
1249 unsigned long address,
1250 unsigned long *page_size)
1251 {
1252 int level;
1253 u64 *pte;
1254
1255 if (address > PM_LEVEL_SIZE(domain->mode))
1256 return NULL;
1257
1258 level = domain->mode - 1;
1259 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1260 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1261
1262 while (level > 0) {
1263
1264 /* Not Present */
1265 if (!IOMMU_PTE_PRESENT(*pte))
1266 return NULL;
1267
1268 /* Large PTE */
1269 if (PM_PTE_LEVEL(*pte) == 7 ||
1270 PM_PTE_LEVEL(*pte) == 0)
1271 break;
1272
1273 /* No level skipping support yet */
1274 if (PM_PTE_LEVEL(*pte) != level)
1275 return NULL;
1276
1277 level -= 1;
1278
1279 /* Walk to the next level */
1280 pte = IOMMU_PTE_PAGE(*pte);
1281 pte = &pte[PM_LEVEL_INDEX(level, address)];
1282 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1283 }
1284
1285 if (PM_PTE_LEVEL(*pte) == 0x07) {
1286 unsigned long pte_mask;
1287
1288 /*
1289 * If we have a series of large PTEs, make
1290 * sure to return a pointer to the first one.
1291 */
1292 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1293 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1294 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1295 }
1296
1297 return pte;
1298 }
1299
1300 /*
1301 * Generic mapping functions. It maps a physical address into a DMA
1302 * address space. It allocates the page table pages if necessary.
1303 * In the future it can be extended to a generic mapping function
1304 * supporting all features of AMD IOMMU page tables like level skipping
1305 * and full 64 bit address spaces.
1306 */
1307 static int iommu_map_page(struct protection_domain *dom,
1308 unsigned long bus_addr,
1309 unsigned long phys_addr,
1310 int prot,
1311 unsigned long page_size)
1312 {
1313 u64 __pte, *pte;
1314 int i, count;
1315
1316 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1317 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1318
1319 if (!(prot & IOMMU_PROT_MASK))
1320 return -EINVAL;
1321
1322 count = PAGE_SIZE_PTE_COUNT(page_size);
1323 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1324
1325 if (!pte)
1326 return -ENOMEM;
1327
1328 for (i = 0; i < count; ++i)
1329 if (IOMMU_PTE_PRESENT(pte[i]))
1330 return -EBUSY;
1331
1332 if (count > 1) {
1333 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1334 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1335 } else
1336 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1337
1338 if (prot & IOMMU_PROT_IR)
1339 __pte |= IOMMU_PTE_IR;
1340 if (prot & IOMMU_PROT_IW)
1341 __pte |= IOMMU_PTE_IW;
1342
1343 for (i = 0; i < count; ++i)
1344 pte[i] = __pte;
1345
1346 update_domain(dom);
1347
1348 return 0;
1349 }
1350
1351 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1352 unsigned long bus_addr,
1353 unsigned long page_size)
1354 {
1355 unsigned long long unmapped;
1356 unsigned long unmap_size;
1357 u64 *pte;
1358
1359 BUG_ON(!is_power_of_2(page_size));
1360
1361 unmapped = 0;
1362
1363 while (unmapped < page_size) {
1364
1365 pte = fetch_pte(dom, bus_addr, &unmap_size);
1366
1367 if (pte) {
1368 int i, count;
1369
1370 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1371 for (i = 0; i < count; i++)
1372 pte[i] = 0ULL;
1373 }
1374
1375 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1376 unmapped += unmap_size;
1377 }
1378
1379 BUG_ON(unmapped && !is_power_of_2(unmapped));
1380
1381 return unmapped;
1382 }
1383
1384 /****************************************************************************
1385 *
1386 * The next functions belong to the address allocator for the dma_ops
1387 * interface functions. They work like the allocators in the other IOMMU
1388 * drivers. Its basically a bitmap which marks the allocated pages in
1389 * the aperture. Maybe it could be enhanced in the future to a more
1390 * efficient allocator.
1391 *
1392 ****************************************************************************/
1393
1394 /*
1395 * The address allocator core functions.
1396 *
1397 * called with domain->lock held
1398 */
1399
1400 /*
1401 * Used to reserve address ranges in the aperture (e.g. for exclusion
1402 * ranges.
1403 */
1404 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1405 unsigned long start_page,
1406 unsigned int pages)
1407 {
1408 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1409
1410 if (start_page + pages > last_page)
1411 pages = last_page - start_page;
1412
1413 for (i = start_page; i < start_page + pages; ++i) {
1414 int index = i / APERTURE_RANGE_PAGES;
1415 int page = i % APERTURE_RANGE_PAGES;
1416 __set_bit(page, dom->aperture[index]->bitmap);
1417 }
1418 }
1419
1420 /*
1421 * This function is used to add a new aperture range to an existing
1422 * aperture in case of dma_ops domain allocation or address allocation
1423 * failure.
1424 */
1425 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1426 bool populate, gfp_t gfp)
1427 {
1428 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1429 unsigned long i, old_size, pte_pgsize;
1430 struct aperture_range *range;
1431 struct amd_iommu *iommu;
1432 unsigned long flags;
1433
1434 #ifdef CONFIG_IOMMU_STRESS
1435 populate = false;
1436 #endif
1437
1438 if (index >= APERTURE_MAX_RANGES)
1439 return -ENOMEM;
1440
1441 range = kzalloc(sizeof(struct aperture_range), gfp);
1442 if (!range)
1443 return -ENOMEM;
1444
1445 range->bitmap = (void *)get_zeroed_page(gfp);
1446 if (!range->bitmap)
1447 goto out_free;
1448
1449 range->offset = dma_dom->aperture_size;
1450
1451 spin_lock_init(&range->bitmap_lock);
1452
1453 if (populate) {
1454 unsigned long address = dma_dom->aperture_size;
1455 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1456 u64 *pte, *pte_page;
1457
1458 for (i = 0; i < num_ptes; ++i) {
1459 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1460 &pte_page, gfp);
1461 if (!pte)
1462 goto out_free;
1463
1464 range->pte_pages[i] = pte_page;
1465
1466 address += APERTURE_RANGE_SIZE / 64;
1467 }
1468 }
1469
1470 spin_lock_irqsave(&dma_dom->domain.lock, flags);
1471
1472 /* First take the bitmap_lock and then publish the range */
1473 spin_lock(&range->bitmap_lock);
1474
1475 old_size = dma_dom->aperture_size;
1476 dma_dom->aperture[index] = range;
1477 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1478
1479 /* Reserve address range used for MSI messages */
1480 if (old_size < MSI_ADDR_BASE_LO &&
1481 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1482 unsigned long spage;
1483 int pages;
1484
1485 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1486 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1487
1488 dma_ops_reserve_addresses(dma_dom, spage, pages);
1489 }
1490
1491 /* Initialize the exclusion range if necessary */
1492 for_each_iommu(iommu) {
1493 if (iommu->exclusion_start &&
1494 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1495 && iommu->exclusion_start < dma_dom->aperture_size) {
1496 unsigned long startpage;
1497 int pages = iommu_num_pages(iommu->exclusion_start,
1498 iommu->exclusion_length,
1499 PAGE_SIZE);
1500 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1501 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1502 }
1503 }
1504
1505 /*
1506 * Check for areas already mapped as present in the new aperture
1507 * range and mark those pages as reserved in the allocator. Such
1508 * mappings may already exist as a result of requested unity
1509 * mappings for devices.
1510 */
1511 for (i = dma_dom->aperture[index]->offset;
1512 i < dma_dom->aperture_size;
1513 i += pte_pgsize) {
1514 u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize);
1515 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1516 continue;
1517
1518 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT,
1519 pte_pgsize >> 12);
1520 }
1521
1522 update_domain(&dma_dom->domain);
1523
1524 spin_unlock(&range->bitmap_lock);
1525
1526 spin_unlock_irqrestore(&dma_dom->domain.lock, flags);
1527
1528 return 0;
1529
1530 out_free:
1531 update_domain(&dma_dom->domain);
1532
1533 free_page((unsigned long)range->bitmap);
1534
1535 kfree(range);
1536
1537 return -ENOMEM;
1538 }
1539
1540 static dma_addr_t dma_ops_aperture_alloc(struct dma_ops_domain *dom,
1541 struct aperture_range *range,
1542 unsigned long pages,
1543 unsigned long dma_mask,
1544 unsigned long boundary_size,
1545 unsigned long align_mask,
1546 bool trylock)
1547 {
1548 unsigned long offset, limit, flags;
1549 dma_addr_t address;
1550 bool flush = false;
1551
1552 offset = range->offset >> PAGE_SHIFT;
1553 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1554 dma_mask >> PAGE_SHIFT);
1555
1556 if (trylock) {
1557 if (!spin_trylock_irqsave(&range->bitmap_lock, flags))
1558 return -1;
1559 } else {
1560 spin_lock_irqsave(&range->bitmap_lock, flags);
1561 }
1562
1563 address = iommu_area_alloc(range->bitmap, limit, range->next_bit,
1564 pages, offset, boundary_size, align_mask);
1565 if (address == -1) {
1566 /* Nothing found, retry one time */
1567 address = iommu_area_alloc(range->bitmap, limit,
1568 0, pages, offset, boundary_size,
1569 align_mask);
1570 flush = true;
1571 }
1572
1573 if (address != -1)
1574 range->next_bit = address + pages;
1575
1576 spin_unlock_irqrestore(&range->bitmap_lock, flags);
1577
1578 if (flush) {
1579 domain_flush_tlb(&dom->domain);
1580 domain_flush_complete(&dom->domain);
1581 }
1582
1583 return address;
1584 }
1585
1586 static unsigned long dma_ops_area_alloc(struct device *dev,
1587 struct dma_ops_domain *dom,
1588 unsigned int pages,
1589 unsigned long align_mask,
1590 u64 dma_mask)
1591 {
1592 unsigned long boundary_size, mask;
1593 unsigned long address = -1;
1594 bool first = true;
1595 u32 start, i;
1596
1597 preempt_disable();
1598
1599 mask = dma_get_seg_boundary(dev);
1600
1601 again:
1602 start = this_cpu_read(*dom->next_index);
1603
1604 /* Sanity check - is it really necessary? */
1605 if (unlikely(start > APERTURE_MAX_RANGES)) {
1606 start = 0;
1607 this_cpu_write(*dom->next_index, 0);
1608 }
1609
1610 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
1611 1UL << (BITS_PER_LONG - PAGE_SHIFT);
1612
1613 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1614 struct aperture_range *range;
1615 int index;
1616
1617 index = (start + i) % APERTURE_MAX_RANGES;
1618
1619 range = dom->aperture[index];
1620
1621 if (!range || range->offset >= dma_mask)
1622 continue;
1623
1624 address = dma_ops_aperture_alloc(dom, range, pages,
1625 dma_mask, boundary_size,
1626 align_mask, first);
1627 if (address != -1) {
1628 address = range->offset + (address << PAGE_SHIFT);
1629 this_cpu_write(*dom->next_index, index);
1630 break;
1631 }
1632 }
1633
1634 if (address == -1 && first) {
1635 first = false;
1636 goto again;
1637 }
1638
1639 preempt_enable();
1640
1641 return address;
1642 }
1643
1644 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1645 struct dma_ops_domain *dom,
1646 unsigned int pages,
1647 unsigned long align_mask,
1648 u64 dma_mask)
1649 {
1650 unsigned long address = -1;
1651
1652 while (address == -1) {
1653 address = dma_ops_area_alloc(dev, dom, pages,
1654 align_mask, dma_mask);
1655
1656 if (address == -1 && alloc_new_range(dom, false, GFP_ATOMIC))
1657 break;
1658 }
1659
1660 if (unlikely(address == -1))
1661 address = DMA_ERROR_CODE;
1662
1663 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1664
1665 return address;
1666 }
1667
1668 /*
1669 * The address free function.
1670 *
1671 * called with domain->lock held
1672 */
1673 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1674 unsigned long address,
1675 unsigned int pages)
1676 {
1677 unsigned i = address >> APERTURE_RANGE_SHIFT;
1678 struct aperture_range *range = dom->aperture[i];
1679 unsigned long flags;
1680
1681 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1682
1683 #ifdef CONFIG_IOMMU_STRESS
1684 if (i < 4)
1685 return;
1686 #endif
1687
1688 if (amd_iommu_unmap_flush) {
1689 domain_flush_tlb(&dom->domain);
1690 domain_flush_complete(&dom->domain);
1691 }
1692
1693 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1694
1695 spin_lock_irqsave(&range->bitmap_lock, flags);
1696 if (address + pages > range->next_bit)
1697 range->next_bit = address + pages;
1698 bitmap_clear(range->bitmap, address, pages);
1699 spin_unlock_irqrestore(&range->bitmap_lock, flags);
1700
1701 }
1702
1703 /****************************************************************************
1704 *
1705 * The next functions belong to the domain allocation. A domain is
1706 * allocated for every IOMMU as the default domain. If device isolation
1707 * is enabled, every device get its own domain. The most important thing
1708 * about domains is the page table mapping the DMA address space they
1709 * contain.
1710 *
1711 ****************************************************************************/
1712
1713 /*
1714 * This function adds a protection domain to the global protection domain list
1715 */
1716 static void add_domain_to_list(struct protection_domain *domain)
1717 {
1718 unsigned long flags;
1719
1720 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1721 list_add(&domain->list, &amd_iommu_pd_list);
1722 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1723 }
1724
1725 /*
1726 * This function removes a protection domain to the global
1727 * protection domain list
1728 */
1729 static void del_domain_from_list(struct protection_domain *domain)
1730 {
1731 unsigned long flags;
1732
1733 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1734 list_del(&domain->list);
1735 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1736 }
1737
1738 static u16 domain_id_alloc(void)
1739 {
1740 unsigned long flags;
1741 int id;
1742
1743 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1744 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1745 BUG_ON(id == 0);
1746 if (id > 0 && id < MAX_DOMAIN_ID)
1747 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1748 else
1749 id = 0;
1750 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1751
1752 return id;
1753 }
1754
1755 static void domain_id_free(int id)
1756 {
1757 unsigned long flags;
1758
1759 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1760 if (id > 0 && id < MAX_DOMAIN_ID)
1761 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1762 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1763 }
1764
1765 #define DEFINE_FREE_PT_FN(LVL, FN) \
1766 static void free_pt_##LVL (unsigned long __pt) \
1767 { \
1768 unsigned long p; \
1769 u64 *pt; \
1770 int i; \
1771 \
1772 pt = (u64 *)__pt; \
1773 \
1774 for (i = 0; i < 512; ++i) { \
1775 /* PTE present? */ \
1776 if (!IOMMU_PTE_PRESENT(pt[i])) \
1777 continue; \
1778 \
1779 /* Large PTE? */ \
1780 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1781 PM_PTE_LEVEL(pt[i]) == 7) \
1782 continue; \
1783 \
1784 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1785 FN(p); \
1786 } \
1787 free_page((unsigned long)pt); \
1788 }
1789
1790 DEFINE_FREE_PT_FN(l2, free_page)
1791 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1792 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1793 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1794 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1795
1796 static void free_pagetable(struct protection_domain *domain)
1797 {
1798 unsigned long root = (unsigned long)domain->pt_root;
1799
1800 switch (domain->mode) {
1801 case PAGE_MODE_NONE:
1802 break;
1803 case PAGE_MODE_1_LEVEL:
1804 free_page(root);
1805 break;
1806 case PAGE_MODE_2_LEVEL:
1807 free_pt_l2(root);
1808 break;
1809 case PAGE_MODE_3_LEVEL:
1810 free_pt_l3(root);
1811 break;
1812 case PAGE_MODE_4_LEVEL:
1813 free_pt_l4(root);
1814 break;
1815 case PAGE_MODE_5_LEVEL:
1816 free_pt_l5(root);
1817 break;
1818 case PAGE_MODE_6_LEVEL:
1819 free_pt_l6(root);
1820 break;
1821 default:
1822 BUG();
1823 }
1824 }
1825
1826 static void free_gcr3_tbl_level1(u64 *tbl)
1827 {
1828 u64 *ptr;
1829 int i;
1830
1831 for (i = 0; i < 512; ++i) {
1832 if (!(tbl[i] & GCR3_VALID))
1833 continue;
1834
1835 ptr = __va(tbl[i] & PAGE_MASK);
1836
1837 free_page((unsigned long)ptr);
1838 }
1839 }
1840
1841 static void free_gcr3_tbl_level2(u64 *tbl)
1842 {
1843 u64 *ptr;
1844 int i;
1845
1846 for (i = 0; i < 512; ++i) {
1847 if (!(tbl[i] & GCR3_VALID))
1848 continue;
1849
1850 ptr = __va(tbl[i] & PAGE_MASK);
1851
1852 free_gcr3_tbl_level1(ptr);
1853 }
1854 }
1855
1856 static void free_gcr3_table(struct protection_domain *domain)
1857 {
1858 if (domain->glx == 2)
1859 free_gcr3_tbl_level2(domain->gcr3_tbl);
1860 else if (domain->glx == 1)
1861 free_gcr3_tbl_level1(domain->gcr3_tbl);
1862 else
1863 BUG_ON(domain->glx != 0);
1864
1865 free_page((unsigned long)domain->gcr3_tbl);
1866 }
1867
1868 /*
1869 * Free a domain, only used if something went wrong in the
1870 * allocation path and we need to free an already allocated page table
1871 */
1872 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1873 {
1874 int i;
1875
1876 if (!dom)
1877 return;
1878
1879 free_percpu(dom->next_index);
1880
1881 del_domain_from_list(&dom->domain);
1882
1883 free_pagetable(&dom->domain);
1884
1885 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1886 if (!dom->aperture[i])
1887 continue;
1888 free_page((unsigned long)dom->aperture[i]->bitmap);
1889 kfree(dom->aperture[i]);
1890 }
1891
1892 kfree(dom);
1893 }
1894
1895 static int dma_ops_domain_alloc_apertures(struct dma_ops_domain *dma_dom,
1896 int max_apertures)
1897 {
1898 int ret, i, apertures;
1899
1900 apertures = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1901 ret = 0;
1902
1903 for (i = apertures; i < max_apertures; ++i) {
1904 ret = alloc_new_range(dma_dom, false, GFP_KERNEL);
1905 if (ret)
1906 break;
1907 }
1908
1909 return ret;
1910 }
1911
1912 /*
1913 * Allocates a new protection domain usable for the dma_ops functions.
1914 * It also initializes the page table and the address allocator data
1915 * structures required for the dma_ops interface
1916 */
1917 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1918 {
1919 struct dma_ops_domain *dma_dom;
1920 int cpu;
1921
1922 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1923 if (!dma_dom)
1924 return NULL;
1925
1926 if (protection_domain_init(&dma_dom->domain))
1927 goto free_dma_dom;
1928
1929 dma_dom->next_index = alloc_percpu(u32);
1930 if (!dma_dom->next_index)
1931 goto free_dma_dom;
1932
1933 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1934 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1935 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1936 dma_dom->domain.priv = dma_dom;
1937 if (!dma_dom->domain.pt_root)
1938 goto free_dma_dom;
1939
1940 add_domain_to_list(&dma_dom->domain);
1941
1942 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1943 goto free_dma_dom;
1944
1945 /*
1946 * mark the first page as allocated so we never return 0 as
1947 * a valid dma-address. So we can use 0 as error value
1948 */
1949 dma_dom->aperture[0]->bitmap[0] = 1;
1950
1951 for_each_possible_cpu(cpu)
1952 *per_cpu_ptr(dma_dom->next_index, cpu) = 0;
1953
1954 return dma_dom;
1955
1956 free_dma_dom:
1957 dma_ops_domain_free(dma_dom);
1958
1959 return NULL;
1960 }
1961
1962 /*
1963 * little helper function to check whether a given protection domain is a
1964 * dma_ops domain
1965 */
1966 static bool dma_ops_domain(struct protection_domain *domain)
1967 {
1968 return domain->flags & PD_DMA_OPS_MASK;
1969 }
1970
1971 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1972 {
1973 u64 pte_root = 0;
1974 u64 flags = 0;
1975
1976 if (domain->mode != PAGE_MODE_NONE)
1977 pte_root = virt_to_phys(domain->pt_root);
1978
1979 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1980 << DEV_ENTRY_MODE_SHIFT;
1981 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1982
1983 flags = amd_iommu_dev_table[devid].data[1];
1984
1985 if (ats)
1986 flags |= DTE_FLAG_IOTLB;
1987
1988 if (domain->flags & PD_IOMMUV2_MASK) {
1989 u64 gcr3 = __pa(domain->gcr3_tbl);
1990 u64 glx = domain->glx;
1991 u64 tmp;
1992
1993 pte_root |= DTE_FLAG_GV;
1994 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1995
1996 /* First mask out possible old values for GCR3 table */
1997 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1998 flags &= ~tmp;
1999
2000 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2001 flags &= ~tmp;
2002
2003 /* Encode GCR3 table into DTE */
2004 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2005 pte_root |= tmp;
2006
2007 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2008 flags |= tmp;
2009
2010 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2011 flags |= tmp;
2012 }
2013
2014 flags &= ~(0xffffUL);
2015 flags |= domain->id;
2016
2017 amd_iommu_dev_table[devid].data[1] = flags;
2018 amd_iommu_dev_table[devid].data[0] = pte_root;
2019 }
2020
2021 static void clear_dte_entry(u16 devid)
2022 {
2023 /* remove entry from the device table seen by the hardware */
2024 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2025 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
2026
2027 amd_iommu_apply_erratum_63(devid);
2028 }
2029
2030 static void do_attach(struct iommu_dev_data *dev_data,
2031 struct protection_domain *domain)
2032 {
2033 struct amd_iommu *iommu;
2034 u16 alias;
2035 bool ats;
2036
2037 iommu = amd_iommu_rlookup_table[dev_data->devid];
2038 alias = amd_iommu_alias_table[dev_data->devid];
2039 ats = dev_data->ats.enabled;
2040
2041 /* Update data structures */
2042 dev_data->domain = domain;
2043 list_add(&dev_data->list, &domain->dev_list);
2044
2045 /* Do reference counting */
2046 domain->dev_iommu[iommu->index] += 1;
2047 domain->dev_cnt += 1;
2048
2049 /* Update device table */
2050 set_dte_entry(dev_data->devid, domain, ats);
2051 if (alias != dev_data->devid)
2052 set_dte_entry(alias, domain, ats);
2053
2054 device_flush_dte(dev_data);
2055 }
2056
2057 static void do_detach(struct iommu_dev_data *dev_data)
2058 {
2059 struct amd_iommu *iommu;
2060 u16 alias;
2061
2062 /*
2063 * First check if the device is still attached. It might already
2064 * be detached from its domain because the generic
2065 * iommu_detach_group code detached it and we try again here in
2066 * our alias handling.
2067 */
2068 if (!dev_data->domain)
2069 return;
2070
2071 iommu = amd_iommu_rlookup_table[dev_data->devid];
2072 alias = amd_iommu_alias_table[dev_data->devid];
2073
2074 /* decrease reference counters */
2075 dev_data->domain->dev_iommu[iommu->index] -= 1;
2076 dev_data->domain->dev_cnt -= 1;
2077
2078 /* Update data structures */
2079 dev_data->domain = NULL;
2080 list_del(&dev_data->list);
2081 clear_dte_entry(dev_data->devid);
2082 if (alias != dev_data->devid)
2083 clear_dte_entry(alias);
2084
2085 /* Flush the DTE entry */
2086 device_flush_dte(dev_data);
2087 }
2088
2089 /*
2090 * If a device is not yet associated with a domain, this function does
2091 * assigns it visible for the hardware
2092 */
2093 static int __attach_device(struct iommu_dev_data *dev_data,
2094 struct protection_domain *domain)
2095 {
2096 int ret;
2097
2098 /*
2099 * Must be called with IRQs disabled. Warn here to detect early
2100 * when its not.
2101 */
2102 WARN_ON(!irqs_disabled());
2103
2104 /* lock domain */
2105 spin_lock(&domain->lock);
2106
2107 ret = -EBUSY;
2108 if (dev_data->domain != NULL)
2109 goto out_unlock;
2110
2111 /* Attach alias group root */
2112 do_attach(dev_data, domain);
2113
2114 ret = 0;
2115
2116 out_unlock:
2117
2118 /* ready */
2119 spin_unlock(&domain->lock);
2120
2121 return ret;
2122 }
2123
2124
2125 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2126 {
2127 pci_disable_ats(pdev);
2128 pci_disable_pri(pdev);
2129 pci_disable_pasid(pdev);
2130 }
2131
2132 /* FIXME: Change generic reset-function to do the same */
2133 static int pri_reset_while_enabled(struct pci_dev *pdev)
2134 {
2135 u16 control;
2136 int pos;
2137
2138 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2139 if (!pos)
2140 return -EINVAL;
2141
2142 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2143 control |= PCI_PRI_CTRL_RESET;
2144 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2145
2146 return 0;
2147 }
2148
2149 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2150 {
2151 bool reset_enable;
2152 int reqs, ret;
2153
2154 /* FIXME: Hardcode number of outstanding requests for now */
2155 reqs = 32;
2156 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2157 reqs = 1;
2158 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2159
2160 /* Only allow access to user-accessible pages */
2161 ret = pci_enable_pasid(pdev, 0);
2162 if (ret)
2163 goto out_err;
2164
2165 /* First reset the PRI state of the device */
2166 ret = pci_reset_pri(pdev);
2167 if (ret)
2168 goto out_err;
2169
2170 /* Enable PRI */
2171 ret = pci_enable_pri(pdev, reqs);
2172 if (ret)
2173 goto out_err;
2174
2175 if (reset_enable) {
2176 ret = pri_reset_while_enabled(pdev);
2177 if (ret)
2178 goto out_err;
2179 }
2180
2181 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2182 if (ret)
2183 goto out_err;
2184
2185 return 0;
2186
2187 out_err:
2188 pci_disable_pri(pdev);
2189 pci_disable_pasid(pdev);
2190
2191 return ret;
2192 }
2193
2194 /* FIXME: Move this to PCI code */
2195 #define PCI_PRI_TLP_OFF (1 << 15)
2196
2197 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2198 {
2199 u16 status;
2200 int pos;
2201
2202 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2203 if (!pos)
2204 return false;
2205
2206 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2207
2208 return (status & PCI_PRI_TLP_OFF) ? true : false;
2209 }
2210
2211 /*
2212 * If a device is not yet associated with a domain, this function
2213 * assigns it visible for the hardware
2214 */
2215 static int attach_device(struct device *dev,
2216 struct protection_domain *domain)
2217 {
2218 struct pci_dev *pdev = to_pci_dev(dev);
2219 struct iommu_dev_data *dev_data;
2220 unsigned long flags;
2221 int ret;
2222
2223 dev_data = get_dev_data(dev);
2224
2225 if (domain->flags & PD_IOMMUV2_MASK) {
2226 if (!dev_data->passthrough)
2227 return -EINVAL;
2228
2229 if (dev_data->iommu_v2) {
2230 if (pdev_iommuv2_enable(pdev) != 0)
2231 return -EINVAL;
2232
2233 dev_data->ats.enabled = true;
2234 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2235 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2236 }
2237 } else if (amd_iommu_iotlb_sup &&
2238 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2239 dev_data->ats.enabled = true;
2240 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2241 }
2242
2243 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2244 ret = __attach_device(dev_data, domain);
2245 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2246
2247 /*
2248 * We might boot into a crash-kernel here. The crashed kernel
2249 * left the caches in the IOMMU dirty. So we have to flush
2250 * here to evict all dirty stuff.
2251 */
2252 domain_flush_tlb_pde(domain);
2253
2254 return ret;
2255 }
2256
2257 /*
2258 * Removes a device from a protection domain (unlocked)
2259 */
2260 static void __detach_device(struct iommu_dev_data *dev_data)
2261 {
2262 struct protection_domain *domain;
2263
2264 /*
2265 * Must be called with IRQs disabled. Warn here to detect early
2266 * when its not.
2267 */
2268 WARN_ON(!irqs_disabled());
2269
2270 if (WARN_ON(!dev_data->domain))
2271 return;
2272
2273 domain = dev_data->domain;
2274
2275 spin_lock(&domain->lock);
2276
2277 do_detach(dev_data);
2278
2279 spin_unlock(&domain->lock);
2280 }
2281
2282 /*
2283 * Removes a device from a protection domain (with devtable_lock held)
2284 */
2285 static void detach_device(struct device *dev)
2286 {
2287 struct protection_domain *domain;
2288 struct iommu_dev_data *dev_data;
2289 unsigned long flags;
2290
2291 dev_data = get_dev_data(dev);
2292 domain = dev_data->domain;
2293
2294 /* lock device table */
2295 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2296 __detach_device(dev_data);
2297 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2298
2299 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2300 pdev_iommuv2_disable(to_pci_dev(dev));
2301 else if (dev_data->ats.enabled)
2302 pci_disable_ats(to_pci_dev(dev));
2303
2304 dev_data->ats.enabled = false;
2305 }
2306
2307 static int amd_iommu_add_device(struct device *dev)
2308 {
2309 struct iommu_dev_data *dev_data;
2310 struct iommu_domain *domain;
2311 struct amd_iommu *iommu;
2312 u16 devid;
2313 int ret;
2314
2315 if (!check_device(dev) || get_dev_data(dev))
2316 return 0;
2317
2318 devid = get_device_id(dev);
2319 iommu = amd_iommu_rlookup_table[devid];
2320
2321 ret = iommu_init_device(dev);
2322 if (ret) {
2323 if (ret != -ENOTSUPP)
2324 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2325 dev_name(dev));
2326
2327 iommu_ignore_device(dev);
2328 dev->archdata.dma_ops = &nommu_dma_ops;
2329 goto out;
2330 }
2331 init_iommu_group(dev);
2332
2333 dev_data = get_dev_data(dev);
2334
2335 BUG_ON(!dev_data);
2336
2337 if (iommu_pass_through || dev_data->iommu_v2)
2338 iommu_request_dm_for_dev(dev);
2339
2340 /* Domains are initialized for this device - have a look what we ended up with */
2341 domain = iommu_get_domain_for_dev(dev);
2342 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2343 dev_data->passthrough = true;
2344 else
2345 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2346
2347 out:
2348 iommu_completion_wait(iommu);
2349
2350 return 0;
2351 }
2352
2353 static void amd_iommu_remove_device(struct device *dev)
2354 {
2355 struct amd_iommu *iommu;
2356 u16 devid;
2357
2358 if (!check_device(dev))
2359 return;
2360
2361 devid = get_device_id(dev);
2362 iommu = amd_iommu_rlookup_table[devid];
2363
2364 iommu_uninit_device(dev);
2365 iommu_completion_wait(iommu);
2366 }
2367
2368 /*****************************************************************************
2369 *
2370 * The next functions belong to the dma_ops mapping/unmapping code.
2371 *
2372 *****************************************************************************/
2373
2374 /*
2375 * In the dma_ops path we only have the struct device. This function
2376 * finds the corresponding IOMMU, the protection domain and the
2377 * requestor id for a given device.
2378 * If the device is not yet associated with a domain this is also done
2379 * in this function.
2380 */
2381 static struct protection_domain *get_domain(struct device *dev)
2382 {
2383 struct protection_domain *domain;
2384 struct iommu_domain *io_domain;
2385
2386 if (!check_device(dev))
2387 return ERR_PTR(-EINVAL);
2388
2389 io_domain = iommu_get_domain_for_dev(dev);
2390 if (!io_domain)
2391 return NULL;
2392
2393 domain = to_pdomain(io_domain);
2394 if (!dma_ops_domain(domain))
2395 return ERR_PTR(-EBUSY);
2396
2397 return domain;
2398 }
2399
2400 static void update_device_table(struct protection_domain *domain)
2401 {
2402 struct iommu_dev_data *dev_data;
2403
2404 list_for_each_entry(dev_data, &domain->dev_list, list)
2405 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2406 }
2407
2408 static void update_domain(struct protection_domain *domain)
2409 {
2410 if (!domain->updated)
2411 return;
2412
2413 update_device_table(domain);
2414
2415 domain_flush_devices(domain);
2416 domain_flush_tlb_pde(domain);
2417
2418 domain->updated = false;
2419 }
2420
2421 /*
2422 * This function fetches the PTE for a given address in the aperture
2423 */
2424 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2425 unsigned long address)
2426 {
2427 struct aperture_range *aperture;
2428 u64 *pte, *pte_page;
2429
2430 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2431 if (!aperture)
2432 return NULL;
2433
2434 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2435 if (!pte) {
2436 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2437 GFP_ATOMIC);
2438 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2439 } else
2440 pte += PM_LEVEL_INDEX(0, address);
2441
2442 update_domain(&dom->domain);
2443
2444 return pte;
2445 }
2446
2447 /*
2448 * This is the generic map function. It maps one 4kb page at paddr to
2449 * the given address in the DMA address space for the domain.
2450 */
2451 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2452 unsigned long address,
2453 phys_addr_t paddr,
2454 int direction)
2455 {
2456 u64 *pte, __pte;
2457
2458 WARN_ON(address > dom->aperture_size);
2459
2460 paddr &= PAGE_MASK;
2461
2462 pte = dma_ops_get_pte(dom, address);
2463 if (!pte)
2464 return DMA_ERROR_CODE;
2465
2466 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2467
2468 if (direction == DMA_TO_DEVICE)
2469 __pte |= IOMMU_PTE_IR;
2470 else if (direction == DMA_FROM_DEVICE)
2471 __pte |= IOMMU_PTE_IW;
2472 else if (direction == DMA_BIDIRECTIONAL)
2473 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2474
2475 WARN_ON_ONCE(*pte);
2476
2477 *pte = __pte;
2478
2479 return (dma_addr_t)address;
2480 }
2481
2482 /*
2483 * The generic unmapping function for on page in the DMA address space.
2484 */
2485 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2486 unsigned long address)
2487 {
2488 struct aperture_range *aperture;
2489 u64 *pte;
2490
2491 if (address >= dom->aperture_size)
2492 return;
2493
2494 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2495 if (!aperture)
2496 return;
2497
2498 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2499 if (!pte)
2500 return;
2501
2502 pte += PM_LEVEL_INDEX(0, address);
2503
2504 WARN_ON_ONCE(!*pte);
2505
2506 *pte = 0ULL;
2507 }
2508
2509 /*
2510 * This function contains common code for mapping of a physically
2511 * contiguous memory region into DMA address space. It is used by all
2512 * mapping functions provided with this IOMMU driver.
2513 * Must be called with the domain lock held.
2514 */
2515 static dma_addr_t __map_single(struct device *dev,
2516 struct dma_ops_domain *dma_dom,
2517 phys_addr_t paddr,
2518 size_t size,
2519 int dir,
2520 bool align,
2521 u64 dma_mask)
2522 {
2523 dma_addr_t offset = paddr & ~PAGE_MASK;
2524 dma_addr_t address, start, ret;
2525 unsigned int pages;
2526 unsigned long align_mask = 0;
2527 int i;
2528
2529 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2530 paddr &= PAGE_MASK;
2531
2532 INC_STATS_COUNTER(total_map_requests);
2533
2534 if (pages > 1)
2535 INC_STATS_COUNTER(cross_page);
2536
2537 if (align)
2538 align_mask = (1UL << get_order(size)) - 1;
2539
2540 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2541 dma_mask);
2542
2543 if (address == DMA_ERROR_CODE)
2544 goto out;
2545
2546 start = address;
2547 for (i = 0; i < pages; ++i) {
2548 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2549 if (ret == DMA_ERROR_CODE)
2550 goto out_unmap;
2551
2552 paddr += PAGE_SIZE;
2553 start += PAGE_SIZE;
2554 }
2555 address += offset;
2556
2557 ADD_STATS_COUNTER(alloced_io_mem, size);
2558
2559 if (unlikely(amd_iommu_np_cache)) {
2560 domain_flush_pages(&dma_dom->domain, address, size);
2561 domain_flush_complete(&dma_dom->domain);
2562 }
2563
2564 out:
2565 return address;
2566
2567 out_unmap:
2568
2569 for (--i; i >= 0; --i) {
2570 start -= PAGE_SIZE;
2571 dma_ops_domain_unmap(dma_dom, start);
2572 }
2573
2574 dma_ops_free_addresses(dma_dom, address, pages);
2575
2576 return DMA_ERROR_CODE;
2577 }
2578
2579 /*
2580 * Does the reverse of the __map_single function. Must be called with
2581 * the domain lock held too
2582 */
2583 static void __unmap_single(struct dma_ops_domain *dma_dom,
2584 dma_addr_t dma_addr,
2585 size_t size,
2586 int dir)
2587 {
2588 dma_addr_t flush_addr;
2589 dma_addr_t i, start;
2590 unsigned int pages;
2591
2592 if ((dma_addr == DMA_ERROR_CODE) ||
2593 (dma_addr + size > dma_dom->aperture_size))
2594 return;
2595
2596 flush_addr = dma_addr;
2597 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2598 dma_addr &= PAGE_MASK;
2599 start = dma_addr;
2600
2601 for (i = 0; i < pages; ++i) {
2602 dma_ops_domain_unmap(dma_dom, start);
2603 start += PAGE_SIZE;
2604 }
2605
2606 SUB_STATS_COUNTER(alloced_io_mem, size);
2607
2608 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2609 }
2610
2611 /*
2612 * The exported map_single function for dma_ops.
2613 */
2614 static dma_addr_t map_page(struct device *dev, struct page *page,
2615 unsigned long offset, size_t size,
2616 enum dma_data_direction dir,
2617 struct dma_attrs *attrs)
2618 {
2619 phys_addr_t paddr = page_to_phys(page) + offset;
2620 struct protection_domain *domain;
2621 u64 dma_mask;
2622
2623 INC_STATS_COUNTER(cnt_map_single);
2624
2625 domain = get_domain(dev);
2626 if (PTR_ERR(domain) == -EINVAL)
2627 return (dma_addr_t)paddr;
2628 else if (IS_ERR(domain))
2629 return DMA_ERROR_CODE;
2630
2631 dma_mask = *dev->dma_mask;
2632
2633 return __map_single(dev, domain->priv, paddr, size, dir, false,
2634 dma_mask);
2635 }
2636
2637 /*
2638 * The exported unmap_single function for dma_ops.
2639 */
2640 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2641 enum dma_data_direction dir, struct dma_attrs *attrs)
2642 {
2643 struct protection_domain *domain;
2644
2645 INC_STATS_COUNTER(cnt_unmap_single);
2646
2647 domain = get_domain(dev);
2648 if (IS_ERR(domain))
2649 return;
2650
2651 __unmap_single(domain->priv, dma_addr, size, dir);
2652 }
2653
2654 /*
2655 * The exported map_sg function for dma_ops (handles scatter-gather
2656 * lists).
2657 */
2658 static int map_sg(struct device *dev, struct scatterlist *sglist,
2659 int nelems, enum dma_data_direction dir,
2660 struct dma_attrs *attrs)
2661 {
2662 struct protection_domain *domain;
2663 int i;
2664 struct scatterlist *s;
2665 phys_addr_t paddr;
2666 int mapped_elems = 0;
2667 u64 dma_mask;
2668
2669 INC_STATS_COUNTER(cnt_map_sg);
2670
2671 domain = get_domain(dev);
2672 if (IS_ERR(domain))
2673 return 0;
2674
2675 dma_mask = *dev->dma_mask;
2676
2677 for_each_sg(sglist, s, nelems, i) {
2678 paddr = sg_phys(s);
2679
2680 s->dma_address = __map_single(dev, domain->priv,
2681 paddr, s->length, dir, false,
2682 dma_mask);
2683
2684 if (s->dma_address) {
2685 s->dma_length = s->length;
2686 mapped_elems++;
2687 } else
2688 goto unmap;
2689 }
2690
2691 return mapped_elems;
2692
2693 unmap:
2694 for_each_sg(sglist, s, mapped_elems, i) {
2695 if (s->dma_address)
2696 __unmap_single(domain->priv, s->dma_address,
2697 s->dma_length, dir);
2698 s->dma_address = s->dma_length = 0;
2699 }
2700
2701 return 0;
2702 }
2703
2704 /*
2705 * The exported map_sg function for dma_ops (handles scatter-gather
2706 * lists).
2707 */
2708 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2709 int nelems, enum dma_data_direction dir,
2710 struct dma_attrs *attrs)
2711 {
2712 struct protection_domain *domain;
2713 struct scatterlist *s;
2714 int i;
2715
2716 INC_STATS_COUNTER(cnt_unmap_sg);
2717
2718 domain = get_domain(dev);
2719 if (IS_ERR(domain))
2720 return;
2721
2722 for_each_sg(sglist, s, nelems, i) {
2723 __unmap_single(domain->priv, s->dma_address,
2724 s->dma_length, dir);
2725 s->dma_address = s->dma_length = 0;
2726 }
2727 }
2728
2729 /*
2730 * The exported alloc_coherent function for dma_ops.
2731 */
2732 static void *alloc_coherent(struct device *dev, size_t size,
2733 dma_addr_t *dma_addr, gfp_t flag,
2734 struct dma_attrs *attrs)
2735 {
2736 u64 dma_mask = dev->coherent_dma_mask;
2737 struct protection_domain *domain;
2738 struct page *page;
2739
2740 INC_STATS_COUNTER(cnt_alloc_coherent);
2741
2742 domain = get_domain(dev);
2743 if (PTR_ERR(domain) == -EINVAL) {
2744 page = alloc_pages(flag, get_order(size));
2745 *dma_addr = page_to_phys(page);
2746 return page_address(page);
2747 } else if (IS_ERR(domain))
2748 return NULL;
2749
2750 size = PAGE_ALIGN(size);
2751 dma_mask = dev->coherent_dma_mask;
2752 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2753 flag |= __GFP_ZERO;
2754
2755 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2756 if (!page) {
2757 if (!gfpflags_allow_blocking(flag))
2758 return NULL;
2759
2760 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2761 get_order(size));
2762 if (!page)
2763 return NULL;
2764 }
2765
2766 if (!dma_mask)
2767 dma_mask = *dev->dma_mask;
2768
2769 *dma_addr = __map_single(dev, domain->priv, page_to_phys(page),
2770 size, DMA_BIDIRECTIONAL, true, dma_mask);
2771
2772 if (*dma_addr == DMA_ERROR_CODE)
2773 goto out_free;
2774
2775 return page_address(page);
2776
2777 out_free:
2778
2779 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2780 __free_pages(page, get_order(size));
2781
2782 return NULL;
2783 }
2784
2785 /*
2786 * The exported free_coherent function for dma_ops.
2787 */
2788 static void free_coherent(struct device *dev, size_t size,
2789 void *virt_addr, dma_addr_t dma_addr,
2790 struct dma_attrs *attrs)
2791 {
2792 struct protection_domain *domain;
2793 struct page *page;
2794
2795 INC_STATS_COUNTER(cnt_free_coherent);
2796
2797 page = virt_to_page(virt_addr);
2798 size = PAGE_ALIGN(size);
2799
2800 domain = get_domain(dev);
2801 if (IS_ERR(domain))
2802 goto free_mem;
2803
2804 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2805
2806 free_mem:
2807 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2808 __free_pages(page, get_order(size));
2809 }
2810
2811 /*
2812 * This function is called by the DMA layer to find out if we can handle a
2813 * particular device. It is part of the dma_ops.
2814 */
2815 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2816 {
2817 return check_device(dev);
2818 }
2819
2820 static int set_dma_mask(struct device *dev, u64 mask)
2821 {
2822 struct protection_domain *domain;
2823 int max_apertures = 1;
2824
2825 domain = get_domain(dev);
2826 if (IS_ERR(domain))
2827 return PTR_ERR(domain);
2828
2829 if (mask == DMA_BIT_MASK(64))
2830 max_apertures = 8;
2831 else if (mask > DMA_BIT_MASK(32))
2832 max_apertures = 4;
2833
2834 /*
2835 * To prevent lock contention it doesn't make sense to allocate more
2836 * apertures than online cpus
2837 */
2838 if (max_apertures > num_online_cpus())
2839 max_apertures = num_online_cpus();
2840
2841 if (dma_ops_domain_alloc_apertures(domain->priv, max_apertures))
2842 dev_err(dev, "Can't allocate %d iommu apertures\n",
2843 max_apertures);
2844
2845 return 0;
2846 }
2847
2848 static struct dma_map_ops amd_iommu_dma_ops = {
2849 .alloc = alloc_coherent,
2850 .free = free_coherent,
2851 .map_page = map_page,
2852 .unmap_page = unmap_page,
2853 .map_sg = map_sg,
2854 .unmap_sg = unmap_sg,
2855 .dma_supported = amd_iommu_dma_supported,
2856 .set_dma_mask = set_dma_mask,
2857 };
2858
2859 int __init amd_iommu_init_api(void)
2860 {
2861 return bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2862 }
2863
2864 int __init amd_iommu_init_dma_ops(void)
2865 {
2866 swiotlb = iommu_pass_through ? 1 : 0;
2867 iommu_detected = 1;
2868
2869 /*
2870 * In case we don't initialize SWIOTLB (actually the common case
2871 * when AMD IOMMU is enabled), make sure there are global
2872 * dma_ops set as a fall-back for devices not handled by this
2873 * driver (for example non-PCI devices).
2874 */
2875 if (!swiotlb)
2876 dma_ops = &nommu_dma_ops;
2877
2878 amd_iommu_stats_init();
2879
2880 if (amd_iommu_unmap_flush)
2881 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2882 else
2883 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2884
2885 return 0;
2886 }
2887
2888 /*****************************************************************************
2889 *
2890 * The following functions belong to the exported interface of AMD IOMMU
2891 *
2892 * This interface allows access to lower level functions of the IOMMU
2893 * like protection domain handling and assignement of devices to domains
2894 * which is not possible with the dma_ops interface.
2895 *
2896 *****************************************************************************/
2897
2898 static void cleanup_domain(struct protection_domain *domain)
2899 {
2900 struct iommu_dev_data *entry;
2901 unsigned long flags;
2902
2903 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2904
2905 while (!list_empty(&domain->dev_list)) {
2906 entry = list_first_entry(&domain->dev_list,
2907 struct iommu_dev_data, list);
2908 __detach_device(entry);
2909 }
2910
2911 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2912 }
2913
2914 static void protection_domain_free(struct protection_domain *domain)
2915 {
2916 if (!domain)
2917 return;
2918
2919 del_domain_from_list(domain);
2920
2921 if (domain->id)
2922 domain_id_free(domain->id);
2923
2924 kfree(domain);
2925 }
2926
2927 static int protection_domain_init(struct protection_domain *domain)
2928 {
2929 spin_lock_init(&domain->lock);
2930 mutex_init(&domain->api_lock);
2931 domain->id = domain_id_alloc();
2932 if (!domain->id)
2933 return -ENOMEM;
2934 INIT_LIST_HEAD(&domain->dev_list);
2935
2936 return 0;
2937 }
2938
2939 static struct protection_domain *protection_domain_alloc(void)
2940 {
2941 struct protection_domain *domain;
2942
2943 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2944 if (!domain)
2945 return NULL;
2946
2947 if (protection_domain_init(domain))
2948 goto out_err;
2949
2950 add_domain_to_list(domain);
2951
2952 return domain;
2953
2954 out_err:
2955 kfree(domain);
2956
2957 return NULL;
2958 }
2959
2960 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2961 {
2962 struct protection_domain *pdomain;
2963 struct dma_ops_domain *dma_domain;
2964
2965 switch (type) {
2966 case IOMMU_DOMAIN_UNMANAGED:
2967 pdomain = protection_domain_alloc();
2968 if (!pdomain)
2969 return NULL;
2970
2971 pdomain->mode = PAGE_MODE_3_LEVEL;
2972 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2973 if (!pdomain->pt_root) {
2974 protection_domain_free(pdomain);
2975 return NULL;
2976 }
2977
2978 pdomain->domain.geometry.aperture_start = 0;
2979 pdomain->domain.geometry.aperture_end = ~0ULL;
2980 pdomain->domain.geometry.force_aperture = true;
2981
2982 break;
2983 case IOMMU_DOMAIN_DMA:
2984 dma_domain = dma_ops_domain_alloc();
2985 if (!dma_domain) {
2986 pr_err("AMD-Vi: Failed to allocate\n");
2987 return NULL;
2988 }
2989 pdomain = &dma_domain->domain;
2990 break;
2991 case IOMMU_DOMAIN_IDENTITY:
2992 pdomain = protection_domain_alloc();
2993 if (!pdomain)
2994 return NULL;
2995
2996 pdomain->mode = PAGE_MODE_NONE;
2997 break;
2998 default:
2999 return NULL;
3000 }
3001
3002 return &pdomain->domain;
3003 }
3004
3005 static void amd_iommu_domain_free(struct iommu_domain *dom)
3006 {
3007 struct protection_domain *domain;
3008
3009 if (!dom)
3010 return;
3011
3012 domain = to_pdomain(dom);
3013
3014 if (domain->dev_cnt > 0)
3015 cleanup_domain(domain);
3016
3017 BUG_ON(domain->dev_cnt != 0);
3018
3019 if (domain->mode != PAGE_MODE_NONE)
3020 free_pagetable(domain);
3021
3022 if (domain->flags & PD_IOMMUV2_MASK)
3023 free_gcr3_table(domain);
3024
3025 protection_domain_free(domain);
3026 }
3027
3028 static void amd_iommu_detach_device(struct iommu_domain *dom,
3029 struct device *dev)
3030 {
3031 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3032 struct amd_iommu *iommu;
3033 u16 devid;
3034
3035 if (!check_device(dev))
3036 return;
3037
3038 devid = get_device_id(dev);
3039
3040 if (dev_data->domain != NULL)
3041 detach_device(dev);
3042
3043 iommu = amd_iommu_rlookup_table[devid];
3044 if (!iommu)
3045 return;
3046
3047 iommu_completion_wait(iommu);
3048 }
3049
3050 static int amd_iommu_attach_device(struct iommu_domain *dom,
3051 struct device *dev)
3052 {
3053 struct protection_domain *domain = to_pdomain(dom);
3054 struct iommu_dev_data *dev_data;
3055 struct amd_iommu *iommu;
3056 int ret;
3057
3058 if (!check_device(dev))
3059 return -EINVAL;
3060
3061 dev_data = dev->archdata.iommu;
3062
3063 iommu = amd_iommu_rlookup_table[dev_data->devid];
3064 if (!iommu)
3065 return -EINVAL;
3066
3067 if (dev_data->domain)
3068 detach_device(dev);
3069
3070 ret = attach_device(dev, domain);
3071
3072 iommu_completion_wait(iommu);
3073
3074 return ret;
3075 }
3076
3077 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3078 phys_addr_t paddr, size_t page_size, int iommu_prot)
3079 {
3080 struct protection_domain *domain = to_pdomain(dom);
3081 int prot = 0;
3082 int ret;
3083
3084 if (domain->mode == PAGE_MODE_NONE)
3085 return -EINVAL;
3086
3087 if (iommu_prot & IOMMU_READ)
3088 prot |= IOMMU_PROT_IR;
3089 if (iommu_prot & IOMMU_WRITE)
3090 prot |= IOMMU_PROT_IW;
3091
3092 mutex_lock(&domain->api_lock);
3093 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3094 mutex_unlock(&domain->api_lock);
3095
3096 return ret;
3097 }
3098
3099 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3100 size_t page_size)
3101 {
3102 struct protection_domain *domain = to_pdomain(dom);
3103 size_t unmap_size;
3104
3105 if (domain->mode == PAGE_MODE_NONE)
3106 return -EINVAL;
3107
3108 mutex_lock(&domain->api_lock);
3109 unmap_size = iommu_unmap_page(domain, iova, page_size);
3110 mutex_unlock(&domain->api_lock);
3111
3112 domain_flush_tlb_pde(domain);
3113
3114 return unmap_size;
3115 }
3116
3117 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3118 dma_addr_t iova)
3119 {
3120 struct protection_domain *domain = to_pdomain(dom);
3121 unsigned long offset_mask, pte_pgsize;
3122 u64 *pte, __pte;
3123
3124 if (domain->mode == PAGE_MODE_NONE)
3125 return iova;
3126
3127 pte = fetch_pte(domain, iova, &pte_pgsize);
3128
3129 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3130 return 0;
3131
3132 offset_mask = pte_pgsize - 1;
3133 __pte = *pte & PM_ADDR_MASK;
3134
3135 return (__pte & ~offset_mask) | (iova & offset_mask);
3136 }
3137
3138 static bool amd_iommu_capable(enum iommu_cap cap)
3139 {
3140 switch (cap) {
3141 case IOMMU_CAP_CACHE_COHERENCY:
3142 return true;
3143 case IOMMU_CAP_INTR_REMAP:
3144 return (irq_remapping_enabled == 1);
3145 case IOMMU_CAP_NOEXEC:
3146 return false;
3147 }
3148
3149 return false;
3150 }
3151
3152 static void amd_iommu_get_dm_regions(struct device *dev,
3153 struct list_head *head)
3154 {
3155 struct unity_map_entry *entry;
3156 u16 devid;
3157
3158 devid = get_device_id(dev);
3159
3160 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3161 struct iommu_dm_region *region;
3162
3163 if (devid < entry->devid_start || devid > entry->devid_end)
3164 continue;
3165
3166 region = kzalloc(sizeof(*region), GFP_KERNEL);
3167 if (!region) {
3168 pr_err("Out of memory allocating dm-regions for %s\n",
3169 dev_name(dev));
3170 return;
3171 }
3172
3173 region->start = entry->address_start;
3174 region->length = entry->address_end - entry->address_start;
3175 if (entry->prot & IOMMU_PROT_IR)
3176 region->prot |= IOMMU_READ;
3177 if (entry->prot & IOMMU_PROT_IW)
3178 region->prot |= IOMMU_WRITE;
3179
3180 list_add_tail(&region->list, head);
3181 }
3182 }
3183
3184 static void amd_iommu_put_dm_regions(struct device *dev,
3185 struct list_head *head)
3186 {
3187 struct iommu_dm_region *entry, *next;
3188
3189 list_for_each_entry_safe(entry, next, head, list)
3190 kfree(entry);
3191 }
3192
3193 static const struct iommu_ops amd_iommu_ops = {
3194 .capable = amd_iommu_capable,
3195 .domain_alloc = amd_iommu_domain_alloc,
3196 .domain_free = amd_iommu_domain_free,
3197 .attach_dev = amd_iommu_attach_device,
3198 .detach_dev = amd_iommu_detach_device,
3199 .map = amd_iommu_map,
3200 .unmap = amd_iommu_unmap,
3201 .map_sg = default_iommu_map_sg,
3202 .iova_to_phys = amd_iommu_iova_to_phys,
3203 .add_device = amd_iommu_add_device,
3204 .remove_device = amd_iommu_remove_device,
3205 .device_group = pci_device_group,
3206 .get_dm_regions = amd_iommu_get_dm_regions,
3207 .put_dm_regions = amd_iommu_put_dm_regions,
3208 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3209 };
3210
3211 /*****************************************************************************
3212 *
3213 * The next functions do a basic initialization of IOMMU for pass through
3214 * mode
3215 *
3216 * In passthrough mode the IOMMU is initialized and enabled but not used for
3217 * DMA-API translation.
3218 *
3219 *****************************************************************************/
3220
3221 /* IOMMUv2 specific functions */
3222 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3223 {
3224 return atomic_notifier_chain_register(&ppr_notifier, nb);
3225 }
3226 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3227
3228 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3229 {
3230 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3231 }
3232 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3233
3234 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3235 {
3236 struct protection_domain *domain = to_pdomain(dom);
3237 unsigned long flags;
3238
3239 spin_lock_irqsave(&domain->lock, flags);
3240
3241 /* Update data structure */
3242 domain->mode = PAGE_MODE_NONE;
3243 domain->updated = true;
3244
3245 /* Make changes visible to IOMMUs */
3246 update_domain(domain);
3247
3248 /* Page-table is not visible to IOMMU anymore, so free it */
3249 free_pagetable(domain);
3250
3251 spin_unlock_irqrestore(&domain->lock, flags);
3252 }
3253 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3254
3255 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3256 {
3257 struct protection_domain *domain = to_pdomain(dom);
3258 unsigned long flags;
3259 int levels, ret;
3260
3261 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3262 return -EINVAL;
3263
3264 /* Number of GCR3 table levels required */
3265 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3266 levels += 1;
3267
3268 if (levels > amd_iommu_max_glx_val)
3269 return -EINVAL;
3270
3271 spin_lock_irqsave(&domain->lock, flags);
3272
3273 /*
3274 * Save us all sanity checks whether devices already in the
3275 * domain support IOMMUv2. Just force that the domain has no
3276 * devices attached when it is switched into IOMMUv2 mode.
3277 */
3278 ret = -EBUSY;
3279 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3280 goto out;
3281
3282 ret = -ENOMEM;
3283 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3284 if (domain->gcr3_tbl == NULL)
3285 goto out;
3286
3287 domain->glx = levels;
3288 domain->flags |= PD_IOMMUV2_MASK;
3289 domain->updated = true;
3290
3291 update_domain(domain);
3292
3293 ret = 0;
3294
3295 out:
3296 spin_unlock_irqrestore(&domain->lock, flags);
3297
3298 return ret;
3299 }
3300 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3301
3302 static int __flush_pasid(struct protection_domain *domain, int pasid,
3303 u64 address, bool size)
3304 {
3305 struct iommu_dev_data *dev_data;
3306 struct iommu_cmd cmd;
3307 int i, ret;
3308
3309 if (!(domain->flags & PD_IOMMUV2_MASK))
3310 return -EINVAL;
3311
3312 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3313
3314 /*
3315 * IOMMU TLB needs to be flushed before Device TLB to
3316 * prevent device TLB refill from IOMMU TLB
3317 */
3318 for (i = 0; i < amd_iommus_present; ++i) {
3319 if (domain->dev_iommu[i] == 0)
3320 continue;
3321
3322 ret = iommu_queue_command(amd_iommus[i], &cmd);
3323 if (ret != 0)
3324 goto out;
3325 }
3326
3327 /* Wait until IOMMU TLB flushes are complete */
3328 domain_flush_complete(domain);
3329
3330 /* Now flush device TLBs */
3331 list_for_each_entry(dev_data, &domain->dev_list, list) {
3332 struct amd_iommu *iommu;
3333 int qdep;
3334
3335 /*
3336 There might be non-IOMMUv2 capable devices in an IOMMUv2
3337 * domain.
3338 */
3339 if (!dev_data->ats.enabled)
3340 continue;
3341
3342 qdep = dev_data->ats.qdep;
3343 iommu = amd_iommu_rlookup_table[dev_data->devid];
3344
3345 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3346 qdep, address, size);
3347
3348 ret = iommu_queue_command(iommu, &cmd);
3349 if (ret != 0)
3350 goto out;
3351 }
3352
3353 /* Wait until all device TLBs are flushed */
3354 domain_flush_complete(domain);
3355
3356 ret = 0;
3357
3358 out:
3359
3360 return ret;
3361 }
3362
3363 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3364 u64 address)
3365 {
3366 INC_STATS_COUNTER(invalidate_iotlb);
3367
3368 return __flush_pasid(domain, pasid, address, false);
3369 }
3370
3371 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3372 u64 address)
3373 {
3374 struct protection_domain *domain = to_pdomain(dom);
3375 unsigned long flags;
3376 int ret;
3377
3378 spin_lock_irqsave(&domain->lock, flags);
3379 ret = __amd_iommu_flush_page(domain, pasid, address);
3380 spin_unlock_irqrestore(&domain->lock, flags);
3381
3382 return ret;
3383 }
3384 EXPORT_SYMBOL(amd_iommu_flush_page);
3385
3386 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3387 {
3388 INC_STATS_COUNTER(invalidate_iotlb_all);
3389
3390 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3391 true);
3392 }
3393
3394 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3395 {
3396 struct protection_domain *domain = to_pdomain(dom);
3397 unsigned long flags;
3398 int ret;
3399
3400 spin_lock_irqsave(&domain->lock, flags);
3401 ret = __amd_iommu_flush_tlb(domain, pasid);
3402 spin_unlock_irqrestore(&domain->lock, flags);
3403
3404 return ret;
3405 }
3406 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3407
3408 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3409 {
3410 int index;
3411 u64 *pte;
3412
3413 while (true) {
3414
3415 index = (pasid >> (9 * level)) & 0x1ff;
3416 pte = &root[index];
3417
3418 if (level == 0)
3419 break;
3420
3421 if (!(*pte & GCR3_VALID)) {
3422 if (!alloc)
3423 return NULL;
3424
3425 root = (void *)get_zeroed_page(GFP_ATOMIC);
3426 if (root == NULL)
3427 return NULL;
3428
3429 *pte = __pa(root) | GCR3_VALID;
3430 }
3431
3432 root = __va(*pte & PAGE_MASK);
3433
3434 level -= 1;
3435 }
3436
3437 return pte;
3438 }
3439
3440 static int __set_gcr3(struct protection_domain *domain, int pasid,
3441 unsigned long cr3)
3442 {
3443 u64 *pte;
3444
3445 if (domain->mode != PAGE_MODE_NONE)
3446 return -EINVAL;
3447
3448 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3449 if (pte == NULL)
3450 return -ENOMEM;
3451
3452 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3453
3454 return __amd_iommu_flush_tlb(domain, pasid);
3455 }
3456
3457 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3458 {
3459 u64 *pte;
3460
3461 if (domain->mode != PAGE_MODE_NONE)
3462 return -EINVAL;
3463
3464 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3465 if (pte == NULL)
3466 return 0;
3467
3468 *pte = 0;
3469
3470 return __amd_iommu_flush_tlb(domain, pasid);
3471 }
3472
3473 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3474 unsigned long cr3)
3475 {
3476 struct protection_domain *domain = to_pdomain(dom);
3477 unsigned long flags;
3478 int ret;
3479
3480 spin_lock_irqsave(&domain->lock, flags);
3481 ret = __set_gcr3(domain, pasid, cr3);
3482 spin_unlock_irqrestore(&domain->lock, flags);
3483
3484 return ret;
3485 }
3486 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3487
3488 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3489 {
3490 struct protection_domain *domain = to_pdomain(dom);
3491 unsigned long flags;
3492 int ret;
3493
3494 spin_lock_irqsave(&domain->lock, flags);
3495 ret = __clear_gcr3(domain, pasid);
3496 spin_unlock_irqrestore(&domain->lock, flags);
3497
3498 return ret;
3499 }
3500 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3501
3502 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3503 int status, int tag)
3504 {
3505 struct iommu_dev_data *dev_data;
3506 struct amd_iommu *iommu;
3507 struct iommu_cmd cmd;
3508
3509 INC_STATS_COUNTER(complete_ppr);
3510
3511 dev_data = get_dev_data(&pdev->dev);
3512 iommu = amd_iommu_rlookup_table[dev_data->devid];
3513
3514 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3515 tag, dev_data->pri_tlp);
3516
3517 return iommu_queue_command(iommu, &cmd);
3518 }
3519 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3520
3521 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3522 {
3523 struct protection_domain *pdomain;
3524
3525 pdomain = get_domain(&pdev->dev);
3526 if (IS_ERR(pdomain))
3527 return NULL;
3528
3529 /* Only return IOMMUv2 domains */
3530 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3531 return NULL;
3532
3533 return &pdomain->domain;
3534 }
3535 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3536
3537 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3538 {
3539 struct iommu_dev_data *dev_data;
3540
3541 if (!amd_iommu_v2_supported())
3542 return;
3543
3544 dev_data = get_dev_data(&pdev->dev);
3545 dev_data->errata |= (1 << erratum);
3546 }
3547 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3548
3549 int amd_iommu_device_info(struct pci_dev *pdev,
3550 struct amd_iommu_device_info *info)
3551 {
3552 int max_pasids;
3553 int pos;
3554
3555 if (pdev == NULL || info == NULL)
3556 return -EINVAL;
3557
3558 if (!amd_iommu_v2_supported())
3559 return -EINVAL;
3560
3561 memset(info, 0, sizeof(*info));
3562
3563 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3564 if (pos)
3565 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3566
3567 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3568 if (pos)
3569 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3570
3571 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3572 if (pos) {
3573 int features;
3574
3575 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3576 max_pasids = min(max_pasids, (1 << 20));
3577
3578 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3579 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3580
3581 features = pci_pasid_features(pdev);
3582 if (features & PCI_PASID_CAP_EXEC)
3583 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3584 if (features & PCI_PASID_CAP_PRIV)
3585 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3586 }
3587
3588 return 0;
3589 }
3590 EXPORT_SYMBOL(amd_iommu_device_info);
3591
3592 #ifdef CONFIG_IRQ_REMAP
3593
3594 /*****************************************************************************
3595 *
3596 * Interrupt Remapping Implementation
3597 *
3598 *****************************************************************************/
3599
3600 union irte {
3601 u32 val;
3602 struct {
3603 u32 valid : 1,
3604 no_fault : 1,
3605 int_type : 3,
3606 rq_eoi : 1,
3607 dm : 1,
3608 rsvd_1 : 1,
3609 destination : 8,
3610 vector : 8,
3611 rsvd_2 : 8;
3612 } fields;
3613 };
3614
3615 struct irq_2_irte {
3616 u16 devid; /* Device ID for IRTE table */
3617 u16 index; /* Index into IRTE table*/
3618 };
3619
3620 struct amd_ir_data {
3621 struct irq_2_irte irq_2_irte;
3622 union irte irte_entry;
3623 union {
3624 struct msi_msg msi_entry;
3625 };
3626 };
3627
3628 static struct irq_chip amd_ir_chip;
3629
3630 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3631 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3632 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3633 #define DTE_IRQ_REMAP_ENABLE 1ULL
3634
3635 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3636 {
3637 u64 dte;
3638
3639 dte = amd_iommu_dev_table[devid].data[2];
3640 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3641 dte |= virt_to_phys(table->table);
3642 dte |= DTE_IRQ_REMAP_INTCTL;
3643 dte |= DTE_IRQ_TABLE_LEN;
3644 dte |= DTE_IRQ_REMAP_ENABLE;
3645
3646 amd_iommu_dev_table[devid].data[2] = dte;
3647 }
3648
3649 #define IRTE_ALLOCATED (~1U)
3650
3651 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3652 {
3653 struct irq_remap_table *table = NULL;
3654 struct amd_iommu *iommu;
3655 unsigned long flags;
3656 u16 alias;
3657
3658 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3659
3660 iommu = amd_iommu_rlookup_table[devid];
3661 if (!iommu)
3662 goto out_unlock;
3663
3664 table = irq_lookup_table[devid];
3665 if (table)
3666 goto out;
3667
3668 alias = amd_iommu_alias_table[devid];
3669 table = irq_lookup_table[alias];
3670 if (table) {
3671 irq_lookup_table[devid] = table;
3672 set_dte_irq_entry(devid, table);
3673 iommu_flush_dte(iommu, devid);
3674 goto out;
3675 }
3676
3677 /* Nothing there yet, allocate new irq remapping table */
3678 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3679 if (!table)
3680 goto out;
3681
3682 /* Initialize table spin-lock */
3683 spin_lock_init(&table->lock);
3684
3685 if (ioapic)
3686 /* Keep the first 32 indexes free for IOAPIC interrupts */
3687 table->min_index = 32;
3688
3689 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3690 if (!table->table) {
3691 kfree(table);
3692 table = NULL;
3693 goto out;
3694 }
3695
3696 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3697
3698 if (ioapic) {
3699 int i;
3700
3701 for (i = 0; i < 32; ++i)
3702 table->table[i] = IRTE_ALLOCATED;
3703 }
3704
3705 irq_lookup_table[devid] = table;
3706 set_dte_irq_entry(devid, table);
3707 iommu_flush_dte(iommu, devid);
3708 if (devid != alias) {
3709 irq_lookup_table[alias] = table;
3710 set_dte_irq_entry(alias, table);
3711 iommu_flush_dte(iommu, alias);
3712 }
3713
3714 out:
3715 iommu_completion_wait(iommu);
3716
3717 out_unlock:
3718 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3719
3720 return table;
3721 }
3722
3723 static int alloc_irq_index(u16 devid, int count)
3724 {
3725 struct irq_remap_table *table;
3726 unsigned long flags;
3727 int index, c;
3728
3729 table = get_irq_table(devid, false);
3730 if (!table)
3731 return -ENODEV;
3732
3733 spin_lock_irqsave(&table->lock, flags);
3734
3735 /* Scan table for free entries */
3736 for (c = 0, index = table->min_index;
3737 index < MAX_IRQS_PER_TABLE;
3738 ++index) {
3739 if (table->table[index] == 0)
3740 c += 1;
3741 else
3742 c = 0;
3743
3744 if (c == count) {
3745 for (; c != 0; --c)
3746 table->table[index - c + 1] = IRTE_ALLOCATED;
3747
3748 index -= count - 1;
3749 goto out;
3750 }
3751 }
3752
3753 index = -ENOSPC;
3754
3755 out:
3756 spin_unlock_irqrestore(&table->lock, flags);
3757
3758 return index;
3759 }
3760
3761 static int modify_irte(u16 devid, int index, union irte irte)
3762 {
3763 struct irq_remap_table *table;
3764 struct amd_iommu *iommu;
3765 unsigned long flags;
3766
3767 iommu = amd_iommu_rlookup_table[devid];
3768 if (iommu == NULL)
3769 return -EINVAL;
3770
3771 table = get_irq_table(devid, false);
3772 if (!table)
3773 return -ENOMEM;
3774
3775 spin_lock_irqsave(&table->lock, flags);
3776 table->table[index] = irte.val;
3777 spin_unlock_irqrestore(&table->lock, flags);
3778
3779 iommu_flush_irt(iommu, devid);
3780 iommu_completion_wait(iommu);
3781
3782 return 0;
3783 }
3784
3785 static void free_irte(u16 devid, int index)
3786 {
3787 struct irq_remap_table *table;
3788 struct amd_iommu *iommu;
3789 unsigned long flags;
3790
3791 iommu = amd_iommu_rlookup_table[devid];
3792 if (iommu == NULL)
3793 return;
3794
3795 table = get_irq_table(devid, false);
3796 if (!table)
3797 return;
3798
3799 spin_lock_irqsave(&table->lock, flags);
3800 table->table[index] = 0;
3801 spin_unlock_irqrestore(&table->lock, flags);
3802
3803 iommu_flush_irt(iommu, devid);
3804 iommu_completion_wait(iommu);
3805 }
3806
3807 static int get_devid(struct irq_alloc_info *info)
3808 {
3809 int devid = -1;
3810
3811 switch (info->type) {
3812 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3813 devid = get_ioapic_devid(info->ioapic_id);
3814 break;
3815 case X86_IRQ_ALLOC_TYPE_HPET:
3816 devid = get_hpet_devid(info->hpet_id);
3817 break;
3818 case X86_IRQ_ALLOC_TYPE_MSI:
3819 case X86_IRQ_ALLOC_TYPE_MSIX:
3820 devid = get_device_id(&info->msi_dev->dev);
3821 break;
3822 default:
3823 BUG_ON(1);
3824 break;
3825 }
3826
3827 return devid;
3828 }
3829
3830 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3831 {
3832 struct amd_iommu *iommu;
3833 int devid;
3834
3835 if (!info)
3836 return NULL;
3837
3838 devid = get_devid(info);
3839 if (devid >= 0) {
3840 iommu = amd_iommu_rlookup_table[devid];
3841 if (iommu)
3842 return iommu->ir_domain;
3843 }
3844
3845 return NULL;
3846 }
3847
3848 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3849 {
3850 struct amd_iommu *iommu;
3851 int devid;
3852
3853 if (!info)
3854 return NULL;
3855
3856 switch (info->type) {
3857 case X86_IRQ_ALLOC_TYPE_MSI:
3858 case X86_IRQ_ALLOC_TYPE_MSIX:
3859 devid = get_device_id(&info->msi_dev->dev);
3860 iommu = amd_iommu_rlookup_table[devid];
3861 if (iommu)
3862 return iommu->msi_domain;
3863 break;
3864 default:
3865 break;
3866 }
3867
3868 return NULL;
3869 }
3870
3871 struct irq_remap_ops amd_iommu_irq_ops = {
3872 .prepare = amd_iommu_prepare,
3873 .enable = amd_iommu_enable,
3874 .disable = amd_iommu_disable,
3875 .reenable = amd_iommu_reenable,
3876 .enable_faulting = amd_iommu_enable_faulting,
3877 .get_ir_irq_domain = get_ir_irq_domain,
3878 .get_irq_domain = get_irq_domain,
3879 };
3880
3881 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3882 struct irq_cfg *irq_cfg,
3883 struct irq_alloc_info *info,
3884 int devid, int index, int sub_handle)
3885 {
3886 struct irq_2_irte *irte_info = &data->irq_2_irte;
3887 struct msi_msg *msg = &data->msi_entry;
3888 union irte *irte = &data->irte_entry;
3889 struct IO_APIC_route_entry *entry;
3890
3891 data->irq_2_irte.devid = devid;
3892 data->irq_2_irte.index = index + sub_handle;
3893
3894 /* Setup IRTE for IOMMU */
3895 irte->val = 0;
3896 irte->fields.vector = irq_cfg->vector;
3897 irte->fields.int_type = apic->irq_delivery_mode;
3898 irte->fields.destination = irq_cfg->dest_apicid;
3899 irte->fields.dm = apic->irq_dest_mode;
3900 irte->fields.valid = 1;
3901
3902 switch (info->type) {
3903 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3904 /* Setup IOAPIC entry */
3905 entry = info->ioapic_entry;
3906 info->ioapic_entry = NULL;
3907 memset(entry, 0, sizeof(*entry));
3908 entry->vector = index;
3909 entry->mask = 0;
3910 entry->trigger = info->ioapic_trigger;
3911 entry->polarity = info->ioapic_polarity;
3912 /* Mask level triggered irqs. */
3913 if (info->ioapic_trigger)
3914 entry->mask = 1;
3915 break;
3916
3917 case X86_IRQ_ALLOC_TYPE_HPET:
3918 case X86_IRQ_ALLOC_TYPE_MSI:
3919 case X86_IRQ_ALLOC_TYPE_MSIX:
3920 msg->address_hi = MSI_ADDR_BASE_HI;
3921 msg->address_lo = MSI_ADDR_BASE_LO;
3922 msg->data = irte_info->index;
3923 break;
3924
3925 default:
3926 BUG_ON(1);
3927 break;
3928 }
3929 }
3930
3931 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3932 unsigned int nr_irqs, void *arg)
3933 {
3934 struct irq_alloc_info *info = arg;
3935 struct irq_data *irq_data;
3936 struct amd_ir_data *data;
3937 struct irq_cfg *cfg;
3938 int i, ret, devid;
3939 int index = -1;
3940
3941 if (!info)
3942 return -EINVAL;
3943 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
3944 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
3945 return -EINVAL;
3946
3947 /*
3948 * With IRQ remapping enabled, don't need contiguous CPU vectors
3949 * to support multiple MSI interrupts.
3950 */
3951 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
3952 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3953
3954 devid = get_devid(info);
3955 if (devid < 0)
3956 return -EINVAL;
3957
3958 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3959 if (ret < 0)
3960 return ret;
3961
3962 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3963 if (get_irq_table(devid, true))
3964 index = info->ioapic_pin;
3965 else
3966 ret = -ENOMEM;
3967 } else {
3968 index = alloc_irq_index(devid, nr_irqs);
3969 }
3970 if (index < 0) {
3971 pr_warn("Failed to allocate IRTE\n");
3972 goto out_free_parent;
3973 }
3974
3975 for (i = 0; i < nr_irqs; i++) {
3976 irq_data = irq_domain_get_irq_data(domain, virq + i);
3977 cfg = irqd_cfg(irq_data);
3978 if (!irq_data || !cfg) {
3979 ret = -EINVAL;
3980 goto out_free_data;
3981 }
3982
3983 ret = -ENOMEM;
3984 data = kzalloc(sizeof(*data), GFP_KERNEL);
3985 if (!data)
3986 goto out_free_data;
3987
3988 irq_data->hwirq = (devid << 16) + i;
3989 irq_data->chip_data = data;
3990 irq_data->chip = &amd_ir_chip;
3991 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3992 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3993 }
3994
3995 return 0;
3996
3997 out_free_data:
3998 for (i--; i >= 0; i--) {
3999 irq_data = irq_domain_get_irq_data(domain, virq + i);
4000 if (irq_data)
4001 kfree(irq_data->chip_data);
4002 }
4003 for (i = 0; i < nr_irqs; i++)
4004 free_irte(devid, index + i);
4005 out_free_parent:
4006 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4007 return ret;
4008 }
4009
4010 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4011 unsigned int nr_irqs)
4012 {
4013 struct irq_2_irte *irte_info;
4014 struct irq_data *irq_data;
4015 struct amd_ir_data *data;
4016 int i;
4017
4018 for (i = 0; i < nr_irqs; i++) {
4019 irq_data = irq_domain_get_irq_data(domain, virq + i);
4020 if (irq_data && irq_data->chip_data) {
4021 data = irq_data->chip_data;
4022 irte_info = &data->irq_2_irte;
4023 free_irte(irte_info->devid, irte_info->index);
4024 kfree(data);
4025 }
4026 }
4027 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4028 }
4029
4030 static void irq_remapping_activate(struct irq_domain *domain,
4031 struct irq_data *irq_data)
4032 {
4033 struct amd_ir_data *data = irq_data->chip_data;
4034 struct irq_2_irte *irte_info = &data->irq_2_irte;
4035
4036 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
4037 }
4038
4039 static void irq_remapping_deactivate(struct irq_domain *domain,
4040 struct irq_data *irq_data)
4041 {
4042 struct amd_ir_data *data = irq_data->chip_data;
4043 struct irq_2_irte *irte_info = &data->irq_2_irte;
4044 union irte entry;
4045
4046 entry.val = 0;
4047 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
4048 }
4049
4050 static struct irq_domain_ops amd_ir_domain_ops = {
4051 .alloc = irq_remapping_alloc,
4052 .free = irq_remapping_free,
4053 .activate = irq_remapping_activate,
4054 .deactivate = irq_remapping_deactivate,
4055 };
4056
4057 static int amd_ir_set_affinity(struct irq_data *data,
4058 const struct cpumask *mask, bool force)
4059 {
4060 struct amd_ir_data *ir_data = data->chip_data;
4061 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4062 struct irq_cfg *cfg = irqd_cfg(data);
4063 struct irq_data *parent = data->parent_data;
4064 int ret;
4065
4066 ret = parent->chip->irq_set_affinity(parent, mask, force);
4067 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4068 return ret;
4069
4070 /*
4071 * Atomically updates the IRTE with the new destination, vector
4072 * and flushes the interrupt entry cache.
4073 */
4074 ir_data->irte_entry.fields.vector = cfg->vector;
4075 ir_data->irte_entry.fields.destination = cfg->dest_apicid;
4076 modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry);
4077
4078 /*
4079 * After this point, all the interrupts will start arriving
4080 * at the new destination. So, time to cleanup the previous
4081 * vector allocation.
4082 */
4083 send_cleanup_vector(cfg);
4084
4085 return IRQ_SET_MASK_OK_DONE;
4086 }
4087
4088 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4089 {
4090 struct amd_ir_data *ir_data = irq_data->chip_data;
4091
4092 *msg = ir_data->msi_entry;
4093 }
4094
4095 static struct irq_chip amd_ir_chip = {
4096 .irq_ack = ir_ack_apic_edge,
4097 .irq_set_affinity = amd_ir_set_affinity,
4098 .irq_compose_msi_msg = ir_compose_msi_msg,
4099 };
4100
4101 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4102 {
4103 iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
4104 if (!iommu->ir_domain)
4105 return -ENOMEM;
4106
4107 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4108 iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
4109
4110 return 0;
4111 }
4112 #endif
Linux kernel - Deliverables
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