2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <linux/dma-contiguous.h>
37 #include <linux/irqdomain.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/io_apic.h>
41 #include <asm/hw_irq.h>
42 #include <asm/msidef.h>
43 #include <asm/proto.h>
44 #include <asm/iommu.h>
48 #include "amd_iommu_proto.h"
49 #include "amd_iommu_types.h"
50 #include "irq_remapping.h"
52 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
54 #define LOOP_TIMEOUT 100000
57 * This bitmap is used to advertise the page sizes our hardware support
58 * to the IOMMU core, which will then use this information to split
59 * physically contiguous memory regions it is mapping into page sizes
62 * 512GB Pages are not supported due to a hardware bug
64 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
66 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
68 /* A list of preallocated protection domains */
69 static LIST_HEAD(iommu_pd_list
);
70 static DEFINE_SPINLOCK(iommu_pd_list_lock
);
72 /* List of all available dev_data structures */
73 static LIST_HEAD(dev_data_list
);
74 static DEFINE_SPINLOCK(dev_data_list_lock
);
76 LIST_HEAD(ioapic_map
);
80 * Domain for untranslated devices - only allocated
81 * if iommu=pt passed on kernel cmd line.
83 static struct protection_domain
*pt_domain
;
85 static const struct iommu_ops amd_iommu_ops
;
87 static ATOMIC_NOTIFIER_HEAD(ppr_notifier
);
88 int amd_iommu_max_glx_val
= -1;
90 static struct dma_map_ops amd_iommu_dma_ops
;
93 * This struct contains device specific data for the IOMMU
95 struct iommu_dev_data
{
96 struct list_head list
; /* For domain->dev_list */
97 struct list_head dev_data_list
; /* For global dev_data_list */
98 struct list_head alias_list
; /* Link alias-groups together */
99 struct iommu_dev_data
*alias_data
;/* The alias dev_data */
100 struct protection_domain
*domain
; /* Domain the device is bound to */
101 u16 devid
; /* PCI Device ID */
102 bool iommu_v2
; /* Device can make use of IOMMUv2 */
103 bool passthrough
; /* Default for device is pt_domain */
107 } ats
; /* ATS state */
108 bool pri_tlp
; /* PASID TLB required for
110 u32 errata
; /* Bitmap for errata to apply */
114 * general struct to manage commands send to an IOMMU
120 struct kmem_cache
*amd_iommu_irq_cache
;
122 static void update_domain(struct protection_domain
*domain
);
123 static int __init
alloc_passthrough_domain(void);
125 /****************************************************************************
129 ****************************************************************************/
131 static struct protection_domain
*to_pdomain(struct iommu_domain
*dom
)
133 return container_of(dom
, struct protection_domain
, domain
);
136 static struct iommu_dev_data
*alloc_dev_data(u16 devid
)
138 struct iommu_dev_data
*dev_data
;
141 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
145 INIT_LIST_HEAD(&dev_data
->alias_list
);
147 dev_data
->devid
= devid
;
149 spin_lock_irqsave(&dev_data_list_lock
, flags
);
150 list_add_tail(&dev_data
->dev_data_list
, &dev_data_list
);
151 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
156 static void free_dev_data(struct iommu_dev_data
*dev_data
)
160 spin_lock_irqsave(&dev_data_list_lock
, flags
);
161 list_del(&dev_data
->dev_data_list
);
162 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
167 static struct iommu_dev_data
*search_dev_data(u16 devid
)
169 struct iommu_dev_data
*dev_data
;
172 spin_lock_irqsave(&dev_data_list_lock
, flags
);
173 list_for_each_entry(dev_data
, &dev_data_list
, dev_data_list
) {
174 if (dev_data
->devid
== devid
)
181 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
186 static struct iommu_dev_data
*find_dev_data(u16 devid
)
188 struct iommu_dev_data
*dev_data
;
190 dev_data
= search_dev_data(devid
);
192 if (dev_data
== NULL
)
193 dev_data
= alloc_dev_data(devid
);
198 static inline u16
get_device_id(struct device
*dev
)
200 struct pci_dev
*pdev
= to_pci_dev(dev
);
202 return PCI_DEVID(pdev
->bus
->number
, pdev
->devfn
);
205 static struct iommu_dev_data
*get_dev_data(struct device
*dev
)
207 return dev
->archdata
.iommu
;
210 static bool pci_iommuv2_capable(struct pci_dev
*pdev
)
212 static const int caps
[] = {
215 PCI_EXT_CAP_ID_PASID
,
219 for (i
= 0; i
< 3; ++i
) {
220 pos
= pci_find_ext_capability(pdev
, caps
[i
]);
228 static bool pdev_pri_erratum(struct pci_dev
*pdev
, u32 erratum
)
230 struct iommu_dev_data
*dev_data
;
232 dev_data
= get_dev_data(&pdev
->dev
);
234 return dev_data
->errata
& (1 << erratum
) ? true : false;
238 * In this function the list of preallocated protection domains is traversed to
239 * find the domain for a specific device
241 static struct dma_ops_domain
*find_protection_domain(u16 devid
)
243 struct dma_ops_domain
*entry
, *ret
= NULL
;
245 u16 alias
= amd_iommu_alias_table
[devid
];
247 if (list_empty(&iommu_pd_list
))
250 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
252 list_for_each_entry(entry
, &iommu_pd_list
, list
) {
253 if (entry
->target_dev
== devid
||
254 entry
->target_dev
== alias
) {
260 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
266 * This function checks if the driver got a valid device from the caller to
267 * avoid dereferencing invalid pointers.
269 static bool check_device(struct device
*dev
)
273 if (!dev
|| !dev
->dma_mask
)
277 if (!dev_is_pci(dev
))
280 devid
= get_device_id(dev
);
282 /* Out of our scope? */
283 if (devid
> amd_iommu_last_bdf
)
286 if (amd_iommu_rlookup_table
[devid
] == NULL
)
292 static void init_iommu_group(struct device
*dev
)
294 struct iommu_group
*group
;
296 group
= iommu_group_get_for_dev(dev
);
298 iommu_group_put(group
);
301 static int __last_alias(struct pci_dev
*pdev
, u16 alias
, void *data
)
303 *(u16
*)data
= alias
;
307 static u16
get_alias(struct device
*dev
)
309 struct pci_dev
*pdev
= to_pci_dev(dev
);
310 u16 devid
, ivrs_alias
, pci_alias
;
312 devid
= get_device_id(dev
);
313 ivrs_alias
= amd_iommu_alias_table
[devid
];
314 pci_for_each_dma_alias(pdev
, __last_alias
, &pci_alias
);
316 if (ivrs_alias
== pci_alias
)
322 * The IVRS is fairly reliable in telling us about aliases, but it
323 * can't know about every screwy device. If we don't have an IVRS
324 * reported alias, use the PCI reported alias. In that case we may
325 * still need to initialize the rlookup and dev_table entries if the
326 * alias is to a non-existent device.
328 if (ivrs_alias
== devid
) {
329 if (!amd_iommu_rlookup_table
[pci_alias
]) {
330 amd_iommu_rlookup_table
[pci_alias
] =
331 amd_iommu_rlookup_table
[devid
];
332 memcpy(amd_iommu_dev_table
[pci_alias
].data
,
333 amd_iommu_dev_table
[devid
].data
,
334 sizeof(amd_iommu_dev_table
[pci_alias
].data
));
340 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
341 "for device %s[%04x:%04x], kernel reported alias "
342 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias
), PCI_SLOT(ivrs_alias
),
343 PCI_FUNC(ivrs_alias
), dev_name(dev
), pdev
->vendor
, pdev
->device
,
344 PCI_BUS_NUM(pci_alias
), PCI_SLOT(pci_alias
),
345 PCI_FUNC(pci_alias
));
348 * If we don't have a PCI DMA alias and the IVRS alias is on the same
349 * bus, then the IVRS table may know about a quirk that we don't.
351 if (pci_alias
== devid
&&
352 PCI_BUS_NUM(ivrs_alias
) == pdev
->bus
->number
) {
353 pdev
->dev_flags
|= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN
;
354 pdev
->dma_alias_devfn
= ivrs_alias
& 0xff;
355 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
356 PCI_SLOT(ivrs_alias
), PCI_FUNC(ivrs_alias
),
363 static int iommu_init_device(struct device
*dev
)
365 struct pci_dev
*pdev
= to_pci_dev(dev
);
366 struct iommu_dev_data
*dev_data
;
369 if (dev
->archdata
.iommu
)
372 dev_data
= find_dev_data(get_device_id(dev
));
376 alias
= get_alias(dev
);
378 if (alias
!= dev_data
->devid
) {
379 struct iommu_dev_data
*alias_data
;
381 alias_data
= find_dev_data(alias
);
382 if (alias_data
== NULL
) {
383 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
385 free_dev_data(dev_data
);
388 dev_data
->alias_data
= alias_data
;
390 /* Add device to the alias_list */
391 list_add(&dev_data
->alias_list
, &alias_data
->alias_list
);
394 if (pci_iommuv2_capable(pdev
)) {
395 struct amd_iommu
*iommu
;
397 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
398 dev_data
->iommu_v2
= iommu
->is_iommu_v2
;
401 dev
->archdata
.iommu
= dev_data
;
403 iommu_device_link(amd_iommu_rlookup_table
[dev_data
->devid
]->iommu_dev
,
409 static void iommu_ignore_device(struct device
*dev
)
413 devid
= get_device_id(dev
);
414 alias
= amd_iommu_alias_table
[devid
];
416 memset(&amd_iommu_dev_table
[devid
], 0, sizeof(struct dev_table_entry
));
417 memset(&amd_iommu_dev_table
[alias
], 0, sizeof(struct dev_table_entry
));
419 amd_iommu_rlookup_table
[devid
] = NULL
;
420 amd_iommu_rlookup_table
[alias
] = NULL
;
423 static void iommu_uninit_device(struct device
*dev
)
425 struct iommu_dev_data
*dev_data
= search_dev_data(get_device_id(dev
));
430 iommu_device_unlink(amd_iommu_rlookup_table
[dev_data
->devid
]->iommu_dev
,
433 iommu_group_remove_device(dev
);
435 /* Unlink from alias, it may change if another device is re-plugged */
436 dev_data
->alias_data
= NULL
;
439 * We keep dev_data around for unplugged devices and reuse it when the
440 * device is re-plugged - not doing so would introduce a ton of races.
444 void __init
amd_iommu_uninit_devices(void)
446 struct iommu_dev_data
*dev_data
, *n
;
447 struct pci_dev
*pdev
= NULL
;
449 for_each_pci_dev(pdev
) {
451 if (!check_device(&pdev
->dev
))
454 iommu_uninit_device(&pdev
->dev
);
457 /* Free all of our dev_data structures */
458 list_for_each_entry_safe(dev_data
, n
, &dev_data_list
, dev_data_list
)
459 free_dev_data(dev_data
);
462 int __init
amd_iommu_init_devices(void)
464 struct pci_dev
*pdev
= NULL
;
467 for_each_pci_dev(pdev
) {
469 if (!check_device(&pdev
->dev
))
472 ret
= iommu_init_device(&pdev
->dev
);
473 if (ret
== -ENOTSUPP
)
474 iommu_ignore_device(&pdev
->dev
);
480 * Initialize IOMMU groups only after iommu_init_device() has
481 * had a chance to populate any IVRS defined aliases.
483 for_each_pci_dev(pdev
) {
484 if (check_device(&pdev
->dev
))
485 init_iommu_group(&pdev
->dev
);
492 amd_iommu_uninit_devices();
496 #ifdef CONFIG_AMD_IOMMU_STATS
499 * Initialization code for statistics collection
502 DECLARE_STATS_COUNTER(compl_wait
);
503 DECLARE_STATS_COUNTER(cnt_map_single
);
504 DECLARE_STATS_COUNTER(cnt_unmap_single
);
505 DECLARE_STATS_COUNTER(cnt_map_sg
);
506 DECLARE_STATS_COUNTER(cnt_unmap_sg
);
507 DECLARE_STATS_COUNTER(cnt_alloc_coherent
);
508 DECLARE_STATS_COUNTER(cnt_free_coherent
);
509 DECLARE_STATS_COUNTER(cross_page
);
510 DECLARE_STATS_COUNTER(domain_flush_single
);
511 DECLARE_STATS_COUNTER(domain_flush_all
);
512 DECLARE_STATS_COUNTER(alloced_io_mem
);
513 DECLARE_STATS_COUNTER(total_map_requests
);
514 DECLARE_STATS_COUNTER(complete_ppr
);
515 DECLARE_STATS_COUNTER(invalidate_iotlb
);
516 DECLARE_STATS_COUNTER(invalidate_iotlb_all
);
517 DECLARE_STATS_COUNTER(pri_requests
);
519 static struct dentry
*stats_dir
;
520 static struct dentry
*de_fflush
;
522 static void amd_iommu_stats_add(struct __iommu_counter
*cnt
)
524 if (stats_dir
== NULL
)
527 cnt
->dent
= debugfs_create_u64(cnt
->name
, 0444, stats_dir
,
531 static void amd_iommu_stats_init(void)
533 stats_dir
= debugfs_create_dir("amd-iommu", NULL
);
534 if (stats_dir
== NULL
)
537 de_fflush
= debugfs_create_bool("fullflush", 0444, stats_dir
,
538 &amd_iommu_unmap_flush
);
540 amd_iommu_stats_add(&compl_wait
);
541 amd_iommu_stats_add(&cnt_map_single
);
542 amd_iommu_stats_add(&cnt_unmap_single
);
543 amd_iommu_stats_add(&cnt_map_sg
);
544 amd_iommu_stats_add(&cnt_unmap_sg
);
545 amd_iommu_stats_add(&cnt_alloc_coherent
);
546 amd_iommu_stats_add(&cnt_free_coherent
);
547 amd_iommu_stats_add(&cross_page
);
548 amd_iommu_stats_add(&domain_flush_single
);
549 amd_iommu_stats_add(&domain_flush_all
);
550 amd_iommu_stats_add(&alloced_io_mem
);
551 amd_iommu_stats_add(&total_map_requests
);
552 amd_iommu_stats_add(&complete_ppr
);
553 amd_iommu_stats_add(&invalidate_iotlb
);
554 amd_iommu_stats_add(&invalidate_iotlb_all
);
555 amd_iommu_stats_add(&pri_requests
);
560 /****************************************************************************
562 * Interrupt handling functions
564 ****************************************************************************/
566 static void dump_dte_entry(u16 devid
)
570 for (i
= 0; i
< 4; ++i
)
571 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i
,
572 amd_iommu_dev_table
[devid
].data
[i
]);
575 static void dump_command(unsigned long phys_addr
)
577 struct iommu_cmd
*cmd
= phys_to_virt(phys_addr
);
580 for (i
= 0; i
< 4; ++i
)
581 pr_err("AMD-Vi: CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
584 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
586 int type
, devid
, domid
, flags
;
587 volatile u32
*event
= __evt
;
592 type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
593 devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
594 domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
595 flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
596 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
599 /* Did we hit the erratum? */
600 if (++count
== LOOP_TIMEOUT
) {
601 pr_err("AMD-Vi: No event written to event log\n");
608 printk(KERN_ERR
"AMD-Vi: Event logged [");
611 case EVENT_TYPE_ILL_DEV
:
612 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
613 "address=0x%016llx flags=0x%04x]\n",
614 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
616 dump_dte_entry(devid
);
618 case EVENT_TYPE_IO_FAULT
:
619 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
620 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
621 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
622 domid
, address
, flags
);
624 case EVENT_TYPE_DEV_TAB_ERR
:
625 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
626 "address=0x%016llx flags=0x%04x]\n",
627 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
630 case EVENT_TYPE_PAGE_TAB_ERR
:
631 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
632 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
633 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
634 domid
, address
, flags
);
636 case EVENT_TYPE_ILL_CMD
:
637 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
638 dump_command(address
);
640 case EVENT_TYPE_CMD_HARD_ERR
:
641 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
642 "flags=0x%04x]\n", address
, flags
);
644 case EVENT_TYPE_IOTLB_INV_TO
:
645 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
646 "address=0x%016llx]\n",
647 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
650 case EVENT_TYPE_INV_DEV_REQ
:
651 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
652 "address=0x%016llx flags=0x%04x]\n",
653 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
657 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
660 memset(__evt
, 0, 4 * sizeof(u32
));
663 static void iommu_poll_events(struct amd_iommu
*iommu
)
667 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
668 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
670 while (head
!= tail
) {
671 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
672 head
= (head
+ EVENT_ENTRY_SIZE
) % iommu
->evt_buf_size
;
675 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
678 static void iommu_handle_ppr_entry(struct amd_iommu
*iommu
, u64
*raw
)
680 struct amd_iommu_fault fault
;
682 INC_STATS_COUNTER(pri_requests
);
684 if (PPR_REQ_TYPE(raw
[0]) != PPR_REQ_FAULT
) {
685 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
689 fault
.address
= raw
[1];
690 fault
.pasid
= PPR_PASID(raw
[0]);
691 fault
.device_id
= PPR_DEVID(raw
[0]);
692 fault
.tag
= PPR_TAG(raw
[0]);
693 fault
.flags
= PPR_FLAGS(raw
[0]);
695 atomic_notifier_call_chain(&ppr_notifier
, 0, &fault
);
698 static void iommu_poll_ppr_log(struct amd_iommu
*iommu
)
702 if (iommu
->ppr_log
== NULL
)
705 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
706 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
708 while (head
!= tail
) {
713 raw
= (u64
*)(iommu
->ppr_log
+ head
);
716 * Hardware bug: Interrupt may arrive before the entry is
717 * written to memory. If this happens we need to wait for the
720 for (i
= 0; i
< LOOP_TIMEOUT
; ++i
) {
721 if (PPR_REQ_TYPE(raw
[0]) != 0)
726 /* Avoid memcpy function-call overhead */
731 * To detect the hardware bug we need to clear the entry
734 raw
[0] = raw
[1] = 0UL;
736 /* Update head pointer of hardware ring-buffer */
737 head
= (head
+ PPR_ENTRY_SIZE
) % PPR_LOG_SIZE
;
738 writel(head
, iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
740 /* Handle PPR entry */
741 iommu_handle_ppr_entry(iommu
, entry
);
743 /* Refresh ring-buffer information */
744 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
745 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
749 irqreturn_t
amd_iommu_int_thread(int irq
, void *data
)
751 struct amd_iommu
*iommu
= (struct amd_iommu
*) data
;
752 u32 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
754 while (status
& (MMIO_STATUS_EVT_INT_MASK
| MMIO_STATUS_PPR_INT_MASK
)) {
755 /* Enable EVT and PPR interrupts again */
756 writel((MMIO_STATUS_EVT_INT_MASK
| MMIO_STATUS_PPR_INT_MASK
),
757 iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
759 if (status
& MMIO_STATUS_EVT_INT_MASK
) {
760 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
761 iommu_poll_events(iommu
);
764 if (status
& MMIO_STATUS_PPR_INT_MASK
) {
765 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
766 iommu_poll_ppr_log(iommu
);
770 * Hardware bug: ERBT1312
771 * When re-enabling interrupt (by writing 1
772 * to clear the bit), the hardware might also try to set
773 * the interrupt bit in the event status register.
774 * In this scenario, the bit will be set, and disable
775 * subsequent interrupts.
777 * Workaround: The IOMMU driver should read back the
778 * status register and check if the interrupt bits are cleared.
779 * If not, driver will need to go through the interrupt handler
780 * again and re-clear the bits
782 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
787 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
789 return IRQ_WAKE_THREAD
;
792 /****************************************************************************
794 * IOMMU command queuing functions
796 ****************************************************************************/
798 static int wait_on_sem(volatile u64
*sem
)
802 while (*sem
== 0 && i
< LOOP_TIMEOUT
) {
807 if (i
== LOOP_TIMEOUT
) {
808 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
815 static void copy_cmd_to_buffer(struct amd_iommu
*iommu
,
816 struct iommu_cmd
*cmd
,
821 target
= iommu
->cmd_buf
+ tail
;
822 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
824 /* Copy command to buffer */
825 memcpy(target
, cmd
, sizeof(*cmd
));
827 /* Tell the IOMMU about it */
828 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
831 static void build_completion_wait(struct iommu_cmd
*cmd
, u64 address
)
833 WARN_ON(address
& 0x7ULL
);
835 memset(cmd
, 0, sizeof(*cmd
));
836 cmd
->data
[0] = lower_32_bits(__pa(address
)) | CMD_COMPL_WAIT_STORE_MASK
;
837 cmd
->data
[1] = upper_32_bits(__pa(address
));
839 CMD_SET_TYPE(cmd
, CMD_COMPL_WAIT
);
842 static void build_inv_dte(struct iommu_cmd
*cmd
, u16 devid
)
844 memset(cmd
, 0, sizeof(*cmd
));
845 cmd
->data
[0] = devid
;
846 CMD_SET_TYPE(cmd
, CMD_INV_DEV_ENTRY
);
849 static void build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
850 size_t size
, u16 domid
, int pde
)
855 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
860 * If we have to flush more than one page, flush all
861 * TLB entries for this domain
863 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
867 address
&= PAGE_MASK
;
869 memset(cmd
, 0, sizeof(*cmd
));
870 cmd
->data
[1] |= domid
;
871 cmd
->data
[2] = lower_32_bits(address
);
872 cmd
->data
[3] = upper_32_bits(address
);
873 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
874 if (s
) /* size bit - we flush more than one 4kb page */
875 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
876 if (pde
) /* PDE bit - we want to flush everything, not only the PTEs */
877 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
880 static void build_inv_iotlb_pages(struct iommu_cmd
*cmd
, u16 devid
, int qdep
,
881 u64 address
, size_t size
)
886 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
891 * If we have to flush more than one page, flush all
892 * TLB entries for this domain
894 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
898 address
&= PAGE_MASK
;
900 memset(cmd
, 0, sizeof(*cmd
));
901 cmd
->data
[0] = devid
;
902 cmd
->data
[0] |= (qdep
& 0xff) << 24;
903 cmd
->data
[1] = devid
;
904 cmd
->data
[2] = lower_32_bits(address
);
905 cmd
->data
[3] = upper_32_bits(address
);
906 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
908 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
911 static void build_inv_iommu_pasid(struct iommu_cmd
*cmd
, u16 domid
, int pasid
,
912 u64 address
, bool size
)
914 memset(cmd
, 0, sizeof(*cmd
));
916 address
&= ~(0xfffULL
);
918 cmd
->data
[0] = pasid
;
919 cmd
->data
[1] = domid
;
920 cmd
->data
[2] = lower_32_bits(address
);
921 cmd
->data
[3] = upper_32_bits(address
);
922 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
923 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
925 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
926 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
929 static void build_inv_iotlb_pasid(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
930 int qdep
, u64 address
, bool size
)
932 memset(cmd
, 0, sizeof(*cmd
));
934 address
&= ~(0xfffULL
);
936 cmd
->data
[0] = devid
;
937 cmd
->data
[0] |= ((pasid
>> 8) & 0xff) << 16;
938 cmd
->data
[0] |= (qdep
& 0xff) << 24;
939 cmd
->data
[1] = devid
;
940 cmd
->data
[1] |= (pasid
& 0xff) << 16;
941 cmd
->data
[2] = lower_32_bits(address
);
942 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
943 cmd
->data
[3] = upper_32_bits(address
);
945 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
946 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
949 static void build_complete_ppr(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
950 int status
, int tag
, bool gn
)
952 memset(cmd
, 0, sizeof(*cmd
));
954 cmd
->data
[0] = devid
;
956 cmd
->data
[1] = pasid
;
957 cmd
->data
[2] = CMD_INV_IOMMU_PAGES_GN_MASK
;
959 cmd
->data
[3] = tag
& 0x1ff;
960 cmd
->data
[3] |= (status
& PPR_STATUS_MASK
) << PPR_STATUS_SHIFT
;
962 CMD_SET_TYPE(cmd
, CMD_COMPLETE_PPR
);
965 static void build_inv_all(struct iommu_cmd
*cmd
)
967 memset(cmd
, 0, sizeof(*cmd
));
968 CMD_SET_TYPE(cmd
, CMD_INV_ALL
);
971 static void build_inv_irt(struct iommu_cmd
*cmd
, u16 devid
)
973 memset(cmd
, 0, sizeof(*cmd
));
974 cmd
->data
[0] = devid
;
975 CMD_SET_TYPE(cmd
, CMD_INV_IRT
);
979 * Writes the command to the IOMMUs command buffer and informs the
980 * hardware about the new command.
982 static int iommu_queue_command_sync(struct amd_iommu
*iommu
,
983 struct iommu_cmd
*cmd
,
986 u32 left
, tail
, head
, next_tail
;
989 WARN_ON(iommu
->cmd_buf_size
& CMD_BUFFER_UNINITIALIZED
);
992 spin_lock_irqsave(&iommu
->lock
, flags
);
994 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
995 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
996 next_tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
997 left
= (head
- next_tail
) % iommu
->cmd_buf_size
;
1000 struct iommu_cmd sync_cmd
;
1001 volatile u64 sem
= 0;
1004 build_completion_wait(&sync_cmd
, (u64
)&sem
);
1005 copy_cmd_to_buffer(iommu
, &sync_cmd
, tail
);
1007 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1009 if ((ret
= wait_on_sem(&sem
)) != 0)
1015 copy_cmd_to_buffer(iommu
, cmd
, tail
);
1017 /* We need to sync now to make sure all commands are processed */
1018 iommu
->need_sync
= sync
;
1020 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1025 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
1027 return iommu_queue_command_sync(iommu
, cmd
, true);
1031 * This function queues a completion wait command into the command
1032 * buffer of an IOMMU
1034 static int iommu_completion_wait(struct amd_iommu
*iommu
)
1036 struct iommu_cmd cmd
;
1037 volatile u64 sem
= 0;
1040 if (!iommu
->need_sync
)
1043 build_completion_wait(&cmd
, (u64
)&sem
);
1045 ret
= iommu_queue_command_sync(iommu
, &cmd
, false);
1049 return wait_on_sem(&sem
);
1052 static int iommu_flush_dte(struct amd_iommu
*iommu
, u16 devid
)
1054 struct iommu_cmd cmd
;
1056 build_inv_dte(&cmd
, devid
);
1058 return iommu_queue_command(iommu
, &cmd
);
1061 static void iommu_flush_dte_all(struct amd_iommu
*iommu
)
1065 for (devid
= 0; devid
<= 0xffff; ++devid
)
1066 iommu_flush_dte(iommu
, devid
);
1068 iommu_completion_wait(iommu
);
1072 * This function uses heavy locking and may disable irqs for some time. But
1073 * this is no issue because it is only called during resume.
1075 static void iommu_flush_tlb_all(struct amd_iommu
*iommu
)
1079 for (dom_id
= 0; dom_id
<= 0xffff; ++dom_id
) {
1080 struct iommu_cmd cmd
;
1081 build_inv_iommu_pages(&cmd
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
1083 iommu_queue_command(iommu
, &cmd
);
1086 iommu_completion_wait(iommu
);
1089 static void iommu_flush_all(struct amd_iommu
*iommu
)
1091 struct iommu_cmd cmd
;
1093 build_inv_all(&cmd
);
1095 iommu_queue_command(iommu
, &cmd
);
1096 iommu_completion_wait(iommu
);
1099 static void iommu_flush_irt(struct amd_iommu
*iommu
, u16 devid
)
1101 struct iommu_cmd cmd
;
1103 build_inv_irt(&cmd
, devid
);
1105 iommu_queue_command(iommu
, &cmd
);
1108 static void iommu_flush_irt_all(struct amd_iommu
*iommu
)
1112 for (devid
= 0; devid
<= MAX_DEV_TABLE_ENTRIES
; devid
++)
1113 iommu_flush_irt(iommu
, devid
);
1115 iommu_completion_wait(iommu
);
1118 void iommu_flush_all_caches(struct amd_iommu
*iommu
)
1120 if (iommu_feature(iommu
, FEATURE_IA
)) {
1121 iommu_flush_all(iommu
);
1123 iommu_flush_dte_all(iommu
);
1124 iommu_flush_irt_all(iommu
);
1125 iommu_flush_tlb_all(iommu
);
1130 * Command send function for flushing on-device TLB
1132 static int device_flush_iotlb(struct iommu_dev_data
*dev_data
,
1133 u64 address
, size_t size
)
1135 struct amd_iommu
*iommu
;
1136 struct iommu_cmd cmd
;
1139 qdep
= dev_data
->ats
.qdep
;
1140 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1142 build_inv_iotlb_pages(&cmd
, dev_data
->devid
, qdep
, address
, size
);
1144 return iommu_queue_command(iommu
, &cmd
);
1148 * Command send function for invalidating a device table entry
1150 static int device_flush_dte(struct iommu_dev_data
*dev_data
)
1152 struct amd_iommu
*iommu
;
1155 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1157 ret
= iommu_flush_dte(iommu
, dev_data
->devid
);
1161 if (dev_data
->ats
.enabled
)
1162 ret
= device_flush_iotlb(dev_data
, 0, ~0UL);
1168 * TLB invalidation function which is called from the mapping functions.
1169 * It invalidates a single PTE if the range to flush is within a single
1170 * page. Otherwise it flushes the whole TLB of the IOMMU.
1172 static void __domain_flush_pages(struct protection_domain
*domain
,
1173 u64 address
, size_t size
, int pde
)
1175 struct iommu_dev_data
*dev_data
;
1176 struct iommu_cmd cmd
;
1179 build_inv_iommu_pages(&cmd
, address
, size
, domain
->id
, pde
);
1181 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1182 if (!domain
->dev_iommu
[i
])
1186 * Devices of this domain are behind this IOMMU
1187 * We need a TLB flush
1189 ret
|= iommu_queue_command(amd_iommus
[i
], &cmd
);
1192 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
1194 if (!dev_data
->ats
.enabled
)
1197 ret
|= device_flush_iotlb(dev_data
, address
, size
);
1203 static void domain_flush_pages(struct protection_domain
*domain
,
1204 u64 address
, size_t size
)
1206 __domain_flush_pages(domain
, address
, size
, 0);
1209 /* Flush the whole IO/TLB for a given protection domain */
1210 static void domain_flush_tlb(struct protection_domain
*domain
)
1212 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
1215 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1216 static void domain_flush_tlb_pde(struct protection_domain
*domain
)
1218 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
1221 static void domain_flush_complete(struct protection_domain
*domain
)
1225 for (i
= 0; i
< amd_iommus_present
; ++i
) {
1226 if (!domain
->dev_iommu
[i
])
1230 * Devices of this domain are behind this IOMMU
1231 * We need to wait for completion of all commands.
1233 iommu_completion_wait(amd_iommus
[i
]);
1239 * This function flushes the DTEs for all devices in domain
1241 static void domain_flush_devices(struct protection_domain
*domain
)
1243 struct iommu_dev_data
*dev_data
;
1245 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
1246 device_flush_dte(dev_data
);
1249 /****************************************************************************
1251 * The functions below are used the create the page table mappings for
1252 * unity mapped regions.
1254 ****************************************************************************/
1257 * This function is used to add another level to an IO page table. Adding
1258 * another level increases the size of the address space by 9 bits to a size up
1261 static bool increase_address_space(struct protection_domain
*domain
,
1266 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
1267 /* address space already 64 bit large */
1270 pte
= (void *)get_zeroed_page(gfp
);
1274 *pte
= PM_LEVEL_PDE(domain
->mode
,
1275 virt_to_phys(domain
->pt_root
));
1276 domain
->pt_root
= pte
;
1278 domain
->updated
= true;
1283 static u64
*alloc_pte(struct protection_domain
*domain
,
1284 unsigned long address
,
1285 unsigned long page_size
,
1292 BUG_ON(!is_power_of_2(page_size
));
1294 while (address
> PM_LEVEL_SIZE(domain
->mode
))
1295 increase_address_space(domain
, gfp
);
1297 level
= domain
->mode
- 1;
1298 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1299 address
= PAGE_SIZE_ALIGN(address
, page_size
);
1300 end_lvl
= PAGE_SIZE_LEVEL(page_size
);
1302 while (level
> end_lvl
) {
1303 if (!IOMMU_PTE_PRESENT(*pte
)) {
1304 page
= (u64
*)get_zeroed_page(gfp
);
1307 *pte
= PM_LEVEL_PDE(level
, virt_to_phys(page
));
1310 /* No level skipping support yet */
1311 if (PM_PTE_LEVEL(*pte
) != level
)
1316 pte
= IOMMU_PTE_PAGE(*pte
);
1318 if (pte_page
&& level
== end_lvl
)
1321 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1328 * This function checks if there is a PTE for a given dma address. If
1329 * there is one, it returns the pointer to it.
1331 static u64
*fetch_pte(struct protection_domain
*domain
,
1332 unsigned long address
,
1333 unsigned long *page_size
)
1338 if (address
> PM_LEVEL_SIZE(domain
->mode
))
1341 level
= domain
->mode
- 1;
1342 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1343 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1348 if (!IOMMU_PTE_PRESENT(*pte
))
1352 if (PM_PTE_LEVEL(*pte
) == 7 ||
1353 PM_PTE_LEVEL(*pte
) == 0)
1356 /* No level skipping support yet */
1357 if (PM_PTE_LEVEL(*pte
) != level
)
1362 /* Walk to the next level */
1363 pte
= IOMMU_PTE_PAGE(*pte
);
1364 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1365 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1368 if (PM_PTE_LEVEL(*pte
) == 0x07) {
1369 unsigned long pte_mask
;
1372 * If we have a series of large PTEs, make
1373 * sure to return a pointer to the first one.
1375 *page_size
= pte_mask
= PTE_PAGE_SIZE(*pte
);
1376 pte_mask
= ~((PAGE_SIZE_PTE_COUNT(pte_mask
) << 3) - 1);
1377 pte
= (u64
*)(((unsigned long)pte
) & pte_mask
);
1384 * Generic mapping functions. It maps a physical address into a DMA
1385 * address space. It allocates the page table pages if necessary.
1386 * In the future it can be extended to a generic mapping function
1387 * supporting all features of AMD IOMMU page tables like level skipping
1388 * and full 64 bit address spaces.
1390 static int iommu_map_page(struct protection_domain
*dom
,
1391 unsigned long bus_addr
,
1392 unsigned long phys_addr
,
1394 unsigned long page_size
)
1399 BUG_ON(!IS_ALIGNED(bus_addr
, page_size
));
1400 BUG_ON(!IS_ALIGNED(phys_addr
, page_size
));
1402 if (!(prot
& IOMMU_PROT_MASK
))
1405 count
= PAGE_SIZE_PTE_COUNT(page_size
);
1406 pte
= alloc_pte(dom
, bus_addr
, page_size
, NULL
, GFP_KERNEL
);
1411 for (i
= 0; i
< count
; ++i
)
1412 if (IOMMU_PTE_PRESENT(pte
[i
]))
1416 __pte
= PAGE_SIZE_PTE(phys_addr
, page_size
);
1417 __pte
|= PM_LEVEL_ENC(7) | IOMMU_PTE_P
| IOMMU_PTE_FC
;
1419 __pte
= phys_addr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1421 if (prot
& IOMMU_PROT_IR
)
1422 __pte
|= IOMMU_PTE_IR
;
1423 if (prot
& IOMMU_PROT_IW
)
1424 __pte
|= IOMMU_PTE_IW
;
1426 for (i
= 0; i
< count
; ++i
)
1434 static unsigned long iommu_unmap_page(struct protection_domain
*dom
,
1435 unsigned long bus_addr
,
1436 unsigned long page_size
)
1438 unsigned long long unmapped
;
1439 unsigned long unmap_size
;
1442 BUG_ON(!is_power_of_2(page_size
));
1446 while (unmapped
< page_size
) {
1448 pte
= fetch_pte(dom
, bus_addr
, &unmap_size
);
1453 count
= PAGE_SIZE_PTE_COUNT(unmap_size
);
1454 for (i
= 0; i
< count
; i
++)
1458 bus_addr
= (bus_addr
& ~(unmap_size
- 1)) + unmap_size
;
1459 unmapped
+= unmap_size
;
1462 BUG_ON(unmapped
&& !is_power_of_2(unmapped
));
1468 * This function checks if a specific unity mapping entry is needed for
1469 * this specific IOMMU.
1471 static int iommu_for_unity_map(struct amd_iommu
*iommu
,
1472 struct unity_map_entry
*entry
)
1476 for (i
= entry
->devid_start
; i
<= entry
->devid_end
; ++i
) {
1477 bdf
= amd_iommu_alias_table
[i
];
1478 if (amd_iommu_rlookup_table
[bdf
] == iommu
)
1486 * This function actually applies the mapping to the page table of the
1489 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
1490 struct unity_map_entry
*e
)
1495 for (addr
= e
->address_start
; addr
< e
->address_end
;
1496 addr
+= PAGE_SIZE
) {
1497 ret
= iommu_map_page(&dma_dom
->domain
, addr
, addr
, e
->prot
,
1502 * if unity mapping is in aperture range mark the page
1503 * as allocated in the aperture
1505 if (addr
< dma_dom
->aperture_size
)
1506 __set_bit(addr
>> PAGE_SHIFT
,
1507 dma_dom
->aperture
[0]->bitmap
);
1514 * Init the unity mappings for a specific IOMMU in the system
1516 * Basically iterates over all unity mapping entries and applies them to
1517 * the default domain DMA of that IOMMU if necessary.
1519 static int iommu_init_unity_mappings(struct amd_iommu
*iommu
)
1521 struct unity_map_entry
*entry
;
1524 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
1525 if (!iommu_for_unity_map(iommu
, entry
))
1527 ret
= dma_ops_unity_map(iommu
->default_dom
, entry
);
1536 * Inits the unity mappings required for a specific device
1538 static int init_unity_mappings_for_device(struct dma_ops_domain
*dma_dom
,
1541 struct unity_map_entry
*e
;
1544 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
1545 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
1547 ret
= dma_ops_unity_map(dma_dom
, e
);
1555 /****************************************************************************
1557 * The next functions belong to the address allocator for the dma_ops
1558 * interface functions. They work like the allocators in the other IOMMU
1559 * drivers. Its basically a bitmap which marks the allocated pages in
1560 * the aperture. Maybe it could be enhanced in the future to a more
1561 * efficient allocator.
1563 ****************************************************************************/
1566 * The address allocator core functions.
1568 * called with domain->lock held
1572 * Used to reserve address ranges in the aperture (e.g. for exclusion
1575 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
1576 unsigned long start_page
,
1579 unsigned int i
, last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
1581 if (start_page
+ pages
> last_page
)
1582 pages
= last_page
- start_page
;
1584 for (i
= start_page
; i
< start_page
+ pages
; ++i
) {
1585 int index
= i
/ APERTURE_RANGE_PAGES
;
1586 int page
= i
% APERTURE_RANGE_PAGES
;
1587 __set_bit(page
, dom
->aperture
[index
]->bitmap
);
1592 * This function is used to add a new aperture range to an existing
1593 * aperture in case of dma_ops domain allocation or address allocation
1596 static int alloc_new_range(struct dma_ops_domain
*dma_dom
,
1597 bool populate
, gfp_t gfp
)
1599 int index
= dma_dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1600 struct amd_iommu
*iommu
;
1601 unsigned long i
, old_size
, pte_pgsize
;
1603 #ifdef CONFIG_IOMMU_STRESS
1607 if (index
>= APERTURE_MAX_RANGES
)
1610 dma_dom
->aperture
[index
] = kzalloc(sizeof(struct aperture_range
), gfp
);
1611 if (!dma_dom
->aperture
[index
])
1614 dma_dom
->aperture
[index
]->bitmap
= (void *)get_zeroed_page(gfp
);
1615 if (!dma_dom
->aperture
[index
]->bitmap
)
1618 dma_dom
->aperture
[index
]->offset
= dma_dom
->aperture_size
;
1621 unsigned long address
= dma_dom
->aperture_size
;
1622 int i
, num_ptes
= APERTURE_RANGE_PAGES
/ 512;
1623 u64
*pte
, *pte_page
;
1625 for (i
= 0; i
< num_ptes
; ++i
) {
1626 pte
= alloc_pte(&dma_dom
->domain
, address
, PAGE_SIZE
,
1631 dma_dom
->aperture
[index
]->pte_pages
[i
] = pte_page
;
1633 address
+= APERTURE_RANGE_SIZE
/ 64;
1637 old_size
= dma_dom
->aperture_size
;
1638 dma_dom
->aperture_size
+= APERTURE_RANGE_SIZE
;
1640 /* Reserve address range used for MSI messages */
1641 if (old_size
< MSI_ADDR_BASE_LO
&&
1642 dma_dom
->aperture_size
> MSI_ADDR_BASE_LO
) {
1643 unsigned long spage
;
1646 pages
= iommu_num_pages(MSI_ADDR_BASE_LO
, 0x10000, PAGE_SIZE
);
1647 spage
= MSI_ADDR_BASE_LO
>> PAGE_SHIFT
;
1649 dma_ops_reserve_addresses(dma_dom
, spage
, pages
);
1652 /* Initialize the exclusion range if necessary */
1653 for_each_iommu(iommu
) {
1654 if (iommu
->exclusion_start
&&
1655 iommu
->exclusion_start
>= dma_dom
->aperture
[index
]->offset
1656 && iommu
->exclusion_start
< dma_dom
->aperture_size
) {
1657 unsigned long startpage
;
1658 int pages
= iommu_num_pages(iommu
->exclusion_start
,
1659 iommu
->exclusion_length
,
1661 startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
1662 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
1667 * Check for areas already mapped as present in the new aperture
1668 * range and mark those pages as reserved in the allocator. Such
1669 * mappings may already exist as a result of requested unity
1670 * mappings for devices.
1672 for (i
= dma_dom
->aperture
[index
]->offset
;
1673 i
< dma_dom
->aperture_size
;
1675 u64
*pte
= fetch_pte(&dma_dom
->domain
, i
, &pte_pgsize
);
1676 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
1679 dma_ops_reserve_addresses(dma_dom
, i
>> PAGE_SHIFT
,
1683 update_domain(&dma_dom
->domain
);
1688 update_domain(&dma_dom
->domain
);
1690 free_page((unsigned long)dma_dom
->aperture
[index
]->bitmap
);
1692 kfree(dma_dom
->aperture
[index
]);
1693 dma_dom
->aperture
[index
] = NULL
;
1698 static unsigned long dma_ops_area_alloc(struct device
*dev
,
1699 struct dma_ops_domain
*dom
,
1701 unsigned long align_mask
,
1703 unsigned long start
)
1705 unsigned long next_bit
= dom
->next_address
% APERTURE_RANGE_SIZE
;
1706 int max_index
= dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1707 int i
= start
>> APERTURE_RANGE_SHIFT
;
1708 unsigned long boundary_size
;
1709 unsigned long address
= -1;
1710 unsigned long limit
;
1712 next_bit
>>= PAGE_SHIFT
;
1714 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
1715 PAGE_SIZE
) >> PAGE_SHIFT
;
1717 for (;i
< max_index
; ++i
) {
1718 unsigned long offset
= dom
->aperture
[i
]->offset
>> PAGE_SHIFT
;
1720 if (dom
->aperture
[i
]->offset
>= dma_mask
)
1723 limit
= iommu_device_max_index(APERTURE_RANGE_PAGES
, offset
,
1724 dma_mask
>> PAGE_SHIFT
);
1726 address
= iommu_area_alloc(dom
->aperture
[i
]->bitmap
,
1727 limit
, next_bit
, pages
, 0,
1728 boundary_size
, align_mask
);
1729 if (address
!= -1) {
1730 address
= dom
->aperture
[i
]->offset
+
1731 (address
<< PAGE_SHIFT
);
1732 dom
->next_address
= address
+ (pages
<< PAGE_SHIFT
);
1742 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
1743 struct dma_ops_domain
*dom
,
1745 unsigned long align_mask
,
1748 unsigned long address
;
1750 #ifdef CONFIG_IOMMU_STRESS
1751 dom
->next_address
= 0;
1752 dom
->need_flush
= true;
1755 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1756 dma_mask
, dom
->next_address
);
1758 if (address
== -1) {
1759 dom
->next_address
= 0;
1760 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1762 dom
->need_flush
= true;
1765 if (unlikely(address
== -1))
1766 address
= DMA_ERROR_CODE
;
1768 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
1774 * The address free function.
1776 * called with domain->lock held
1778 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
1779 unsigned long address
,
1782 unsigned i
= address
>> APERTURE_RANGE_SHIFT
;
1783 struct aperture_range
*range
= dom
->aperture
[i
];
1785 BUG_ON(i
>= APERTURE_MAX_RANGES
|| range
== NULL
);
1787 #ifdef CONFIG_IOMMU_STRESS
1792 if (address
>= dom
->next_address
)
1793 dom
->need_flush
= true;
1795 address
= (address
% APERTURE_RANGE_SIZE
) >> PAGE_SHIFT
;
1797 bitmap_clear(range
->bitmap
, address
, pages
);
1801 /****************************************************************************
1803 * The next functions belong to the domain allocation. A domain is
1804 * allocated for every IOMMU as the default domain. If device isolation
1805 * is enabled, every device get its own domain. The most important thing
1806 * about domains is the page table mapping the DMA address space they
1809 ****************************************************************************/
1812 * This function adds a protection domain to the global protection domain list
1814 static void add_domain_to_list(struct protection_domain
*domain
)
1816 unsigned long flags
;
1818 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1819 list_add(&domain
->list
, &amd_iommu_pd_list
);
1820 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1824 * This function removes a protection domain to the global
1825 * protection domain list
1827 static void del_domain_from_list(struct protection_domain
*domain
)
1829 unsigned long flags
;
1831 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1832 list_del(&domain
->list
);
1833 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1836 static u16
domain_id_alloc(void)
1838 unsigned long flags
;
1841 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1842 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1844 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1845 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1848 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1853 static void domain_id_free(int id
)
1855 unsigned long flags
;
1857 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1858 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1859 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1860 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1863 #define DEFINE_FREE_PT_FN(LVL, FN) \
1864 static void free_pt_##LVL (unsigned long __pt) \
1872 for (i = 0; i < 512; ++i) { \
1873 if (!IOMMU_PTE_PRESENT(pt[i])) \
1876 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1879 free_page((unsigned long)pt); \
1882 DEFINE_FREE_PT_FN(l2
, free_page
)
1883 DEFINE_FREE_PT_FN(l3
, free_pt_l2
)
1884 DEFINE_FREE_PT_FN(l4
, free_pt_l3
)
1885 DEFINE_FREE_PT_FN(l5
, free_pt_l4
)
1886 DEFINE_FREE_PT_FN(l6
, free_pt_l5
)
1888 static void free_pagetable(struct protection_domain
*domain
)
1890 unsigned long root
= (unsigned long)domain
->pt_root
;
1892 switch (domain
->mode
) {
1893 case PAGE_MODE_NONE
:
1895 case PAGE_MODE_1_LEVEL
:
1898 case PAGE_MODE_2_LEVEL
:
1901 case PAGE_MODE_3_LEVEL
:
1904 case PAGE_MODE_4_LEVEL
:
1907 case PAGE_MODE_5_LEVEL
:
1910 case PAGE_MODE_6_LEVEL
:
1918 static void free_gcr3_tbl_level1(u64
*tbl
)
1923 for (i
= 0; i
< 512; ++i
) {
1924 if (!(tbl
[i
] & GCR3_VALID
))
1927 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1929 free_page((unsigned long)ptr
);
1933 static void free_gcr3_tbl_level2(u64
*tbl
)
1938 for (i
= 0; i
< 512; ++i
) {
1939 if (!(tbl
[i
] & GCR3_VALID
))
1942 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1944 free_gcr3_tbl_level1(ptr
);
1948 static void free_gcr3_table(struct protection_domain
*domain
)
1950 if (domain
->glx
== 2)
1951 free_gcr3_tbl_level2(domain
->gcr3_tbl
);
1952 else if (domain
->glx
== 1)
1953 free_gcr3_tbl_level1(domain
->gcr3_tbl
);
1954 else if (domain
->glx
!= 0)
1957 free_page((unsigned long)domain
->gcr3_tbl
);
1961 * Free a domain, only used if something went wrong in the
1962 * allocation path and we need to free an already allocated page table
1964 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1971 del_domain_from_list(&dom
->domain
);
1973 free_pagetable(&dom
->domain
);
1975 for (i
= 0; i
< APERTURE_MAX_RANGES
; ++i
) {
1976 if (!dom
->aperture
[i
])
1978 free_page((unsigned long)dom
->aperture
[i
]->bitmap
);
1979 kfree(dom
->aperture
[i
]);
1986 * Allocates a new protection domain usable for the dma_ops functions.
1987 * It also initializes the page table and the address allocator data
1988 * structures required for the dma_ops interface
1990 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
1992 struct dma_ops_domain
*dma_dom
;
1994 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
1998 spin_lock_init(&dma_dom
->domain
.lock
);
2000 dma_dom
->domain
.id
= domain_id_alloc();
2001 if (dma_dom
->domain
.id
== 0)
2003 INIT_LIST_HEAD(&dma_dom
->domain
.dev_list
);
2004 dma_dom
->domain
.mode
= PAGE_MODE_2_LEVEL
;
2005 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2006 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
2007 dma_dom
->domain
.priv
= dma_dom
;
2008 if (!dma_dom
->domain
.pt_root
)
2011 dma_dom
->need_flush
= false;
2012 dma_dom
->target_dev
= 0xffff;
2014 add_domain_to_list(&dma_dom
->domain
);
2016 if (alloc_new_range(dma_dom
, true, GFP_KERNEL
))
2020 * mark the first page as allocated so we never return 0 as
2021 * a valid dma-address. So we can use 0 as error value
2023 dma_dom
->aperture
[0]->bitmap
[0] = 1;
2024 dma_dom
->next_address
= 0;
2030 dma_ops_domain_free(dma_dom
);
2036 * little helper function to check whether a given protection domain is a
2039 static bool dma_ops_domain(struct protection_domain
*domain
)
2041 return domain
->flags
& PD_DMA_OPS_MASK
;
2044 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
, bool ats
)
2049 if (domain
->mode
!= PAGE_MODE_NONE
)
2050 pte_root
= virt_to_phys(domain
->pt_root
);
2052 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
2053 << DEV_ENTRY_MODE_SHIFT
;
2054 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
2056 flags
= amd_iommu_dev_table
[devid
].data
[1];
2059 flags
|= DTE_FLAG_IOTLB
;
2061 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2062 u64 gcr3
= __pa(domain
->gcr3_tbl
);
2063 u64 glx
= domain
->glx
;
2066 pte_root
|= DTE_FLAG_GV
;
2067 pte_root
|= (glx
& DTE_GLX_MASK
) << DTE_GLX_SHIFT
;
2069 /* First mask out possible old values for GCR3 table */
2070 tmp
= DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B
;
2073 tmp
= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C
;
2076 /* Encode GCR3 table into DTE */
2077 tmp
= DTE_GCR3_VAL_A(gcr3
) << DTE_GCR3_SHIFT_A
;
2080 tmp
= DTE_GCR3_VAL_B(gcr3
) << DTE_GCR3_SHIFT_B
;
2083 tmp
= DTE_GCR3_VAL_C(gcr3
) << DTE_GCR3_SHIFT_C
;
2087 flags
&= ~(0xffffUL
);
2088 flags
|= domain
->id
;
2090 amd_iommu_dev_table
[devid
].data
[1] = flags
;
2091 amd_iommu_dev_table
[devid
].data
[0] = pte_root
;
2094 static void clear_dte_entry(u16 devid
)
2096 /* remove entry from the device table seen by the hardware */
2097 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
2098 amd_iommu_dev_table
[devid
].data
[1] = 0;
2100 amd_iommu_apply_erratum_63(devid
);
2103 static void do_attach(struct iommu_dev_data
*dev_data
,
2104 struct protection_domain
*domain
)
2106 struct amd_iommu
*iommu
;
2109 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
2110 ats
= dev_data
->ats
.enabled
;
2112 /* Update data structures */
2113 dev_data
->domain
= domain
;
2114 list_add(&dev_data
->list
, &domain
->dev_list
);
2115 set_dte_entry(dev_data
->devid
, domain
, ats
);
2117 /* Do reference counting */
2118 domain
->dev_iommu
[iommu
->index
] += 1;
2119 domain
->dev_cnt
+= 1;
2121 /* Flush the DTE entry */
2122 device_flush_dte(dev_data
);
2125 static void do_detach(struct iommu_dev_data
*dev_data
)
2127 struct amd_iommu
*iommu
;
2129 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
2131 /* decrease reference counters */
2132 dev_data
->domain
->dev_iommu
[iommu
->index
] -= 1;
2133 dev_data
->domain
->dev_cnt
-= 1;
2135 /* Update data structures */
2136 dev_data
->domain
= NULL
;
2137 list_del(&dev_data
->list
);
2138 clear_dte_entry(dev_data
->devid
);
2140 /* Flush the DTE entry */
2141 device_flush_dte(dev_data
);
2145 * If a device is not yet associated with a domain, this function does
2146 * assigns it visible for the hardware
2148 static int __attach_device(struct iommu_dev_data
*dev_data
,
2149 struct protection_domain
*domain
)
2151 struct iommu_dev_data
*head
, *entry
;
2155 spin_lock(&domain
->lock
);
2159 if (head
->alias_data
!= NULL
)
2160 head
= head
->alias_data
;
2162 /* Now we have the root of the alias group, if any */
2165 if (head
->domain
!= NULL
)
2168 /* Attach alias group root */
2169 do_attach(head
, domain
);
2171 /* Attach other devices in the alias group */
2172 list_for_each_entry(entry
, &head
->alias_list
, alias_list
)
2173 do_attach(entry
, domain
);
2180 spin_unlock(&domain
->lock
);
2186 static void pdev_iommuv2_disable(struct pci_dev
*pdev
)
2188 pci_disable_ats(pdev
);
2189 pci_disable_pri(pdev
);
2190 pci_disable_pasid(pdev
);
2193 /* FIXME: Change generic reset-function to do the same */
2194 static int pri_reset_while_enabled(struct pci_dev
*pdev
)
2199 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2203 pci_read_config_word(pdev
, pos
+ PCI_PRI_CTRL
, &control
);
2204 control
|= PCI_PRI_CTRL_RESET
;
2205 pci_write_config_word(pdev
, pos
+ PCI_PRI_CTRL
, control
);
2210 static int pdev_iommuv2_enable(struct pci_dev
*pdev
)
2215 /* FIXME: Hardcode number of outstanding requests for now */
2217 if (pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE
))
2219 reset_enable
= pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_ENABLE_RESET
);
2221 /* Only allow access to user-accessible pages */
2222 ret
= pci_enable_pasid(pdev
, 0);
2226 /* First reset the PRI state of the device */
2227 ret
= pci_reset_pri(pdev
);
2232 ret
= pci_enable_pri(pdev
, reqs
);
2237 ret
= pri_reset_while_enabled(pdev
);
2242 ret
= pci_enable_ats(pdev
, PAGE_SHIFT
);
2249 pci_disable_pri(pdev
);
2250 pci_disable_pasid(pdev
);
2255 /* FIXME: Move this to PCI code */
2256 #define PCI_PRI_TLP_OFF (1 << 15)
2258 static bool pci_pri_tlp_required(struct pci_dev
*pdev
)
2263 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2267 pci_read_config_word(pdev
, pos
+ PCI_PRI_STATUS
, &status
);
2269 return (status
& PCI_PRI_TLP_OFF
) ? true : false;
2273 * If a device is not yet associated with a domain, this function
2274 * assigns it visible for the hardware
2276 static int attach_device(struct device
*dev
,
2277 struct protection_domain
*domain
)
2279 struct pci_dev
*pdev
= to_pci_dev(dev
);
2280 struct iommu_dev_data
*dev_data
;
2281 unsigned long flags
;
2284 dev_data
= get_dev_data(dev
);
2286 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2287 if (!dev_data
->iommu_v2
|| !dev_data
->passthrough
)
2290 if (pdev_iommuv2_enable(pdev
) != 0)
2293 dev_data
->ats
.enabled
= true;
2294 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2295 dev_data
->pri_tlp
= pci_pri_tlp_required(pdev
);
2296 } else if (amd_iommu_iotlb_sup
&&
2297 pci_enable_ats(pdev
, PAGE_SHIFT
) == 0) {
2298 dev_data
->ats
.enabled
= true;
2299 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2302 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2303 ret
= __attach_device(dev_data
, domain
);
2304 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2307 * We might boot into a crash-kernel here. The crashed kernel
2308 * left the caches in the IOMMU dirty. So we have to flush
2309 * here to evict all dirty stuff.
2311 domain_flush_tlb_pde(domain
);
2317 * Removes a device from a protection domain (unlocked)
2319 static void __detach_device(struct iommu_dev_data
*dev_data
)
2321 struct iommu_dev_data
*head
, *entry
;
2322 struct protection_domain
*domain
;
2323 unsigned long flags
;
2325 BUG_ON(!dev_data
->domain
);
2327 domain
= dev_data
->domain
;
2329 spin_lock_irqsave(&domain
->lock
, flags
);
2332 if (head
->alias_data
!= NULL
)
2333 head
= head
->alias_data
;
2335 list_for_each_entry(entry
, &head
->alias_list
, alias_list
)
2340 spin_unlock_irqrestore(&domain
->lock
, flags
);
2343 * If we run in passthrough mode the device must be assigned to the
2344 * passthrough domain if it is detached from any other domain.
2345 * Make sure we can deassign from the pt_domain itself.
2347 if (dev_data
->passthrough
&&
2348 (dev_data
->domain
== NULL
&& domain
!= pt_domain
))
2349 __attach_device(dev_data
, pt_domain
);
2353 * Removes a device from a protection domain (with devtable_lock held)
2355 static void detach_device(struct device
*dev
)
2357 struct protection_domain
*domain
;
2358 struct iommu_dev_data
*dev_data
;
2359 unsigned long flags
;
2361 dev_data
= get_dev_data(dev
);
2362 domain
= dev_data
->domain
;
2364 /* lock device table */
2365 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2366 __detach_device(dev_data
);
2367 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2369 if (domain
->flags
& PD_IOMMUV2_MASK
)
2370 pdev_iommuv2_disable(to_pci_dev(dev
));
2371 else if (dev_data
->ats
.enabled
)
2372 pci_disable_ats(to_pci_dev(dev
));
2374 dev_data
->ats
.enabled
= false;
2378 * Find out the protection domain structure for a given PCI device. This
2379 * will give us the pointer to the page table root for example.
2381 static struct protection_domain
*domain_for_device(struct device
*dev
)
2383 struct iommu_dev_data
*dev_data
;
2384 struct protection_domain
*dom
= NULL
;
2385 unsigned long flags
;
2387 dev_data
= get_dev_data(dev
);
2389 if (dev_data
->domain
)
2390 return dev_data
->domain
;
2392 if (dev_data
->alias_data
!= NULL
) {
2393 struct iommu_dev_data
*alias_data
= dev_data
->alias_data
;
2395 read_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2396 if (alias_data
->domain
!= NULL
) {
2397 __attach_device(dev_data
, alias_data
->domain
);
2398 dom
= alias_data
->domain
;
2400 read_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2406 static int device_change_notifier(struct notifier_block
*nb
,
2407 unsigned long action
, void *data
)
2409 struct dma_ops_domain
*dma_domain
;
2410 struct protection_domain
*domain
;
2411 struct iommu_dev_data
*dev_data
;
2412 struct device
*dev
= data
;
2413 struct amd_iommu
*iommu
;
2414 unsigned long flags
;
2417 if (!check_device(dev
))
2420 devid
= get_device_id(dev
);
2421 iommu
= amd_iommu_rlookup_table
[devid
];
2422 dev_data
= get_dev_data(dev
);
2425 case BUS_NOTIFY_ADD_DEVICE
:
2427 iommu_init_device(dev
);
2428 init_iommu_group(dev
);
2431 * dev_data is still NULL and
2432 * got initialized in iommu_init_device
2434 dev_data
= get_dev_data(dev
);
2436 if (iommu_pass_through
|| dev_data
->iommu_v2
) {
2437 dev_data
->passthrough
= true;
2438 attach_device(dev
, pt_domain
);
2442 domain
= domain_for_device(dev
);
2444 /* allocate a protection domain if a device is added */
2445 dma_domain
= find_protection_domain(devid
);
2447 dma_domain
= dma_ops_domain_alloc();
2450 dma_domain
->target_dev
= devid
;
2452 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
2453 list_add_tail(&dma_domain
->list
, &iommu_pd_list
);
2454 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
2457 dev
->archdata
.dma_ops
= &amd_iommu_dma_ops
;
2460 case BUS_NOTIFY_REMOVED_DEVICE
:
2462 iommu_uninit_device(dev
);
2468 iommu_completion_wait(iommu
);
2474 static struct notifier_block device_nb
= {
2475 .notifier_call
= device_change_notifier
,
2478 void amd_iommu_init_notifier(void)
2480 bus_register_notifier(&pci_bus_type
, &device_nb
);
2483 /*****************************************************************************
2485 * The next functions belong to the dma_ops mapping/unmapping code.
2487 *****************************************************************************/
2490 * In the dma_ops path we only have the struct device. This function
2491 * finds the corresponding IOMMU, the protection domain and the
2492 * requestor id for a given device.
2493 * If the device is not yet associated with a domain this is also done
2496 static struct protection_domain
*get_domain(struct device
*dev
)
2498 struct protection_domain
*domain
;
2499 struct dma_ops_domain
*dma_dom
;
2500 u16 devid
= get_device_id(dev
);
2502 if (!check_device(dev
))
2503 return ERR_PTR(-EINVAL
);
2505 domain
= domain_for_device(dev
);
2506 if (domain
!= NULL
&& !dma_ops_domain(domain
))
2507 return ERR_PTR(-EBUSY
);
2512 /* Device not bound yet - bind it */
2513 dma_dom
= find_protection_domain(devid
);
2515 dma_dom
= amd_iommu_rlookup_table
[devid
]->default_dom
;
2516 attach_device(dev
, &dma_dom
->domain
);
2517 DUMP_printk("Using protection domain %d for device %s\n",
2518 dma_dom
->domain
.id
, dev_name(dev
));
2520 return &dma_dom
->domain
;
2523 static void update_device_table(struct protection_domain
*domain
)
2525 struct iommu_dev_data
*dev_data
;
2527 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
2528 set_dte_entry(dev_data
->devid
, domain
, dev_data
->ats
.enabled
);
2531 static void update_domain(struct protection_domain
*domain
)
2533 if (!domain
->updated
)
2536 update_device_table(domain
);
2538 domain_flush_devices(domain
);
2539 domain_flush_tlb_pde(domain
);
2541 domain
->updated
= false;
2545 * This function fetches the PTE for a given address in the aperture
2547 static u64
* dma_ops_get_pte(struct dma_ops_domain
*dom
,
2548 unsigned long address
)
2550 struct aperture_range
*aperture
;
2551 u64
*pte
, *pte_page
;
2553 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
2557 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
2559 pte
= alloc_pte(&dom
->domain
, address
, PAGE_SIZE
, &pte_page
,
2561 aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)] = pte_page
;
2563 pte
+= PM_LEVEL_INDEX(0, address
);
2565 update_domain(&dom
->domain
);
2571 * This is the generic map function. It maps one 4kb page at paddr to
2572 * the given address in the DMA address space for the domain.
2574 static dma_addr_t
dma_ops_domain_map(struct dma_ops_domain
*dom
,
2575 unsigned long address
,
2581 WARN_ON(address
> dom
->aperture_size
);
2585 pte
= dma_ops_get_pte(dom
, address
);
2587 return DMA_ERROR_CODE
;
2589 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
2591 if (direction
== DMA_TO_DEVICE
)
2592 __pte
|= IOMMU_PTE_IR
;
2593 else if (direction
== DMA_FROM_DEVICE
)
2594 __pte
|= IOMMU_PTE_IW
;
2595 else if (direction
== DMA_BIDIRECTIONAL
)
2596 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
2602 return (dma_addr_t
)address
;
2606 * The generic unmapping function for on page in the DMA address space.
2608 static void dma_ops_domain_unmap(struct dma_ops_domain
*dom
,
2609 unsigned long address
)
2611 struct aperture_range
*aperture
;
2614 if (address
>= dom
->aperture_size
)
2617 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
2621 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
2625 pte
+= PM_LEVEL_INDEX(0, address
);
2633 * This function contains common code for mapping of a physically
2634 * contiguous memory region into DMA address space. It is used by all
2635 * mapping functions provided with this IOMMU driver.
2636 * Must be called with the domain lock held.
2638 static dma_addr_t
__map_single(struct device
*dev
,
2639 struct dma_ops_domain
*dma_dom
,
2646 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
2647 dma_addr_t address
, start
, ret
;
2649 unsigned long align_mask
= 0;
2652 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
2655 INC_STATS_COUNTER(total_map_requests
);
2658 INC_STATS_COUNTER(cross_page
);
2661 align_mask
= (1UL << get_order(size
)) - 1;
2664 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
, align_mask
,
2666 if (unlikely(address
== DMA_ERROR_CODE
)) {
2668 * setting next_address here will let the address
2669 * allocator only scan the new allocated range in the
2670 * first run. This is a small optimization.
2672 dma_dom
->next_address
= dma_dom
->aperture_size
;
2674 if (alloc_new_range(dma_dom
, false, GFP_ATOMIC
))
2678 * aperture was successfully enlarged by 128 MB, try
2685 for (i
= 0; i
< pages
; ++i
) {
2686 ret
= dma_ops_domain_map(dma_dom
, start
, paddr
, dir
);
2687 if (ret
== DMA_ERROR_CODE
)
2695 ADD_STATS_COUNTER(alloced_io_mem
, size
);
2697 if (unlikely(dma_dom
->need_flush
&& !amd_iommu_unmap_flush
)) {
2698 domain_flush_tlb(&dma_dom
->domain
);
2699 dma_dom
->need_flush
= false;
2700 } else if (unlikely(amd_iommu_np_cache
))
2701 domain_flush_pages(&dma_dom
->domain
, address
, size
);
2708 for (--i
; i
>= 0; --i
) {
2710 dma_ops_domain_unmap(dma_dom
, start
);
2713 dma_ops_free_addresses(dma_dom
, address
, pages
);
2715 return DMA_ERROR_CODE
;
2719 * Does the reverse of the __map_single function. Must be called with
2720 * the domain lock held too
2722 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
2723 dma_addr_t dma_addr
,
2727 dma_addr_t flush_addr
;
2728 dma_addr_t i
, start
;
2731 if ((dma_addr
== DMA_ERROR_CODE
) ||
2732 (dma_addr
+ size
> dma_dom
->aperture_size
))
2735 flush_addr
= dma_addr
;
2736 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
2737 dma_addr
&= PAGE_MASK
;
2740 for (i
= 0; i
< pages
; ++i
) {
2741 dma_ops_domain_unmap(dma_dom
, start
);
2745 SUB_STATS_COUNTER(alloced_io_mem
, size
);
2747 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
2749 if (amd_iommu_unmap_flush
|| dma_dom
->need_flush
) {
2750 domain_flush_pages(&dma_dom
->domain
, flush_addr
, size
);
2751 dma_dom
->need_flush
= false;
2756 * The exported map_single function for dma_ops.
2758 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
2759 unsigned long offset
, size_t size
,
2760 enum dma_data_direction dir
,
2761 struct dma_attrs
*attrs
)
2763 unsigned long flags
;
2764 struct protection_domain
*domain
;
2767 phys_addr_t paddr
= page_to_phys(page
) + offset
;
2769 INC_STATS_COUNTER(cnt_map_single
);
2771 domain
= get_domain(dev
);
2772 if (PTR_ERR(domain
) == -EINVAL
)
2773 return (dma_addr_t
)paddr
;
2774 else if (IS_ERR(domain
))
2775 return DMA_ERROR_CODE
;
2777 dma_mask
= *dev
->dma_mask
;
2779 spin_lock_irqsave(&domain
->lock
, flags
);
2781 addr
= __map_single(dev
, domain
->priv
, paddr
, size
, dir
, false,
2783 if (addr
== DMA_ERROR_CODE
)
2786 domain_flush_complete(domain
);
2789 spin_unlock_irqrestore(&domain
->lock
, flags
);
2795 * The exported unmap_single function for dma_ops.
2797 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
2798 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
2800 unsigned long flags
;
2801 struct protection_domain
*domain
;
2803 INC_STATS_COUNTER(cnt_unmap_single
);
2805 domain
= get_domain(dev
);
2809 spin_lock_irqsave(&domain
->lock
, flags
);
2811 __unmap_single(domain
->priv
, dma_addr
, size
, dir
);
2813 domain_flush_complete(domain
);
2815 spin_unlock_irqrestore(&domain
->lock
, flags
);
2819 * The exported map_sg function for dma_ops (handles scatter-gather
2822 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
2823 int nelems
, enum dma_data_direction dir
,
2824 struct dma_attrs
*attrs
)
2826 unsigned long flags
;
2827 struct protection_domain
*domain
;
2829 struct scatterlist
*s
;
2831 int mapped_elems
= 0;
2834 INC_STATS_COUNTER(cnt_map_sg
);
2836 domain
= get_domain(dev
);
2840 dma_mask
= *dev
->dma_mask
;
2842 spin_lock_irqsave(&domain
->lock
, flags
);
2844 for_each_sg(sglist
, s
, nelems
, i
) {
2847 s
->dma_address
= __map_single(dev
, domain
->priv
,
2848 paddr
, s
->length
, dir
, false,
2851 if (s
->dma_address
) {
2852 s
->dma_length
= s
->length
;
2858 domain_flush_complete(domain
);
2861 spin_unlock_irqrestore(&domain
->lock
, flags
);
2863 return mapped_elems
;
2865 for_each_sg(sglist
, s
, mapped_elems
, i
) {
2867 __unmap_single(domain
->priv
, s
->dma_address
,
2868 s
->dma_length
, dir
);
2869 s
->dma_address
= s
->dma_length
= 0;
2878 * The exported map_sg function for dma_ops (handles scatter-gather
2881 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2882 int nelems
, enum dma_data_direction dir
,
2883 struct dma_attrs
*attrs
)
2885 unsigned long flags
;
2886 struct protection_domain
*domain
;
2887 struct scatterlist
*s
;
2890 INC_STATS_COUNTER(cnt_unmap_sg
);
2892 domain
= get_domain(dev
);
2896 spin_lock_irqsave(&domain
->lock
, flags
);
2898 for_each_sg(sglist
, s
, nelems
, i
) {
2899 __unmap_single(domain
->priv
, s
->dma_address
,
2900 s
->dma_length
, dir
);
2901 s
->dma_address
= s
->dma_length
= 0;
2904 domain_flush_complete(domain
);
2906 spin_unlock_irqrestore(&domain
->lock
, flags
);
2910 * The exported alloc_coherent function for dma_ops.
2912 static void *alloc_coherent(struct device
*dev
, size_t size
,
2913 dma_addr_t
*dma_addr
, gfp_t flag
,
2914 struct dma_attrs
*attrs
)
2916 u64 dma_mask
= dev
->coherent_dma_mask
;
2917 struct protection_domain
*domain
;
2918 unsigned long flags
;
2921 INC_STATS_COUNTER(cnt_alloc_coherent
);
2923 domain
= get_domain(dev
);
2924 if (PTR_ERR(domain
) == -EINVAL
) {
2925 page
= alloc_pages(flag
, get_order(size
));
2926 *dma_addr
= page_to_phys(page
);
2927 return page_address(page
);
2928 } else if (IS_ERR(domain
))
2931 size
= PAGE_ALIGN(size
);
2932 dma_mask
= dev
->coherent_dma_mask
;
2933 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2936 page
= alloc_pages(flag
| __GFP_NOWARN
, get_order(size
));
2938 if (!(flag
& __GFP_WAIT
))
2941 page
= dma_alloc_from_contiguous(dev
, size
>> PAGE_SHIFT
,
2948 dma_mask
= *dev
->dma_mask
;
2950 spin_lock_irqsave(&domain
->lock
, flags
);
2952 *dma_addr
= __map_single(dev
, domain
->priv
, page_to_phys(page
),
2953 size
, DMA_BIDIRECTIONAL
, true, dma_mask
);
2955 if (*dma_addr
== DMA_ERROR_CODE
) {
2956 spin_unlock_irqrestore(&domain
->lock
, flags
);
2960 domain_flush_complete(domain
);
2962 spin_unlock_irqrestore(&domain
->lock
, flags
);
2964 return page_address(page
);
2968 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2969 __free_pages(page
, get_order(size
));
2975 * The exported free_coherent function for dma_ops.
2977 static void free_coherent(struct device
*dev
, size_t size
,
2978 void *virt_addr
, dma_addr_t dma_addr
,
2979 struct dma_attrs
*attrs
)
2981 struct protection_domain
*domain
;
2982 unsigned long flags
;
2985 INC_STATS_COUNTER(cnt_free_coherent
);
2987 page
= virt_to_page(virt_addr
);
2988 size
= PAGE_ALIGN(size
);
2990 domain
= get_domain(dev
);
2994 spin_lock_irqsave(&domain
->lock
, flags
);
2996 __unmap_single(domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
2998 domain_flush_complete(domain
);
3000 spin_unlock_irqrestore(&domain
->lock
, flags
);
3003 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
3004 __free_pages(page
, get_order(size
));
3008 * This function is called by the DMA layer to find out if we can handle a
3009 * particular device. It is part of the dma_ops.
3011 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
3013 return check_device(dev
);
3017 * The function for pre-allocating protection domains.
3019 * If the driver core informs the DMA layer if a driver grabs a device
3020 * we don't need to preallocate the protection domains anymore.
3021 * For now we have to.
3023 static void __init
prealloc_protection_domains(void)
3025 struct iommu_dev_data
*dev_data
;
3026 struct dma_ops_domain
*dma_dom
;
3027 struct pci_dev
*dev
= NULL
;
3030 for_each_pci_dev(dev
) {
3032 /* Do we handle this device? */
3033 if (!check_device(&dev
->dev
))
3036 dev_data
= get_dev_data(&dev
->dev
);
3037 if (!amd_iommu_force_isolation
&& dev_data
->iommu_v2
) {
3038 /* Make sure passthrough domain is allocated */
3039 alloc_passthrough_domain();
3040 dev_data
->passthrough
= true;
3041 attach_device(&dev
->dev
, pt_domain
);
3042 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
3043 dev_name(&dev
->dev
));
3046 /* Is there already any domain for it? */
3047 if (domain_for_device(&dev
->dev
))
3050 devid
= get_device_id(&dev
->dev
);
3052 dma_dom
= dma_ops_domain_alloc();
3055 init_unity_mappings_for_device(dma_dom
, devid
);
3056 dma_dom
->target_dev
= devid
;
3058 attach_device(&dev
->dev
, &dma_dom
->domain
);
3060 list_add_tail(&dma_dom
->list
, &iommu_pd_list
);
3064 static struct dma_map_ops amd_iommu_dma_ops
= {
3065 .alloc
= alloc_coherent
,
3066 .free
= free_coherent
,
3067 .map_page
= map_page
,
3068 .unmap_page
= unmap_page
,
3070 .unmap_sg
= unmap_sg
,
3071 .dma_supported
= amd_iommu_dma_supported
,
3074 static unsigned device_dma_ops_init(void)
3076 struct iommu_dev_data
*dev_data
;
3077 struct pci_dev
*pdev
= NULL
;
3078 unsigned unhandled
= 0;
3080 for_each_pci_dev(pdev
) {
3081 if (!check_device(&pdev
->dev
)) {
3083 iommu_ignore_device(&pdev
->dev
);
3089 dev_data
= get_dev_data(&pdev
->dev
);
3091 if (!dev_data
->passthrough
)
3092 pdev
->dev
.archdata
.dma_ops
= &amd_iommu_dma_ops
;
3094 pdev
->dev
.archdata
.dma_ops
= &nommu_dma_ops
;
3101 * The function which clues the AMD IOMMU driver into dma_ops.
3104 void __init
amd_iommu_init_api(void)
3106 bus_set_iommu(&pci_bus_type
, &amd_iommu_ops
);
3109 int __init
amd_iommu_init_dma_ops(void)
3111 struct amd_iommu
*iommu
;
3115 * first allocate a default protection domain for every IOMMU we
3116 * found in the system. Devices not assigned to any other
3117 * protection domain will be assigned to the default one.
3119 for_each_iommu(iommu
) {
3120 iommu
->default_dom
= dma_ops_domain_alloc();
3121 if (iommu
->default_dom
== NULL
)
3123 iommu
->default_dom
->domain
.flags
|= PD_DEFAULT_MASK
;
3124 ret
= iommu_init_unity_mappings(iommu
);
3130 * Pre-allocate the protection domains for each device.
3132 prealloc_protection_domains();
3137 /* Make the driver finally visible to the drivers */
3138 unhandled
= device_dma_ops_init();
3139 if (unhandled
&& max_pfn
> MAX_DMA32_PFN
) {
3140 /* There are unhandled devices - initialize swiotlb for them */
3144 amd_iommu_stats_init();
3146 if (amd_iommu_unmap_flush
)
3147 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3149 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3155 for_each_iommu(iommu
) {
3156 dma_ops_domain_free(iommu
->default_dom
);
3162 /*****************************************************************************
3164 * The following functions belong to the exported interface of AMD IOMMU
3166 * This interface allows access to lower level functions of the IOMMU
3167 * like protection domain handling and assignement of devices to domains
3168 * which is not possible with the dma_ops interface.
3170 *****************************************************************************/
3172 static void cleanup_domain(struct protection_domain
*domain
)
3174 struct iommu_dev_data
*entry
;
3175 unsigned long flags
;
3177 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3179 while (!list_empty(&domain
->dev_list
)) {
3180 entry
= list_first_entry(&domain
->dev_list
,
3181 struct iommu_dev_data
, list
);
3182 __detach_device(entry
);
3185 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3188 static void protection_domain_free(struct protection_domain
*domain
)
3193 del_domain_from_list(domain
);
3196 domain_id_free(domain
->id
);
3201 static struct protection_domain
*protection_domain_alloc(void)
3203 struct protection_domain
*domain
;
3205 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
3209 spin_lock_init(&domain
->lock
);
3210 mutex_init(&domain
->api_lock
);
3211 domain
->id
= domain_id_alloc();
3214 INIT_LIST_HEAD(&domain
->dev_list
);
3216 add_domain_to_list(domain
);
3226 static int __init
alloc_passthrough_domain(void)
3228 if (pt_domain
!= NULL
)
3231 /* allocate passthrough domain */
3232 pt_domain
= protection_domain_alloc();
3236 pt_domain
->mode
= PAGE_MODE_NONE
;
3241 static struct iommu_domain
*amd_iommu_domain_alloc(unsigned type
)
3243 struct protection_domain
*pdomain
;
3245 /* We only support unmanaged domains for now */
3246 if (type
!= IOMMU_DOMAIN_UNMANAGED
)
3249 pdomain
= protection_domain_alloc();
3253 pdomain
->mode
= PAGE_MODE_3_LEVEL
;
3254 pdomain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
3255 if (!pdomain
->pt_root
)
3258 pdomain
->domain
.geometry
.aperture_start
= 0;
3259 pdomain
->domain
.geometry
.aperture_end
= ~0ULL;
3260 pdomain
->domain
.geometry
.force_aperture
= true;
3262 return &pdomain
->domain
;
3265 protection_domain_free(pdomain
);
3270 static void amd_iommu_domain_free(struct iommu_domain
*dom
)
3272 struct protection_domain
*domain
;
3277 domain
= to_pdomain(dom
);
3279 if (domain
->dev_cnt
> 0)
3280 cleanup_domain(domain
);
3282 BUG_ON(domain
->dev_cnt
!= 0);
3284 if (domain
->mode
!= PAGE_MODE_NONE
)
3285 free_pagetable(domain
);
3287 if (domain
->flags
& PD_IOMMUV2_MASK
)
3288 free_gcr3_table(domain
);
3290 protection_domain_free(domain
);
3293 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
3296 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
3297 struct amd_iommu
*iommu
;
3300 if (!check_device(dev
))
3303 devid
= get_device_id(dev
);
3305 if (dev_data
->domain
!= NULL
)
3308 iommu
= amd_iommu_rlookup_table
[devid
];
3312 iommu_completion_wait(iommu
);
3315 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
3318 struct protection_domain
*domain
= to_pdomain(dom
);
3319 struct iommu_dev_data
*dev_data
;
3320 struct amd_iommu
*iommu
;
3323 if (!check_device(dev
))
3326 dev_data
= dev
->archdata
.iommu
;
3328 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3332 if (dev_data
->domain
)
3335 ret
= attach_device(dev
, domain
);
3337 iommu_completion_wait(iommu
);
3342 static int amd_iommu_map(struct iommu_domain
*dom
, unsigned long iova
,
3343 phys_addr_t paddr
, size_t page_size
, int iommu_prot
)
3345 struct protection_domain
*domain
= to_pdomain(dom
);
3349 if (domain
->mode
== PAGE_MODE_NONE
)
3352 if (iommu_prot
& IOMMU_READ
)
3353 prot
|= IOMMU_PROT_IR
;
3354 if (iommu_prot
& IOMMU_WRITE
)
3355 prot
|= IOMMU_PROT_IW
;
3357 mutex_lock(&domain
->api_lock
);
3358 ret
= iommu_map_page(domain
, iova
, paddr
, prot
, page_size
);
3359 mutex_unlock(&domain
->api_lock
);
3364 static size_t amd_iommu_unmap(struct iommu_domain
*dom
, unsigned long iova
,
3367 struct protection_domain
*domain
= to_pdomain(dom
);
3370 if (domain
->mode
== PAGE_MODE_NONE
)
3373 mutex_lock(&domain
->api_lock
);
3374 unmap_size
= iommu_unmap_page(domain
, iova
, page_size
);
3375 mutex_unlock(&domain
->api_lock
);
3377 domain_flush_tlb_pde(domain
);
3382 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
3385 struct protection_domain
*domain
= to_pdomain(dom
);
3386 unsigned long offset_mask
, pte_pgsize
;
3389 if (domain
->mode
== PAGE_MODE_NONE
)
3392 pte
= fetch_pte(domain
, iova
, &pte_pgsize
);
3394 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
3397 offset_mask
= pte_pgsize
- 1;
3398 __pte
= *pte
& PM_ADDR_MASK
;
3400 return (__pte
& ~offset_mask
) | (iova
& offset_mask
);
3403 static bool amd_iommu_capable(enum iommu_cap cap
)
3406 case IOMMU_CAP_CACHE_COHERENCY
:
3408 case IOMMU_CAP_INTR_REMAP
:
3409 return (irq_remapping_enabled
== 1);
3410 case IOMMU_CAP_NOEXEC
:
3417 static const struct iommu_ops amd_iommu_ops
= {
3418 .capable
= amd_iommu_capable
,
3419 .domain_alloc
= amd_iommu_domain_alloc
,
3420 .domain_free
= amd_iommu_domain_free
,
3421 .attach_dev
= amd_iommu_attach_device
,
3422 .detach_dev
= amd_iommu_detach_device
,
3423 .map
= amd_iommu_map
,
3424 .unmap
= amd_iommu_unmap
,
3425 .map_sg
= default_iommu_map_sg
,
3426 .iova_to_phys
= amd_iommu_iova_to_phys
,
3427 .pgsize_bitmap
= AMD_IOMMU_PGSIZES
,
3430 /*****************************************************************************
3432 * The next functions do a basic initialization of IOMMU for pass through
3435 * In passthrough mode the IOMMU is initialized and enabled but not used for
3436 * DMA-API translation.
3438 *****************************************************************************/
3440 int __init
amd_iommu_init_passthrough(void)
3442 struct iommu_dev_data
*dev_data
;
3443 struct pci_dev
*dev
= NULL
;
3446 ret
= alloc_passthrough_domain();
3450 for_each_pci_dev(dev
) {
3451 if (!check_device(&dev
->dev
))
3454 dev_data
= get_dev_data(&dev
->dev
);
3455 dev_data
->passthrough
= true;
3457 attach_device(&dev
->dev
, pt_domain
);
3460 amd_iommu_stats_init();
3462 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3467 /* IOMMUv2 specific functions */
3468 int amd_iommu_register_ppr_notifier(struct notifier_block
*nb
)
3470 return atomic_notifier_chain_register(&ppr_notifier
, nb
);
3472 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier
);
3474 int amd_iommu_unregister_ppr_notifier(struct notifier_block
*nb
)
3476 return atomic_notifier_chain_unregister(&ppr_notifier
, nb
);
3478 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier
);
3480 void amd_iommu_domain_direct_map(struct iommu_domain
*dom
)
3482 struct protection_domain
*domain
= to_pdomain(dom
);
3483 unsigned long flags
;
3485 spin_lock_irqsave(&domain
->lock
, flags
);
3487 /* Update data structure */
3488 domain
->mode
= PAGE_MODE_NONE
;
3489 domain
->updated
= true;
3491 /* Make changes visible to IOMMUs */
3492 update_domain(domain
);
3494 /* Page-table is not visible to IOMMU anymore, so free it */
3495 free_pagetable(domain
);
3497 spin_unlock_irqrestore(&domain
->lock
, flags
);
3499 EXPORT_SYMBOL(amd_iommu_domain_direct_map
);
3501 int amd_iommu_domain_enable_v2(struct iommu_domain
*dom
, int pasids
)
3503 struct protection_domain
*domain
= to_pdomain(dom
);
3504 unsigned long flags
;
3507 if (pasids
<= 0 || pasids
> (PASID_MASK
+ 1))
3510 /* Number of GCR3 table levels required */
3511 for (levels
= 0; (pasids
- 1) & ~0x1ff; pasids
>>= 9)
3514 if (levels
> amd_iommu_max_glx_val
)
3517 spin_lock_irqsave(&domain
->lock
, flags
);
3520 * Save us all sanity checks whether devices already in the
3521 * domain support IOMMUv2. Just force that the domain has no
3522 * devices attached when it is switched into IOMMUv2 mode.
3525 if (domain
->dev_cnt
> 0 || domain
->flags
& PD_IOMMUV2_MASK
)
3529 domain
->gcr3_tbl
= (void *)get_zeroed_page(GFP_ATOMIC
);
3530 if (domain
->gcr3_tbl
== NULL
)
3533 domain
->glx
= levels
;
3534 domain
->flags
|= PD_IOMMUV2_MASK
;
3535 domain
->updated
= true;
3537 update_domain(domain
);
3542 spin_unlock_irqrestore(&domain
->lock
, flags
);
3546 EXPORT_SYMBOL(amd_iommu_domain_enable_v2
);
3548 static int __flush_pasid(struct protection_domain
*domain
, int pasid
,
3549 u64 address
, bool size
)
3551 struct iommu_dev_data
*dev_data
;
3552 struct iommu_cmd cmd
;
3555 if (!(domain
->flags
& PD_IOMMUV2_MASK
))
3558 build_inv_iommu_pasid(&cmd
, domain
->id
, pasid
, address
, size
);
3561 * IOMMU TLB needs to be flushed before Device TLB to
3562 * prevent device TLB refill from IOMMU TLB
3564 for (i
= 0; i
< amd_iommus_present
; ++i
) {
3565 if (domain
->dev_iommu
[i
] == 0)
3568 ret
= iommu_queue_command(amd_iommus
[i
], &cmd
);
3573 /* Wait until IOMMU TLB flushes are complete */
3574 domain_flush_complete(domain
);
3576 /* Now flush device TLBs */
3577 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
3578 struct amd_iommu
*iommu
;
3581 BUG_ON(!dev_data
->ats
.enabled
);
3583 qdep
= dev_data
->ats
.qdep
;
3584 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3586 build_inv_iotlb_pasid(&cmd
, dev_data
->devid
, pasid
,
3587 qdep
, address
, size
);
3589 ret
= iommu_queue_command(iommu
, &cmd
);
3594 /* Wait until all device TLBs are flushed */
3595 domain_flush_complete(domain
);
3604 static int __amd_iommu_flush_page(struct protection_domain
*domain
, int pasid
,
3607 INC_STATS_COUNTER(invalidate_iotlb
);
3609 return __flush_pasid(domain
, pasid
, address
, false);
3612 int amd_iommu_flush_page(struct iommu_domain
*dom
, int pasid
,
3615 struct protection_domain
*domain
= to_pdomain(dom
);
3616 unsigned long flags
;
3619 spin_lock_irqsave(&domain
->lock
, flags
);
3620 ret
= __amd_iommu_flush_page(domain
, pasid
, address
);
3621 spin_unlock_irqrestore(&domain
->lock
, flags
);
3625 EXPORT_SYMBOL(amd_iommu_flush_page
);
3627 static int __amd_iommu_flush_tlb(struct protection_domain
*domain
, int pasid
)
3629 INC_STATS_COUNTER(invalidate_iotlb_all
);
3631 return __flush_pasid(domain
, pasid
, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
3635 int amd_iommu_flush_tlb(struct iommu_domain
*dom
, int pasid
)
3637 struct protection_domain
*domain
= to_pdomain(dom
);
3638 unsigned long flags
;
3641 spin_lock_irqsave(&domain
->lock
, flags
);
3642 ret
= __amd_iommu_flush_tlb(domain
, pasid
);
3643 spin_unlock_irqrestore(&domain
->lock
, flags
);
3647 EXPORT_SYMBOL(amd_iommu_flush_tlb
);
3649 static u64
*__get_gcr3_pte(u64
*root
, int level
, int pasid
, bool alloc
)
3656 index
= (pasid
>> (9 * level
)) & 0x1ff;
3662 if (!(*pte
& GCR3_VALID
)) {
3666 root
= (void *)get_zeroed_page(GFP_ATOMIC
);
3670 *pte
= __pa(root
) | GCR3_VALID
;
3673 root
= __va(*pte
& PAGE_MASK
);
3681 static int __set_gcr3(struct protection_domain
*domain
, int pasid
,
3686 if (domain
->mode
!= PAGE_MODE_NONE
)
3689 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, true);
3693 *pte
= (cr3
& PAGE_MASK
) | GCR3_VALID
;
3695 return __amd_iommu_flush_tlb(domain
, pasid
);
3698 static int __clear_gcr3(struct protection_domain
*domain
, int pasid
)
3702 if (domain
->mode
!= PAGE_MODE_NONE
)
3705 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, false);
3711 return __amd_iommu_flush_tlb(domain
, pasid
);
3714 int amd_iommu_domain_set_gcr3(struct iommu_domain
*dom
, int pasid
,
3717 struct protection_domain
*domain
= to_pdomain(dom
);
3718 unsigned long flags
;
3721 spin_lock_irqsave(&domain
->lock
, flags
);
3722 ret
= __set_gcr3(domain
, pasid
, cr3
);
3723 spin_unlock_irqrestore(&domain
->lock
, flags
);
3727 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3
);
3729 int amd_iommu_domain_clear_gcr3(struct iommu_domain
*dom
, int pasid
)
3731 struct protection_domain
*domain
= to_pdomain(dom
);
3732 unsigned long flags
;
3735 spin_lock_irqsave(&domain
->lock
, flags
);
3736 ret
= __clear_gcr3(domain
, pasid
);
3737 spin_unlock_irqrestore(&domain
->lock
, flags
);
3741 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3
);
3743 int amd_iommu_complete_ppr(struct pci_dev
*pdev
, int pasid
,
3744 int status
, int tag
)
3746 struct iommu_dev_data
*dev_data
;
3747 struct amd_iommu
*iommu
;
3748 struct iommu_cmd cmd
;
3750 INC_STATS_COUNTER(complete_ppr
);
3752 dev_data
= get_dev_data(&pdev
->dev
);
3753 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3755 build_complete_ppr(&cmd
, dev_data
->devid
, pasid
, status
,
3756 tag
, dev_data
->pri_tlp
);
3758 return iommu_queue_command(iommu
, &cmd
);
3760 EXPORT_SYMBOL(amd_iommu_complete_ppr
);
3762 struct iommu_domain
*amd_iommu_get_v2_domain(struct pci_dev
*pdev
)
3764 struct protection_domain
*pdomain
;
3766 pdomain
= get_domain(&pdev
->dev
);
3767 if (IS_ERR(pdomain
))
3770 /* Only return IOMMUv2 domains */
3771 if (!(pdomain
->flags
& PD_IOMMUV2_MASK
))
3774 return &pdomain
->domain
;
3776 EXPORT_SYMBOL(amd_iommu_get_v2_domain
);
3778 void amd_iommu_enable_device_erratum(struct pci_dev
*pdev
, u32 erratum
)
3780 struct iommu_dev_data
*dev_data
;
3782 if (!amd_iommu_v2_supported())
3785 dev_data
= get_dev_data(&pdev
->dev
);
3786 dev_data
->errata
|= (1 << erratum
);
3788 EXPORT_SYMBOL(amd_iommu_enable_device_erratum
);
3790 int amd_iommu_device_info(struct pci_dev
*pdev
,
3791 struct amd_iommu_device_info
*info
)
3796 if (pdev
== NULL
|| info
== NULL
)
3799 if (!amd_iommu_v2_supported())
3802 memset(info
, 0, sizeof(*info
));
3804 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ATS
);
3806 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_ATS_SUP
;
3808 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
3810 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRI_SUP
;
3812 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PASID
);
3816 max_pasids
= 1 << (9 * (amd_iommu_max_glx_val
+ 1));
3817 max_pasids
= min(max_pasids
, (1 << 20));
3819 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PASID_SUP
;
3820 info
->max_pasids
= min(pci_max_pasids(pdev
), max_pasids
);
3822 features
= pci_pasid_features(pdev
);
3823 if (features
& PCI_PASID_CAP_EXEC
)
3824 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP
;
3825 if (features
& PCI_PASID_CAP_PRIV
)
3826 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP
;
3831 EXPORT_SYMBOL(amd_iommu_device_info
);
3833 #ifdef CONFIG_IRQ_REMAP
3835 /*****************************************************************************
3837 * Interrupt Remapping Implementation
3839 *****************************************************************************/
3857 u16 devid
; /* Device ID for IRTE table */
3858 u16 index
; /* Index into IRTE table*/
3861 struct amd_ir_data
{
3862 struct irq_2_irte irq_2_irte
;
3863 union irte irte_entry
;
3865 struct msi_msg msi_entry
;
3869 static struct irq_chip amd_ir_chip
;
3871 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3872 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3873 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3874 #define DTE_IRQ_REMAP_ENABLE 1ULL
3876 static void set_dte_irq_entry(u16 devid
, struct irq_remap_table
*table
)
3880 dte
= amd_iommu_dev_table
[devid
].data
[2];
3881 dte
&= ~DTE_IRQ_PHYS_ADDR_MASK
;
3882 dte
|= virt_to_phys(table
->table
);
3883 dte
|= DTE_IRQ_REMAP_INTCTL
;
3884 dte
|= DTE_IRQ_TABLE_LEN
;
3885 dte
|= DTE_IRQ_REMAP_ENABLE
;
3887 amd_iommu_dev_table
[devid
].data
[2] = dte
;
3890 #define IRTE_ALLOCATED (~1U)
3892 static struct irq_remap_table
*get_irq_table(u16 devid
, bool ioapic
)
3894 struct irq_remap_table
*table
= NULL
;
3895 struct amd_iommu
*iommu
;
3896 unsigned long flags
;
3899 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3901 iommu
= amd_iommu_rlookup_table
[devid
];
3905 table
= irq_lookup_table
[devid
];
3909 alias
= amd_iommu_alias_table
[devid
];
3910 table
= irq_lookup_table
[alias
];
3912 irq_lookup_table
[devid
] = table
;
3913 set_dte_irq_entry(devid
, table
);
3914 iommu_flush_dte(iommu
, devid
);
3918 /* Nothing there yet, allocate new irq remapping table */
3919 table
= kzalloc(sizeof(*table
), GFP_ATOMIC
);
3923 /* Initialize table spin-lock */
3924 spin_lock_init(&table
->lock
);
3927 /* Keep the first 32 indexes free for IOAPIC interrupts */
3928 table
->min_index
= 32;
3930 table
->table
= kmem_cache_alloc(amd_iommu_irq_cache
, GFP_ATOMIC
);
3931 if (!table
->table
) {
3937 memset(table
->table
, 0, MAX_IRQS_PER_TABLE
* sizeof(u32
));
3942 for (i
= 0; i
< 32; ++i
)
3943 table
->table
[i
] = IRTE_ALLOCATED
;
3946 irq_lookup_table
[devid
] = table
;
3947 set_dte_irq_entry(devid
, table
);
3948 iommu_flush_dte(iommu
, devid
);
3949 if (devid
!= alias
) {
3950 irq_lookup_table
[alias
] = table
;
3951 set_dte_irq_entry(alias
, table
);
3952 iommu_flush_dte(iommu
, alias
);
3956 iommu_completion_wait(iommu
);
3959 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3964 static int alloc_irq_index(u16 devid
, int count
)
3966 struct irq_remap_table
*table
;
3967 unsigned long flags
;
3970 table
= get_irq_table(devid
, false);
3974 spin_lock_irqsave(&table
->lock
, flags
);
3976 /* Scan table for free entries */
3977 for (c
= 0, index
= table
->min_index
;
3978 index
< MAX_IRQS_PER_TABLE
;
3980 if (table
->table
[index
] == 0)
3987 table
->table
[index
- c
+ 1] = IRTE_ALLOCATED
;
3997 spin_unlock_irqrestore(&table
->lock
, flags
);
4002 static int modify_irte(u16 devid
, int index
, union irte irte
)
4004 struct irq_remap_table
*table
;
4005 struct amd_iommu
*iommu
;
4006 unsigned long flags
;
4008 iommu
= amd_iommu_rlookup_table
[devid
];
4012 table
= get_irq_table(devid
, false);
4016 spin_lock_irqsave(&table
->lock
, flags
);
4017 table
->table
[index
] = irte
.val
;
4018 spin_unlock_irqrestore(&table
->lock
, flags
);
4020 iommu_flush_irt(iommu
, devid
);
4021 iommu_completion_wait(iommu
);
4026 static void free_irte(u16 devid
, int index
)
4028 struct irq_remap_table
*table
;
4029 struct amd_iommu
*iommu
;
4030 unsigned long flags
;
4032 iommu
= amd_iommu_rlookup_table
[devid
];
4036 table
= get_irq_table(devid
, false);
4040 spin_lock_irqsave(&table
->lock
, flags
);
4041 table
->table
[index
] = 0;
4042 spin_unlock_irqrestore(&table
->lock
, flags
);
4044 iommu_flush_irt(iommu
, devid
);
4045 iommu_completion_wait(iommu
);
4048 static int get_devid(struct irq_alloc_info
*info
)
4052 switch (info
->type
) {
4053 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
4054 devid
= get_ioapic_devid(info
->ioapic_id
);
4056 case X86_IRQ_ALLOC_TYPE_HPET
:
4057 devid
= get_hpet_devid(info
->hpet_id
);
4059 case X86_IRQ_ALLOC_TYPE_MSI
:
4060 case X86_IRQ_ALLOC_TYPE_MSIX
:
4061 devid
= get_device_id(&info
->msi_dev
->dev
);
4071 static struct irq_domain
*get_ir_irq_domain(struct irq_alloc_info
*info
)
4073 struct amd_iommu
*iommu
;
4079 devid
= get_devid(info
);
4081 iommu
= amd_iommu_rlookup_table
[devid
];
4083 return iommu
->ir_domain
;
4089 static struct irq_domain
*get_irq_domain(struct irq_alloc_info
*info
)
4091 struct amd_iommu
*iommu
;
4097 switch (info
->type
) {
4098 case X86_IRQ_ALLOC_TYPE_MSI
:
4099 case X86_IRQ_ALLOC_TYPE_MSIX
:
4100 devid
= get_device_id(&info
->msi_dev
->dev
);
4102 iommu
= amd_iommu_rlookup_table
[devid
];
4104 return iommu
->msi_domain
;
4114 struct irq_remap_ops amd_iommu_irq_ops
= {
4115 .prepare
= amd_iommu_prepare
,
4116 .enable
= amd_iommu_enable
,
4117 .disable
= amd_iommu_disable
,
4118 .reenable
= amd_iommu_reenable
,
4119 .enable_faulting
= amd_iommu_enable_faulting
,
4120 .get_ir_irq_domain
= get_ir_irq_domain
,
4121 .get_irq_domain
= get_irq_domain
,
4124 static void irq_remapping_prepare_irte(struct amd_ir_data
*data
,
4125 struct irq_cfg
*irq_cfg
,
4126 struct irq_alloc_info
*info
,
4127 int devid
, int index
, int sub_handle
)
4129 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4130 struct msi_msg
*msg
= &data
->msi_entry
;
4131 union irte
*irte
= &data
->irte_entry
;
4132 struct IO_APIC_route_entry
*entry
;
4134 data
->irq_2_irte
.devid
= devid
;
4135 data
->irq_2_irte
.index
= index
+ sub_handle
;
4137 /* Setup IRTE for IOMMU */
4139 irte
->fields
.vector
= irq_cfg
->vector
;
4140 irte
->fields
.int_type
= apic
->irq_delivery_mode
;
4141 irte
->fields
.destination
= irq_cfg
->dest_apicid
;
4142 irte
->fields
.dm
= apic
->irq_dest_mode
;
4143 irte
->fields
.valid
= 1;
4145 switch (info
->type
) {
4146 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
4147 /* Setup IOAPIC entry */
4148 entry
= info
->ioapic_entry
;
4149 info
->ioapic_entry
= NULL
;
4150 memset(entry
, 0, sizeof(*entry
));
4151 entry
->vector
= index
;
4153 entry
->trigger
= info
->ioapic_trigger
;
4154 entry
->polarity
= info
->ioapic_polarity
;
4155 /* Mask level triggered irqs. */
4156 if (info
->ioapic_trigger
)
4160 case X86_IRQ_ALLOC_TYPE_HPET
:
4161 case X86_IRQ_ALLOC_TYPE_MSI
:
4162 case X86_IRQ_ALLOC_TYPE_MSIX
:
4163 msg
->address_hi
= MSI_ADDR_BASE_HI
;
4164 msg
->address_lo
= MSI_ADDR_BASE_LO
;
4165 msg
->data
= irte_info
->index
;
4174 static int irq_remapping_alloc(struct irq_domain
*domain
, unsigned int virq
,
4175 unsigned int nr_irqs
, void *arg
)
4177 struct irq_alloc_info
*info
= arg
;
4178 struct irq_data
*irq_data
;
4179 struct amd_ir_data
*data
;
4180 struct irq_cfg
*cfg
;
4186 if (nr_irqs
> 1 && info
->type
!= X86_IRQ_ALLOC_TYPE_MSI
&&
4187 info
->type
!= X86_IRQ_ALLOC_TYPE_MSIX
)
4191 * With IRQ remapping enabled, don't need contiguous CPU vectors
4192 * to support multiple MSI interrupts.
4194 if (info
->type
== X86_IRQ_ALLOC_TYPE_MSI
)
4195 info
->flags
&= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS
;
4197 devid
= get_devid(info
);
4201 ret
= irq_domain_alloc_irqs_parent(domain
, virq
, nr_irqs
, arg
);
4206 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
4208 goto out_free_parent
;
4210 if (info
->type
== X86_IRQ_ALLOC_TYPE_IOAPIC
) {
4211 if (get_irq_table(devid
, true))
4212 index
= info
->ioapic_pin
;
4216 index
= alloc_irq_index(devid
, nr_irqs
);
4219 pr_warn("Failed to allocate IRTE\n");
4221 goto out_free_parent
;
4224 for (i
= 0; i
< nr_irqs
; i
++) {
4225 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4226 cfg
= irqd_cfg(irq_data
);
4227 if (!irq_data
|| !cfg
) {
4233 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
4237 irq_data
->hwirq
= (devid
<< 16) + i
;
4238 irq_data
->chip_data
= data
;
4239 irq_data
->chip
= &amd_ir_chip
;
4240 irq_remapping_prepare_irte(data
, cfg
, info
, devid
, index
, i
);
4241 irq_set_status_flags(virq
+ i
, IRQ_MOVE_PCNTXT
);
4246 for (i
--; i
>= 0; i
--) {
4247 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4249 kfree(irq_data
->chip_data
);
4251 for (i
= 0; i
< nr_irqs
; i
++)
4252 free_irte(devid
, index
+ i
);
4254 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4258 static void irq_remapping_free(struct irq_domain
*domain
, unsigned int virq
,
4259 unsigned int nr_irqs
)
4261 struct irq_2_irte
*irte_info
;
4262 struct irq_data
*irq_data
;
4263 struct amd_ir_data
*data
;
4266 for (i
= 0; i
< nr_irqs
; i
++) {
4267 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4268 if (irq_data
&& irq_data
->chip_data
) {
4269 data
= irq_data
->chip_data
;
4270 irte_info
= &data
->irq_2_irte
;
4271 free_irte(irte_info
->devid
, irte_info
->index
);
4275 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4278 static void irq_remapping_activate(struct irq_domain
*domain
,
4279 struct irq_data
*irq_data
)
4281 struct amd_ir_data
*data
= irq_data
->chip_data
;
4282 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4284 modify_irte(irte_info
->devid
, irte_info
->index
, data
->irte_entry
);
4287 static void irq_remapping_deactivate(struct irq_domain
*domain
,
4288 struct irq_data
*irq_data
)
4290 struct amd_ir_data
*data
= irq_data
->chip_data
;
4291 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4295 modify_irte(irte_info
->devid
, irte_info
->index
, data
->irte_entry
);
4298 static struct irq_domain_ops amd_ir_domain_ops
= {
4299 .alloc
= irq_remapping_alloc
,
4300 .free
= irq_remapping_free
,
4301 .activate
= irq_remapping_activate
,
4302 .deactivate
= irq_remapping_deactivate
,
4305 static int amd_ir_set_affinity(struct irq_data
*data
,
4306 const struct cpumask
*mask
, bool force
)
4308 struct amd_ir_data
*ir_data
= data
->chip_data
;
4309 struct irq_2_irte
*irte_info
= &ir_data
->irq_2_irte
;
4310 struct irq_cfg
*cfg
= irqd_cfg(data
);
4311 struct irq_data
*parent
= data
->parent_data
;
4314 ret
= parent
->chip
->irq_set_affinity(parent
, mask
, force
);
4315 if (ret
< 0 || ret
== IRQ_SET_MASK_OK_DONE
)
4319 * Atomically updates the IRTE with the new destination, vector
4320 * and flushes the interrupt entry cache.
4322 ir_data
->irte_entry
.fields
.vector
= cfg
->vector
;
4323 ir_data
->irte_entry
.fields
.destination
= cfg
->dest_apicid
;
4324 modify_irte(irte_info
->devid
, irte_info
->index
, ir_data
->irte_entry
);
4327 * After this point, all the interrupts will start arriving
4328 * at the new destination. So, time to cleanup the previous
4329 * vector allocation.
4331 send_cleanup_vector(cfg
);
4333 return IRQ_SET_MASK_OK_DONE
;
4336 static void ir_compose_msi_msg(struct irq_data
*irq_data
, struct msi_msg
*msg
)
4338 struct amd_ir_data
*ir_data
= irq_data
->chip_data
;
4340 *msg
= ir_data
->msi_entry
;
4343 static struct irq_chip amd_ir_chip
= {
4344 .irq_ack
= ir_ack_apic_edge
,
4345 .irq_set_affinity
= amd_ir_set_affinity
,
4346 .irq_compose_msi_msg
= ir_compose_msi_msg
,
4349 int amd_iommu_create_irq_domain(struct amd_iommu
*iommu
)
4351 iommu
->ir_domain
= irq_domain_add_tree(NULL
, &amd_ir_domain_ops
, iommu
);
4352 if (!iommu
->ir_domain
)
4355 iommu
->ir_domain
->parent
= arch_get_ir_parent_domain();
4356 iommu
->msi_domain
= arch_create_msi_irq_domain(iommu
->ir_domain
);