projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
iommu/amd: Handle large pages correctly in free_pagetable
[deliverable/linux.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <linux/dma-contiguous.h>
37 #include <asm/irq_remapping.h>
38 #include <asm/io_apic.h>
39 #include <asm/apic.h>
40 #include <asm/hw_irq.h>
41 #include <asm/msidef.h>
42 #include <asm/proto.h>
43 #include <asm/iommu.h>
44 #include <asm/gart.h>
45 #include <asm/dma.h>
46
47 #include "amd_iommu_proto.h"
48 #include "amd_iommu_types.h"
49 #include "irq_remapping.h"
50
51 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
52
53 #define LOOP_TIMEOUT 100000
54
55 /*
56 * This bitmap is used to advertise the page sizes our hardware support
57 * to the IOMMU core, which will then use this information to split
58 * physically contiguous memory regions it is mapping into page sizes
59 * that we support.
60 *
61 * 512GB Pages are not supported due to a hardware bug
62 */
63 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
64
65 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
66
67 /* A list of preallocated protection domains */
68 static LIST_HEAD(iommu_pd_list);
69 static DEFINE_SPINLOCK(iommu_pd_list_lock);
70
71 /* List of all available dev_data structures */
72 static LIST_HEAD(dev_data_list);
73 static DEFINE_SPINLOCK(dev_data_list_lock);
74
75 LIST_HEAD(ioapic_map);
76 LIST_HEAD(hpet_map);
77
78 /*
79 * Domain for untranslated devices - only allocated
80 * if iommu=pt passed on kernel cmd line.
81 */
82 static struct protection_domain *pt_domain;
83
84 static const struct iommu_ops amd_iommu_ops;
85
86 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
87 int amd_iommu_max_glx_val = -1;
88
89 static struct dma_map_ops amd_iommu_dma_ops;
90
91 /*
92 * This struct contains device specific data for the IOMMU
93 */
94 struct iommu_dev_data {
95 struct list_head list; /* For domain->dev_list */
96 struct list_head dev_data_list; /* For global dev_data_list */
97 struct list_head alias_list; /* Link alias-groups together */
98 struct iommu_dev_data *alias_data;/* The alias dev_data */
99 struct protection_domain *domain; /* Domain the device is bound to */
100 u16 devid; /* PCI Device ID */
101 bool iommu_v2; /* Device can make use of IOMMUv2 */
102 bool passthrough; /* Default for device is pt_domain */
103 struct {
104 bool enabled;
105 int qdep;
106 } ats; /* ATS state */
107 bool pri_tlp; /* PASID TLB required for
108 PPR completions */
109 u32 errata; /* Bitmap for errata to apply */
110 };
111
112 /*
113 * general struct to manage commands send to an IOMMU
114 */
115 struct iommu_cmd {
116 u32 data[4];
117 };
118
119 struct kmem_cache *amd_iommu_irq_cache;
120
121 static void update_domain(struct protection_domain *domain);
122 static int __init alloc_passthrough_domain(void);
123
124 /****************************************************************************
125 *
126 * Helper functions
127 *
128 ****************************************************************************/
129
130 static struct iommu_dev_data *alloc_dev_data(u16 devid)
131 {
132 struct iommu_dev_data *dev_data;
133 unsigned long flags;
134
135 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
136 if (!dev_data)
137 return NULL;
138
139 INIT_LIST_HEAD(&dev_data->alias_list);
140
141 dev_data->devid = devid;
142
143 spin_lock_irqsave(&dev_data_list_lock, flags);
144 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
145 spin_unlock_irqrestore(&dev_data_list_lock, flags);
146
147 return dev_data;
148 }
149
150 static void free_dev_data(struct iommu_dev_data *dev_data)
151 {
152 unsigned long flags;
153
154 spin_lock_irqsave(&dev_data_list_lock, flags);
155 list_del(&dev_data->dev_data_list);
156 spin_unlock_irqrestore(&dev_data_list_lock, flags);
157
158 kfree(dev_data);
159 }
160
161 static struct iommu_dev_data *search_dev_data(u16 devid)
162 {
163 struct iommu_dev_data *dev_data;
164 unsigned long flags;
165
166 spin_lock_irqsave(&dev_data_list_lock, flags);
167 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
168 if (dev_data->devid == devid)
169 goto out_unlock;
170 }
171
172 dev_data = NULL;
173
174 out_unlock:
175 spin_unlock_irqrestore(&dev_data_list_lock, flags);
176
177 return dev_data;
178 }
179
180 static struct iommu_dev_data *find_dev_data(u16 devid)
181 {
182 struct iommu_dev_data *dev_data;
183
184 dev_data = search_dev_data(devid);
185
186 if (dev_data == NULL)
187 dev_data = alloc_dev_data(devid);
188
189 return dev_data;
190 }
191
192 static inline u16 get_device_id(struct device *dev)
193 {
194 struct pci_dev *pdev = to_pci_dev(dev);
195
196 return PCI_DEVID(pdev->bus->number, pdev->devfn);
197 }
198
199 static struct iommu_dev_data *get_dev_data(struct device *dev)
200 {
201 return dev->archdata.iommu;
202 }
203
204 static bool pci_iommuv2_capable(struct pci_dev *pdev)
205 {
206 static const int caps[] = {
207 PCI_EXT_CAP_ID_ATS,
208 PCI_EXT_CAP_ID_PRI,
209 PCI_EXT_CAP_ID_PASID,
210 };
211 int i, pos;
212
213 for (i = 0; i < 3; ++i) {
214 pos = pci_find_ext_capability(pdev, caps[i]);
215 if (pos == 0)
216 return false;
217 }
218
219 return true;
220 }
221
222 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
223 {
224 struct iommu_dev_data *dev_data;
225
226 dev_data = get_dev_data(&pdev->dev);
227
228 return dev_data->errata & (1 << erratum) ? true : false;
229 }
230
231 /*
232 * In this function the list of preallocated protection domains is traversed to
233 * find the domain for a specific device
234 */
235 static struct dma_ops_domain *find_protection_domain(u16 devid)
236 {
237 struct dma_ops_domain *entry, *ret = NULL;
238 unsigned long flags;
239 u16 alias = amd_iommu_alias_table[devid];
240
241 if (list_empty(&iommu_pd_list))
242 return NULL;
243
244 spin_lock_irqsave(&iommu_pd_list_lock, flags);
245
246 list_for_each_entry(entry, &iommu_pd_list, list) {
247 if (entry->target_dev == devid ||
248 entry->target_dev == alias) {
249 ret = entry;
250 break;
251 }
252 }
253
254 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
255
256 return ret;
257 }
258
259 /*
260 * This function checks if the driver got a valid device from the caller to
261 * avoid dereferencing invalid pointers.
262 */
263 static bool check_device(struct device *dev)
264 {
265 u16 devid;
266
267 if (!dev || !dev->dma_mask)
268 return false;
269
270 /* No PCI device */
271 if (!dev_is_pci(dev))
272 return false;
273
274 devid = get_device_id(dev);
275
276 /* Out of our scope? */
277 if (devid > amd_iommu_last_bdf)
278 return false;
279
280 if (amd_iommu_rlookup_table[devid] == NULL)
281 return false;
282
283 return true;
284 }
285
286 static void init_iommu_group(struct device *dev)
287 {
288 struct iommu_group *group;
289
290 group = iommu_group_get_for_dev(dev);
291 if (!IS_ERR(group))
292 iommu_group_put(group);
293 }
294
295 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
296 {
297 *(u16 *)data = alias;
298 return 0;
299 }
300
301 static u16 get_alias(struct device *dev)
302 {
303 struct pci_dev *pdev = to_pci_dev(dev);
304 u16 devid, ivrs_alias, pci_alias;
305
306 devid = get_device_id(dev);
307 ivrs_alias = amd_iommu_alias_table[devid];
308 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
309
310 if (ivrs_alias == pci_alias)
311 return ivrs_alias;
312
313 /*
314 * DMA alias showdown
315 *
316 * The IVRS is fairly reliable in telling us about aliases, but it
317 * can't know about every screwy device. If we don't have an IVRS
318 * reported alias, use the PCI reported alias. In that case we may
319 * still need to initialize the rlookup and dev_table entries if the
320 * alias is to a non-existent device.
321 */
322 if (ivrs_alias == devid) {
323 if (!amd_iommu_rlookup_table[pci_alias]) {
324 amd_iommu_rlookup_table[pci_alias] =
325 amd_iommu_rlookup_table[devid];
326 memcpy(amd_iommu_dev_table[pci_alias].data,
327 amd_iommu_dev_table[devid].data,
328 sizeof(amd_iommu_dev_table[pci_alias].data));
329 }
330
331 return pci_alias;
332 }
333
334 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
335 "for device %s[%04x:%04x], kernel reported alias "
336 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
337 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
338 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
339 PCI_FUNC(pci_alias));
340
341 /*
342 * If we don't have a PCI DMA alias and the IVRS alias is on the same
343 * bus, then the IVRS table may know about a quirk that we don't.
344 */
345 if (pci_alias == devid &&
346 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
347 pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
348 pdev->dma_alias_devfn = ivrs_alias & 0xff;
349 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
350 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
351 dev_name(dev));
352 }
353
354 return ivrs_alias;
355 }
356
357 static int iommu_init_device(struct device *dev)
358 {
359 struct pci_dev *pdev = to_pci_dev(dev);
360 struct iommu_dev_data *dev_data;
361 u16 alias;
362
363 if (dev->archdata.iommu)
364 return 0;
365
366 dev_data = find_dev_data(get_device_id(dev));
367 if (!dev_data)
368 return -ENOMEM;
369
370 alias = get_alias(dev);
371
372 if (alias != dev_data->devid) {
373 struct iommu_dev_data *alias_data;
374
375 alias_data = find_dev_data(alias);
376 if (alias_data == NULL) {
377 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
378 dev_name(dev));
379 free_dev_data(dev_data);
380 return -ENOTSUPP;
381 }
382 dev_data->alias_data = alias_data;
383
384 /* Add device to the alias_list */
385 list_add(&dev_data->alias_list, &alias_data->alias_list);
386 }
387
388 if (pci_iommuv2_capable(pdev)) {
389 struct amd_iommu *iommu;
390
391 iommu = amd_iommu_rlookup_table[dev_data->devid];
392 dev_data->iommu_v2 = iommu->is_iommu_v2;
393 }
394
395 dev->archdata.iommu = dev_data;
396
397 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
398 dev);
399
400 return 0;
401 }
402
403 static void iommu_ignore_device(struct device *dev)
404 {
405 u16 devid, alias;
406
407 devid = get_device_id(dev);
408 alias = amd_iommu_alias_table[devid];
409
410 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
411 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
412
413 amd_iommu_rlookup_table[devid] = NULL;
414 amd_iommu_rlookup_table[alias] = NULL;
415 }
416
417 static void iommu_uninit_device(struct device *dev)
418 {
419 struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev));
420
421 if (!dev_data)
422 return;
423
424 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
425 dev);
426
427 iommu_group_remove_device(dev);
428
429 /* Unlink from alias, it may change if another device is re-plugged */
430 dev_data->alias_data = NULL;
431
432 /*
433 * We keep dev_data around for unplugged devices and reuse it when the
434 * device is re-plugged - not doing so would introduce a ton of races.
435 */
436 }
437
438 void __init amd_iommu_uninit_devices(void)
439 {
440 struct iommu_dev_data *dev_data, *n;
441 struct pci_dev *pdev = NULL;
442
443 for_each_pci_dev(pdev) {
444
445 if (!check_device(&pdev->dev))
446 continue;
447
448 iommu_uninit_device(&pdev->dev);
449 }
450
451 /* Free all of our dev_data structures */
452 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
453 free_dev_data(dev_data);
454 }
455
456 int __init amd_iommu_init_devices(void)
457 {
458 struct pci_dev *pdev = NULL;
459 int ret = 0;
460
461 for_each_pci_dev(pdev) {
462
463 if (!check_device(&pdev->dev))
464 continue;
465
466 ret = iommu_init_device(&pdev->dev);
467 if (ret == -ENOTSUPP)
468 iommu_ignore_device(&pdev->dev);
469 else if (ret)
470 goto out_free;
471 }
472
473 /*
474 * Initialize IOMMU groups only after iommu_init_device() has
475 * had a chance to populate any IVRS defined aliases.
476 */
477 for_each_pci_dev(pdev) {
478 if (check_device(&pdev->dev))
479 init_iommu_group(&pdev->dev);
480 }
481
482 return 0;
483
484 out_free:
485
486 amd_iommu_uninit_devices();
487
488 return ret;
489 }
490 #ifdef CONFIG_AMD_IOMMU_STATS
491
492 /*
493 * Initialization code for statistics collection
494 */
495
496 DECLARE_STATS_COUNTER(compl_wait);
497 DECLARE_STATS_COUNTER(cnt_map_single);
498 DECLARE_STATS_COUNTER(cnt_unmap_single);
499 DECLARE_STATS_COUNTER(cnt_map_sg);
500 DECLARE_STATS_COUNTER(cnt_unmap_sg);
501 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
502 DECLARE_STATS_COUNTER(cnt_free_coherent);
503 DECLARE_STATS_COUNTER(cross_page);
504 DECLARE_STATS_COUNTER(domain_flush_single);
505 DECLARE_STATS_COUNTER(domain_flush_all);
506 DECLARE_STATS_COUNTER(alloced_io_mem);
507 DECLARE_STATS_COUNTER(total_map_requests);
508 DECLARE_STATS_COUNTER(complete_ppr);
509 DECLARE_STATS_COUNTER(invalidate_iotlb);
510 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
511 DECLARE_STATS_COUNTER(pri_requests);
512
513 static struct dentry *stats_dir;
514 static struct dentry *de_fflush;
515
516 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
517 {
518 if (stats_dir == NULL)
519 return;
520
521 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
522 &cnt->value);
523 }
524
525 static void amd_iommu_stats_init(void)
526 {
527 stats_dir = debugfs_create_dir("amd-iommu", NULL);
528 if (stats_dir == NULL)
529 return;
530
531 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
532 &amd_iommu_unmap_flush);
533
534 amd_iommu_stats_add(&compl_wait);
535 amd_iommu_stats_add(&cnt_map_single);
536 amd_iommu_stats_add(&cnt_unmap_single);
537 amd_iommu_stats_add(&cnt_map_sg);
538 amd_iommu_stats_add(&cnt_unmap_sg);
539 amd_iommu_stats_add(&cnt_alloc_coherent);
540 amd_iommu_stats_add(&cnt_free_coherent);
541 amd_iommu_stats_add(&cross_page);
542 amd_iommu_stats_add(&domain_flush_single);
543 amd_iommu_stats_add(&domain_flush_all);
544 amd_iommu_stats_add(&alloced_io_mem);
545 amd_iommu_stats_add(&total_map_requests);
546 amd_iommu_stats_add(&complete_ppr);
547 amd_iommu_stats_add(&invalidate_iotlb);
548 amd_iommu_stats_add(&invalidate_iotlb_all);
549 amd_iommu_stats_add(&pri_requests);
550 }
551
552 #endif
553
554 /****************************************************************************
555 *
556 * Interrupt handling functions
557 *
558 ****************************************************************************/
559
560 static void dump_dte_entry(u16 devid)
561 {
562 int i;
563
564 for (i = 0; i < 4; ++i)
565 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
566 amd_iommu_dev_table[devid].data[i]);
567 }
568
569 static void dump_command(unsigned long phys_addr)
570 {
571 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
572 int i;
573
574 for (i = 0; i < 4; ++i)
575 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
576 }
577
578 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
579 {
580 int type, devid, domid, flags;
581 volatile u32 *event = __evt;
582 int count = 0;
583 u64 address;
584
585 retry:
586 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
587 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
588 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
589 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
590 address = (u64)(((u64)event[3]) << 32) | event[2];
591
592 if (type == 0) {
593 /* Did we hit the erratum? */
594 if (++count == LOOP_TIMEOUT) {
595 pr_err("AMD-Vi: No event written to event log\n");
596 return;
597 }
598 udelay(1);
599 goto retry;
600 }
601
602 printk(KERN_ERR "AMD-Vi: Event logged [");
603
604 switch (type) {
605 case EVENT_TYPE_ILL_DEV:
606 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
607 "address=0x%016llx flags=0x%04x]\n",
608 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
609 address, flags);
610 dump_dte_entry(devid);
611 break;
612 case EVENT_TYPE_IO_FAULT:
613 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
614 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
615 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
616 domid, address, flags);
617 break;
618 case EVENT_TYPE_DEV_TAB_ERR:
619 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
620 "address=0x%016llx flags=0x%04x]\n",
621 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
622 address, flags);
623 break;
624 case EVENT_TYPE_PAGE_TAB_ERR:
625 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
626 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
627 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
628 domid, address, flags);
629 break;
630 case EVENT_TYPE_ILL_CMD:
631 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
632 dump_command(address);
633 break;
634 case EVENT_TYPE_CMD_HARD_ERR:
635 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
636 "flags=0x%04x]\n", address, flags);
637 break;
638 case EVENT_TYPE_IOTLB_INV_TO:
639 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
640 "address=0x%016llx]\n",
641 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
642 address);
643 break;
644 case EVENT_TYPE_INV_DEV_REQ:
645 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
646 "address=0x%016llx flags=0x%04x]\n",
647 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
648 address, flags);
649 break;
650 default:
651 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
652 }
653
654 memset(__evt, 0, 4 * sizeof(u32));
655 }
656
657 static void iommu_poll_events(struct amd_iommu *iommu)
658 {
659 u32 head, tail;
660
661 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
662 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
663
664 while (head != tail) {
665 iommu_print_event(iommu, iommu->evt_buf + head);
666 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
667 }
668
669 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
670 }
671
672 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
673 {
674 struct amd_iommu_fault fault;
675
676 INC_STATS_COUNTER(pri_requests);
677
678 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
679 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
680 return;
681 }
682
683 fault.address = raw[1];
684 fault.pasid = PPR_PASID(raw[0]);
685 fault.device_id = PPR_DEVID(raw[0]);
686 fault.tag = PPR_TAG(raw[0]);
687 fault.flags = PPR_FLAGS(raw[0]);
688
689 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
690 }
691
692 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
693 {
694 u32 head, tail;
695
696 if (iommu->ppr_log == NULL)
697 return;
698
699 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
700 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
701
702 while (head != tail) {
703 volatile u64 *raw;
704 u64 entry[2];
705 int i;
706
707 raw = (u64 *)(iommu->ppr_log + head);
708
709 /*
710 * Hardware bug: Interrupt may arrive before the entry is
711 * written to memory. If this happens we need to wait for the
712 * entry to arrive.
713 */
714 for (i = 0; i < LOOP_TIMEOUT; ++i) {
715 if (PPR_REQ_TYPE(raw[0]) != 0)
716 break;
717 udelay(1);
718 }
719
720 /* Avoid memcpy function-call overhead */
721 entry[0] = raw[0];
722 entry[1] = raw[1];
723
724 /*
725 * To detect the hardware bug we need to clear the entry
726 * back to zero.
727 */
728 raw[0] = raw[1] = 0UL;
729
730 /* Update head pointer of hardware ring-buffer */
731 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
732 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
733
734 /* Handle PPR entry */
735 iommu_handle_ppr_entry(iommu, entry);
736
737 /* Refresh ring-buffer information */
738 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
739 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
740 }
741 }
742
743 irqreturn_t amd_iommu_int_thread(int irq, void *data)
744 {
745 struct amd_iommu *iommu = (struct amd_iommu *) data;
746 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
747
748 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
749 /* Enable EVT and PPR interrupts again */
750 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
751 iommu->mmio_base + MMIO_STATUS_OFFSET);
752
753 if (status & MMIO_STATUS_EVT_INT_MASK) {
754 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
755 iommu_poll_events(iommu);
756 }
757
758 if (status & MMIO_STATUS_PPR_INT_MASK) {
759 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
760 iommu_poll_ppr_log(iommu);
761 }
762
763 /*
764 * Hardware bug: ERBT1312
765 * When re-enabling interrupt (by writing 1
766 * to clear the bit), the hardware might also try to set
767 * the interrupt bit in the event status register.
768 * In this scenario, the bit will be set, and disable
769 * subsequent interrupts.
770 *
771 * Workaround: The IOMMU driver should read back the
772 * status register and check if the interrupt bits are cleared.
773 * If not, driver will need to go through the interrupt handler
774 * again and re-clear the bits
775 */
776 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
777 }
778 return IRQ_HANDLED;
779 }
780
781 irqreturn_t amd_iommu_int_handler(int irq, void *data)
782 {
783 return IRQ_WAKE_THREAD;
784 }
785
786 /****************************************************************************
787 *
788 * IOMMU command queuing functions
789 *
790 ****************************************************************************/
791
792 static int wait_on_sem(volatile u64 *sem)
793 {
794 int i = 0;
795
796 while (*sem == 0 && i < LOOP_TIMEOUT) {
797 udelay(1);
798 i += 1;
799 }
800
801 if (i == LOOP_TIMEOUT) {
802 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
803 return -EIO;
804 }
805
806 return 0;
807 }
808
809 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
810 struct iommu_cmd *cmd,
811 u32 tail)
812 {
813 u8 *target;
814
815 target = iommu->cmd_buf + tail;
816 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
817
818 /* Copy command to buffer */
819 memcpy(target, cmd, sizeof(*cmd));
820
821 /* Tell the IOMMU about it */
822 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
823 }
824
825 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
826 {
827 WARN_ON(address & 0x7ULL);
828
829 memset(cmd, 0, sizeof(*cmd));
830 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
831 cmd->data[1] = upper_32_bits(__pa(address));
832 cmd->data[2] = 1;
833 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
834 }
835
836 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
837 {
838 memset(cmd, 0, sizeof(*cmd));
839 cmd->data[0] = devid;
840 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
841 }
842
843 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
844 size_t size, u16 domid, int pde)
845 {
846 u64 pages;
847 bool s;
848
849 pages = iommu_num_pages(address, size, PAGE_SIZE);
850 s = false;
851
852 if (pages > 1) {
853 /*
854 * If we have to flush more than one page, flush all
855 * TLB entries for this domain
856 */
857 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
858 s = true;
859 }
860
861 address &= PAGE_MASK;
862
863 memset(cmd, 0, sizeof(*cmd));
864 cmd->data[1] |= domid;
865 cmd->data[2] = lower_32_bits(address);
866 cmd->data[3] = upper_32_bits(address);
867 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
868 if (s) /* size bit - we flush more than one 4kb page */
869 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
870 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
871 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
872 }
873
874 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
875 u64 address, size_t size)
876 {
877 u64 pages;
878 bool s;
879
880 pages = iommu_num_pages(address, size, PAGE_SIZE);
881 s = false;
882
883 if (pages > 1) {
884 /*
885 * If we have to flush more than one page, flush all
886 * TLB entries for this domain
887 */
888 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
889 s = true;
890 }
891
892 address &= PAGE_MASK;
893
894 memset(cmd, 0, sizeof(*cmd));
895 cmd->data[0] = devid;
896 cmd->data[0] |= (qdep & 0xff) << 24;
897 cmd->data[1] = devid;
898 cmd->data[2] = lower_32_bits(address);
899 cmd->data[3] = upper_32_bits(address);
900 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
901 if (s)
902 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
903 }
904
905 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
906 u64 address, bool size)
907 {
908 memset(cmd, 0, sizeof(*cmd));
909
910 address &= ~(0xfffULL);
911
912 cmd->data[0] = pasid;
913 cmd->data[1] = domid;
914 cmd->data[2] = lower_32_bits(address);
915 cmd->data[3] = upper_32_bits(address);
916 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
917 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
918 if (size)
919 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
920 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
921 }
922
923 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
924 int qdep, u64 address, bool size)
925 {
926 memset(cmd, 0, sizeof(*cmd));
927
928 address &= ~(0xfffULL);
929
930 cmd->data[0] = devid;
931 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
932 cmd->data[0] |= (qdep & 0xff) << 24;
933 cmd->data[1] = devid;
934 cmd->data[1] |= (pasid & 0xff) << 16;
935 cmd->data[2] = lower_32_bits(address);
936 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
937 cmd->data[3] = upper_32_bits(address);
938 if (size)
939 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
940 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
941 }
942
943 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
944 int status, int tag, bool gn)
945 {
946 memset(cmd, 0, sizeof(*cmd));
947
948 cmd->data[0] = devid;
949 if (gn) {
950 cmd->data[1] = pasid;
951 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
952 }
953 cmd->data[3] = tag & 0x1ff;
954 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
955
956 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
957 }
958
959 static void build_inv_all(struct iommu_cmd *cmd)
960 {
961 memset(cmd, 0, sizeof(*cmd));
962 CMD_SET_TYPE(cmd, CMD_INV_ALL);
963 }
964
965 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
966 {
967 memset(cmd, 0, sizeof(*cmd));
968 cmd->data[0] = devid;
969 CMD_SET_TYPE(cmd, CMD_INV_IRT);
970 }
971
972 /*
973 * Writes the command to the IOMMUs command buffer and informs the
974 * hardware about the new command.
975 */
976 static int iommu_queue_command_sync(struct amd_iommu *iommu,
977 struct iommu_cmd *cmd,
978 bool sync)
979 {
980 u32 left, tail, head, next_tail;
981 unsigned long flags;
982
983 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
984
985 again:
986 spin_lock_irqsave(&iommu->lock, flags);
987
988 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
989 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
990 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
991 left = (head - next_tail) % iommu->cmd_buf_size;
992
993 if (left <= 2) {
994 struct iommu_cmd sync_cmd;
995 volatile u64 sem = 0;
996 int ret;
997
998 build_completion_wait(&sync_cmd, (u64)&sem);
999 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
1000
1001 spin_unlock_irqrestore(&iommu->lock, flags);
1002
1003 if ((ret = wait_on_sem(&sem)) != 0)
1004 return ret;
1005
1006 goto again;
1007 }
1008
1009 copy_cmd_to_buffer(iommu, cmd, tail);
1010
1011 /* We need to sync now to make sure all commands are processed */
1012 iommu->need_sync = sync;
1013
1014 spin_unlock_irqrestore(&iommu->lock, flags);
1015
1016 return 0;
1017 }
1018
1019 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1020 {
1021 return iommu_queue_command_sync(iommu, cmd, true);
1022 }
1023
1024 /*
1025 * This function queues a completion wait command into the command
1026 * buffer of an IOMMU
1027 */
1028 static int iommu_completion_wait(struct amd_iommu *iommu)
1029 {
1030 struct iommu_cmd cmd;
1031 volatile u64 sem = 0;
1032 int ret;
1033
1034 if (!iommu->need_sync)
1035 return 0;
1036
1037 build_completion_wait(&cmd, (u64)&sem);
1038
1039 ret = iommu_queue_command_sync(iommu, &cmd, false);
1040 if (ret)
1041 return ret;
1042
1043 return wait_on_sem(&sem);
1044 }
1045
1046 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1047 {
1048 struct iommu_cmd cmd;
1049
1050 build_inv_dte(&cmd, devid);
1051
1052 return iommu_queue_command(iommu, &cmd);
1053 }
1054
1055 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1056 {
1057 u32 devid;
1058
1059 for (devid = 0; devid <= 0xffff; ++devid)
1060 iommu_flush_dte(iommu, devid);
1061
1062 iommu_completion_wait(iommu);
1063 }
1064
1065 /*
1066 * This function uses heavy locking and may disable irqs for some time. But
1067 * this is no issue because it is only called during resume.
1068 */
1069 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1070 {
1071 u32 dom_id;
1072
1073 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1074 struct iommu_cmd cmd;
1075 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1076 dom_id, 1);
1077 iommu_queue_command(iommu, &cmd);
1078 }
1079
1080 iommu_completion_wait(iommu);
1081 }
1082
1083 static void iommu_flush_all(struct amd_iommu *iommu)
1084 {
1085 struct iommu_cmd cmd;
1086
1087 build_inv_all(&cmd);
1088
1089 iommu_queue_command(iommu, &cmd);
1090 iommu_completion_wait(iommu);
1091 }
1092
1093 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1094 {
1095 struct iommu_cmd cmd;
1096
1097 build_inv_irt(&cmd, devid);
1098
1099 iommu_queue_command(iommu, &cmd);
1100 }
1101
1102 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1103 {
1104 u32 devid;
1105
1106 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1107 iommu_flush_irt(iommu, devid);
1108
1109 iommu_completion_wait(iommu);
1110 }
1111
1112 void iommu_flush_all_caches(struct amd_iommu *iommu)
1113 {
1114 if (iommu_feature(iommu, FEATURE_IA)) {
1115 iommu_flush_all(iommu);
1116 } else {
1117 iommu_flush_dte_all(iommu);
1118 iommu_flush_irt_all(iommu);
1119 iommu_flush_tlb_all(iommu);
1120 }
1121 }
1122
1123 /*
1124 * Command send function for flushing on-device TLB
1125 */
1126 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1127 u64 address, size_t size)
1128 {
1129 struct amd_iommu *iommu;
1130 struct iommu_cmd cmd;
1131 int qdep;
1132
1133 qdep = dev_data->ats.qdep;
1134 iommu = amd_iommu_rlookup_table[dev_data->devid];
1135
1136 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1137
1138 return iommu_queue_command(iommu, &cmd);
1139 }
1140
1141 /*
1142 * Command send function for invalidating a device table entry
1143 */
1144 static int device_flush_dte(struct iommu_dev_data *dev_data)
1145 {
1146 struct amd_iommu *iommu;
1147 int ret;
1148
1149 iommu = amd_iommu_rlookup_table[dev_data->devid];
1150
1151 ret = iommu_flush_dte(iommu, dev_data->devid);
1152 if (ret)
1153 return ret;
1154
1155 if (dev_data->ats.enabled)
1156 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1157
1158 return ret;
1159 }
1160
1161 /*
1162 * TLB invalidation function which is called from the mapping functions.
1163 * It invalidates a single PTE if the range to flush is within a single
1164 * page. Otherwise it flushes the whole TLB of the IOMMU.
1165 */
1166 static void __domain_flush_pages(struct protection_domain *domain,
1167 u64 address, size_t size, int pde)
1168 {
1169 struct iommu_dev_data *dev_data;
1170 struct iommu_cmd cmd;
1171 int ret = 0, i;
1172
1173 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1174
1175 for (i = 0; i < amd_iommus_present; ++i) {
1176 if (!domain->dev_iommu[i])
1177 continue;
1178
1179 /*
1180 * Devices of this domain are behind this IOMMU
1181 * We need a TLB flush
1182 */
1183 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1184 }
1185
1186 list_for_each_entry(dev_data, &domain->dev_list, list) {
1187
1188 if (!dev_data->ats.enabled)
1189 continue;
1190
1191 ret |= device_flush_iotlb(dev_data, address, size);
1192 }
1193
1194 WARN_ON(ret);
1195 }
1196
1197 static void domain_flush_pages(struct protection_domain *domain,
1198 u64 address, size_t size)
1199 {
1200 __domain_flush_pages(domain, address, size, 0);
1201 }
1202
1203 /* Flush the whole IO/TLB for a given protection domain */
1204 static void domain_flush_tlb(struct protection_domain *domain)
1205 {
1206 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1207 }
1208
1209 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1210 static void domain_flush_tlb_pde(struct protection_domain *domain)
1211 {
1212 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1213 }
1214
1215 static void domain_flush_complete(struct protection_domain *domain)
1216 {
1217 int i;
1218
1219 for (i = 0; i < amd_iommus_present; ++i) {
1220 if (!domain->dev_iommu[i])
1221 continue;
1222
1223 /*
1224 * Devices of this domain are behind this IOMMU
1225 * We need to wait for completion of all commands.
1226 */
1227 iommu_completion_wait(amd_iommus[i]);
1228 }
1229 }
1230
1231
1232 /*
1233 * This function flushes the DTEs for all devices in domain
1234 */
1235 static void domain_flush_devices(struct protection_domain *domain)
1236 {
1237 struct iommu_dev_data *dev_data;
1238
1239 list_for_each_entry(dev_data, &domain->dev_list, list)
1240 device_flush_dte(dev_data);
1241 }
1242
1243 /****************************************************************************
1244 *
1245 * The functions below are used the create the page table mappings for
1246 * unity mapped regions.
1247 *
1248 ****************************************************************************/
1249
1250 /*
1251 * This function is used to add another level to an IO page table. Adding
1252 * another level increases the size of the address space by 9 bits to a size up
1253 * to 64 bits.
1254 */
1255 static bool increase_address_space(struct protection_domain *domain,
1256 gfp_t gfp)
1257 {
1258 u64 *pte;
1259
1260 if (domain->mode == PAGE_MODE_6_LEVEL)
1261 /* address space already 64 bit large */
1262 return false;
1263
1264 pte = (void *)get_zeroed_page(gfp);
1265 if (!pte)
1266 return false;
1267
1268 *pte = PM_LEVEL_PDE(domain->mode,
1269 virt_to_phys(domain->pt_root));
1270 domain->pt_root = pte;
1271 domain->mode += 1;
1272 domain->updated = true;
1273
1274 return true;
1275 }
1276
1277 static u64 *alloc_pte(struct protection_domain *domain,
1278 unsigned long address,
1279 unsigned long page_size,
1280 u64 **pte_page,
1281 gfp_t gfp)
1282 {
1283 int level, end_lvl;
1284 u64 *pte, *page;
1285
1286 BUG_ON(!is_power_of_2(page_size));
1287
1288 while (address > PM_LEVEL_SIZE(domain->mode))
1289 increase_address_space(domain, gfp);
1290
1291 level = domain->mode - 1;
1292 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1293 address = PAGE_SIZE_ALIGN(address, page_size);
1294 end_lvl = PAGE_SIZE_LEVEL(page_size);
1295
1296 while (level > end_lvl) {
1297 if (!IOMMU_PTE_PRESENT(*pte)) {
1298 page = (u64 *)get_zeroed_page(gfp);
1299 if (!page)
1300 return NULL;
1301 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1302 }
1303
1304 /* No level skipping support yet */
1305 if (PM_PTE_LEVEL(*pte) != level)
1306 return NULL;
1307
1308 level -= 1;
1309
1310 pte = IOMMU_PTE_PAGE(*pte);
1311
1312 if (pte_page && level == end_lvl)
1313 *pte_page = pte;
1314
1315 pte = &pte[PM_LEVEL_INDEX(level, address)];
1316 }
1317
1318 return pte;
1319 }
1320
1321 /*
1322 * This function checks if there is a PTE for a given dma address. If
1323 * there is one, it returns the pointer to it.
1324 */
1325 static u64 *fetch_pte(struct protection_domain *domain,
1326 unsigned long address,
1327 unsigned long *page_size)
1328 {
1329 int level;
1330 u64 *pte;
1331
1332 if (address > PM_LEVEL_SIZE(domain->mode))
1333 return NULL;
1334
1335 level = domain->mode - 1;
1336 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1337 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1338
1339 while (level > 0) {
1340
1341 /* Not Present */
1342 if (!IOMMU_PTE_PRESENT(*pte))
1343 return NULL;
1344
1345 /* Large PTE */
1346 if (PM_PTE_LEVEL(*pte) == 7 ||
1347 PM_PTE_LEVEL(*pte) == 0)
1348 break;
1349
1350 /* No level skipping support yet */
1351 if (PM_PTE_LEVEL(*pte) != level)
1352 return NULL;
1353
1354 level -= 1;
1355
1356 /* Walk to the next level */
1357 pte = IOMMU_PTE_PAGE(*pte);
1358 pte = &pte[PM_LEVEL_INDEX(level, address)];
1359 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1360 }
1361
1362 if (PM_PTE_LEVEL(*pte) == 0x07) {
1363 unsigned long pte_mask;
1364
1365 /*
1366 * If we have a series of large PTEs, make
1367 * sure to return a pointer to the first one.
1368 */
1369 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1370 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1371 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1372 }
1373
1374 return pte;
1375 }
1376
1377 /*
1378 * Generic mapping functions. It maps a physical address into a DMA
1379 * address space. It allocates the page table pages if necessary.
1380 * In the future it can be extended to a generic mapping function
1381 * supporting all features of AMD IOMMU page tables like level skipping
1382 * and full 64 bit address spaces.
1383 */
1384 static int iommu_map_page(struct protection_domain *dom,
1385 unsigned long bus_addr,
1386 unsigned long phys_addr,
1387 int prot,
1388 unsigned long page_size)
1389 {
1390 u64 __pte, *pte;
1391 int i, count;
1392
1393 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1394 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1395
1396 if (!(prot & IOMMU_PROT_MASK))
1397 return -EINVAL;
1398
1399 count = PAGE_SIZE_PTE_COUNT(page_size);
1400 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1401
1402 if (!pte)
1403 return -ENOMEM;
1404
1405 for (i = 0; i < count; ++i)
1406 if (IOMMU_PTE_PRESENT(pte[i]))
1407 return -EBUSY;
1408
1409 if (count > 1) {
1410 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1411 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1412 } else
1413 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1414
1415 if (prot & IOMMU_PROT_IR)
1416 __pte |= IOMMU_PTE_IR;
1417 if (prot & IOMMU_PROT_IW)
1418 __pte |= IOMMU_PTE_IW;
1419
1420 for (i = 0; i < count; ++i)
1421 pte[i] = __pte;
1422
1423 update_domain(dom);
1424
1425 return 0;
1426 }
1427
1428 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1429 unsigned long bus_addr,
1430 unsigned long page_size)
1431 {
1432 unsigned long long unmapped;
1433 unsigned long unmap_size;
1434 u64 *pte;
1435
1436 BUG_ON(!is_power_of_2(page_size));
1437
1438 unmapped = 0;
1439
1440 while (unmapped < page_size) {
1441
1442 pte = fetch_pte(dom, bus_addr, &unmap_size);
1443
1444 if (pte) {
1445 int i, count;
1446
1447 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1448 for (i = 0; i < count; i++)
1449 pte[i] = 0ULL;
1450 }
1451
1452 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1453 unmapped += unmap_size;
1454 }
1455
1456 BUG_ON(unmapped && !is_power_of_2(unmapped));
1457
1458 return unmapped;
1459 }
1460
1461 /*
1462 * This function checks if a specific unity mapping entry is needed for
1463 * this specific IOMMU.
1464 */
1465 static int iommu_for_unity_map(struct amd_iommu *iommu,
1466 struct unity_map_entry *entry)
1467 {
1468 u16 bdf, i;
1469
1470 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1471 bdf = amd_iommu_alias_table[i];
1472 if (amd_iommu_rlookup_table[bdf] == iommu)
1473 return 1;
1474 }
1475
1476 return 0;
1477 }
1478
1479 /*
1480 * This function actually applies the mapping to the page table of the
1481 * dma_ops domain.
1482 */
1483 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1484 struct unity_map_entry *e)
1485 {
1486 u64 addr;
1487 int ret;
1488
1489 for (addr = e->address_start; addr < e->address_end;
1490 addr += PAGE_SIZE) {
1491 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1492 PAGE_SIZE);
1493 if (ret)
1494 return ret;
1495 /*
1496 * if unity mapping is in aperture range mark the page
1497 * as allocated in the aperture
1498 */
1499 if (addr < dma_dom->aperture_size)
1500 __set_bit(addr >> PAGE_SHIFT,
1501 dma_dom->aperture[0]->bitmap);
1502 }
1503
1504 return 0;
1505 }
1506
1507 /*
1508 * Init the unity mappings for a specific IOMMU in the system
1509 *
1510 * Basically iterates over all unity mapping entries and applies them to
1511 * the default domain DMA of that IOMMU if necessary.
1512 */
1513 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1514 {
1515 struct unity_map_entry *entry;
1516 int ret;
1517
1518 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1519 if (!iommu_for_unity_map(iommu, entry))
1520 continue;
1521 ret = dma_ops_unity_map(iommu->default_dom, entry);
1522 if (ret)
1523 return ret;
1524 }
1525
1526 return 0;
1527 }
1528
1529 /*
1530 * Inits the unity mappings required for a specific device
1531 */
1532 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1533 u16 devid)
1534 {
1535 struct unity_map_entry *e;
1536 int ret;
1537
1538 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1539 if (!(devid >= e->devid_start && devid <= e->devid_end))
1540 continue;
1541 ret = dma_ops_unity_map(dma_dom, e);
1542 if (ret)
1543 return ret;
1544 }
1545
1546 return 0;
1547 }
1548
1549 /****************************************************************************
1550 *
1551 * The next functions belong to the address allocator for the dma_ops
1552 * interface functions. They work like the allocators in the other IOMMU
1553 * drivers. Its basically a bitmap which marks the allocated pages in
1554 * the aperture. Maybe it could be enhanced in the future to a more
1555 * efficient allocator.
1556 *
1557 ****************************************************************************/
1558
1559 /*
1560 * The address allocator core functions.
1561 *
1562 * called with domain->lock held
1563 */
1564
1565 /*
1566 * Used to reserve address ranges in the aperture (e.g. for exclusion
1567 * ranges.
1568 */
1569 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1570 unsigned long start_page,
1571 unsigned int pages)
1572 {
1573 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1574
1575 if (start_page + pages > last_page)
1576 pages = last_page - start_page;
1577
1578 for (i = start_page; i < start_page + pages; ++i) {
1579 int index = i / APERTURE_RANGE_PAGES;
1580 int page = i % APERTURE_RANGE_PAGES;
1581 __set_bit(page, dom->aperture[index]->bitmap);
1582 }
1583 }
1584
1585 /*
1586 * This function is used to add a new aperture range to an existing
1587 * aperture in case of dma_ops domain allocation or address allocation
1588 * failure.
1589 */
1590 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1591 bool populate, gfp_t gfp)
1592 {
1593 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1594 struct amd_iommu *iommu;
1595 unsigned long i, old_size, pte_pgsize;
1596
1597 #ifdef CONFIG_IOMMU_STRESS
1598 populate = false;
1599 #endif
1600
1601 if (index >= APERTURE_MAX_RANGES)
1602 return -ENOMEM;
1603
1604 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1605 if (!dma_dom->aperture[index])
1606 return -ENOMEM;
1607
1608 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1609 if (!dma_dom->aperture[index]->bitmap)
1610 goto out_free;
1611
1612 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1613
1614 if (populate) {
1615 unsigned long address = dma_dom->aperture_size;
1616 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1617 u64 *pte, *pte_page;
1618
1619 for (i = 0; i < num_ptes; ++i) {
1620 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1621 &pte_page, gfp);
1622 if (!pte)
1623 goto out_free;
1624
1625 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1626
1627 address += APERTURE_RANGE_SIZE / 64;
1628 }
1629 }
1630
1631 old_size = dma_dom->aperture_size;
1632 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1633
1634 /* Reserve address range used for MSI messages */
1635 if (old_size < MSI_ADDR_BASE_LO &&
1636 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1637 unsigned long spage;
1638 int pages;
1639
1640 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1641 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1642
1643 dma_ops_reserve_addresses(dma_dom, spage, pages);
1644 }
1645
1646 /* Initialize the exclusion range if necessary */
1647 for_each_iommu(iommu) {
1648 if (iommu->exclusion_start &&
1649 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1650 && iommu->exclusion_start < dma_dom->aperture_size) {
1651 unsigned long startpage;
1652 int pages = iommu_num_pages(iommu->exclusion_start,
1653 iommu->exclusion_length,
1654 PAGE_SIZE);
1655 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1656 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1657 }
1658 }
1659
1660 /*
1661 * Check for areas already mapped as present in the new aperture
1662 * range and mark those pages as reserved in the allocator. Such
1663 * mappings may already exist as a result of requested unity
1664 * mappings for devices.
1665 */
1666 for (i = dma_dom->aperture[index]->offset;
1667 i < dma_dom->aperture_size;
1668 i += pte_pgsize) {
1669 u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize);
1670 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1671 continue;
1672
1673 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT,
1674 pte_pgsize >> 12);
1675 }
1676
1677 update_domain(&dma_dom->domain);
1678
1679 return 0;
1680
1681 out_free:
1682 update_domain(&dma_dom->domain);
1683
1684 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1685
1686 kfree(dma_dom->aperture[index]);
1687 dma_dom->aperture[index] = NULL;
1688
1689 return -ENOMEM;
1690 }
1691
1692 static unsigned long dma_ops_area_alloc(struct device *dev,
1693 struct dma_ops_domain *dom,
1694 unsigned int pages,
1695 unsigned long align_mask,
1696 u64 dma_mask,
1697 unsigned long start)
1698 {
1699 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1700 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1701 int i = start >> APERTURE_RANGE_SHIFT;
1702 unsigned long boundary_size, mask;
1703 unsigned long address = -1;
1704 unsigned long limit;
1705
1706 next_bit >>= PAGE_SHIFT;
1707
1708 mask = dma_get_seg_boundary(dev);
1709
1710 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
1711 1UL << (BITS_PER_LONG - PAGE_SHIFT);
1712
1713 for (;i < max_index; ++i) {
1714 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1715
1716 if (dom->aperture[i]->offset >= dma_mask)
1717 break;
1718
1719 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1720 dma_mask >> PAGE_SHIFT);
1721
1722 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1723 limit, next_bit, pages, 0,
1724 boundary_size, align_mask);
1725 if (address != -1) {
1726 address = dom->aperture[i]->offset +
1727 (address << PAGE_SHIFT);
1728 dom->next_address = address + (pages << PAGE_SHIFT);
1729 break;
1730 }
1731
1732 next_bit = 0;
1733 }
1734
1735 return address;
1736 }
1737
1738 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1739 struct dma_ops_domain *dom,
1740 unsigned int pages,
1741 unsigned long align_mask,
1742 u64 dma_mask)
1743 {
1744 unsigned long address;
1745
1746 #ifdef CONFIG_IOMMU_STRESS
1747 dom->next_address = 0;
1748 dom->need_flush = true;
1749 #endif
1750
1751 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1752 dma_mask, dom->next_address);
1753
1754 if (address == -1) {
1755 dom->next_address = 0;
1756 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1757 dma_mask, 0);
1758 dom->need_flush = true;
1759 }
1760
1761 if (unlikely(address == -1))
1762 address = DMA_ERROR_CODE;
1763
1764 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1765
1766 return address;
1767 }
1768
1769 /*
1770 * The address free function.
1771 *
1772 * called with domain->lock held
1773 */
1774 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1775 unsigned long address,
1776 unsigned int pages)
1777 {
1778 unsigned i = address >> APERTURE_RANGE_SHIFT;
1779 struct aperture_range *range = dom->aperture[i];
1780
1781 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1782
1783 #ifdef CONFIG_IOMMU_STRESS
1784 if (i < 4)
1785 return;
1786 #endif
1787
1788 if (address >= dom->next_address)
1789 dom->need_flush = true;
1790
1791 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1792
1793 bitmap_clear(range->bitmap, address, pages);
1794
1795 }
1796
1797 /****************************************************************************
1798 *
1799 * The next functions belong to the domain allocation. A domain is
1800 * allocated for every IOMMU as the default domain. If device isolation
1801 * is enabled, every device get its own domain. The most important thing
1802 * about domains is the page table mapping the DMA address space they
1803 * contain.
1804 *
1805 ****************************************************************************/
1806
1807 /*
1808 * This function adds a protection domain to the global protection domain list
1809 */
1810 static void add_domain_to_list(struct protection_domain *domain)
1811 {
1812 unsigned long flags;
1813
1814 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1815 list_add(&domain->list, &amd_iommu_pd_list);
1816 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1817 }
1818
1819 /*
1820 * This function removes a protection domain to the global
1821 * protection domain list
1822 */
1823 static void del_domain_from_list(struct protection_domain *domain)
1824 {
1825 unsigned long flags;
1826
1827 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1828 list_del(&domain->list);
1829 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1830 }
1831
1832 static u16 domain_id_alloc(void)
1833 {
1834 unsigned long flags;
1835 int id;
1836
1837 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1838 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1839 BUG_ON(id == 0);
1840 if (id > 0 && id < MAX_DOMAIN_ID)
1841 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1842 else
1843 id = 0;
1844 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1845
1846 return id;
1847 }
1848
1849 static void domain_id_free(int id)
1850 {
1851 unsigned long flags;
1852
1853 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1854 if (id > 0 && id < MAX_DOMAIN_ID)
1855 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1856 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1857 }
1858
1859 #define DEFINE_FREE_PT_FN(LVL, FN) \
1860 static void free_pt_##LVL (unsigned long __pt) \
1861 { \
1862 unsigned long p; \
1863 u64 *pt; \
1864 int i; \
1865 \
1866 pt = (u64 *)__pt; \
1867 \
1868 for (i = 0; i < 512; ++i) { \
1869 /* PTE present? */ \
1870 if (!IOMMU_PTE_PRESENT(pt[i])) \
1871 continue; \
1872 \
1873 /* Large PTE? */ \
1874 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1875 PM_PTE_LEVEL(pt[i]) == 7) \
1876 continue; \
1877 \
1878 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1879 FN(p); \
1880 } \
1881 free_page((unsigned long)pt); \
1882 }
1883
1884 DEFINE_FREE_PT_FN(l2, free_page)
1885 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1886 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1887 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1888 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1889
1890 static void free_pagetable(struct protection_domain *domain)
1891 {
1892 unsigned long root = (unsigned long)domain->pt_root;
1893
1894 switch (domain->mode) {
1895 case PAGE_MODE_NONE:
1896 break;
1897 case PAGE_MODE_1_LEVEL:
1898 free_page(root);
1899 break;
1900 case PAGE_MODE_2_LEVEL:
1901 free_pt_l2(root);
1902 break;
1903 case PAGE_MODE_3_LEVEL:
1904 free_pt_l3(root);
1905 break;
1906 case PAGE_MODE_4_LEVEL:
1907 free_pt_l4(root);
1908 break;
1909 case PAGE_MODE_5_LEVEL:
1910 free_pt_l5(root);
1911 break;
1912 case PAGE_MODE_6_LEVEL:
1913 free_pt_l6(root);
1914 break;
1915 default:
1916 BUG();
1917 }
1918 }
1919
1920 static void free_gcr3_tbl_level1(u64 *tbl)
1921 {
1922 u64 *ptr;
1923 int i;
1924
1925 for (i = 0; i < 512; ++i) {
1926 if (!(tbl[i] & GCR3_VALID))
1927 continue;
1928
1929 ptr = __va(tbl[i] & PAGE_MASK);
1930
1931 free_page((unsigned long)ptr);
1932 }
1933 }
1934
1935 static void free_gcr3_tbl_level2(u64 *tbl)
1936 {
1937 u64 *ptr;
1938 int i;
1939
1940 for (i = 0; i < 512; ++i) {
1941 if (!(tbl[i] & GCR3_VALID))
1942 continue;
1943
1944 ptr = __va(tbl[i] & PAGE_MASK);
1945
1946 free_gcr3_tbl_level1(ptr);
1947 }
1948 }
1949
1950 static void free_gcr3_table(struct protection_domain *domain)
1951 {
1952 if (domain->glx == 2)
1953 free_gcr3_tbl_level2(domain->gcr3_tbl);
1954 else if (domain->glx == 1)
1955 free_gcr3_tbl_level1(domain->gcr3_tbl);
1956 else if (domain->glx != 0)
1957 BUG();
1958
1959 free_page((unsigned long)domain->gcr3_tbl);
1960 }
1961
1962 /*
1963 * Free a domain, only used if something went wrong in the
1964 * allocation path and we need to free an already allocated page table
1965 */
1966 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1967 {
1968 int i;
1969
1970 if (!dom)
1971 return;
1972
1973 del_domain_from_list(&dom->domain);
1974
1975 free_pagetable(&dom->domain);
1976
1977 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1978 if (!dom->aperture[i])
1979 continue;
1980 free_page((unsigned long)dom->aperture[i]->bitmap);
1981 kfree(dom->aperture[i]);
1982 }
1983
1984 kfree(dom);
1985 }
1986
1987 /*
1988 * Allocates a new protection domain usable for the dma_ops functions.
1989 * It also initializes the page table and the address allocator data
1990 * structures required for the dma_ops interface
1991 */
1992 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1993 {
1994 struct dma_ops_domain *dma_dom;
1995
1996 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1997 if (!dma_dom)
1998 return NULL;
1999
2000 spin_lock_init(&dma_dom->domain.lock);
2001
2002 dma_dom->domain.id = domain_id_alloc();
2003 if (dma_dom->domain.id == 0)
2004 goto free_dma_dom;
2005 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
2006 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
2007 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2008 dma_dom->domain.flags = PD_DMA_OPS_MASK;
2009 dma_dom->domain.priv = dma_dom;
2010 if (!dma_dom->domain.pt_root)
2011 goto free_dma_dom;
2012
2013 dma_dom->need_flush = false;
2014 dma_dom->target_dev = 0xffff;
2015
2016 add_domain_to_list(&dma_dom->domain);
2017
2018 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
2019 goto free_dma_dom;
2020
2021 /*
2022 * mark the first page as allocated so we never return 0 as
2023 * a valid dma-address. So we can use 0 as error value
2024 */
2025 dma_dom->aperture[0]->bitmap[0] = 1;
2026 dma_dom->next_address = 0;
2027
2028
2029 return dma_dom;
2030
2031 free_dma_dom:
2032 dma_ops_domain_free(dma_dom);
2033
2034 return NULL;
2035 }
2036
2037 /*
2038 * little helper function to check whether a given protection domain is a
2039 * dma_ops domain
2040 */
2041 static bool dma_ops_domain(struct protection_domain *domain)
2042 {
2043 return domain->flags & PD_DMA_OPS_MASK;
2044 }
2045
2046 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
2047 {
2048 u64 pte_root = 0;
2049 u64 flags = 0;
2050
2051 if (domain->mode != PAGE_MODE_NONE)
2052 pte_root = virt_to_phys(domain->pt_root);
2053
2054 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2055 << DEV_ENTRY_MODE_SHIFT;
2056 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
2057
2058 flags = amd_iommu_dev_table[devid].data[1];
2059
2060 if (ats)
2061 flags |= DTE_FLAG_IOTLB;
2062
2063 if (domain->flags & PD_IOMMUV2_MASK) {
2064 u64 gcr3 = __pa(domain->gcr3_tbl);
2065 u64 glx = domain->glx;
2066 u64 tmp;
2067
2068 pte_root |= DTE_FLAG_GV;
2069 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2070
2071 /* First mask out possible old values for GCR3 table */
2072 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2073 flags &= ~tmp;
2074
2075 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2076 flags &= ~tmp;
2077
2078 /* Encode GCR3 table into DTE */
2079 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2080 pte_root |= tmp;
2081
2082 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2083 flags |= tmp;
2084
2085 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2086 flags |= tmp;
2087 }
2088
2089 flags &= ~(0xffffUL);
2090 flags |= domain->id;
2091
2092 amd_iommu_dev_table[devid].data[1] = flags;
2093 amd_iommu_dev_table[devid].data[0] = pte_root;
2094 }
2095
2096 static void clear_dte_entry(u16 devid)
2097 {
2098 /* remove entry from the device table seen by the hardware */
2099 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2100 amd_iommu_dev_table[devid].data[1] = 0;
2101
2102 amd_iommu_apply_erratum_63(devid);
2103 }
2104
2105 static void do_attach(struct iommu_dev_data *dev_data,
2106 struct protection_domain *domain)
2107 {
2108 struct amd_iommu *iommu;
2109 bool ats;
2110
2111 iommu = amd_iommu_rlookup_table[dev_data->devid];
2112 ats = dev_data->ats.enabled;
2113
2114 /* Update data structures */
2115 dev_data->domain = domain;
2116 list_add(&dev_data->list, &domain->dev_list);
2117 set_dte_entry(dev_data->devid, domain, ats);
2118
2119 /* Do reference counting */
2120 domain->dev_iommu[iommu->index] += 1;
2121 domain->dev_cnt += 1;
2122
2123 /* Flush the DTE entry */
2124 device_flush_dte(dev_data);
2125 }
2126
2127 static void do_detach(struct iommu_dev_data *dev_data)
2128 {
2129 struct amd_iommu *iommu;
2130
2131 iommu = amd_iommu_rlookup_table[dev_data->devid];
2132
2133 /* decrease reference counters */
2134 dev_data->domain->dev_iommu[iommu->index] -= 1;
2135 dev_data->domain->dev_cnt -= 1;
2136
2137 /* Update data structures */
2138 dev_data->domain = NULL;
2139 list_del(&dev_data->list);
2140 clear_dte_entry(dev_data->devid);
2141
2142 /* Flush the DTE entry */
2143 device_flush_dte(dev_data);
2144 }
2145
2146 /*
2147 * If a device is not yet associated with a domain, this function does
2148 * assigns it visible for the hardware
2149 */
2150 static int __attach_device(struct iommu_dev_data *dev_data,
2151 struct protection_domain *domain)
2152 {
2153 struct iommu_dev_data *head, *entry;
2154 int ret;
2155
2156 /* lock domain */
2157 spin_lock(&domain->lock);
2158
2159 head = dev_data;
2160
2161 if (head->alias_data != NULL)
2162 head = head->alias_data;
2163
2164 /* Now we have the root of the alias group, if any */
2165
2166 ret = -EBUSY;
2167 if (head->domain != NULL)
2168 goto out_unlock;
2169
2170 /* Attach alias group root */
2171 do_attach(head, domain);
2172
2173 /* Attach other devices in the alias group */
2174 list_for_each_entry(entry, &head->alias_list, alias_list)
2175 do_attach(entry, domain);
2176
2177 ret = 0;
2178
2179 out_unlock:
2180
2181 /* ready */
2182 spin_unlock(&domain->lock);
2183
2184 return ret;
2185 }
2186
2187
2188 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2189 {
2190 pci_disable_ats(pdev);
2191 pci_disable_pri(pdev);
2192 pci_disable_pasid(pdev);
2193 }
2194
2195 /* FIXME: Change generic reset-function to do the same */
2196 static int pri_reset_while_enabled(struct pci_dev *pdev)
2197 {
2198 u16 control;
2199 int pos;
2200
2201 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2202 if (!pos)
2203 return -EINVAL;
2204
2205 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2206 control |= PCI_PRI_CTRL_RESET;
2207 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2208
2209 return 0;
2210 }
2211
2212 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2213 {
2214 bool reset_enable;
2215 int reqs, ret;
2216
2217 /* FIXME: Hardcode number of outstanding requests for now */
2218 reqs = 32;
2219 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2220 reqs = 1;
2221 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2222
2223 /* Only allow access to user-accessible pages */
2224 ret = pci_enable_pasid(pdev, 0);
2225 if (ret)
2226 goto out_err;
2227
2228 /* First reset the PRI state of the device */
2229 ret = pci_reset_pri(pdev);
2230 if (ret)
2231 goto out_err;
2232
2233 /* Enable PRI */
2234 ret = pci_enable_pri(pdev, reqs);
2235 if (ret)
2236 goto out_err;
2237
2238 if (reset_enable) {
2239 ret = pri_reset_while_enabled(pdev);
2240 if (ret)
2241 goto out_err;
2242 }
2243
2244 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2245 if (ret)
2246 goto out_err;
2247
2248 return 0;
2249
2250 out_err:
2251 pci_disable_pri(pdev);
2252 pci_disable_pasid(pdev);
2253
2254 return ret;
2255 }
2256
2257 /* FIXME: Move this to PCI code */
2258 #define PCI_PRI_TLP_OFF (1 << 15)
2259
2260 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2261 {
2262 u16 status;
2263 int pos;
2264
2265 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2266 if (!pos)
2267 return false;
2268
2269 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2270
2271 return (status & PCI_PRI_TLP_OFF) ? true : false;
2272 }
2273
2274 /*
2275 * If a device is not yet associated with a domain, this function
2276 * assigns it visible for the hardware
2277 */
2278 static int attach_device(struct device *dev,
2279 struct protection_domain *domain)
2280 {
2281 struct pci_dev *pdev = to_pci_dev(dev);
2282 struct iommu_dev_data *dev_data;
2283 unsigned long flags;
2284 int ret;
2285
2286 dev_data = get_dev_data(dev);
2287
2288 if (domain->flags & PD_IOMMUV2_MASK) {
2289 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2290 return -EINVAL;
2291
2292 if (pdev_iommuv2_enable(pdev) != 0)
2293 return -EINVAL;
2294
2295 dev_data->ats.enabled = true;
2296 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2297 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2298 } else if (amd_iommu_iotlb_sup &&
2299 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2300 dev_data->ats.enabled = true;
2301 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2302 }
2303
2304 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2305 ret = __attach_device(dev_data, domain);
2306 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2307
2308 /*
2309 * We might boot into a crash-kernel here. The crashed kernel
2310 * left the caches in the IOMMU dirty. So we have to flush
2311 * here to evict all dirty stuff.
2312 */
2313 domain_flush_tlb_pde(domain);
2314
2315 return ret;
2316 }
2317
2318 /*
2319 * Removes a device from a protection domain (unlocked)
2320 */
2321 static void __detach_device(struct iommu_dev_data *dev_data)
2322 {
2323 struct iommu_dev_data *head, *entry;
2324 struct protection_domain *domain;
2325 unsigned long flags;
2326
2327 BUG_ON(!dev_data->domain);
2328
2329 domain = dev_data->domain;
2330
2331 spin_lock_irqsave(&domain->lock, flags);
2332
2333 head = dev_data;
2334 if (head->alias_data != NULL)
2335 head = head->alias_data;
2336
2337 list_for_each_entry(entry, &head->alias_list, alias_list)
2338 do_detach(entry);
2339
2340 do_detach(head);
2341
2342 spin_unlock_irqrestore(&domain->lock, flags);
2343
2344 /*
2345 * If we run in passthrough mode the device must be assigned to the
2346 * passthrough domain if it is detached from any other domain.
2347 * Make sure we can deassign from the pt_domain itself.
2348 */
2349 if (dev_data->passthrough &&
2350 (dev_data->domain == NULL && domain != pt_domain))
2351 __attach_device(dev_data, pt_domain);
2352 }
2353
2354 /*
2355 * Removes a device from a protection domain (with devtable_lock held)
2356 */
2357 static void detach_device(struct device *dev)
2358 {
2359 struct protection_domain *domain;
2360 struct iommu_dev_data *dev_data;
2361 unsigned long flags;
2362
2363 dev_data = get_dev_data(dev);
2364 domain = dev_data->domain;
2365
2366 /* lock device table */
2367 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2368 __detach_device(dev_data);
2369 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2370
2371 if (domain->flags & PD_IOMMUV2_MASK)
2372 pdev_iommuv2_disable(to_pci_dev(dev));
2373 else if (dev_data->ats.enabled)
2374 pci_disable_ats(to_pci_dev(dev));
2375
2376 dev_data->ats.enabled = false;
2377 }
2378
2379 /*
2380 * Find out the protection domain structure for a given PCI device. This
2381 * will give us the pointer to the page table root for example.
2382 */
2383 static struct protection_domain *domain_for_device(struct device *dev)
2384 {
2385 struct iommu_dev_data *dev_data;
2386 struct protection_domain *dom = NULL;
2387 unsigned long flags;
2388
2389 dev_data = get_dev_data(dev);
2390
2391 if (dev_data->domain)
2392 return dev_data->domain;
2393
2394 if (dev_data->alias_data != NULL) {
2395 struct iommu_dev_data *alias_data = dev_data->alias_data;
2396
2397 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2398 if (alias_data->domain != NULL) {
2399 __attach_device(dev_data, alias_data->domain);
2400 dom = alias_data->domain;
2401 }
2402 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2403 }
2404
2405 return dom;
2406 }
2407
2408 static int device_change_notifier(struct notifier_block *nb,
2409 unsigned long action, void *data)
2410 {
2411 struct dma_ops_domain *dma_domain;
2412 struct protection_domain *domain;
2413 struct iommu_dev_data *dev_data;
2414 struct device *dev = data;
2415 struct amd_iommu *iommu;
2416 unsigned long flags;
2417 u16 devid;
2418
2419 if (!check_device(dev))
2420 return 0;
2421
2422 devid = get_device_id(dev);
2423 iommu = amd_iommu_rlookup_table[devid];
2424 dev_data = get_dev_data(dev);
2425
2426 switch (action) {
2427 case BUS_NOTIFY_ADD_DEVICE:
2428
2429 iommu_init_device(dev);
2430 init_iommu_group(dev);
2431
2432 /*
2433 * dev_data is still NULL and
2434 * got initialized in iommu_init_device
2435 */
2436 dev_data = get_dev_data(dev);
2437
2438 if (iommu_pass_through || dev_data->iommu_v2) {
2439 dev_data->passthrough = true;
2440 attach_device(dev, pt_domain);
2441 break;
2442 }
2443
2444 domain = domain_for_device(dev);
2445
2446 /* allocate a protection domain if a device is added */
2447 dma_domain = find_protection_domain(devid);
2448 if (!dma_domain) {
2449 dma_domain = dma_ops_domain_alloc();
2450 if (!dma_domain)
2451 goto out;
2452 dma_domain->target_dev = devid;
2453
2454 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2455 list_add_tail(&dma_domain->list, &iommu_pd_list);
2456 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2457 }
2458
2459 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2460
2461 break;
2462 case BUS_NOTIFY_REMOVED_DEVICE:
2463
2464 iommu_uninit_device(dev);
2465
2466 default:
2467 goto out;
2468 }
2469
2470 iommu_completion_wait(iommu);
2471
2472 out:
2473 return 0;
2474 }
2475
2476 static struct notifier_block device_nb = {
2477 .notifier_call = device_change_notifier,
2478 };
2479
2480 void amd_iommu_init_notifier(void)
2481 {
2482 bus_register_notifier(&pci_bus_type, &device_nb);
2483 }
2484
2485 /*****************************************************************************
2486 *
2487 * The next functions belong to the dma_ops mapping/unmapping code.
2488 *
2489 *****************************************************************************/
2490
2491 /*
2492 * In the dma_ops path we only have the struct device. This function
2493 * finds the corresponding IOMMU, the protection domain and the
2494 * requestor id for a given device.
2495 * If the device is not yet associated with a domain this is also done
2496 * in this function.
2497 */
2498 static struct protection_domain *get_domain(struct device *dev)
2499 {
2500 struct protection_domain *domain;
2501 struct dma_ops_domain *dma_dom;
2502 u16 devid = get_device_id(dev);
2503
2504 if (!check_device(dev))
2505 return ERR_PTR(-EINVAL);
2506
2507 domain = domain_for_device(dev);
2508 if (domain != NULL && !dma_ops_domain(domain))
2509 return ERR_PTR(-EBUSY);
2510
2511 if (domain != NULL)
2512 return domain;
2513
2514 /* Device not bound yet - bind it */
2515 dma_dom = find_protection_domain(devid);
2516 if (!dma_dom)
2517 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2518 attach_device(dev, &dma_dom->domain);
2519 DUMP_printk("Using protection domain %d for device %s\n",
2520 dma_dom->domain.id, dev_name(dev));
2521
2522 return &dma_dom->domain;
2523 }
2524
2525 static void update_device_table(struct protection_domain *domain)
2526 {
2527 struct iommu_dev_data *dev_data;
2528
2529 list_for_each_entry(dev_data, &domain->dev_list, list)
2530 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2531 }
2532
2533 static void update_domain(struct protection_domain *domain)
2534 {
2535 if (!domain->updated)
2536 return;
2537
2538 update_device_table(domain);
2539
2540 domain_flush_devices(domain);
2541 domain_flush_tlb_pde(domain);
2542
2543 domain->updated = false;
2544 }
2545
2546 /*
2547 * This function fetches the PTE for a given address in the aperture
2548 */
2549 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2550 unsigned long address)
2551 {
2552 struct aperture_range *aperture;
2553 u64 *pte, *pte_page;
2554
2555 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2556 if (!aperture)
2557 return NULL;
2558
2559 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2560 if (!pte) {
2561 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2562 GFP_ATOMIC);
2563 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2564 } else
2565 pte += PM_LEVEL_INDEX(0, address);
2566
2567 update_domain(&dom->domain);
2568
2569 return pte;
2570 }
2571
2572 /*
2573 * This is the generic map function. It maps one 4kb page at paddr to
2574 * the given address in the DMA address space for the domain.
2575 */
2576 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2577 unsigned long address,
2578 phys_addr_t paddr,
2579 int direction)
2580 {
2581 u64 *pte, __pte;
2582
2583 WARN_ON(address > dom->aperture_size);
2584
2585 paddr &= PAGE_MASK;
2586
2587 pte = dma_ops_get_pte(dom, address);
2588 if (!pte)
2589 return DMA_ERROR_CODE;
2590
2591 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2592
2593 if (direction == DMA_TO_DEVICE)
2594 __pte |= IOMMU_PTE_IR;
2595 else if (direction == DMA_FROM_DEVICE)
2596 __pte |= IOMMU_PTE_IW;
2597 else if (direction == DMA_BIDIRECTIONAL)
2598 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2599
2600 WARN_ON(*pte);
2601
2602 *pte = __pte;
2603
2604 return (dma_addr_t)address;
2605 }
2606
2607 /*
2608 * The generic unmapping function for on page in the DMA address space.
2609 */
2610 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2611 unsigned long address)
2612 {
2613 struct aperture_range *aperture;
2614 u64 *pte;
2615
2616 if (address >= dom->aperture_size)
2617 return;
2618
2619 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2620 if (!aperture)
2621 return;
2622
2623 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2624 if (!pte)
2625 return;
2626
2627 pte += PM_LEVEL_INDEX(0, address);
2628
2629 WARN_ON(!*pte);
2630
2631 *pte = 0ULL;
2632 }
2633
2634 /*
2635 * This function contains common code for mapping of a physically
2636 * contiguous memory region into DMA address space. It is used by all
2637 * mapping functions provided with this IOMMU driver.
2638 * Must be called with the domain lock held.
2639 */
2640 static dma_addr_t __map_single(struct device *dev,
2641 struct dma_ops_domain *dma_dom,
2642 phys_addr_t paddr,
2643 size_t size,
2644 int dir,
2645 bool align,
2646 u64 dma_mask)
2647 {
2648 dma_addr_t offset = paddr & ~PAGE_MASK;
2649 dma_addr_t address, start, ret;
2650 unsigned int pages;
2651 unsigned long align_mask = 0;
2652 int i;
2653
2654 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2655 paddr &= PAGE_MASK;
2656
2657 INC_STATS_COUNTER(total_map_requests);
2658
2659 if (pages > 1)
2660 INC_STATS_COUNTER(cross_page);
2661
2662 if (align)
2663 align_mask = (1UL << get_order(size)) - 1;
2664
2665 retry:
2666 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2667 dma_mask);
2668 if (unlikely(address == DMA_ERROR_CODE)) {
2669 /*
2670 * setting next_address here will let the address
2671 * allocator only scan the new allocated range in the
2672 * first run. This is a small optimization.
2673 */
2674 dma_dom->next_address = dma_dom->aperture_size;
2675
2676 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2677 goto out;
2678
2679 /*
2680 * aperture was successfully enlarged by 128 MB, try
2681 * allocation again
2682 */
2683 goto retry;
2684 }
2685
2686 start = address;
2687 for (i = 0; i < pages; ++i) {
2688 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2689 if (ret == DMA_ERROR_CODE)
2690 goto out_unmap;
2691
2692 paddr += PAGE_SIZE;
2693 start += PAGE_SIZE;
2694 }
2695 address += offset;
2696
2697 ADD_STATS_COUNTER(alloced_io_mem, size);
2698
2699 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2700 domain_flush_tlb(&dma_dom->domain);
2701 dma_dom->need_flush = false;
2702 } else if (unlikely(amd_iommu_np_cache))
2703 domain_flush_pages(&dma_dom->domain, address, size);
2704
2705 out:
2706 return address;
2707
2708 out_unmap:
2709
2710 for (--i; i >= 0; --i) {
2711 start -= PAGE_SIZE;
2712 dma_ops_domain_unmap(dma_dom, start);
2713 }
2714
2715 dma_ops_free_addresses(dma_dom, address, pages);
2716
2717 return DMA_ERROR_CODE;
2718 }
2719
2720 /*
2721 * Does the reverse of the __map_single function. Must be called with
2722 * the domain lock held too
2723 */
2724 static void __unmap_single(struct dma_ops_domain *dma_dom,
2725 dma_addr_t dma_addr,
2726 size_t size,
2727 int dir)
2728 {
2729 dma_addr_t flush_addr;
2730 dma_addr_t i, start;
2731 unsigned int pages;
2732
2733 if ((dma_addr == DMA_ERROR_CODE) ||
2734 (dma_addr + size > dma_dom->aperture_size))
2735 return;
2736
2737 flush_addr = dma_addr;
2738 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2739 dma_addr &= PAGE_MASK;
2740 start = dma_addr;
2741
2742 for (i = 0; i < pages; ++i) {
2743 dma_ops_domain_unmap(dma_dom, start);
2744 start += PAGE_SIZE;
2745 }
2746
2747 SUB_STATS_COUNTER(alloced_io_mem, size);
2748
2749 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2750
2751 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2752 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2753 dma_dom->need_flush = false;
2754 }
2755 }
2756
2757 /*
2758 * The exported map_single function for dma_ops.
2759 */
2760 static dma_addr_t map_page(struct device *dev, struct page *page,
2761 unsigned long offset, size_t size,
2762 enum dma_data_direction dir,
2763 struct dma_attrs *attrs)
2764 {
2765 unsigned long flags;
2766 struct protection_domain *domain;
2767 dma_addr_t addr;
2768 u64 dma_mask;
2769 phys_addr_t paddr = page_to_phys(page) + offset;
2770
2771 INC_STATS_COUNTER(cnt_map_single);
2772
2773 domain = get_domain(dev);
2774 if (PTR_ERR(domain) == -EINVAL)
2775 return (dma_addr_t)paddr;
2776 else if (IS_ERR(domain))
2777 return DMA_ERROR_CODE;
2778
2779 dma_mask = *dev->dma_mask;
2780
2781 spin_lock_irqsave(&domain->lock, flags);
2782
2783 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2784 dma_mask);
2785 if (addr == DMA_ERROR_CODE)
2786 goto out;
2787
2788 domain_flush_complete(domain);
2789
2790 out:
2791 spin_unlock_irqrestore(&domain->lock, flags);
2792
2793 return addr;
2794 }
2795
2796 /*
2797 * The exported unmap_single function for dma_ops.
2798 */
2799 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2800 enum dma_data_direction dir, struct dma_attrs *attrs)
2801 {
2802 unsigned long flags;
2803 struct protection_domain *domain;
2804
2805 INC_STATS_COUNTER(cnt_unmap_single);
2806
2807 domain = get_domain(dev);
2808 if (IS_ERR(domain))
2809 return;
2810
2811 spin_lock_irqsave(&domain->lock, flags);
2812
2813 __unmap_single(domain->priv, dma_addr, size, dir);
2814
2815 domain_flush_complete(domain);
2816
2817 spin_unlock_irqrestore(&domain->lock, flags);
2818 }
2819
2820 /*
2821 * The exported map_sg function for dma_ops (handles scatter-gather
2822 * lists).
2823 */
2824 static int map_sg(struct device *dev, struct scatterlist *sglist,
2825 int nelems, enum dma_data_direction dir,
2826 struct dma_attrs *attrs)
2827 {
2828 unsigned long flags;
2829 struct protection_domain *domain;
2830 int i;
2831 struct scatterlist *s;
2832 phys_addr_t paddr;
2833 int mapped_elems = 0;
2834 u64 dma_mask;
2835
2836 INC_STATS_COUNTER(cnt_map_sg);
2837
2838 domain = get_domain(dev);
2839 if (IS_ERR(domain))
2840 return 0;
2841
2842 dma_mask = *dev->dma_mask;
2843
2844 spin_lock_irqsave(&domain->lock, flags);
2845
2846 for_each_sg(sglist, s, nelems, i) {
2847 paddr = sg_phys(s);
2848
2849 s->dma_address = __map_single(dev, domain->priv,
2850 paddr, s->length, dir, false,
2851 dma_mask);
2852
2853 if (s->dma_address) {
2854 s->dma_length = s->length;
2855 mapped_elems++;
2856 } else
2857 goto unmap;
2858 }
2859
2860 domain_flush_complete(domain);
2861
2862 out:
2863 spin_unlock_irqrestore(&domain->lock, flags);
2864
2865 return mapped_elems;
2866 unmap:
2867 for_each_sg(sglist, s, mapped_elems, i) {
2868 if (s->dma_address)
2869 __unmap_single(domain->priv, s->dma_address,
2870 s->dma_length, dir);
2871 s->dma_address = s->dma_length = 0;
2872 }
2873
2874 mapped_elems = 0;
2875
2876 goto out;
2877 }
2878
2879 /*
2880 * The exported map_sg function for dma_ops (handles scatter-gather
2881 * lists).
2882 */
2883 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2884 int nelems, enum dma_data_direction dir,
2885 struct dma_attrs *attrs)
2886 {
2887 unsigned long flags;
2888 struct protection_domain *domain;
2889 struct scatterlist *s;
2890 int i;
2891
2892 INC_STATS_COUNTER(cnt_unmap_sg);
2893
2894 domain = get_domain(dev);
2895 if (IS_ERR(domain))
2896 return;
2897
2898 spin_lock_irqsave(&domain->lock, flags);
2899
2900 for_each_sg(sglist, s, nelems, i) {
2901 __unmap_single(domain->priv, s->dma_address,
2902 s->dma_length, dir);
2903 s->dma_address = s->dma_length = 0;
2904 }
2905
2906 domain_flush_complete(domain);
2907
2908 spin_unlock_irqrestore(&domain->lock, flags);
2909 }
2910
2911 /*
2912 * The exported alloc_coherent function for dma_ops.
2913 */
2914 static void *alloc_coherent(struct device *dev, size_t size,
2915 dma_addr_t *dma_addr, gfp_t flag,
2916 struct dma_attrs *attrs)
2917 {
2918 u64 dma_mask = dev->coherent_dma_mask;
2919 struct protection_domain *domain;
2920 unsigned long flags;
2921 struct page *page;
2922
2923 INC_STATS_COUNTER(cnt_alloc_coherent);
2924
2925 domain = get_domain(dev);
2926 if (PTR_ERR(domain) == -EINVAL) {
2927 page = alloc_pages(flag, get_order(size));
2928 *dma_addr = page_to_phys(page);
2929 return page_address(page);
2930 } else if (IS_ERR(domain))
2931 return NULL;
2932
2933 size = PAGE_ALIGN(size);
2934 dma_mask = dev->coherent_dma_mask;
2935 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2936
2937 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2938 if (!page) {
2939 if (!(flag & __GFP_WAIT))
2940 return NULL;
2941
2942 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2943 get_order(size));
2944 if (!page)
2945 return NULL;
2946 }
2947
2948 if (!dma_mask)
2949 dma_mask = *dev->dma_mask;
2950
2951 spin_lock_irqsave(&domain->lock, flags);
2952
2953 *dma_addr = __map_single(dev, domain->priv, page_to_phys(page),
2954 size, DMA_BIDIRECTIONAL, true, dma_mask);
2955
2956 if (*dma_addr == DMA_ERROR_CODE) {
2957 spin_unlock_irqrestore(&domain->lock, flags);
2958 goto out_free;
2959 }
2960
2961 domain_flush_complete(domain);
2962
2963 spin_unlock_irqrestore(&domain->lock, flags);
2964
2965 return page_address(page);
2966
2967 out_free:
2968
2969 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2970 __free_pages(page, get_order(size));
2971
2972 return NULL;
2973 }
2974
2975 /*
2976 * The exported free_coherent function for dma_ops.
2977 */
2978 static void free_coherent(struct device *dev, size_t size,
2979 void *virt_addr, dma_addr_t dma_addr,
2980 struct dma_attrs *attrs)
2981 {
2982 struct protection_domain *domain;
2983 unsigned long flags;
2984 struct page *page;
2985
2986 INC_STATS_COUNTER(cnt_free_coherent);
2987
2988 page = virt_to_page(virt_addr);
2989 size = PAGE_ALIGN(size);
2990
2991 domain = get_domain(dev);
2992 if (IS_ERR(domain))
2993 goto free_mem;
2994
2995 spin_lock_irqsave(&domain->lock, flags);
2996
2997 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2998
2999 domain_flush_complete(domain);
3000
3001 spin_unlock_irqrestore(&domain->lock, flags);
3002
3003 free_mem:
3004 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3005 __free_pages(page, get_order(size));
3006 }
3007
3008 /*
3009 * This function is called by the DMA layer to find out if we can handle a
3010 * particular device. It is part of the dma_ops.
3011 */
3012 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
3013 {
3014 return check_device(dev);
3015 }
3016
3017 /*
3018 * The function for pre-allocating protection domains.
3019 *
3020 * If the driver core informs the DMA layer if a driver grabs a device
3021 * we don't need to preallocate the protection domains anymore.
3022 * For now we have to.
3023 */
3024 static void __init prealloc_protection_domains(void)
3025 {
3026 struct iommu_dev_data *dev_data;
3027 struct dma_ops_domain *dma_dom;
3028 struct pci_dev *dev = NULL;
3029 u16 devid;
3030
3031 for_each_pci_dev(dev) {
3032
3033 /* Do we handle this device? */
3034 if (!check_device(&dev->dev))
3035 continue;
3036
3037 dev_data = get_dev_data(&dev->dev);
3038 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
3039 /* Make sure passthrough domain is allocated */
3040 alloc_passthrough_domain();
3041 dev_data->passthrough = true;
3042 attach_device(&dev->dev, pt_domain);
3043 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
3044 dev_name(&dev->dev));
3045 }
3046
3047 /* Is there already any domain for it? */
3048 if (domain_for_device(&dev->dev))
3049 continue;
3050
3051 devid = get_device_id(&dev->dev);
3052
3053 dma_dom = dma_ops_domain_alloc();
3054 if (!dma_dom)
3055 continue;
3056 init_unity_mappings_for_device(dma_dom, devid);
3057 dma_dom->target_dev = devid;
3058
3059 attach_device(&dev->dev, &dma_dom->domain);
3060
3061 list_add_tail(&dma_dom->list, &iommu_pd_list);
3062 }
3063 }
3064
3065 static struct dma_map_ops amd_iommu_dma_ops = {
3066 .alloc = alloc_coherent,
3067 .free = free_coherent,
3068 .map_page = map_page,
3069 .unmap_page = unmap_page,
3070 .map_sg = map_sg,
3071 .unmap_sg = unmap_sg,
3072 .dma_supported = amd_iommu_dma_supported,
3073 };
3074
3075 static unsigned device_dma_ops_init(void)
3076 {
3077 struct iommu_dev_data *dev_data;
3078 struct pci_dev *pdev = NULL;
3079 unsigned unhandled = 0;
3080
3081 for_each_pci_dev(pdev) {
3082 if (!check_device(&pdev->dev)) {
3083
3084 iommu_ignore_device(&pdev->dev);
3085
3086 unhandled += 1;
3087 continue;
3088 }
3089
3090 dev_data = get_dev_data(&pdev->dev);
3091
3092 if (!dev_data->passthrough)
3093 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
3094 else
3095 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
3096 }
3097
3098 return unhandled;
3099 }
3100
3101 /*
3102 * The function which clues the AMD IOMMU driver into dma_ops.
3103 */
3104
3105 void __init amd_iommu_init_api(void)
3106 {
3107 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
3108 }
3109
3110 int __init amd_iommu_init_dma_ops(void)
3111 {
3112 struct amd_iommu *iommu;
3113 int ret, unhandled;
3114
3115 /*
3116 * first allocate a default protection domain for every IOMMU we
3117 * found in the system. Devices not assigned to any other
3118 * protection domain will be assigned to the default one.
3119 */
3120 for_each_iommu(iommu) {
3121 iommu->default_dom = dma_ops_domain_alloc();
3122 if (iommu->default_dom == NULL)
3123 return -ENOMEM;
3124 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
3125 ret = iommu_init_unity_mappings(iommu);
3126 if (ret)
3127 goto free_domains;
3128 }
3129
3130 /*
3131 * Pre-allocate the protection domains for each device.
3132 */
3133 prealloc_protection_domains();
3134
3135 iommu_detected = 1;
3136 swiotlb = 0;
3137
3138 /* Make the driver finally visible to the drivers */
3139 unhandled = device_dma_ops_init();
3140 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3141 /* There are unhandled devices - initialize swiotlb for them */
3142 swiotlb = 1;
3143 }
3144
3145 amd_iommu_stats_init();
3146
3147 if (amd_iommu_unmap_flush)
3148 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3149 else
3150 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3151
3152 return 0;
3153
3154 free_domains:
3155
3156 for_each_iommu(iommu) {
3157 dma_ops_domain_free(iommu->default_dom);
3158 }
3159
3160 return ret;
3161 }
3162
3163 /*****************************************************************************
3164 *
3165 * The following functions belong to the exported interface of AMD IOMMU
3166 *
3167 * This interface allows access to lower level functions of the IOMMU
3168 * like protection domain handling and assignement of devices to domains
3169 * which is not possible with the dma_ops interface.
3170 *
3171 *****************************************************************************/
3172
3173 static void cleanup_domain(struct protection_domain *domain)
3174 {
3175 struct iommu_dev_data *entry;
3176 unsigned long flags;
3177
3178 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3179
3180 while (!list_empty(&domain->dev_list)) {
3181 entry = list_first_entry(&domain->dev_list,
3182 struct iommu_dev_data, list);
3183 __detach_device(entry);
3184 }
3185
3186 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3187 }
3188
3189 static void protection_domain_free(struct protection_domain *domain)
3190 {
3191 if (!domain)
3192 return;
3193
3194 del_domain_from_list(domain);
3195
3196 if (domain->id)
3197 domain_id_free(domain->id);
3198
3199 kfree(domain);
3200 }
3201
3202 static struct protection_domain *protection_domain_alloc(void)
3203 {
3204 struct protection_domain *domain;
3205
3206 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3207 if (!domain)
3208 return NULL;
3209
3210 spin_lock_init(&domain->lock);
3211 mutex_init(&domain->api_lock);
3212 domain->id = domain_id_alloc();
3213 if (!domain->id)
3214 goto out_err;
3215 INIT_LIST_HEAD(&domain->dev_list);
3216
3217 add_domain_to_list(domain);
3218
3219 return domain;
3220
3221 out_err:
3222 kfree(domain);
3223
3224 return NULL;
3225 }
3226
3227 static int __init alloc_passthrough_domain(void)
3228 {
3229 if (pt_domain != NULL)
3230 return 0;
3231
3232 /* allocate passthrough domain */
3233 pt_domain = protection_domain_alloc();
3234 if (!pt_domain)
3235 return -ENOMEM;
3236
3237 pt_domain->mode = PAGE_MODE_NONE;
3238
3239 return 0;
3240 }
3241 static int amd_iommu_domain_init(struct iommu_domain *dom)
3242 {
3243 struct protection_domain *domain;
3244
3245 domain = protection_domain_alloc();
3246 if (!domain)
3247 goto out_free;
3248
3249 domain->mode = PAGE_MODE_3_LEVEL;
3250 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3251 if (!domain->pt_root)
3252 goto out_free;
3253
3254 domain->iommu_domain = dom;
3255
3256 dom->priv = domain;
3257
3258 dom->geometry.aperture_start = 0;
3259 dom->geometry.aperture_end = ~0ULL;
3260 dom->geometry.force_aperture = true;
3261
3262 return 0;
3263
3264 out_free:
3265 protection_domain_free(domain);
3266
3267 return -ENOMEM;
3268 }
3269
3270 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3271 {
3272 struct protection_domain *domain = dom->priv;
3273
3274 if (!domain)
3275 return;
3276
3277 if (domain->dev_cnt > 0)
3278 cleanup_domain(domain);
3279
3280 BUG_ON(domain->dev_cnt != 0);
3281
3282 if (domain->mode != PAGE_MODE_NONE)
3283 free_pagetable(domain);
3284
3285 if (domain->flags & PD_IOMMUV2_MASK)
3286 free_gcr3_table(domain);
3287
3288 protection_domain_free(domain);
3289
3290 dom->priv = NULL;
3291 }
3292
3293 static void amd_iommu_detach_device(struct iommu_domain *dom,
3294 struct device *dev)
3295 {
3296 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3297 struct amd_iommu *iommu;
3298 u16 devid;
3299
3300 if (!check_device(dev))
3301 return;
3302
3303 devid = get_device_id(dev);
3304
3305 if (dev_data->domain != NULL)
3306 detach_device(dev);
3307
3308 iommu = amd_iommu_rlookup_table[devid];
3309 if (!iommu)
3310 return;
3311
3312 iommu_completion_wait(iommu);
3313 }
3314
3315 static int amd_iommu_attach_device(struct iommu_domain *dom,
3316 struct device *dev)
3317 {
3318 struct protection_domain *domain = dom->priv;
3319 struct iommu_dev_data *dev_data;
3320 struct amd_iommu *iommu;
3321 int ret;
3322
3323 if (!check_device(dev))
3324 return -EINVAL;
3325
3326 dev_data = dev->archdata.iommu;
3327
3328 iommu = amd_iommu_rlookup_table[dev_data->devid];
3329 if (!iommu)
3330 return -EINVAL;
3331
3332 if (dev_data->domain)
3333 detach_device(dev);
3334
3335 ret = attach_device(dev, domain);
3336
3337 iommu_completion_wait(iommu);
3338
3339 return ret;
3340 }
3341
3342 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3343 phys_addr_t paddr, size_t page_size, int iommu_prot)
3344 {
3345 struct protection_domain *domain = dom->priv;
3346 int prot = 0;
3347 int ret;
3348
3349 if (domain->mode == PAGE_MODE_NONE)
3350 return -EINVAL;
3351
3352 if (iommu_prot & IOMMU_READ)
3353 prot |= IOMMU_PROT_IR;
3354 if (iommu_prot & IOMMU_WRITE)
3355 prot |= IOMMU_PROT_IW;
3356
3357 mutex_lock(&domain->api_lock);
3358 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3359 mutex_unlock(&domain->api_lock);
3360
3361 return ret;
3362 }
3363
3364 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3365 size_t page_size)
3366 {
3367 struct protection_domain *domain = dom->priv;
3368 size_t unmap_size;
3369
3370 if (domain->mode == PAGE_MODE_NONE)
3371 return -EINVAL;
3372
3373 mutex_lock(&domain->api_lock);
3374 unmap_size = iommu_unmap_page(domain, iova, page_size);
3375 mutex_unlock(&domain->api_lock);
3376
3377 domain_flush_tlb_pde(domain);
3378
3379 return unmap_size;
3380 }
3381
3382 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3383 dma_addr_t iova)
3384 {
3385 struct protection_domain *domain = dom->priv;
3386 unsigned long offset_mask, pte_pgsize;
3387 u64 *pte, __pte;
3388
3389 if (domain->mode == PAGE_MODE_NONE)
3390 return iova;
3391
3392 pte = fetch_pte(domain, iova, &pte_pgsize);
3393
3394 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3395 return 0;
3396
3397 offset_mask = pte_pgsize - 1;
3398 __pte = *pte & PM_ADDR_MASK;
3399
3400 return (__pte & ~offset_mask) | (iova & offset_mask);
3401 }
3402
3403 static bool amd_iommu_capable(enum iommu_cap cap)
3404 {
3405 switch (cap) {
3406 case IOMMU_CAP_CACHE_COHERENCY:
3407 return true;
3408 case IOMMU_CAP_INTR_REMAP:
3409 return (irq_remapping_enabled == 1);
3410 case IOMMU_CAP_NOEXEC:
3411 return false;
3412 }
3413
3414 return false;
3415 }
3416
3417 static const struct iommu_ops amd_iommu_ops = {
3418 .capable = amd_iommu_capable,
3419 .domain_init = amd_iommu_domain_init,
3420 .domain_destroy = amd_iommu_domain_destroy,
3421 .attach_dev = amd_iommu_attach_device,
3422 .detach_dev = amd_iommu_detach_device,
3423 .map = amd_iommu_map,
3424 .unmap = amd_iommu_unmap,
3425 .map_sg = default_iommu_map_sg,
3426 .iova_to_phys = amd_iommu_iova_to_phys,
3427 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3428 };
3429
3430 /*****************************************************************************
3431 *
3432 * The next functions do a basic initialization of IOMMU for pass through
3433 * mode
3434 *
3435 * In passthrough mode the IOMMU is initialized and enabled but not used for
3436 * DMA-API translation.
3437 *
3438 *****************************************************************************/
3439
3440 int __init amd_iommu_init_passthrough(void)
3441 {
3442 struct iommu_dev_data *dev_data;
3443 struct pci_dev *dev = NULL;
3444 int ret;
3445
3446 ret = alloc_passthrough_domain();
3447 if (ret)
3448 return ret;
3449
3450 for_each_pci_dev(dev) {
3451 if (!check_device(&dev->dev))
3452 continue;
3453
3454 dev_data = get_dev_data(&dev->dev);
3455 dev_data->passthrough = true;
3456
3457 attach_device(&dev->dev, pt_domain);
3458 }
3459
3460 amd_iommu_stats_init();
3461
3462 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3463
3464 return 0;
3465 }
3466
3467 /* IOMMUv2 specific functions */
3468 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3469 {
3470 return atomic_notifier_chain_register(&ppr_notifier, nb);
3471 }
3472 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3473
3474 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3475 {
3476 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3477 }
3478 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3479
3480 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3481 {
3482 struct protection_domain *domain = dom->priv;
3483 unsigned long flags;
3484
3485 spin_lock_irqsave(&domain->lock, flags);
3486
3487 /* Update data structure */
3488 domain->mode = PAGE_MODE_NONE;
3489 domain->updated = true;
3490
3491 /* Make changes visible to IOMMUs */
3492 update_domain(domain);
3493
3494 /* Page-table is not visible to IOMMU anymore, so free it */
3495 free_pagetable(domain);
3496
3497 spin_unlock_irqrestore(&domain->lock, flags);
3498 }
3499 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3500
3501 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3502 {
3503 struct protection_domain *domain = dom->priv;
3504 unsigned long flags;
3505 int levels, ret;
3506
3507 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3508 return -EINVAL;
3509
3510 /* Number of GCR3 table levels required */
3511 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3512 levels += 1;
3513
3514 if (levels > amd_iommu_max_glx_val)
3515 return -EINVAL;
3516
3517 spin_lock_irqsave(&domain->lock, flags);
3518
3519 /*
3520 * Save us all sanity checks whether devices already in the
3521 * domain support IOMMUv2. Just force that the domain has no
3522 * devices attached when it is switched into IOMMUv2 mode.
3523 */
3524 ret = -EBUSY;
3525 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3526 goto out;
3527
3528 ret = -ENOMEM;
3529 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3530 if (domain->gcr3_tbl == NULL)
3531 goto out;
3532
3533 domain->glx = levels;
3534 domain->flags |= PD_IOMMUV2_MASK;
3535 domain->updated = true;
3536
3537 update_domain(domain);
3538
3539 ret = 0;
3540
3541 out:
3542 spin_unlock_irqrestore(&domain->lock, flags);
3543
3544 return ret;
3545 }
3546 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3547
3548 static int __flush_pasid(struct protection_domain *domain, int pasid,
3549 u64 address, bool size)
3550 {
3551 struct iommu_dev_data *dev_data;
3552 struct iommu_cmd cmd;
3553 int i, ret;
3554
3555 if (!(domain->flags & PD_IOMMUV2_MASK))
3556 return -EINVAL;
3557
3558 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3559
3560 /*
3561 * IOMMU TLB needs to be flushed before Device TLB to
3562 * prevent device TLB refill from IOMMU TLB
3563 */
3564 for (i = 0; i < amd_iommus_present; ++i) {
3565 if (domain->dev_iommu[i] == 0)
3566 continue;
3567
3568 ret = iommu_queue_command(amd_iommus[i], &cmd);
3569 if (ret != 0)
3570 goto out;
3571 }
3572
3573 /* Wait until IOMMU TLB flushes are complete */
3574 domain_flush_complete(domain);
3575
3576 /* Now flush device TLBs */
3577 list_for_each_entry(dev_data, &domain->dev_list, list) {
3578 struct amd_iommu *iommu;
3579 int qdep;
3580
3581 BUG_ON(!dev_data->ats.enabled);
3582
3583 qdep = dev_data->ats.qdep;
3584 iommu = amd_iommu_rlookup_table[dev_data->devid];
3585
3586 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3587 qdep, address, size);
3588
3589 ret = iommu_queue_command(iommu, &cmd);
3590 if (ret != 0)
3591 goto out;
3592 }
3593
3594 /* Wait until all device TLBs are flushed */
3595 domain_flush_complete(domain);
3596
3597 ret = 0;
3598
3599 out:
3600
3601 return ret;
3602 }
3603
3604 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3605 u64 address)
3606 {
3607 INC_STATS_COUNTER(invalidate_iotlb);
3608
3609 return __flush_pasid(domain, pasid, address, false);
3610 }
3611
3612 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3613 u64 address)
3614 {
3615 struct protection_domain *domain = dom->priv;
3616 unsigned long flags;
3617 int ret;
3618
3619 spin_lock_irqsave(&domain->lock, flags);
3620 ret = __amd_iommu_flush_page(domain, pasid, address);
3621 spin_unlock_irqrestore(&domain->lock, flags);
3622
3623 return ret;
3624 }
3625 EXPORT_SYMBOL(amd_iommu_flush_page);
3626
3627 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3628 {
3629 INC_STATS_COUNTER(invalidate_iotlb_all);
3630
3631 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3632 true);
3633 }
3634
3635 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3636 {
3637 struct protection_domain *domain = dom->priv;
3638 unsigned long flags;
3639 int ret;
3640
3641 spin_lock_irqsave(&domain->lock, flags);
3642 ret = __amd_iommu_flush_tlb(domain, pasid);
3643 spin_unlock_irqrestore(&domain->lock, flags);
3644
3645 return ret;
3646 }
3647 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3648
3649 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3650 {
3651 int index;
3652 u64 *pte;
3653
3654 while (true) {
3655
3656 index = (pasid >> (9 * level)) & 0x1ff;
3657 pte = &root[index];
3658
3659 if (level == 0)
3660 break;
3661
3662 if (!(*pte & GCR3_VALID)) {
3663 if (!alloc)
3664 return NULL;
3665
3666 root = (void *)get_zeroed_page(GFP_ATOMIC);
3667 if (root == NULL)
3668 return NULL;
3669
3670 *pte = __pa(root) | GCR3_VALID;
3671 }
3672
3673 root = __va(*pte & PAGE_MASK);
3674
3675 level -= 1;
3676 }
3677
3678 return pte;
3679 }
3680
3681 static int __set_gcr3(struct protection_domain *domain, int pasid,
3682 unsigned long cr3)
3683 {
3684 u64 *pte;
3685
3686 if (domain->mode != PAGE_MODE_NONE)
3687 return -EINVAL;
3688
3689 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3690 if (pte == NULL)
3691 return -ENOMEM;
3692
3693 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3694
3695 return __amd_iommu_flush_tlb(domain, pasid);
3696 }
3697
3698 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3699 {
3700 u64 *pte;
3701
3702 if (domain->mode != PAGE_MODE_NONE)
3703 return -EINVAL;
3704
3705 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3706 if (pte == NULL)
3707 return 0;
3708
3709 *pte = 0;
3710
3711 return __amd_iommu_flush_tlb(domain, pasid);
3712 }
3713
3714 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3715 unsigned long cr3)
3716 {
3717 struct protection_domain *domain = dom->priv;
3718 unsigned long flags;
3719 int ret;
3720
3721 spin_lock_irqsave(&domain->lock, flags);
3722 ret = __set_gcr3(domain, pasid, cr3);
3723 spin_unlock_irqrestore(&domain->lock, flags);
3724
3725 return ret;
3726 }
3727 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3728
3729 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3730 {
3731 struct protection_domain *domain = dom->priv;
3732 unsigned long flags;
3733 int ret;
3734
3735 spin_lock_irqsave(&domain->lock, flags);
3736 ret = __clear_gcr3(domain, pasid);
3737 spin_unlock_irqrestore(&domain->lock, flags);
3738
3739 return ret;
3740 }
3741 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3742
3743 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3744 int status, int tag)
3745 {
3746 struct iommu_dev_data *dev_data;
3747 struct amd_iommu *iommu;
3748 struct iommu_cmd cmd;
3749
3750 INC_STATS_COUNTER(complete_ppr);
3751
3752 dev_data = get_dev_data(&pdev->dev);
3753 iommu = amd_iommu_rlookup_table[dev_data->devid];
3754
3755 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3756 tag, dev_data->pri_tlp);
3757
3758 return iommu_queue_command(iommu, &cmd);
3759 }
3760 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3761
3762 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3763 {
3764 struct protection_domain *domain;
3765
3766 domain = get_domain(&pdev->dev);
3767 if (IS_ERR(domain))
3768 return NULL;
3769
3770 /* Only return IOMMUv2 domains */
3771 if (!(domain->flags & PD_IOMMUV2_MASK))
3772 return NULL;
3773
3774 return domain->iommu_domain;
3775 }
3776 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3777
3778 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3779 {
3780 struct iommu_dev_data *dev_data;
3781
3782 if (!amd_iommu_v2_supported())
3783 return;
3784
3785 dev_data = get_dev_data(&pdev->dev);
3786 dev_data->errata |= (1 << erratum);
3787 }
3788 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3789
3790 int amd_iommu_device_info(struct pci_dev *pdev,
3791 struct amd_iommu_device_info *info)
3792 {
3793 int max_pasids;
3794 int pos;
3795
3796 if (pdev == NULL || info == NULL)
3797 return -EINVAL;
3798
3799 if (!amd_iommu_v2_supported())
3800 return -EINVAL;
3801
3802 memset(info, 0, sizeof(*info));
3803
3804 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3805 if (pos)
3806 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3807
3808 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3809 if (pos)
3810 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3811
3812 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3813 if (pos) {
3814 int features;
3815
3816 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3817 max_pasids = min(max_pasids, (1 << 20));
3818
3819 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3820 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3821
3822 features = pci_pasid_features(pdev);
3823 if (features & PCI_PASID_CAP_EXEC)
3824 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3825 if (features & PCI_PASID_CAP_PRIV)
3826 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3827 }
3828
3829 return 0;
3830 }
3831 EXPORT_SYMBOL(amd_iommu_device_info);
3832
3833 #ifdef CONFIG_IRQ_REMAP
3834
3835 /*****************************************************************************
3836 *
3837 * Interrupt Remapping Implementation
3838 *
3839 *****************************************************************************/
3840
3841 union irte {
3842 u32 val;
3843 struct {
3844 u32 valid : 1,
3845 no_fault : 1,
3846 int_type : 3,
3847 rq_eoi : 1,
3848 dm : 1,
3849 rsvd_1 : 1,
3850 destination : 8,
3851 vector : 8,
3852 rsvd_2 : 8;
3853 } fields;
3854 };
3855
3856 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3857 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3858 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3859 #define DTE_IRQ_REMAP_ENABLE 1ULL
3860
3861 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3862 {
3863 u64 dte;
3864
3865 dte = amd_iommu_dev_table[devid].data[2];
3866 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3867 dte |= virt_to_phys(table->table);
3868 dte |= DTE_IRQ_REMAP_INTCTL;
3869 dte |= DTE_IRQ_TABLE_LEN;
3870 dte |= DTE_IRQ_REMAP_ENABLE;
3871
3872 amd_iommu_dev_table[devid].data[2] = dte;
3873 }
3874
3875 #define IRTE_ALLOCATED (~1U)
3876
3877 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3878 {
3879 struct irq_remap_table *table = NULL;
3880 struct amd_iommu *iommu;
3881 unsigned long flags;
3882 u16 alias;
3883
3884 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3885
3886 iommu = amd_iommu_rlookup_table[devid];
3887 if (!iommu)
3888 goto out_unlock;
3889
3890 table = irq_lookup_table[devid];
3891 if (table)
3892 goto out;
3893
3894 alias = amd_iommu_alias_table[devid];
3895 table = irq_lookup_table[alias];
3896 if (table) {
3897 irq_lookup_table[devid] = table;
3898 set_dte_irq_entry(devid, table);
3899 iommu_flush_dte(iommu, devid);
3900 goto out;
3901 }
3902
3903 /* Nothing there yet, allocate new irq remapping table */
3904 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3905 if (!table)
3906 goto out;
3907
3908 /* Initialize table spin-lock */
3909 spin_lock_init(&table->lock);
3910
3911 if (ioapic)
3912 /* Keep the first 32 indexes free for IOAPIC interrupts */
3913 table->min_index = 32;
3914
3915 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3916 if (!table->table) {
3917 kfree(table);
3918 table = NULL;
3919 goto out;
3920 }
3921
3922 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3923
3924 if (ioapic) {
3925 int i;
3926
3927 for (i = 0; i < 32; ++i)
3928 table->table[i] = IRTE_ALLOCATED;
3929 }
3930
3931 irq_lookup_table[devid] = table;
3932 set_dte_irq_entry(devid, table);
3933 iommu_flush_dte(iommu, devid);
3934 if (devid != alias) {
3935 irq_lookup_table[alias] = table;
3936 set_dte_irq_entry(alias, table);
3937 iommu_flush_dte(iommu, alias);
3938 }
3939
3940 out:
3941 iommu_completion_wait(iommu);
3942
3943 out_unlock:
3944 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3945
3946 return table;
3947 }
3948
3949 static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3950 {
3951 struct irq_remap_table *table;
3952 unsigned long flags;
3953 int index, c;
3954
3955 table = get_irq_table(devid, false);
3956 if (!table)
3957 return -ENODEV;
3958
3959 spin_lock_irqsave(&table->lock, flags);
3960
3961 /* Scan table for free entries */
3962 for (c = 0, index = table->min_index;
3963 index < MAX_IRQS_PER_TABLE;
3964 ++index) {
3965 if (table->table[index] == 0)
3966 c += 1;
3967 else
3968 c = 0;
3969
3970 if (c == count) {
3971 struct irq_2_irte *irte_info;
3972
3973 for (; c != 0; --c)
3974 table->table[index - c + 1] = IRTE_ALLOCATED;
3975
3976 index -= count - 1;
3977
3978 cfg->remapped = 1;
3979 irte_info = &cfg->irq_2_irte;
3980 irte_info->devid = devid;
3981 irte_info->index = index;
3982
3983 goto out;
3984 }
3985 }
3986
3987 index = -ENOSPC;
3988
3989 out:
3990 spin_unlock_irqrestore(&table->lock, flags);
3991
3992 return index;
3993 }
3994
3995 static int get_irte(u16 devid, int index, union irte *irte)
3996 {
3997 struct irq_remap_table *table;
3998 unsigned long flags;
3999
4000 table = get_irq_table(devid, false);
4001 if (!table)
4002 return -ENOMEM;
4003
4004 spin_lock_irqsave(&table->lock, flags);
4005 irte->val = table->table[index];
4006 spin_unlock_irqrestore(&table->lock, flags);
4007
4008 return 0;
4009 }
4010
4011 static int modify_irte(u16 devid, int index, union irte irte)
4012 {
4013 struct irq_remap_table *table;
4014 struct amd_iommu *iommu;
4015 unsigned long flags;
4016
4017 iommu = amd_iommu_rlookup_table[devid];
4018 if (iommu == NULL)
4019 return -EINVAL;
4020
4021 table = get_irq_table(devid, false);
4022 if (!table)
4023 return -ENOMEM;
4024
4025 spin_lock_irqsave(&table->lock, flags);
4026 table->table[index] = irte.val;
4027 spin_unlock_irqrestore(&table->lock, flags);
4028
4029 iommu_flush_irt(iommu, devid);
4030 iommu_completion_wait(iommu);
4031
4032 return 0;
4033 }
4034
4035 static void free_irte(u16 devid, int index)
4036 {
4037 struct irq_remap_table *table;
4038 struct amd_iommu *iommu;
4039 unsigned long flags;
4040
4041 iommu = amd_iommu_rlookup_table[devid];
4042 if (iommu == NULL)
4043 return;
4044
4045 table = get_irq_table(devid, false);
4046 if (!table)
4047 return;
4048
4049 spin_lock_irqsave(&table->lock, flags);
4050 table->table[index] = 0;
4051 spin_unlock_irqrestore(&table->lock, flags);
4052
4053 iommu_flush_irt(iommu, devid);
4054 iommu_completion_wait(iommu);
4055 }
4056
4057 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4058 unsigned int destination, int vector,
4059 struct io_apic_irq_attr *attr)
4060 {
4061 struct irq_remap_table *table;
4062 struct irq_2_irte *irte_info;
4063 struct irq_cfg *cfg;
4064 union irte irte;
4065 int ioapic_id;
4066 int index;
4067 int devid;
4068 int ret;
4069
4070 cfg = irq_cfg(irq);
4071 if (!cfg)
4072 return -EINVAL;
4073
4074 irte_info = &cfg->irq_2_irte;
4075 ioapic_id = mpc_ioapic_id(attr->ioapic);
4076 devid = get_ioapic_devid(ioapic_id);
4077
4078 if (devid < 0)
4079 return devid;
4080
4081 table = get_irq_table(devid, true);
4082 if (table == NULL)
4083 return -ENOMEM;
4084
4085 index = attr->ioapic_pin;
4086
4087 /* Setup IRQ remapping info */
4088 cfg->remapped = 1;
4089 irte_info->devid = devid;
4090 irte_info->index = index;
4091
4092 /* Setup IRTE for IOMMU */
4093 irte.val = 0;
4094 irte.fields.vector = vector;
4095 irte.fields.int_type = apic->irq_delivery_mode;
4096 irte.fields.destination = destination;
4097 irte.fields.dm = apic->irq_dest_mode;
4098 irte.fields.valid = 1;
4099
4100 ret = modify_irte(devid, index, irte);
4101 if (ret)
4102 return ret;
4103
4104 /* Setup IOAPIC entry */
4105 memset(entry, 0, sizeof(*entry));
4106
4107 entry->vector = index;
4108 entry->mask = 0;
4109 entry->trigger = attr->trigger;
4110 entry->polarity = attr->polarity;
4111
4112 /*
4113 * Mask level triggered irqs.
4114 */
4115 if (attr->trigger)
4116 entry->mask = 1;
4117
4118 return 0;
4119 }
4120
4121 static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4122 bool force)
4123 {
4124 struct irq_2_irte *irte_info;
4125 unsigned int dest, irq;
4126 struct irq_cfg *cfg;
4127 union irte irte;
4128 int err;
4129
4130 if (!config_enabled(CONFIG_SMP))
4131 return -1;
4132
4133 cfg = irqd_cfg(data);
4134 irq = data->irq;
4135 irte_info = &cfg->irq_2_irte;
4136
4137 if (!cpumask_intersects(mask, cpu_online_mask))
4138 return -EINVAL;
4139
4140 if (get_irte(irte_info->devid, irte_info->index, &irte))
4141 return -EBUSY;
4142
4143 if (assign_irq_vector(irq, cfg, mask))
4144 return -EBUSY;
4145
4146 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
4147 if (err) {
4148 if (assign_irq_vector(irq, cfg, data->affinity))
4149 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
4150 return err;
4151 }
4152
4153 irte.fields.vector = cfg->vector;
4154 irte.fields.destination = dest;
4155
4156 modify_irte(irte_info->devid, irte_info->index, irte);
4157
4158 if (cfg->move_in_progress)
4159 send_cleanup_vector(cfg);
4160
4161 cpumask_copy(data->affinity, mask);
4162
4163 return 0;
4164 }
4165
4166 static int free_irq(int irq)
4167 {
4168 struct irq_2_irte *irte_info;
4169 struct irq_cfg *cfg;
4170
4171 cfg = irq_cfg(irq);
4172 if (!cfg)
4173 return -EINVAL;
4174
4175 irte_info = &cfg->irq_2_irte;
4176
4177 free_irte(irte_info->devid, irte_info->index);
4178
4179 return 0;
4180 }
4181
4182 static void compose_msi_msg(struct pci_dev *pdev,
4183 unsigned int irq, unsigned int dest,
4184 struct msi_msg *msg, u8 hpet_id)
4185 {
4186 struct irq_2_irte *irte_info;
4187 struct irq_cfg *cfg;
4188 union irte irte;
4189
4190 cfg = irq_cfg(irq);
4191 if (!cfg)
4192 return;
4193
4194 irte_info = &cfg->irq_2_irte;
4195
4196 irte.val = 0;
4197 irte.fields.vector = cfg->vector;
4198 irte.fields.int_type = apic->irq_delivery_mode;
4199 irte.fields.destination = dest;
4200 irte.fields.dm = apic->irq_dest_mode;
4201 irte.fields.valid = 1;
4202
4203 modify_irte(irte_info->devid, irte_info->index, irte);
4204
4205 msg->address_hi = MSI_ADDR_BASE_HI;
4206 msg->address_lo = MSI_ADDR_BASE_LO;
4207 msg->data = irte_info->index;
4208 }
4209
4210 static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
4211 {
4212 struct irq_cfg *cfg;
4213 int index;
4214 u16 devid;
4215
4216 if (!pdev)
4217 return -EINVAL;
4218
4219 cfg = irq_cfg(irq);
4220 if (!cfg)
4221 return -EINVAL;
4222
4223 devid = get_device_id(&pdev->dev);
4224 index = alloc_irq_index(cfg, devid, nvec);
4225
4226 return index < 0 ? MAX_IRQS_PER_TABLE : index;
4227 }
4228
4229 static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4230 int index, int offset)
4231 {
4232 struct irq_2_irte *irte_info;
4233 struct irq_cfg *cfg;
4234 u16 devid;
4235
4236 if (!pdev)
4237 return -EINVAL;
4238
4239 cfg = irq_cfg(irq);
4240 if (!cfg)
4241 return -EINVAL;
4242
4243 if (index >= MAX_IRQS_PER_TABLE)
4244 return 0;
4245
4246 devid = get_device_id(&pdev->dev);
4247 irte_info = &cfg->irq_2_irte;
4248
4249 cfg->remapped = 1;
4250 irte_info->devid = devid;
4251 irte_info->index = index + offset;
4252
4253 return 0;
4254 }
4255
4256 static int alloc_hpet_msi(unsigned int irq, unsigned int id)
4257 {
4258 struct irq_2_irte *irte_info;
4259 struct irq_cfg *cfg;
4260 int index, devid;
4261
4262 cfg = irq_cfg(irq);
4263 if (!cfg)
4264 return -EINVAL;
4265
4266 irte_info = &cfg->irq_2_irte;
4267 devid = get_hpet_devid(id);
4268 if (devid < 0)
4269 return devid;
4270
4271 index = alloc_irq_index(cfg, devid, 1);
4272 if (index < 0)
4273 return index;
4274
4275 cfg->remapped = 1;
4276 irte_info->devid = devid;
4277 irte_info->index = index;
4278
4279 return 0;
4280 }
4281
4282 struct irq_remap_ops amd_iommu_irq_ops = {
4283 .prepare = amd_iommu_prepare,
4284 .enable = amd_iommu_enable,
4285 .disable = amd_iommu_disable,
4286 .reenable = amd_iommu_reenable,
4287 .enable_faulting = amd_iommu_enable_faulting,
4288 .setup_ioapic_entry = setup_ioapic_entry,
4289 .set_affinity = set_affinity,
4290 .free_irq = free_irq,
4291 .compose_msi_msg = compose_msi_msg,
4292 .msi_alloc_irq = msi_alloc_irq,
4293 .msi_setup_irq = msi_setup_irq,
4294 .alloc_hpet_msi = alloc_hpet_msi,
4295 };
4296 #endif
Linux kernel - Deliverables
This page took 0.112403 seconds and 6 git commands to generate.