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Merge branches 'x86/apic', 'x86/asm', 'x86/mm' and 'x86/platform' into x86/core,...
[deliverable/linux.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <linux/dma-contiguous.h>
37 #include <linux/irqdomain.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/io_apic.h>
40 #include <asm/apic.h>
41 #include <asm/hw_irq.h>
42 #include <asm/msidef.h>
43 #include <asm/proto.h>
44 #include <asm/iommu.h>
45 #include <asm/gart.h>
46 #include <asm/dma.h>
47
48 #include "amd_iommu_proto.h"
49 #include "amd_iommu_types.h"
50 #include "irq_remapping.h"
51
52 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
53
54 #define LOOP_TIMEOUT 100000
55
56 /*
57 * This bitmap is used to advertise the page sizes our hardware support
58 * to the IOMMU core, which will then use this information to split
59 * physically contiguous memory regions it is mapping into page sizes
60 * that we support.
61 *
62 * 512GB Pages are not supported due to a hardware bug
63 */
64 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
65
66 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
67
68 /* A list of preallocated protection domains */
69 static LIST_HEAD(iommu_pd_list);
70 static DEFINE_SPINLOCK(iommu_pd_list_lock);
71
72 /* List of all available dev_data structures */
73 static LIST_HEAD(dev_data_list);
74 static DEFINE_SPINLOCK(dev_data_list_lock);
75
76 LIST_HEAD(ioapic_map);
77 LIST_HEAD(hpet_map);
78
79 /*
80 * Domain for untranslated devices - only allocated
81 * if iommu=pt passed on kernel cmd line.
82 */
83 static struct protection_domain *pt_domain;
84
85 static const struct iommu_ops amd_iommu_ops;
86
87 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
88 int amd_iommu_max_glx_val = -1;
89
90 static struct dma_map_ops amd_iommu_dma_ops;
91
92 /*
93 * This struct contains device specific data for the IOMMU
94 */
95 struct iommu_dev_data {
96 struct list_head list; /* For domain->dev_list */
97 struct list_head dev_data_list; /* For global dev_data_list */
98 struct list_head alias_list; /* Link alias-groups together */
99 struct iommu_dev_data *alias_data;/* The alias dev_data */
100 struct protection_domain *domain; /* Domain the device is bound to */
101 u16 devid; /* PCI Device ID */
102 bool iommu_v2; /* Device can make use of IOMMUv2 */
103 bool passthrough; /* Default for device is pt_domain */
104 struct {
105 bool enabled;
106 int qdep;
107 } ats; /* ATS state */
108 bool pri_tlp; /* PASID TLB required for
109 PPR completions */
110 u32 errata; /* Bitmap for errata to apply */
111 };
112
113 /*
114 * general struct to manage commands send to an IOMMU
115 */
116 struct iommu_cmd {
117 u32 data[4];
118 };
119
120 struct kmem_cache *amd_iommu_irq_cache;
121
122 static void update_domain(struct protection_domain *domain);
123 static int __init alloc_passthrough_domain(void);
124
125 /****************************************************************************
126 *
127 * Helper functions
128 *
129 ****************************************************************************/
130
131 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
132 {
133 return container_of(dom, struct protection_domain, domain);
134 }
135
136 static struct iommu_dev_data *alloc_dev_data(u16 devid)
137 {
138 struct iommu_dev_data *dev_data;
139 unsigned long flags;
140
141 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
142 if (!dev_data)
143 return NULL;
144
145 INIT_LIST_HEAD(&dev_data->alias_list);
146
147 dev_data->devid = devid;
148
149 spin_lock_irqsave(&dev_data_list_lock, flags);
150 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
151 spin_unlock_irqrestore(&dev_data_list_lock, flags);
152
153 return dev_data;
154 }
155
156 static void free_dev_data(struct iommu_dev_data *dev_data)
157 {
158 unsigned long flags;
159
160 spin_lock_irqsave(&dev_data_list_lock, flags);
161 list_del(&dev_data->dev_data_list);
162 spin_unlock_irqrestore(&dev_data_list_lock, flags);
163
164 kfree(dev_data);
165 }
166
167 static struct iommu_dev_data *search_dev_data(u16 devid)
168 {
169 struct iommu_dev_data *dev_data;
170 unsigned long flags;
171
172 spin_lock_irqsave(&dev_data_list_lock, flags);
173 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
174 if (dev_data->devid == devid)
175 goto out_unlock;
176 }
177
178 dev_data = NULL;
179
180 out_unlock:
181 spin_unlock_irqrestore(&dev_data_list_lock, flags);
182
183 return dev_data;
184 }
185
186 static struct iommu_dev_data *find_dev_data(u16 devid)
187 {
188 struct iommu_dev_data *dev_data;
189
190 dev_data = search_dev_data(devid);
191
192 if (dev_data == NULL)
193 dev_data = alloc_dev_data(devid);
194
195 return dev_data;
196 }
197
198 static inline u16 get_device_id(struct device *dev)
199 {
200 struct pci_dev *pdev = to_pci_dev(dev);
201
202 return PCI_DEVID(pdev->bus->number, pdev->devfn);
203 }
204
205 static struct iommu_dev_data *get_dev_data(struct device *dev)
206 {
207 return dev->archdata.iommu;
208 }
209
210 static bool pci_iommuv2_capable(struct pci_dev *pdev)
211 {
212 static const int caps[] = {
213 PCI_EXT_CAP_ID_ATS,
214 PCI_EXT_CAP_ID_PRI,
215 PCI_EXT_CAP_ID_PASID,
216 };
217 int i, pos;
218
219 for (i = 0; i < 3; ++i) {
220 pos = pci_find_ext_capability(pdev, caps[i]);
221 if (pos == 0)
222 return false;
223 }
224
225 return true;
226 }
227
228 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
229 {
230 struct iommu_dev_data *dev_data;
231
232 dev_data = get_dev_data(&pdev->dev);
233
234 return dev_data->errata & (1 << erratum) ? true : false;
235 }
236
237 /*
238 * In this function the list of preallocated protection domains is traversed to
239 * find the domain for a specific device
240 */
241 static struct dma_ops_domain *find_protection_domain(u16 devid)
242 {
243 struct dma_ops_domain *entry, *ret = NULL;
244 unsigned long flags;
245 u16 alias = amd_iommu_alias_table[devid];
246
247 if (list_empty(&iommu_pd_list))
248 return NULL;
249
250 spin_lock_irqsave(&iommu_pd_list_lock, flags);
251
252 list_for_each_entry(entry, &iommu_pd_list, list) {
253 if (entry->target_dev == devid ||
254 entry->target_dev == alias) {
255 ret = entry;
256 break;
257 }
258 }
259
260 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
261
262 return ret;
263 }
264
265 /*
266 * This function checks if the driver got a valid device from the caller to
267 * avoid dereferencing invalid pointers.
268 */
269 static bool check_device(struct device *dev)
270 {
271 u16 devid;
272
273 if (!dev || !dev->dma_mask)
274 return false;
275
276 /* No PCI device */
277 if (!dev_is_pci(dev))
278 return false;
279
280 devid = get_device_id(dev);
281
282 /* Out of our scope? */
283 if (devid > amd_iommu_last_bdf)
284 return false;
285
286 if (amd_iommu_rlookup_table[devid] == NULL)
287 return false;
288
289 return true;
290 }
291
292 static void init_iommu_group(struct device *dev)
293 {
294 struct iommu_group *group;
295
296 group = iommu_group_get_for_dev(dev);
297 if (!IS_ERR(group))
298 iommu_group_put(group);
299 }
300
301 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
302 {
303 *(u16 *)data = alias;
304 return 0;
305 }
306
307 static u16 get_alias(struct device *dev)
308 {
309 struct pci_dev *pdev = to_pci_dev(dev);
310 u16 devid, ivrs_alias, pci_alias;
311
312 devid = get_device_id(dev);
313 ivrs_alias = amd_iommu_alias_table[devid];
314 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
315
316 if (ivrs_alias == pci_alias)
317 return ivrs_alias;
318
319 /*
320 * DMA alias showdown
321 *
322 * The IVRS is fairly reliable in telling us about aliases, but it
323 * can't know about every screwy device. If we don't have an IVRS
324 * reported alias, use the PCI reported alias. In that case we may
325 * still need to initialize the rlookup and dev_table entries if the
326 * alias is to a non-existent device.
327 */
328 if (ivrs_alias == devid) {
329 if (!amd_iommu_rlookup_table[pci_alias]) {
330 amd_iommu_rlookup_table[pci_alias] =
331 amd_iommu_rlookup_table[devid];
332 memcpy(amd_iommu_dev_table[pci_alias].data,
333 amd_iommu_dev_table[devid].data,
334 sizeof(amd_iommu_dev_table[pci_alias].data));
335 }
336
337 return pci_alias;
338 }
339
340 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
341 "for device %s[%04x:%04x], kernel reported alias "
342 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
343 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
344 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
345 PCI_FUNC(pci_alias));
346
347 /*
348 * If we don't have a PCI DMA alias and the IVRS alias is on the same
349 * bus, then the IVRS table may know about a quirk that we don't.
350 */
351 if (pci_alias == devid &&
352 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
353 pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
354 pdev->dma_alias_devfn = ivrs_alias & 0xff;
355 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
356 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
357 dev_name(dev));
358 }
359
360 return ivrs_alias;
361 }
362
363 static int iommu_init_device(struct device *dev)
364 {
365 struct pci_dev *pdev = to_pci_dev(dev);
366 struct iommu_dev_data *dev_data;
367 u16 alias;
368
369 if (dev->archdata.iommu)
370 return 0;
371
372 dev_data = find_dev_data(get_device_id(dev));
373 if (!dev_data)
374 return -ENOMEM;
375
376 alias = get_alias(dev);
377
378 if (alias != dev_data->devid) {
379 struct iommu_dev_data *alias_data;
380
381 alias_data = find_dev_data(alias);
382 if (alias_data == NULL) {
383 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
384 dev_name(dev));
385 free_dev_data(dev_data);
386 return -ENOTSUPP;
387 }
388 dev_data->alias_data = alias_data;
389
390 /* Add device to the alias_list */
391 list_add(&dev_data->alias_list, &alias_data->alias_list);
392 }
393
394 if (pci_iommuv2_capable(pdev)) {
395 struct amd_iommu *iommu;
396
397 iommu = amd_iommu_rlookup_table[dev_data->devid];
398 dev_data->iommu_v2 = iommu->is_iommu_v2;
399 }
400
401 dev->archdata.iommu = dev_data;
402
403 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
404 dev);
405
406 return 0;
407 }
408
409 static void iommu_ignore_device(struct device *dev)
410 {
411 u16 devid, alias;
412
413 devid = get_device_id(dev);
414 alias = amd_iommu_alias_table[devid];
415
416 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
417 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
418
419 amd_iommu_rlookup_table[devid] = NULL;
420 amd_iommu_rlookup_table[alias] = NULL;
421 }
422
423 static void iommu_uninit_device(struct device *dev)
424 {
425 struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev));
426
427 if (!dev_data)
428 return;
429
430 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
431 dev);
432
433 iommu_group_remove_device(dev);
434
435 /* Unlink from alias, it may change if another device is re-plugged */
436 dev_data->alias_data = NULL;
437
438 /*
439 * We keep dev_data around for unplugged devices and reuse it when the
440 * device is re-plugged - not doing so would introduce a ton of races.
441 */
442 }
443
444 void __init amd_iommu_uninit_devices(void)
445 {
446 struct iommu_dev_data *dev_data, *n;
447 struct pci_dev *pdev = NULL;
448
449 for_each_pci_dev(pdev) {
450
451 if (!check_device(&pdev->dev))
452 continue;
453
454 iommu_uninit_device(&pdev->dev);
455 }
456
457 /* Free all of our dev_data structures */
458 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
459 free_dev_data(dev_data);
460 }
461
462 int __init amd_iommu_init_devices(void)
463 {
464 struct pci_dev *pdev = NULL;
465 int ret = 0;
466
467 for_each_pci_dev(pdev) {
468
469 if (!check_device(&pdev->dev))
470 continue;
471
472 ret = iommu_init_device(&pdev->dev);
473 if (ret == -ENOTSUPP)
474 iommu_ignore_device(&pdev->dev);
475 else if (ret)
476 goto out_free;
477 }
478
479 /*
480 * Initialize IOMMU groups only after iommu_init_device() has
481 * had a chance to populate any IVRS defined aliases.
482 */
483 for_each_pci_dev(pdev) {
484 if (check_device(&pdev->dev))
485 init_iommu_group(&pdev->dev);
486 }
487
488 return 0;
489
490 out_free:
491
492 amd_iommu_uninit_devices();
493
494 return ret;
495 }
496 #ifdef CONFIG_AMD_IOMMU_STATS
497
498 /*
499 * Initialization code for statistics collection
500 */
501
502 DECLARE_STATS_COUNTER(compl_wait);
503 DECLARE_STATS_COUNTER(cnt_map_single);
504 DECLARE_STATS_COUNTER(cnt_unmap_single);
505 DECLARE_STATS_COUNTER(cnt_map_sg);
506 DECLARE_STATS_COUNTER(cnt_unmap_sg);
507 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
508 DECLARE_STATS_COUNTER(cnt_free_coherent);
509 DECLARE_STATS_COUNTER(cross_page);
510 DECLARE_STATS_COUNTER(domain_flush_single);
511 DECLARE_STATS_COUNTER(domain_flush_all);
512 DECLARE_STATS_COUNTER(alloced_io_mem);
513 DECLARE_STATS_COUNTER(total_map_requests);
514 DECLARE_STATS_COUNTER(complete_ppr);
515 DECLARE_STATS_COUNTER(invalidate_iotlb);
516 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
517 DECLARE_STATS_COUNTER(pri_requests);
518
519 static struct dentry *stats_dir;
520 static struct dentry *de_fflush;
521
522 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
523 {
524 if (stats_dir == NULL)
525 return;
526
527 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
528 &cnt->value);
529 }
530
531 static void amd_iommu_stats_init(void)
532 {
533 stats_dir = debugfs_create_dir("amd-iommu", NULL);
534 if (stats_dir == NULL)
535 return;
536
537 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
538 &amd_iommu_unmap_flush);
539
540 amd_iommu_stats_add(&compl_wait);
541 amd_iommu_stats_add(&cnt_map_single);
542 amd_iommu_stats_add(&cnt_unmap_single);
543 amd_iommu_stats_add(&cnt_map_sg);
544 amd_iommu_stats_add(&cnt_unmap_sg);
545 amd_iommu_stats_add(&cnt_alloc_coherent);
546 amd_iommu_stats_add(&cnt_free_coherent);
547 amd_iommu_stats_add(&cross_page);
548 amd_iommu_stats_add(&domain_flush_single);
549 amd_iommu_stats_add(&domain_flush_all);
550 amd_iommu_stats_add(&alloced_io_mem);
551 amd_iommu_stats_add(&total_map_requests);
552 amd_iommu_stats_add(&complete_ppr);
553 amd_iommu_stats_add(&invalidate_iotlb);
554 amd_iommu_stats_add(&invalidate_iotlb_all);
555 amd_iommu_stats_add(&pri_requests);
556 }
557
558 #endif
559
560 /****************************************************************************
561 *
562 * Interrupt handling functions
563 *
564 ****************************************************************************/
565
566 static void dump_dte_entry(u16 devid)
567 {
568 int i;
569
570 for (i = 0; i < 4; ++i)
571 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
572 amd_iommu_dev_table[devid].data[i]);
573 }
574
575 static void dump_command(unsigned long phys_addr)
576 {
577 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
578 int i;
579
580 for (i = 0; i < 4; ++i)
581 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
582 }
583
584 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
585 {
586 int type, devid, domid, flags;
587 volatile u32 *event = __evt;
588 int count = 0;
589 u64 address;
590
591 retry:
592 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
593 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
594 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
595 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
596 address = (u64)(((u64)event[3]) << 32) | event[2];
597
598 if (type == 0) {
599 /* Did we hit the erratum? */
600 if (++count == LOOP_TIMEOUT) {
601 pr_err("AMD-Vi: No event written to event log\n");
602 return;
603 }
604 udelay(1);
605 goto retry;
606 }
607
608 printk(KERN_ERR "AMD-Vi: Event logged [");
609
610 switch (type) {
611 case EVENT_TYPE_ILL_DEV:
612 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
613 "address=0x%016llx flags=0x%04x]\n",
614 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
615 address, flags);
616 dump_dte_entry(devid);
617 break;
618 case EVENT_TYPE_IO_FAULT:
619 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
620 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
621 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
622 domid, address, flags);
623 break;
624 case EVENT_TYPE_DEV_TAB_ERR:
625 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
626 "address=0x%016llx flags=0x%04x]\n",
627 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
628 address, flags);
629 break;
630 case EVENT_TYPE_PAGE_TAB_ERR:
631 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
632 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
633 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
634 domid, address, flags);
635 break;
636 case EVENT_TYPE_ILL_CMD:
637 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
638 dump_command(address);
639 break;
640 case EVENT_TYPE_CMD_HARD_ERR:
641 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
642 "flags=0x%04x]\n", address, flags);
643 break;
644 case EVENT_TYPE_IOTLB_INV_TO:
645 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
646 "address=0x%016llx]\n",
647 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
648 address);
649 break;
650 case EVENT_TYPE_INV_DEV_REQ:
651 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
652 "address=0x%016llx flags=0x%04x]\n",
653 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
654 address, flags);
655 break;
656 default:
657 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
658 }
659
660 memset(__evt, 0, 4 * sizeof(u32));
661 }
662
663 static void iommu_poll_events(struct amd_iommu *iommu)
664 {
665 u32 head, tail;
666
667 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
668 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
669
670 while (head != tail) {
671 iommu_print_event(iommu, iommu->evt_buf + head);
672 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
673 }
674
675 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
676 }
677
678 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
679 {
680 struct amd_iommu_fault fault;
681
682 INC_STATS_COUNTER(pri_requests);
683
684 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
685 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
686 return;
687 }
688
689 fault.address = raw[1];
690 fault.pasid = PPR_PASID(raw[0]);
691 fault.device_id = PPR_DEVID(raw[0]);
692 fault.tag = PPR_TAG(raw[0]);
693 fault.flags = PPR_FLAGS(raw[0]);
694
695 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
696 }
697
698 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
699 {
700 u32 head, tail;
701
702 if (iommu->ppr_log == NULL)
703 return;
704
705 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
706 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
707
708 while (head != tail) {
709 volatile u64 *raw;
710 u64 entry[2];
711 int i;
712
713 raw = (u64 *)(iommu->ppr_log + head);
714
715 /*
716 * Hardware bug: Interrupt may arrive before the entry is
717 * written to memory. If this happens we need to wait for the
718 * entry to arrive.
719 */
720 for (i = 0; i < LOOP_TIMEOUT; ++i) {
721 if (PPR_REQ_TYPE(raw[0]) != 0)
722 break;
723 udelay(1);
724 }
725
726 /* Avoid memcpy function-call overhead */
727 entry[0] = raw[0];
728 entry[1] = raw[1];
729
730 /*
731 * To detect the hardware bug we need to clear the entry
732 * back to zero.
733 */
734 raw[0] = raw[1] = 0UL;
735
736 /* Update head pointer of hardware ring-buffer */
737 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
738 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
739
740 /* Handle PPR entry */
741 iommu_handle_ppr_entry(iommu, entry);
742
743 /* Refresh ring-buffer information */
744 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
745 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
746 }
747 }
748
749 irqreturn_t amd_iommu_int_thread(int irq, void *data)
750 {
751 struct amd_iommu *iommu = (struct amd_iommu *) data;
752 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
753
754 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
755 /* Enable EVT and PPR interrupts again */
756 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
757 iommu->mmio_base + MMIO_STATUS_OFFSET);
758
759 if (status & MMIO_STATUS_EVT_INT_MASK) {
760 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
761 iommu_poll_events(iommu);
762 }
763
764 if (status & MMIO_STATUS_PPR_INT_MASK) {
765 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
766 iommu_poll_ppr_log(iommu);
767 }
768
769 /*
770 * Hardware bug: ERBT1312
771 * When re-enabling interrupt (by writing 1
772 * to clear the bit), the hardware might also try to set
773 * the interrupt bit in the event status register.
774 * In this scenario, the bit will be set, and disable
775 * subsequent interrupts.
776 *
777 * Workaround: The IOMMU driver should read back the
778 * status register and check if the interrupt bits are cleared.
779 * If not, driver will need to go through the interrupt handler
780 * again and re-clear the bits
781 */
782 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
783 }
784 return IRQ_HANDLED;
785 }
786
787 irqreturn_t amd_iommu_int_handler(int irq, void *data)
788 {
789 return IRQ_WAKE_THREAD;
790 }
791
792 /****************************************************************************
793 *
794 * IOMMU command queuing functions
795 *
796 ****************************************************************************/
797
798 static int wait_on_sem(volatile u64 *sem)
799 {
800 int i = 0;
801
802 while (*sem == 0 && i < LOOP_TIMEOUT) {
803 udelay(1);
804 i += 1;
805 }
806
807 if (i == LOOP_TIMEOUT) {
808 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
809 return -EIO;
810 }
811
812 return 0;
813 }
814
815 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
816 struct iommu_cmd *cmd,
817 u32 tail)
818 {
819 u8 *target;
820
821 target = iommu->cmd_buf + tail;
822 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
823
824 /* Copy command to buffer */
825 memcpy(target, cmd, sizeof(*cmd));
826
827 /* Tell the IOMMU about it */
828 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
829 }
830
831 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
832 {
833 WARN_ON(address & 0x7ULL);
834
835 memset(cmd, 0, sizeof(*cmd));
836 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
837 cmd->data[1] = upper_32_bits(__pa(address));
838 cmd->data[2] = 1;
839 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
840 }
841
842 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
843 {
844 memset(cmd, 0, sizeof(*cmd));
845 cmd->data[0] = devid;
846 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
847 }
848
849 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
850 size_t size, u16 domid, int pde)
851 {
852 u64 pages;
853 bool s;
854
855 pages = iommu_num_pages(address, size, PAGE_SIZE);
856 s = false;
857
858 if (pages > 1) {
859 /*
860 * If we have to flush more than one page, flush all
861 * TLB entries for this domain
862 */
863 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
864 s = true;
865 }
866
867 address &= PAGE_MASK;
868
869 memset(cmd, 0, sizeof(*cmd));
870 cmd->data[1] |= domid;
871 cmd->data[2] = lower_32_bits(address);
872 cmd->data[3] = upper_32_bits(address);
873 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
874 if (s) /* size bit - we flush more than one 4kb page */
875 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
876 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
877 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
878 }
879
880 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
881 u64 address, size_t size)
882 {
883 u64 pages;
884 bool s;
885
886 pages = iommu_num_pages(address, size, PAGE_SIZE);
887 s = false;
888
889 if (pages > 1) {
890 /*
891 * If we have to flush more than one page, flush all
892 * TLB entries for this domain
893 */
894 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
895 s = true;
896 }
897
898 address &= PAGE_MASK;
899
900 memset(cmd, 0, sizeof(*cmd));
901 cmd->data[0] = devid;
902 cmd->data[0] |= (qdep & 0xff) << 24;
903 cmd->data[1] = devid;
904 cmd->data[2] = lower_32_bits(address);
905 cmd->data[3] = upper_32_bits(address);
906 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
907 if (s)
908 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
909 }
910
911 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
912 u64 address, bool size)
913 {
914 memset(cmd, 0, sizeof(*cmd));
915
916 address &= ~(0xfffULL);
917
918 cmd->data[0] = pasid;
919 cmd->data[1] = domid;
920 cmd->data[2] = lower_32_bits(address);
921 cmd->data[3] = upper_32_bits(address);
922 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
923 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
924 if (size)
925 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
926 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
927 }
928
929 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
930 int qdep, u64 address, bool size)
931 {
932 memset(cmd, 0, sizeof(*cmd));
933
934 address &= ~(0xfffULL);
935
936 cmd->data[0] = devid;
937 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
938 cmd->data[0] |= (qdep & 0xff) << 24;
939 cmd->data[1] = devid;
940 cmd->data[1] |= (pasid & 0xff) << 16;
941 cmd->data[2] = lower_32_bits(address);
942 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
943 cmd->data[3] = upper_32_bits(address);
944 if (size)
945 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
946 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
947 }
948
949 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
950 int status, int tag, bool gn)
951 {
952 memset(cmd, 0, sizeof(*cmd));
953
954 cmd->data[0] = devid;
955 if (gn) {
956 cmd->data[1] = pasid;
957 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
958 }
959 cmd->data[3] = tag & 0x1ff;
960 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
961
962 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
963 }
964
965 static void build_inv_all(struct iommu_cmd *cmd)
966 {
967 memset(cmd, 0, sizeof(*cmd));
968 CMD_SET_TYPE(cmd, CMD_INV_ALL);
969 }
970
971 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
972 {
973 memset(cmd, 0, sizeof(*cmd));
974 cmd->data[0] = devid;
975 CMD_SET_TYPE(cmd, CMD_INV_IRT);
976 }
977
978 /*
979 * Writes the command to the IOMMUs command buffer and informs the
980 * hardware about the new command.
981 */
982 static int iommu_queue_command_sync(struct amd_iommu *iommu,
983 struct iommu_cmd *cmd,
984 bool sync)
985 {
986 u32 left, tail, head, next_tail;
987 unsigned long flags;
988
989 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
990
991 again:
992 spin_lock_irqsave(&iommu->lock, flags);
993
994 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
995 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
996 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
997 left = (head - next_tail) % iommu->cmd_buf_size;
998
999 if (left <= 2) {
1000 struct iommu_cmd sync_cmd;
1001 volatile u64 sem = 0;
1002 int ret;
1003
1004 build_completion_wait(&sync_cmd, (u64)&sem);
1005 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
1006
1007 spin_unlock_irqrestore(&iommu->lock, flags);
1008
1009 if ((ret = wait_on_sem(&sem)) != 0)
1010 return ret;
1011
1012 goto again;
1013 }
1014
1015 copy_cmd_to_buffer(iommu, cmd, tail);
1016
1017 /* We need to sync now to make sure all commands are processed */
1018 iommu->need_sync = sync;
1019
1020 spin_unlock_irqrestore(&iommu->lock, flags);
1021
1022 return 0;
1023 }
1024
1025 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1026 {
1027 return iommu_queue_command_sync(iommu, cmd, true);
1028 }
1029
1030 /*
1031 * This function queues a completion wait command into the command
1032 * buffer of an IOMMU
1033 */
1034 static int iommu_completion_wait(struct amd_iommu *iommu)
1035 {
1036 struct iommu_cmd cmd;
1037 volatile u64 sem = 0;
1038 int ret;
1039
1040 if (!iommu->need_sync)
1041 return 0;
1042
1043 build_completion_wait(&cmd, (u64)&sem);
1044
1045 ret = iommu_queue_command_sync(iommu, &cmd, false);
1046 if (ret)
1047 return ret;
1048
1049 return wait_on_sem(&sem);
1050 }
1051
1052 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1053 {
1054 struct iommu_cmd cmd;
1055
1056 build_inv_dte(&cmd, devid);
1057
1058 return iommu_queue_command(iommu, &cmd);
1059 }
1060
1061 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1062 {
1063 u32 devid;
1064
1065 for (devid = 0; devid <= 0xffff; ++devid)
1066 iommu_flush_dte(iommu, devid);
1067
1068 iommu_completion_wait(iommu);
1069 }
1070
1071 /*
1072 * This function uses heavy locking and may disable irqs for some time. But
1073 * this is no issue because it is only called during resume.
1074 */
1075 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1076 {
1077 u32 dom_id;
1078
1079 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1080 struct iommu_cmd cmd;
1081 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1082 dom_id, 1);
1083 iommu_queue_command(iommu, &cmd);
1084 }
1085
1086 iommu_completion_wait(iommu);
1087 }
1088
1089 static void iommu_flush_all(struct amd_iommu *iommu)
1090 {
1091 struct iommu_cmd cmd;
1092
1093 build_inv_all(&cmd);
1094
1095 iommu_queue_command(iommu, &cmd);
1096 iommu_completion_wait(iommu);
1097 }
1098
1099 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1100 {
1101 struct iommu_cmd cmd;
1102
1103 build_inv_irt(&cmd, devid);
1104
1105 iommu_queue_command(iommu, &cmd);
1106 }
1107
1108 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1109 {
1110 u32 devid;
1111
1112 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1113 iommu_flush_irt(iommu, devid);
1114
1115 iommu_completion_wait(iommu);
1116 }
1117
1118 void iommu_flush_all_caches(struct amd_iommu *iommu)
1119 {
1120 if (iommu_feature(iommu, FEATURE_IA)) {
1121 iommu_flush_all(iommu);
1122 } else {
1123 iommu_flush_dte_all(iommu);
1124 iommu_flush_irt_all(iommu);
1125 iommu_flush_tlb_all(iommu);
1126 }
1127 }
1128
1129 /*
1130 * Command send function for flushing on-device TLB
1131 */
1132 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1133 u64 address, size_t size)
1134 {
1135 struct amd_iommu *iommu;
1136 struct iommu_cmd cmd;
1137 int qdep;
1138
1139 qdep = dev_data->ats.qdep;
1140 iommu = amd_iommu_rlookup_table[dev_data->devid];
1141
1142 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1143
1144 return iommu_queue_command(iommu, &cmd);
1145 }
1146
1147 /*
1148 * Command send function for invalidating a device table entry
1149 */
1150 static int device_flush_dte(struct iommu_dev_data *dev_data)
1151 {
1152 struct amd_iommu *iommu;
1153 int ret;
1154
1155 iommu = amd_iommu_rlookup_table[dev_data->devid];
1156
1157 ret = iommu_flush_dte(iommu, dev_data->devid);
1158 if (ret)
1159 return ret;
1160
1161 if (dev_data->ats.enabled)
1162 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1163
1164 return ret;
1165 }
1166
1167 /*
1168 * TLB invalidation function which is called from the mapping functions.
1169 * It invalidates a single PTE if the range to flush is within a single
1170 * page. Otherwise it flushes the whole TLB of the IOMMU.
1171 */
1172 static void __domain_flush_pages(struct protection_domain *domain,
1173 u64 address, size_t size, int pde)
1174 {
1175 struct iommu_dev_data *dev_data;
1176 struct iommu_cmd cmd;
1177 int ret = 0, i;
1178
1179 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1180
1181 for (i = 0; i < amd_iommus_present; ++i) {
1182 if (!domain->dev_iommu[i])
1183 continue;
1184
1185 /*
1186 * Devices of this domain are behind this IOMMU
1187 * We need a TLB flush
1188 */
1189 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1190 }
1191
1192 list_for_each_entry(dev_data, &domain->dev_list, list) {
1193
1194 if (!dev_data->ats.enabled)
1195 continue;
1196
1197 ret |= device_flush_iotlb(dev_data, address, size);
1198 }
1199
1200 WARN_ON(ret);
1201 }
1202
1203 static void domain_flush_pages(struct protection_domain *domain,
1204 u64 address, size_t size)
1205 {
1206 __domain_flush_pages(domain, address, size, 0);
1207 }
1208
1209 /* Flush the whole IO/TLB for a given protection domain */
1210 static void domain_flush_tlb(struct protection_domain *domain)
1211 {
1212 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1213 }
1214
1215 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1216 static void domain_flush_tlb_pde(struct protection_domain *domain)
1217 {
1218 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1219 }
1220
1221 static void domain_flush_complete(struct protection_domain *domain)
1222 {
1223 int i;
1224
1225 for (i = 0; i < amd_iommus_present; ++i) {
1226 if (!domain->dev_iommu[i])
1227 continue;
1228
1229 /*
1230 * Devices of this domain are behind this IOMMU
1231 * We need to wait for completion of all commands.
1232 */
1233 iommu_completion_wait(amd_iommus[i]);
1234 }
1235 }
1236
1237
1238 /*
1239 * This function flushes the DTEs for all devices in domain
1240 */
1241 static void domain_flush_devices(struct protection_domain *domain)
1242 {
1243 struct iommu_dev_data *dev_data;
1244
1245 list_for_each_entry(dev_data, &domain->dev_list, list)
1246 device_flush_dte(dev_data);
1247 }
1248
1249 /****************************************************************************
1250 *
1251 * The functions below are used the create the page table mappings for
1252 * unity mapped regions.
1253 *
1254 ****************************************************************************/
1255
1256 /*
1257 * This function is used to add another level to an IO page table. Adding
1258 * another level increases the size of the address space by 9 bits to a size up
1259 * to 64 bits.
1260 */
1261 static bool increase_address_space(struct protection_domain *domain,
1262 gfp_t gfp)
1263 {
1264 u64 *pte;
1265
1266 if (domain->mode == PAGE_MODE_6_LEVEL)
1267 /* address space already 64 bit large */
1268 return false;
1269
1270 pte = (void *)get_zeroed_page(gfp);
1271 if (!pte)
1272 return false;
1273
1274 *pte = PM_LEVEL_PDE(domain->mode,
1275 virt_to_phys(domain->pt_root));
1276 domain->pt_root = pte;
1277 domain->mode += 1;
1278 domain->updated = true;
1279
1280 return true;
1281 }
1282
1283 static u64 *alloc_pte(struct protection_domain *domain,
1284 unsigned long address,
1285 unsigned long page_size,
1286 u64 **pte_page,
1287 gfp_t gfp)
1288 {
1289 int level, end_lvl;
1290 u64 *pte, *page;
1291
1292 BUG_ON(!is_power_of_2(page_size));
1293
1294 while (address > PM_LEVEL_SIZE(domain->mode))
1295 increase_address_space(domain, gfp);
1296
1297 level = domain->mode - 1;
1298 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1299 address = PAGE_SIZE_ALIGN(address, page_size);
1300 end_lvl = PAGE_SIZE_LEVEL(page_size);
1301
1302 while (level > end_lvl) {
1303 if (!IOMMU_PTE_PRESENT(*pte)) {
1304 page = (u64 *)get_zeroed_page(gfp);
1305 if (!page)
1306 return NULL;
1307 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1308 }
1309
1310 /* No level skipping support yet */
1311 if (PM_PTE_LEVEL(*pte) != level)
1312 return NULL;
1313
1314 level -= 1;
1315
1316 pte = IOMMU_PTE_PAGE(*pte);
1317
1318 if (pte_page && level == end_lvl)
1319 *pte_page = pte;
1320
1321 pte = &pte[PM_LEVEL_INDEX(level, address)];
1322 }
1323
1324 return pte;
1325 }
1326
1327 /*
1328 * This function checks if there is a PTE for a given dma address. If
1329 * there is one, it returns the pointer to it.
1330 */
1331 static u64 *fetch_pte(struct protection_domain *domain,
1332 unsigned long address,
1333 unsigned long *page_size)
1334 {
1335 int level;
1336 u64 *pte;
1337
1338 if (address > PM_LEVEL_SIZE(domain->mode))
1339 return NULL;
1340
1341 level = domain->mode - 1;
1342 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1343 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1344
1345 while (level > 0) {
1346
1347 /* Not Present */
1348 if (!IOMMU_PTE_PRESENT(*pte))
1349 return NULL;
1350
1351 /* Large PTE */
1352 if (PM_PTE_LEVEL(*pte) == 7 ||
1353 PM_PTE_LEVEL(*pte) == 0)
1354 break;
1355
1356 /* No level skipping support yet */
1357 if (PM_PTE_LEVEL(*pte) != level)
1358 return NULL;
1359
1360 level -= 1;
1361
1362 /* Walk to the next level */
1363 pte = IOMMU_PTE_PAGE(*pte);
1364 pte = &pte[PM_LEVEL_INDEX(level, address)];
1365 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1366 }
1367
1368 if (PM_PTE_LEVEL(*pte) == 0x07) {
1369 unsigned long pte_mask;
1370
1371 /*
1372 * If we have a series of large PTEs, make
1373 * sure to return a pointer to the first one.
1374 */
1375 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1376 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1377 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1378 }
1379
1380 return pte;
1381 }
1382
1383 /*
1384 * Generic mapping functions. It maps a physical address into a DMA
1385 * address space. It allocates the page table pages if necessary.
1386 * In the future it can be extended to a generic mapping function
1387 * supporting all features of AMD IOMMU page tables like level skipping
1388 * and full 64 bit address spaces.
1389 */
1390 static int iommu_map_page(struct protection_domain *dom,
1391 unsigned long bus_addr,
1392 unsigned long phys_addr,
1393 int prot,
1394 unsigned long page_size)
1395 {
1396 u64 __pte, *pte;
1397 int i, count;
1398
1399 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1400 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1401
1402 if (!(prot & IOMMU_PROT_MASK))
1403 return -EINVAL;
1404
1405 count = PAGE_SIZE_PTE_COUNT(page_size);
1406 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1407
1408 if (!pte)
1409 return -ENOMEM;
1410
1411 for (i = 0; i < count; ++i)
1412 if (IOMMU_PTE_PRESENT(pte[i]))
1413 return -EBUSY;
1414
1415 if (count > 1) {
1416 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1417 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1418 } else
1419 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1420
1421 if (prot & IOMMU_PROT_IR)
1422 __pte |= IOMMU_PTE_IR;
1423 if (prot & IOMMU_PROT_IW)
1424 __pte |= IOMMU_PTE_IW;
1425
1426 for (i = 0; i < count; ++i)
1427 pte[i] = __pte;
1428
1429 update_domain(dom);
1430
1431 return 0;
1432 }
1433
1434 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1435 unsigned long bus_addr,
1436 unsigned long page_size)
1437 {
1438 unsigned long long unmapped;
1439 unsigned long unmap_size;
1440 u64 *pte;
1441
1442 BUG_ON(!is_power_of_2(page_size));
1443
1444 unmapped = 0;
1445
1446 while (unmapped < page_size) {
1447
1448 pte = fetch_pte(dom, bus_addr, &unmap_size);
1449
1450 if (pte) {
1451 int i, count;
1452
1453 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1454 for (i = 0; i < count; i++)
1455 pte[i] = 0ULL;
1456 }
1457
1458 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1459 unmapped += unmap_size;
1460 }
1461
1462 BUG_ON(unmapped && !is_power_of_2(unmapped));
1463
1464 return unmapped;
1465 }
1466
1467 /*
1468 * This function checks if a specific unity mapping entry is needed for
1469 * this specific IOMMU.
1470 */
1471 static int iommu_for_unity_map(struct amd_iommu *iommu,
1472 struct unity_map_entry *entry)
1473 {
1474 u16 bdf, i;
1475
1476 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1477 bdf = amd_iommu_alias_table[i];
1478 if (amd_iommu_rlookup_table[bdf] == iommu)
1479 return 1;
1480 }
1481
1482 return 0;
1483 }
1484
1485 /*
1486 * This function actually applies the mapping to the page table of the
1487 * dma_ops domain.
1488 */
1489 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1490 struct unity_map_entry *e)
1491 {
1492 u64 addr;
1493 int ret;
1494
1495 for (addr = e->address_start; addr < e->address_end;
1496 addr += PAGE_SIZE) {
1497 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1498 PAGE_SIZE);
1499 if (ret)
1500 return ret;
1501 /*
1502 * if unity mapping is in aperture range mark the page
1503 * as allocated in the aperture
1504 */
1505 if (addr < dma_dom->aperture_size)
1506 __set_bit(addr >> PAGE_SHIFT,
1507 dma_dom->aperture[0]->bitmap);
1508 }
1509
1510 return 0;
1511 }
1512
1513 /*
1514 * Init the unity mappings for a specific IOMMU in the system
1515 *
1516 * Basically iterates over all unity mapping entries and applies them to
1517 * the default domain DMA of that IOMMU if necessary.
1518 */
1519 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1520 {
1521 struct unity_map_entry *entry;
1522 int ret;
1523
1524 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1525 if (!iommu_for_unity_map(iommu, entry))
1526 continue;
1527 ret = dma_ops_unity_map(iommu->default_dom, entry);
1528 if (ret)
1529 return ret;
1530 }
1531
1532 return 0;
1533 }
1534
1535 /*
1536 * Inits the unity mappings required for a specific device
1537 */
1538 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1539 u16 devid)
1540 {
1541 struct unity_map_entry *e;
1542 int ret;
1543
1544 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1545 if (!(devid >= e->devid_start && devid <= e->devid_end))
1546 continue;
1547 ret = dma_ops_unity_map(dma_dom, e);
1548 if (ret)
1549 return ret;
1550 }
1551
1552 return 0;
1553 }
1554
1555 /****************************************************************************
1556 *
1557 * The next functions belong to the address allocator for the dma_ops
1558 * interface functions. They work like the allocators in the other IOMMU
1559 * drivers. Its basically a bitmap which marks the allocated pages in
1560 * the aperture. Maybe it could be enhanced in the future to a more
1561 * efficient allocator.
1562 *
1563 ****************************************************************************/
1564
1565 /*
1566 * The address allocator core functions.
1567 *
1568 * called with domain->lock held
1569 */
1570
1571 /*
1572 * Used to reserve address ranges in the aperture (e.g. for exclusion
1573 * ranges.
1574 */
1575 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1576 unsigned long start_page,
1577 unsigned int pages)
1578 {
1579 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1580
1581 if (start_page + pages > last_page)
1582 pages = last_page - start_page;
1583
1584 for (i = start_page; i < start_page + pages; ++i) {
1585 int index = i / APERTURE_RANGE_PAGES;
1586 int page = i % APERTURE_RANGE_PAGES;
1587 __set_bit(page, dom->aperture[index]->bitmap);
1588 }
1589 }
1590
1591 /*
1592 * This function is used to add a new aperture range to an existing
1593 * aperture in case of dma_ops domain allocation or address allocation
1594 * failure.
1595 */
1596 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1597 bool populate, gfp_t gfp)
1598 {
1599 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1600 struct amd_iommu *iommu;
1601 unsigned long i, old_size, pte_pgsize;
1602
1603 #ifdef CONFIG_IOMMU_STRESS
1604 populate = false;
1605 #endif
1606
1607 if (index >= APERTURE_MAX_RANGES)
1608 return -ENOMEM;
1609
1610 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1611 if (!dma_dom->aperture[index])
1612 return -ENOMEM;
1613
1614 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1615 if (!dma_dom->aperture[index]->bitmap)
1616 goto out_free;
1617
1618 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1619
1620 if (populate) {
1621 unsigned long address = dma_dom->aperture_size;
1622 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1623 u64 *pte, *pte_page;
1624
1625 for (i = 0; i < num_ptes; ++i) {
1626 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1627 &pte_page, gfp);
1628 if (!pte)
1629 goto out_free;
1630
1631 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1632
1633 address += APERTURE_RANGE_SIZE / 64;
1634 }
1635 }
1636
1637 old_size = dma_dom->aperture_size;
1638 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1639
1640 /* Reserve address range used for MSI messages */
1641 if (old_size < MSI_ADDR_BASE_LO &&
1642 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1643 unsigned long spage;
1644 int pages;
1645
1646 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1647 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1648
1649 dma_ops_reserve_addresses(dma_dom, spage, pages);
1650 }
1651
1652 /* Initialize the exclusion range if necessary */
1653 for_each_iommu(iommu) {
1654 if (iommu->exclusion_start &&
1655 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1656 && iommu->exclusion_start < dma_dom->aperture_size) {
1657 unsigned long startpage;
1658 int pages = iommu_num_pages(iommu->exclusion_start,
1659 iommu->exclusion_length,
1660 PAGE_SIZE);
1661 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1662 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1663 }
1664 }
1665
1666 /*
1667 * Check for areas already mapped as present in the new aperture
1668 * range and mark those pages as reserved in the allocator. Such
1669 * mappings may already exist as a result of requested unity
1670 * mappings for devices.
1671 */
1672 for (i = dma_dom->aperture[index]->offset;
1673 i < dma_dom->aperture_size;
1674 i += pte_pgsize) {
1675 u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize);
1676 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1677 continue;
1678
1679 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT,
1680 pte_pgsize >> 12);
1681 }
1682
1683 update_domain(&dma_dom->domain);
1684
1685 return 0;
1686
1687 out_free:
1688 update_domain(&dma_dom->domain);
1689
1690 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1691
1692 kfree(dma_dom->aperture[index]);
1693 dma_dom->aperture[index] = NULL;
1694
1695 return -ENOMEM;
1696 }
1697
1698 static unsigned long dma_ops_area_alloc(struct device *dev,
1699 struct dma_ops_domain *dom,
1700 unsigned int pages,
1701 unsigned long align_mask,
1702 u64 dma_mask,
1703 unsigned long start)
1704 {
1705 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1706 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1707 int i = start >> APERTURE_RANGE_SHIFT;
1708 unsigned long boundary_size;
1709 unsigned long address = -1;
1710 unsigned long limit;
1711
1712 next_bit >>= PAGE_SHIFT;
1713
1714 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1715 PAGE_SIZE) >> PAGE_SHIFT;
1716
1717 for (;i < max_index; ++i) {
1718 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1719
1720 if (dom->aperture[i]->offset >= dma_mask)
1721 break;
1722
1723 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1724 dma_mask >> PAGE_SHIFT);
1725
1726 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1727 limit, next_bit, pages, 0,
1728 boundary_size, align_mask);
1729 if (address != -1) {
1730 address = dom->aperture[i]->offset +
1731 (address << PAGE_SHIFT);
1732 dom->next_address = address + (pages << PAGE_SHIFT);
1733 break;
1734 }
1735
1736 next_bit = 0;
1737 }
1738
1739 return address;
1740 }
1741
1742 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1743 struct dma_ops_domain *dom,
1744 unsigned int pages,
1745 unsigned long align_mask,
1746 u64 dma_mask)
1747 {
1748 unsigned long address;
1749
1750 #ifdef CONFIG_IOMMU_STRESS
1751 dom->next_address = 0;
1752 dom->need_flush = true;
1753 #endif
1754
1755 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1756 dma_mask, dom->next_address);
1757
1758 if (address == -1) {
1759 dom->next_address = 0;
1760 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1761 dma_mask, 0);
1762 dom->need_flush = true;
1763 }
1764
1765 if (unlikely(address == -1))
1766 address = DMA_ERROR_CODE;
1767
1768 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1769
1770 return address;
1771 }
1772
1773 /*
1774 * The address free function.
1775 *
1776 * called with domain->lock held
1777 */
1778 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1779 unsigned long address,
1780 unsigned int pages)
1781 {
1782 unsigned i = address >> APERTURE_RANGE_SHIFT;
1783 struct aperture_range *range = dom->aperture[i];
1784
1785 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1786
1787 #ifdef CONFIG_IOMMU_STRESS
1788 if (i < 4)
1789 return;
1790 #endif
1791
1792 if (address >= dom->next_address)
1793 dom->need_flush = true;
1794
1795 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1796
1797 bitmap_clear(range->bitmap, address, pages);
1798
1799 }
1800
1801 /****************************************************************************
1802 *
1803 * The next functions belong to the domain allocation. A domain is
1804 * allocated for every IOMMU as the default domain. If device isolation
1805 * is enabled, every device get its own domain. The most important thing
1806 * about domains is the page table mapping the DMA address space they
1807 * contain.
1808 *
1809 ****************************************************************************/
1810
1811 /*
1812 * This function adds a protection domain to the global protection domain list
1813 */
1814 static void add_domain_to_list(struct protection_domain *domain)
1815 {
1816 unsigned long flags;
1817
1818 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1819 list_add(&domain->list, &amd_iommu_pd_list);
1820 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1821 }
1822
1823 /*
1824 * This function removes a protection domain to the global
1825 * protection domain list
1826 */
1827 static void del_domain_from_list(struct protection_domain *domain)
1828 {
1829 unsigned long flags;
1830
1831 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1832 list_del(&domain->list);
1833 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1834 }
1835
1836 static u16 domain_id_alloc(void)
1837 {
1838 unsigned long flags;
1839 int id;
1840
1841 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1842 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1843 BUG_ON(id == 0);
1844 if (id > 0 && id < MAX_DOMAIN_ID)
1845 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1846 else
1847 id = 0;
1848 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1849
1850 return id;
1851 }
1852
1853 static void domain_id_free(int id)
1854 {
1855 unsigned long flags;
1856
1857 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1858 if (id > 0 && id < MAX_DOMAIN_ID)
1859 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1860 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1861 }
1862
1863 #define DEFINE_FREE_PT_FN(LVL, FN) \
1864 static void free_pt_##LVL (unsigned long __pt) \
1865 { \
1866 unsigned long p; \
1867 u64 *pt; \
1868 int i; \
1869 \
1870 pt = (u64 *)__pt; \
1871 \
1872 for (i = 0; i < 512; ++i) { \
1873 if (!IOMMU_PTE_PRESENT(pt[i])) \
1874 continue; \
1875 \
1876 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1877 FN(p); \
1878 } \
1879 free_page((unsigned long)pt); \
1880 }
1881
1882 DEFINE_FREE_PT_FN(l2, free_page)
1883 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1884 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1885 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1886 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1887
1888 static void free_pagetable(struct protection_domain *domain)
1889 {
1890 unsigned long root = (unsigned long)domain->pt_root;
1891
1892 switch (domain->mode) {
1893 case PAGE_MODE_NONE:
1894 break;
1895 case PAGE_MODE_1_LEVEL:
1896 free_page(root);
1897 break;
1898 case PAGE_MODE_2_LEVEL:
1899 free_pt_l2(root);
1900 break;
1901 case PAGE_MODE_3_LEVEL:
1902 free_pt_l3(root);
1903 break;
1904 case PAGE_MODE_4_LEVEL:
1905 free_pt_l4(root);
1906 break;
1907 case PAGE_MODE_5_LEVEL:
1908 free_pt_l5(root);
1909 break;
1910 case PAGE_MODE_6_LEVEL:
1911 free_pt_l6(root);
1912 break;
1913 default:
1914 BUG();
1915 }
1916 }
1917
1918 static void free_gcr3_tbl_level1(u64 *tbl)
1919 {
1920 u64 *ptr;
1921 int i;
1922
1923 for (i = 0; i < 512; ++i) {
1924 if (!(tbl[i] & GCR3_VALID))
1925 continue;
1926
1927 ptr = __va(tbl[i] & PAGE_MASK);
1928
1929 free_page((unsigned long)ptr);
1930 }
1931 }
1932
1933 static void free_gcr3_tbl_level2(u64 *tbl)
1934 {
1935 u64 *ptr;
1936 int i;
1937
1938 for (i = 0; i < 512; ++i) {
1939 if (!(tbl[i] & GCR3_VALID))
1940 continue;
1941
1942 ptr = __va(tbl[i] & PAGE_MASK);
1943
1944 free_gcr3_tbl_level1(ptr);
1945 }
1946 }
1947
1948 static void free_gcr3_table(struct protection_domain *domain)
1949 {
1950 if (domain->glx == 2)
1951 free_gcr3_tbl_level2(domain->gcr3_tbl);
1952 else if (domain->glx == 1)
1953 free_gcr3_tbl_level1(domain->gcr3_tbl);
1954 else if (domain->glx != 0)
1955 BUG();
1956
1957 free_page((unsigned long)domain->gcr3_tbl);
1958 }
1959
1960 /*
1961 * Free a domain, only used if something went wrong in the
1962 * allocation path and we need to free an already allocated page table
1963 */
1964 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1965 {
1966 int i;
1967
1968 if (!dom)
1969 return;
1970
1971 del_domain_from_list(&dom->domain);
1972
1973 free_pagetable(&dom->domain);
1974
1975 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1976 if (!dom->aperture[i])
1977 continue;
1978 free_page((unsigned long)dom->aperture[i]->bitmap);
1979 kfree(dom->aperture[i]);
1980 }
1981
1982 kfree(dom);
1983 }
1984
1985 /*
1986 * Allocates a new protection domain usable for the dma_ops functions.
1987 * It also initializes the page table and the address allocator data
1988 * structures required for the dma_ops interface
1989 */
1990 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1991 {
1992 struct dma_ops_domain *dma_dom;
1993
1994 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1995 if (!dma_dom)
1996 return NULL;
1997
1998 spin_lock_init(&dma_dom->domain.lock);
1999
2000 dma_dom->domain.id = domain_id_alloc();
2001 if (dma_dom->domain.id == 0)
2002 goto free_dma_dom;
2003 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
2004 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
2005 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2006 dma_dom->domain.flags = PD_DMA_OPS_MASK;
2007 dma_dom->domain.priv = dma_dom;
2008 if (!dma_dom->domain.pt_root)
2009 goto free_dma_dom;
2010
2011 dma_dom->need_flush = false;
2012 dma_dom->target_dev = 0xffff;
2013
2014 add_domain_to_list(&dma_dom->domain);
2015
2016 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
2017 goto free_dma_dom;
2018
2019 /*
2020 * mark the first page as allocated so we never return 0 as
2021 * a valid dma-address. So we can use 0 as error value
2022 */
2023 dma_dom->aperture[0]->bitmap[0] = 1;
2024 dma_dom->next_address = 0;
2025
2026
2027 return dma_dom;
2028
2029 free_dma_dom:
2030 dma_ops_domain_free(dma_dom);
2031
2032 return NULL;
2033 }
2034
2035 /*
2036 * little helper function to check whether a given protection domain is a
2037 * dma_ops domain
2038 */
2039 static bool dma_ops_domain(struct protection_domain *domain)
2040 {
2041 return domain->flags & PD_DMA_OPS_MASK;
2042 }
2043
2044 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
2045 {
2046 u64 pte_root = 0;
2047 u64 flags = 0;
2048
2049 if (domain->mode != PAGE_MODE_NONE)
2050 pte_root = virt_to_phys(domain->pt_root);
2051
2052 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2053 << DEV_ENTRY_MODE_SHIFT;
2054 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
2055
2056 flags = amd_iommu_dev_table[devid].data[1];
2057
2058 if (ats)
2059 flags |= DTE_FLAG_IOTLB;
2060
2061 if (domain->flags & PD_IOMMUV2_MASK) {
2062 u64 gcr3 = __pa(domain->gcr3_tbl);
2063 u64 glx = domain->glx;
2064 u64 tmp;
2065
2066 pte_root |= DTE_FLAG_GV;
2067 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2068
2069 /* First mask out possible old values for GCR3 table */
2070 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2071 flags &= ~tmp;
2072
2073 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2074 flags &= ~tmp;
2075
2076 /* Encode GCR3 table into DTE */
2077 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2078 pte_root |= tmp;
2079
2080 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2081 flags |= tmp;
2082
2083 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2084 flags |= tmp;
2085 }
2086
2087 flags &= ~(0xffffUL);
2088 flags |= domain->id;
2089
2090 amd_iommu_dev_table[devid].data[1] = flags;
2091 amd_iommu_dev_table[devid].data[0] = pte_root;
2092 }
2093
2094 static void clear_dte_entry(u16 devid)
2095 {
2096 /* remove entry from the device table seen by the hardware */
2097 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2098 amd_iommu_dev_table[devid].data[1] = 0;
2099
2100 amd_iommu_apply_erratum_63(devid);
2101 }
2102
2103 static void do_attach(struct iommu_dev_data *dev_data,
2104 struct protection_domain *domain)
2105 {
2106 struct amd_iommu *iommu;
2107 bool ats;
2108
2109 iommu = amd_iommu_rlookup_table[dev_data->devid];
2110 ats = dev_data->ats.enabled;
2111
2112 /* Update data structures */
2113 dev_data->domain = domain;
2114 list_add(&dev_data->list, &domain->dev_list);
2115 set_dte_entry(dev_data->devid, domain, ats);
2116
2117 /* Do reference counting */
2118 domain->dev_iommu[iommu->index] += 1;
2119 domain->dev_cnt += 1;
2120
2121 /* Flush the DTE entry */
2122 device_flush_dte(dev_data);
2123 }
2124
2125 static void do_detach(struct iommu_dev_data *dev_data)
2126 {
2127 struct amd_iommu *iommu;
2128
2129 iommu = amd_iommu_rlookup_table[dev_data->devid];
2130
2131 /* decrease reference counters */
2132 dev_data->domain->dev_iommu[iommu->index] -= 1;
2133 dev_data->domain->dev_cnt -= 1;
2134
2135 /* Update data structures */
2136 dev_data->domain = NULL;
2137 list_del(&dev_data->list);
2138 clear_dte_entry(dev_data->devid);
2139
2140 /* Flush the DTE entry */
2141 device_flush_dte(dev_data);
2142 }
2143
2144 /*
2145 * If a device is not yet associated with a domain, this function does
2146 * assigns it visible for the hardware
2147 */
2148 static int __attach_device(struct iommu_dev_data *dev_data,
2149 struct protection_domain *domain)
2150 {
2151 struct iommu_dev_data *head, *entry;
2152 int ret;
2153
2154 /* lock domain */
2155 spin_lock(&domain->lock);
2156
2157 head = dev_data;
2158
2159 if (head->alias_data != NULL)
2160 head = head->alias_data;
2161
2162 /* Now we have the root of the alias group, if any */
2163
2164 ret = -EBUSY;
2165 if (head->domain != NULL)
2166 goto out_unlock;
2167
2168 /* Attach alias group root */
2169 do_attach(head, domain);
2170
2171 /* Attach other devices in the alias group */
2172 list_for_each_entry(entry, &head->alias_list, alias_list)
2173 do_attach(entry, domain);
2174
2175 ret = 0;
2176
2177 out_unlock:
2178
2179 /* ready */
2180 spin_unlock(&domain->lock);
2181
2182 return ret;
2183 }
2184
2185
2186 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2187 {
2188 pci_disable_ats(pdev);
2189 pci_disable_pri(pdev);
2190 pci_disable_pasid(pdev);
2191 }
2192
2193 /* FIXME: Change generic reset-function to do the same */
2194 static int pri_reset_while_enabled(struct pci_dev *pdev)
2195 {
2196 u16 control;
2197 int pos;
2198
2199 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2200 if (!pos)
2201 return -EINVAL;
2202
2203 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2204 control |= PCI_PRI_CTRL_RESET;
2205 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2206
2207 return 0;
2208 }
2209
2210 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2211 {
2212 bool reset_enable;
2213 int reqs, ret;
2214
2215 /* FIXME: Hardcode number of outstanding requests for now */
2216 reqs = 32;
2217 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2218 reqs = 1;
2219 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2220
2221 /* Only allow access to user-accessible pages */
2222 ret = pci_enable_pasid(pdev, 0);
2223 if (ret)
2224 goto out_err;
2225
2226 /* First reset the PRI state of the device */
2227 ret = pci_reset_pri(pdev);
2228 if (ret)
2229 goto out_err;
2230
2231 /* Enable PRI */
2232 ret = pci_enable_pri(pdev, reqs);
2233 if (ret)
2234 goto out_err;
2235
2236 if (reset_enable) {
2237 ret = pri_reset_while_enabled(pdev);
2238 if (ret)
2239 goto out_err;
2240 }
2241
2242 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2243 if (ret)
2244 goto out_err;
2245
2246 return 0;
2247
2248 out_err:
2249 pci_disable_pri(pdev);
2250 pci_disable_pasid(pdev);
2251
2252 return ret;
2253 }
2254
2255 /* FIXME: Move this to PCI code */
2256 #define PCI_PRI_TLP_OFF (1 << 15)
2257
2258 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2259 {
2260 u16 status;
2261 int pos;
2262
2263 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2264 if (!pos)
2265 return false;
2266
2267 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2268
2269 return (status & PCI_PRI_TLP_OFF) ? true : false;
2270 }
2271
2272 /*
2273 * If a device is not yet associated with a domain, this function
2274 * assigns it visible for the hardware
2275 */
2276 static int attach_device(struct device *dev,
2277 struct protection_domain *domain)
2278 {
2279 struct pci_dev *pdev = to_pci_dev(dev);
2280 struct iommu_dev_data *dev_data;
2281 unsigned long flags;
2282 int ret;
2283
2284 dev_data = get_dev_data(dev);
2285
2286 if (domain->flags & PD_IOMMUV2_MASK) {
2287 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2288 return -EINVAL;
2289
2290 if (pdev_iommuv2_enable(pdev) != 0)
2291 return -EINVAL;
2292
2293 dev_data->ats.enabled = true;
2294 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2295 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2296 } else if (amd_iommu_iotlb_sup &&
2297 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2298 dev_data->ats.enabled = true;
2299 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2300 }
2301
2302 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2303 ret = __attach_device(dev_data, domain);
2304 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2305
2306 /*
2307 * We might boot into a crash-kernel here. The crashed kernel
2308 * left the caches in the IOMMU dirty. So we have to flush
2309 * here to evict all dirty stuff.
2310 */
2311 domain_flush_tlb_pde(domain);
2312
2313 return ret;
2314 }
2315
2316 /*
2317 * Removes a device from a protection domain (unlocked)
2318 */
2319 static void __detach_device(struct iommu_dev_data *dev_data)
2320 {
2321 struct iommu_dev_data *head, *entry;
2322 struct protection_domain *domain;
2323 unsigned long flags;
2324
2325 BUG_ON(!dev_data->domain);
2326
2327 domain = dev_data->domain;
2328
2329 spin_lock_irqsave(&domain->lock, flags);
2330
2331 head = dev_data;
2332 if (head->alias_data != NULL)
2333 head = head->alias_data;
2334
2335 list_for_each_entry(entry, &head->alias_list, alias_list)
2336 do_detach(entry);
2337
2338 do_detach(head);
2339
2340 spin_unlock_irqrestore(&domain->lock, flags);
2341
2342 /*
2343 * If we run in passthrough mode the device must be assigned to the
2344 * passthrough domain if it is detached from any other domain.
2345 * Make sure we can deassign from the pt_domain itself.
2346 */
2347 if (dev_data->passthrough &&
2348 (dev_data->domain == NULL && domain != pt_domain))
2349 __attach_device(dev_data, pt_domain);
2350 }
2351
2352 /*
2353 * Removes a device from a protection domain (with devtable_lock held)
2354 */
2355 static void detach_device(struct device *dev)
2356 {
2357 struct protection_domain *domain;
2358 struct iommu_dev_data *dev_data;
2359 unsigned long flags;
2360
2361 dev_data = get_dev_data(dev);
2362 domain = dev_data->domain;
2363
2364 /* lock device table */
2365 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2366 __detach_device(dev_data);
2367 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2368
2369 if (domain->flags & PD_IOMMUV2_MASK)
2370 pdev_iommuv2_disable(to_pci_dev(dev));
2371 else if (dev_data->ats.enabled)
2372 pci_disable_ats(to_pci_dev(dev));
2373
2374 dev_data->ats.enabled = false;
2375 }
2376
2377 /*
2378 * Find out the protection domain structure for a given PCI device. This
2379 * will give us the pointer to the page table root for example.
2380 */
2381 static struct protection_domain *domain_for_device(struct device *dev)
2382 {
2383 struct iommu_dev_data *dev_data;
2384 struct protection_domain *dom = NULL;
2385 unsigned long flags;
2386
2387 dev_data = get_dev_data(dev);
2388
2389 if (dev_data->domain)
2390 return dev_data->domain;
2391
2392 if (dev_data->alias_data != NULL) {
2393 struct iommu_dev_data *alias_data = dev_data->alias_data;
2394
2395 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2396 if (alias_data->domain != NULL) {
2397 __attach_device(dev_data, alias_data->domain);
2398 dom = alias_data->domain;
2399 }
2400 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2401 }
2402
2403 return dom;
2404 }
2405
2406 static int device_change_notifier(struct notifier_block *nb,
2407 unsigned long action, void *data)
2408 {
2409 struct dma_ops_domain *dma_domain;
2410 struct protection_domain *domain;
2411 struct iommu_dev_data *dev_data;
2412 struct device *dev = data;
2413 struct amd_iommu *iommu;
2414 unsigned long flags;
2415 u16 devid;
2416
2417 if (!check_device(dev))
2418 return 0;
2419
2420 devid = get_device_id(dev);
2421 iommu = amd_iommu_rlookup_table[devid];
2422 dev_data = get_dev_data(dev);
2423
2424 switch (action) {
2425 case BUS_NOTIFY_ADD_DEVICE:
2426
2427 iommu_init_device(dev);
2428 init_iommu_group(dev);
2429
2430 /*
2431 * dev_data is still NULL and
2432 * got initialized in iommu_init_device
2433 */
2434 dev_data = get_dev_data(dev);
2435
2436 if (iommu_pass_through || dev_data->iommu_v2) {
2437 dev_data->passthrough = true;
2438 attach_device(dev, pt_domain);
2439 break;
2440 }
2441
2442 domain = domain_for_device(dev);
2443
2444 /* allocate a protection domain if a device is added */
2445 dma_domain = find_protection_domain(devid);
2446 if (!dma_domain) {
2447 dma_domain = dma_ops_domain_alloc();
2448 if (!dma_domain)
2449 goto out;
2450 dma_domain->target_dev = devid;
2451
2452 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2453 list_add_tail(&dma_domain->list, &iommu_pd_list);
2454 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2455 }
2456
2457 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2458
2459 break;
2460 case BUS_NOTIFY_REMOVED_DEVICE:
2461
2462 iommu_uninit_device(dev);
2463
2464 default:
2465 goto out;
2466 }
2467
2468 iommu_completion_wait(iommu);
2469
2470 out:
2471 return 0;
2472 }
2473
2474 static struct notifier_block device_nb = {
2475 .notifier_call = device_change_notifier,
2476 };
2477
2478 void amd_iommu_init_notifier(void)
2479 {
2480 bus_register_notifier(&pci_bus_type, &device_nb);
2481 }
2482
2483 /*****************************************************************************
2484 *
2485 * The next functions belong to the dma_ops mapping/unmapping code.
2486 *
2487 *****************************************************************************/
2488
2489 /*
2490 * In the dma_ops path we only have the struct device. This function
2491 * finds the corresponding IOMMU, the protection domain and the
2492 * requestor id for a given device.
2493 * If the device is not yet associated with a domain this is also done
2494 * in this function.
2495 */
2496 static struct protection_domain *get_domain(struct device *dev)
2497 {
2498 struct protection_domain *domain;
2499 struct dma_ops_domain *dma_dom;
2500 u16 devid = get_device_id(dev);
2501
2502 if (!check_device(dev))
2503 return ERR_PTR(-EINVAL);
2504
2505 domain = domain_for_device(dev);
2506 if (domain != NULL && !dma_ops_domain(domain))
2507 return ERR_PTR(-EBUSY);
2508
2509 if (domain != NULL)
2510 return domain;
2511
2512 /* Device not bound yet - bind it */
2513 dma_dom = find_protection_domain(devid);
2514 if (!dma_dom)
2515 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2516 attach_device(dev, &dma_dom->domain);
2517 DUMP_printk("Using protection domain %d for device %s\n",
2518 dma_dom->domain.id, dev_name(dev));
2519
2520 return &dma_dom->domain;
2521 }
2522
2523 static void update_device_table(struct protection_domain *domain)
2524 {
2525 struct iommu_dev_data *dev_data;
2526
2527 list_for_each_entry(dev_data, &domain->dev_list, list)
2528 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2529 }
2530
2531 static void update_domain(struct protection_domain *domain)
2532 {
2533 if (!domain->updated)
2534 return;
2535
2536 update_device_table(domain);
2537
2538 domain_flush_devices(domain);
2539 domain_flush_tlb_pde(domain);
2540
2541 domain->updated = false;
2542 }
2543
2544 /*
2545 * This function fetches the PTE for a given address in the aperture
2546 */
2547 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2548 unsigned long address)
2549 {
2550 struct aperture_range *aperture;
2551 u64 *pte, *pte_page;
2552
2553 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2554 if (!aperture)
2555 return NULL;
2556
2557 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2558 if (!pte) {
2559 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2560 GFP_ATOMIC);
2561 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2562 } else
2563 pte += PM_LEVEL_INDEX(0, address);
2564
2565 update_domain(&dom->domain);
2566
2567 return pte;
2568 }
2569
2570 /*
2571 * This is the generic map function. It maps one 4kb page at paddr to
2572 * the given address in the DMA address space for the domain.
2573 */
2574 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2575 unsigned long address,
2576 phys_addr_t paddr,
2577 int direction)
2578 {
2579 u64 *pte, __pte;
2580
2581 WARN_ON(address > dom->aperture_size);
2582
2583 paddr &= PAGE_MASK;
2584
2585 pte = dma_ops_get_pte(dom, address);
2586 if (!pte)
2587 return DMA_ERROR_CODE;
2588
2589 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2590
2591 if (direction == DMA_TO_DEVICE)
2592 __pte |= IOMMU_PTE_IR;
2593 else if (direction == DMA_FROM_DEVICE)
2594 __pte |= IOMMU_PTE_IW;
2595 else if (direction == DMA_BIDIRECTIONAL)
2596 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2597
2598 WARN_ON(*pte);
2599
2600 *pte = __pte;
2601
2602 return (dma_addr_t)address;
2603 }
2604
2605 /*
2606 * The generic unmapping function for on page in the DMA address space.
2607 */
2608 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2609 unsigned long address)
2610 {
2611 struct aperture_range *aperture;
2612 u64 *pte;
2613
2614 if (address >= dom->aperture_size)
2615 return;
2616
2617 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2618 if (!aperture)
2619 return;
2620
2621 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2622 if (!pte)
2623 return;
2624
2625 pte += PM_LEVEL_INDEX(0, address);
2626
2627 WARN_ON(!*pte);
2628
2629 *pte = 0ULL;
2630 }
2631
2632 /*
2633 * This function contains common code for mapping of a physically
2634 * contiguous memory region into DMA address space. It is used by all
2635 * mapping functions provided with this IOMMU driver.
2636 * Must be called with the domain lock held.
2637 */
2638 static dma_addr_t __map_single(struct device *dev,
2639 struct dma_ops_domain *dma_dom,
2640 phys_addr_t paddr,
2641 size_t size,
2642 int dir,
2643 bool align,
2644 u64 dma_mask)
2645 {
2646 dma_addr_t offset = paddr & ~PAGE_MASK;
2647 dma_addr_t address, start, ret;
2648 unsigned int pages;
2649 unsigned long align_mask = 0;
2650 int i;
2651
2652 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2653 paddr &= PAGE_MASK;
2654
2655 INC_STATS_COUNTER(total_map_requests);
2656
2657 if (pages > 1)
2658 INC_STATS_COUNTER(cross_page);
2659
2660 if (align)
2661 align_mask = (1UL << get_order(size)) - 1;
2662
2663 retry:
2664 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2665 dma_mask);
2666 if (unlikely(address == DMA_ERROR_CODE)) {
2667 /*
2668 * setting next_address here will let the address
2669 * allocator only scan the new allocated range in the
2670 * first run. This is a small optimization.
2671 */
2672 dma_dom->next_address = dma_dom->aperture_size;
2673
2674 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2675 goto out;
2676
2677 /*
2678 * aperture was successfully enlarged by 128 MB, try
2679 * allocation again
2680 */
2681 goto retry;
2682 }
2683
2684 start = address;
2685 for (i = 0; i < pages; ++i) {
2686 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2687 if (ret == DMA_ERROR_CODE)
2688 goto out_unmap;
2689
2690 paddr += PAGE_SIZE;
2691 start += PAGE_SIZE;
2692 }
2693 address += offset;
2694
2695 ADD_STATS_COUNTER(alloced_io_mem, size);
2696
2697 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2698 domain_flush_tlb(&dma_dom->domain);
2699 dma_dom->need_flush = false;
2700 } else if (unlikely(amd_iommu_np_cache))
2701 domain_flush_pages(&dma_dom->domain, address, size);
2702
2703 out:
2704 return address;
2705
2706 out_unmap:
2707
2708 for (--i; i >= 0; --i) {
2709 start -= PAGE_SIZE;
2710 dma_ops_domain_unmap(dma_dom, start);
2711 }
2712
2713 dma_ops_free_addresses(dma_dom, address, pages);
2714
2715 return DMA_ERROR_CODE;
2716 }
2717
2718 /*
2719 * Does the reverse of the __map_single function. Must be called with
2720 * the domain lock held too
2721 */
2722 static void __unmap_single(struct dma_ops_domain *dma_dom,
2723 dma_addr_t dma_addr,
2724 size_t size,
2725 int dir)
2726 {
2727 dma_addr_t flush_addr;
2728 dma_addr_t i, start;
2729 unsigned int pages;
2730
2731 if ((dma_addr == DMA_ERROR_CODE) ||
2732 (dma_addr + size > dma_dom->aperture_size))
2733 return;
2734
2735 flush_addr = dma_addr;
2736 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2737 dma_addr &= PAGE_MASK;
2738 start = dma_addr;
2739
2740 for (i = 0; i < pages; ++i) {
2741 dma_ops_domain_unmap(dma_dom, start);
2742 start += PAGE_SIZE;
2743 }
2744
2745 SUB_STATS_COUNTER(alloced_io_mem, size);
2746
2747 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2748
2749 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2750 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2751 dma_dom->need_flush = false;
2752 }
2753 }
2754
2755 /*
2756 * The exported map_single function for dma_ops.
2757 */
2758 static dma_addr_t map_page(struct device *dev, struct page *page,
2759 unsigned long offset, size_t size,
2760 enum dma_data_direction dir,
2761 struct dma_attrs *attrs)
2762 {
2763 unsigned long flags;
2764 struct protection_domain *domain;
2765 dma_addr_t addr;
2766 u64 dma_mask;
2767 phys_addr_t paddr = page_to_phys(page) + offset;
2768
2769 INC_STATS_COUNTER(cnt_map_single);
2770
2771 domain = get_domain(dev);
2772 if (PTR_ERR(domain) == -EINVAL)
2773 return (dma_addr_t)paddr;
2774 else if (IS_ERR(domain))
2775 return DMA_ERROR_CODE;
2776
2777 dma_mask = *dev->dma_mask;
2778
2779 spin_lock_irqsave(&domain->lock, flags);
2780
2781 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2782 dma_mask);
2783 if (addr == DMA_ERROR_CODE)
2784 goto out;
2785
2786 domain_flush_complete(domain);
2787
2788 out:
2789 spin_unlock_irqrestore(&domain->lock, flags);
2790
2791 return addr;
2792 }
2793
2794 /*
2795 * The exported unmap_single function for dma_ops.
2796 */
2797 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2798 enum dma_data_direction dir, struct dma_attrs *attrs)
2799 {
2800 unsigned long flags;
2801 struct protection_domain *domain;
2802
2803 INC_STATS_COUNTER(cnt_unmap_single);
2804
2805 domain = get_domain(dev);
2806 if (IS_ERR(domain))
2807 return;
2808
2809 spin_lock_irqsave(&domain->lock, flags);
2810
2811 __unmap_single(domain->priv, dma_addr, size, dir);
2812
2813 domain_flush_complete(domain);
2814
2815 spin_unlock_irqrestore(&domain->lock, flags);
2816 }
2817
2818 /*
2819 * The exported map_sg function for dma_ops (handles scatter-gather
2820 * lists).
2821 */
2822 static int map_sg(struct device *dev, struct scatterlist *sglist,
2823 int nelems, enum dma_data_direction dir,
2824 struct dma_attrs *attrs)
2825 {
2826 unsigned long flags;
2827 struct protection_domain *domain;
2828 int i;
2829 struct scatterlist *s;
2830 phys_addr_t paddr;
2831 int mapped_elems = 0;
2832 u64 dma_mask;
2833
2834 INC_STATS_COUNTER(cnt_map_sg);
2835
2836 domain = get_domain(dev);
2837 if (IS_ERR(domain))
2838 return 0;
2839
2840 dma_mask = *dev->dma_mask;
2841
2842 spin_lock_irqsave(&domain->lock, flags);
2843
2844 for_each_sg(sglist, s, nelems, i) {
2845 paddr = sg_phys(s);
2846
2847 s->dma_address = __map_single(dev, domain->priv,
2848 paddr, s->length, dir, false,
2849 dma_mask);
2850
2851 if (s->dma_address) {
2852 s->dma_length = s->length;
2853 mapped_elems++;
2854 } else
2855 goto unmap;
2856 }
2857
2858 domain_flush_complete(domain);
2859
2860 out:
2861 spin_unlock_irqrestore(&domain->lock, flags);
2862
2863 return mapped_elems;
2864 unmap:
2865 for_each_sg(sglist, s, mapped_elems, i) {
2866 if (s->dma_address)
2867 __unmap_single(domain->priv, s->dma_address,
2868 s->dma_length, dir);
2869 s->dma_address = s->dma_length = 0;
2870 }
2871
2872 mapped_elems = 0;
2873
2874 goto out;
2875 }
2876
2877 /*
2878 * The exported map_sg function for dma_ops (handles scatter-gather
2879 * lists).
2880 */
2881 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2882 int nelems, enum dma_data_direction dir,
2883 struct dma_attrs *attrs)
2884 {
2885 unsigned long flags;
2886 struct protection_domain *domain;
2887 struct scatterlist *s;
2888 int i;
2889
2890 INC_STATS_COUNTER(cnt_unmap_sg);
2891
2892 domain = get_domain(dev);
2893 if (IS_ERR(domain))
2894 return;
2895
2896 spin_lock_irqsave(&domain->lock, flags);
2897
2898 for_each_sg(sglist, s, nelems, i) {
2899 __unmap_single(domain->priv, s->dma_address,
2900 s->dma_length, dir);
2901 s->dma_address = s->dma_length = 0;
2902 }
2903
2904 domain_flush_complete(domain);
2905
2906 spin_unlock_irqrestore(&domain->lock, flags);
2907 }
2908
2909 /*
2910 * The exported alloc_coherent function for dma_ops.
2911 */
2912 static void *alloc_coherent(struct device *dev, size_t size,
2913 dma_addr_t *dma_addr, gfp_t flag,
2914 struct dma_attrs *attrs)
2915 {
2916 u64 dma_mask = dev->coherent_dma_mask;
2917 struct protection_domain *domain;
2918 unsigned long flags;
2919 struct page *page;
2920
2921 INC_STATS_COUNTER(cnt_alloc_coherent);
2922
2923 domain = get_domain(dev);
2924 if (PTR_ERR(domain) == -EINVAL) {
2925 page = alloc_pages(flag, get_order(size));
2926 *dma_addr = page_to_phys(page);
2927 return page_address(page);
2928 } else if (IS_ERR(domain))
2929 return NULL;
2930
2931 size = PAGE_ALIGN(size);
2932 dma_mask = dev->coherent_dma_mask;
2933 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2934
2935 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2936 if (!page) {
2937 if (!(flag & __GFP_WAIT))
2938 return NULL;
2939
2940 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2941 get_order(size));
2942 if (!page)
2943 return NULL;
2944 }
2945
2946 if (!dma_mask)
2947 dma_mask = *dev->dma_mask;
2948
2949 spin_lock_irqsave(&domain->lock, flags);
2950
2951 *dma_addr = __map_single(dev, domain->priv, page_to_phys(page),
2952 size, DMA_BIDIRECTIONAL, true, dma_mask);
2953
2954 if (*dma_addr == DMA_ERROR_CODE) {
2955 spin_unlock_irqrestore(&domain->lock, flags);
2956 goto out_free;
2957 }
2958
2959 domain_flush_complete(domain);
2960
2961 spin_unlock_irqrestore(&domain->lock, flags);
2962
2963 return page_address(page);
2964
2965 out_free:
2966
2967 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2968 __free_pages(page, get_order(size));
2969
2970 return NULL;
2971 }
2972
2973 /*
2974 * The exported free_coherent function for dma_ops.
2975 */
2976 static void free_coherent(struct device *dev, size_t size,
2977 void *virt_addr, dma_addr_t dma_addr,
2978 struct dma_attrs *attrs)
2979 {
2980 struct protection_domain *domain;
2981 unsigned long flags;
2982 struct page *page;
2983
2984 INC_STATS_COUNTER(cnt_free_coherent);
2985
2986 page = virt_to_page(virt_addr);
2987 size = PAGE_ALIGN(size);
2988
2989 domain = get_domain(dev);
2990 if (IS_ERR(domain))
2991 goto free_mem;
2992
2993 spin_lock_irqsave(&domain->lock, flags);
2994
2995 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2996
2997 domain_flush_complete(domain);
2998
2999 spin_unlock_irqrestore(&domain->lock, flags);
3000
3001 free_mem:
3002 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3003 __free_pages(page, get_order(size));
3004 }
3005
3006 /*
3007 * This function is called by the DMA layer to find out if we can handle a
3008 * particular device. It is part of the dma_ops.
3009 */
3010 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
3011 {
3012 return check_device(dev);
3013 }
3014
3015 /*
3016 * The function for pre-allocating protection domains.
3017 *
3018 * If the driver core informs the DMA layer if a driver grabs a device
3019 * we don't need to preallocate the protection domains anymore.
3020 * For now we have to.
3021 */
3022 static void __init prealloc_protection_domains(void)
3023 {
3024 struct iommu_dev_data *dev_data;
3025 struct dma_ops_domain *dma_dom;
3026 struct pci_dev *dev = NULL;
3027 u16 devid;
3028
3029 for_each_pci_dev(dev) {
3030
3031 /* Do we handle this device? */
3032 if (!check_device(&dev->dev))
3033 continue;
3034
3035 dev_data = get_dev_data(&dev->dev);
3036 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
3037 /* Make sure passthrough domain is allocated */
3038 alloc_passthrough_domain();
3039 dev_data->passthrough = true;
3040 attach_device(&dev->dev, pt_domain);
3041 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
3042 dev_name(&dev->dev));
3043 }
3044
3045 /* Is there already any domain for it? */
3046 if (domain_for_device(&dev->dev))
3047 continue;
3048
3049 devid = get_device_id(&dev->dev);
3050
3051 dma_dom = dma_ops_domain_alloc();
3052 if (!dma_dom)
3053 continue;
3054 init_unity_mappings_for_device(dma_dom, devid);
3055 dma_dom->target_dev = devid;
3056
3057 attach_device(&dev->dev, &dma_dom->domain);
3058
3059 list_add_tail(&dma_dom->list, &iommu_pd_list);
3060 }
3061 }
3062
3063 static struct dma_map_ops amd_iommu_dma_ops = {
3064 .alloc = alloc_coherent,
3065 .free = free_coherent,
3066 .map_page = map_page,
3067 .unmap_page = unmap_page,
3068 .map_sg = map_sg,
3069 .unmap_sg = unmap_sg,
3070 .dma_supported = amd_iommu_dma_supported,
3071 };
3072
3073 static unsigned device_dma_ops_init(void)
3074 {
3075 struct iommu_dev_data *dev_data;
3076 struct pci_dev *pdev = NULL;
3077 unsigned unhandled = 0;
3078
3079 for_each_pci_dev(pdev) {
3080 if (!check_device(&pdev->dev)) {
3081
3082 iommu_ignore_device(&pdev->dev);
3083
3084 unhandled += 1;
3085 continue;
3086 }
3087
3088 dev_data = get_dev_data(&pdev->dev);
3089
3090 if (!dev_data->passthrough)
3091 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
3092 else
3093 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
3094 }
3095
3096 return unhandled;
3097 }
3098
3099 /*
3100 * The function which clues the AMD IOMMU driver into dma_ops.
3101 */
3102
3103 void __init amd_iommu_init_api(void)
3104 {
3105 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
3106 }
3107
3108 int __init amd_iommu_init_dma_ops(void)
3109 {
3110 struct amd_iommu *iommu;
3111 int ret, unhandled;
3112
3113 /*
3114 * first allocate a default protection domain for every IOMMU we
3115 * found in the system. Devices not assigned to any other
3116 * protection domain will be assigned to the default one.
3117 */
3118 for_each_iommu(iommu) {
3119 iommu->default_dom = dma_ops_domain_alloc();
3120 if (iommu->default_dom == NULL)
3121 return -ENOMEM;
3122 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
3123 ret = iommu_init_unity_mappings(iommu);
3124 if (ret)
3125 goto free_domains;
3126 }
3127
3128 /*
3129 * Pre-allocate the protection domains for each device.
3130 */
3131 prealloc_protection_domains();
3132
3133 iommu_detected = 1;
3134 swiotlb = 0;
3135
3136 /* Make the driver finally visible to the drivers */
3137 unhandled = device_dma_ops_init();
3138 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3139 /* There are unhandled devices - initialize swiotlb for them */
3140 swiotlb = 1;
3141 }
3142
3143 amd_iommu_stats_init();
3144
3145 if (amd_iommu_unmap_flush)
3146 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3147 else
3148 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3149
3150 return 0;
3151
3152 free_domains:
3153
3154 for_each_iommu(iommu) {
3155 dma_ops_domain_free(iommu->default_dom);
3156 }
3157
3158 return ret;
3159 }
3160
3161 /*****************************************************************************
3162 *
3163 * The following functions belong to the exported interface of AMD IOMMU
3164 *
3165 * This interface allows access to lower level functions of the IOMMU
3166 * like protection domain handling and assignement of devices to domains
3167 * which is not possible with the dma_ops interface.
3168 *
3169 *****************************************************************************/
3170
3171 static void cleanup_domain(struct protection_domain *domain)
3172 {
3173 struct iommu_dev_data *entry;
3174 unsigned long flags;
3175
3176 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3177
3178 while (!list_empty(&domain->dev_list)) {
3179 entry = list_first_entry(&domain->dev_list,
3180 struct iommu_dev_data, list);
3181 __detach_device(entry);
3182 }
3183
3184 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3185 }
3186
3187 static void protection_domain_free(struct protection_domain *domain)
3188 {
3189 if (!domain)
3190 return;
3191
3192 del_domain_from_list(domain);
3193
3194 if (domain->id)
3195 domain_id_free(domain->id);
3196
3197 kfree(domain);
3198 }
3199
3200 static struct protection_domain *protection_domain_alloc(void)
3201 {
3202 struct protection_domain *domain;
3203
3204 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3205 if (!domain)
3206 return NULL;
3207
3208 spin_lock_init(&domain->lock);
3209 mutex_init(&domain->api_lock);
3210 domain->id = domain_id_alloc();
3211 if (!domain->id)
3212 goto out_err;
3213 INIT_LIST_HEAD(&domain->dev_list);
3214
3215 add_domain_to_list(domain);
3216
3217 return domain;
3218
3219 out_err:
3220 kfree(domain);
3221
3222 return NULL;
3223 }
3224
3225 static int __init alloc_passthrough_domain(void)
3226 {
3227 if (pt_domain != NULL)
3228 return 0;
3229
3230 /* allocate passthrough domain */
3231 pt_domain = protection_domain_alloc();
3232 if (!pt_domain)
3233 return -ENOMEM;
3234
3235 pt_domain->mode = PAGE_MODE_NONE;
3236
3237 return 0;
3238 }
3239
3240 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
3241 {
3242 struct protection_domain *pdomain;
3243
3244 /* We only support unmanaged domains for now */
3245 if (type != IOMMU_DOMAIN_UNMANAGED)
3246 return NULL;
3247
3248 pdomain = protection_domain_alloc();
3249 if (!pdomain)
3250 goto out_free;
3251
3252 pdomain->mode = PAGE_MODE_3_LEVEL;
3253 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3254 if (!pdomain->pt_root)
3255 goto out_free;
3256
3257 pdomain->domain.geometry.aperture_start = 0;
3258 pdomain->domain.geometry.aperture_end = ~0ULL;
3259 pdomain->domain.geometry.force_aperture = true;
3260
3261 return &pdomain->domain;
3262
3263 out_free:
3264 protection_domain_free(pdomain);
3265
3266 return NULL;
3267 }
3268
3269 static void amd_iommu_domain_free(struct iommu_domain *dom)
3270 {
3271 struct protection_domain *domain;
3272
3273 if (!dom)
3274 return;
3275
3276 domain = to_pdomain(dom);
3277
3278 if (domain->dev_cnt > 0)
3279 cleanup_domain(domain);
3280
3281 BUG_ON(domain->dev_cnt != 0);
3282
3283 if (domain->mode != PAGE_MODE_NONE)
3284 free_pagetable(domain);
3285
3286 if (domain->flags & PD_IOMMUV2_MASK)
3287 free_gcr3_table(domain);
3288
3289 protection_domain_free(domain);
3290 }
3291
3292 static void amd_iommu_detach_device(struct iommu_domain *dom,
3293 struct device *dev)
3294 {
3295 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3296 struct amd_iommu *iommu;
3297 u16 devid;
3298
3299 if (!check_device(dev))
3300 return;
3301
3302 devid = get_device_id(dev);
3303
3304 if (dev_data->domain != NULL)
3305 detach_device(dev);
3306
3307 iommu = amd_iommu_rlookup_table[devid];
3308 if (!iommu)
3309 return;
3310
3311 iommu_completion_wait(iommu);
3312 }
3313
3314 static int amd_iommu_attach_device(struct iommu_domain *dom,
3315 struct device *dev)
3316 {
3317 struct protection_domain *domain = to_pdomain(dom);
3318 struct iommu_dev_data *dev_data;
3319 struct amd_iommu *iommu;
3320 int ret;
3321
3322 if (!check_device(dev))
3323 return -EINVAL;
3324
3325 dev_data = dev->archdata.iommu;
3326
3327 iommu = amd_iommu_rlookup_table[dev_data->devid];
3328 if (!iommu)
3329 return -EINVAL;
3330
3331 if (dev_data->domain)
3332 detach_device(dev);
3333
3334 ret = attach_device(dev, domain);
3335
3336 iommu_completion_wait(iommu);
3337
3338 return ret;
3339 }
3340
3341 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3342 phys_addr_t paddr, size_t page_size, int iommu_prot)
3343 {
3344 struct protection_domain *domain = to_pdomain(dom);
3345 int prot = 0;
3346 int ret;
3347
3348 if (domain->mode == PAGE_MODE_NONE)
3349 return -EINVAL;
3350
3351 if (iommu_prot & IOMMU_READ)
3352 prot |= IOMMU_PROT_IR;
3353 if (iommu_prot & IOMMU_WRITE)
3354 prot |= IOMMU_PROT_IW;
3355
3356 mutex_lock(&domain->api_lock);
3357 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3358 mutex_unlock(&domain->api_lock);
3359
3360 return ret;
3361 }
3362
3363 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3364 size_t page_size)
3365 {
3366 struct protection_domain *domain = to_pdomain(dom);
3367 size_t unmap_size;
3368
3369 if (domain->mode == PAGE_MODE_NONE)
3370 return -EINVAL;
3371
3372 mutex_lock(&domain->api_lock);
3373 unmap_size = iommu_unmap_page(domain, iova, page_size);
3374 mutex_unlock(&domain->api_lock);
3375
3376 domain_flush_tlb_pde(domain);
3377
3378 return unmap_size;
3379 }
3380
3381 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3382 dma_addr_t iova)
3383 {
3384 struct protection_domain *domain = to_pdomain(dom);
3385 unsigned long offset_mask, pte_pgsize;
3386 u64 *pte, __pte;
3387
3388 if (domain->mode == PAGE_MODE_NONE)
3389 return iova;
3390
3391 pte = fetch_pte(domain, iova, &pte_pgsize);
3392
3393 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3394 return 0;
3395
3396 offset_mask = pte_pgsize - 1;
3397 __pte = *pte & PM_ADDR_MASK;
3398
3399 return (__pte & ~offset_mask) | (iova & offset_mask);
3400 }
3401
3402 static bool amd_iommu_capable(enum iommu_cap cap)
3403 {
3404 switch (cap) {
3405 case IOMMU_CAP_CACHE_COHERENCY:
3406 return true;
3407 case IOMMU_CAP_INTR_REMAP:
3408 return (irq_remapping_enabled == 1);
3409 case IOMMU_CAP_NOEXEC:
3410 return false;
3411 }
3412
3413 return false;
3414 }
3415
3416 static const struct iommu_ops amd_iommu_ops = {
3417 .capable = amd_iommu_capable,
3418 .domain_alloc = amd_iommu_domain_alloc,
3419 .domain_free = amd_iommu_domain_free,
3420 .attach_dev = amd_iommu_attach_device,
3421 .detach_dev = amd_iommu_detach_device,
3422 .map = amd_iommu_map,
3423 .unmap = amd_iommu_unmap,
3424 .map_sg = default_iommu_map_sg,
3425 .iova_to_phys = amd_iommu_iova_to_phys,
3426 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3427 };
3428
3429 /*****************************************************************************
3430 *
3431 * The next functions do a basic initialization of IOMMU for pass through
3432 * mode
3433 *
3434 * In passthrough mode the IOMMU is initialized and enabled but not used for
3435 * DMA-API translation.
3436 *
3437 *****************************************************************************/
3438
3439 int __init amd_iommu_init_passthrough(void)
3440 {
3441 struct iommu_dev_data *dev_data;
3442 struct pci_dev *dev = NULL;
3443 int ret;
3444
3445 ret = alloc_passthrough_domain();
3446 if (ret)
3447 return ret;
3448
3449 for_each_pci_dev(dev) {
3450 if (!check_device(&dev->dev))
3451 continue;
3452
3453 dev_data = get_dev_data(&dev->dev);
3454 dev_data->passthrough = true;
3455
3456 attach_device(&dev->dev, pt_domain);
3457 }
3458
3459 amd_iommu_stats_init();
3460
3461 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3462
3463 return 0;
3464 }
3465
3466 /* IOMMUv2 specific functions */
3467 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3468 {
3469 return atomic_notifier_chain_register(&ppr_notifier, nb);
3470 }
3471 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3472
3473 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3474 {
3475 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3476 }
3477 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3478
3479 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3480 {
3481 struct protection_domain *domain = to_pdomain(dom);
3482 unsigned long flags;
3483
3484 spin_lock_irqsave(&domain->lock, flags);
3485
3486 /* Update data structure */
3487 domain->mode = PAGE_MODE_NONE;
3488 domain->updated = true;
3489
3490 /* Make changes visible to IOMMUs */
3491 update_domain(domain);
3492
3493 /* Page-table is not visible to IOMMU anymore, so free it */
3494 free_pagetable(domain);
3495
3496 spin_unlock_irqrestore(&domain->lock, flags);
3497 }
3498 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3499
3500 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3501 {
3502 struct protection_domain *domain = to_pdomain(dom);
3503 unsigned long flags;
3504 int levels, ret;
3505
3506 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3507 return -EINVAL;
3508
3509 /* Number of GCR3 table levels required */
3510 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3511 levels += 1;
3512
3513 if (levels > amd_iommu_max_glx_val)
3514 return -EINVAL;
3515
3516 spin_lock_irqsave(&domain->lock, flags);
3517
3518 /*
3519 * Save us all sanity checks whether devices already in the
3520 * domain support IOMMUv2. Just force that the domain has no
3521 * devices attached when it is switched into IOMMUv2 mode.
3522 */
3523 ret = -EBUSY;
3524 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3525 goto out;
3526
3527 ret = -ENOMEM;
3528 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3529 if (domain->gcr3_tbl == NULL)
3530 goto out;
3531
3532 domain->glx = levels;
3533 domain->flags |= PD_IOMMUV2_MASK;
3534 domain->updated = true;
3535
3536 update_domain(domain);
3537
3538 ret = 0;
3539
3540 out:
3541 spin_unlock_irqrestore(&domain->lock, flags);
3542
3543 return ret;
3544 }
3545 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3546
3547 static int __flush_pasid(struct protection_domain *domain, int pasid,
3548 u64 address, bool size)
3549 {
3550 struct iommu_dev_data *dev_data;
3551 struct iommu_cmd cmd;
3552 int i, ret;
3553
3554 if (!(domain->flags & PD_IOMMUV2_MASK))
3555 return -EINVAL;
3556
3557 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3558
3559 /*
3560 * IOMMU TLB needs to be flushed before Device TLB to
3561 * prevent device TLB refill from IOMMU TLB
3562 */
3563 for (i = 0; i < amd_iommus_present; ++i) {
3564 if (domain->dev_iommu[i] == 0)
3565 continue;
3566
3567 ret = iommu_queue_command(amd_iommus[i], &cmd);
3568 if (ret != 0)
3569 goto out;
3570 }
3571
3572 /* Wait until IOMMU TLB flushes are complete */
3573 domain_flush_complete(domain);
3574
3575 /* Now flush device TLBs */
3576 list_for_each_entry(dev_data, &domain->dev_list, list) {
3577 struct amd_iommu *iommu;
3578 int qdep;
3579
3580 BUG_ON(!dev_data->ats.enabled);
3581
3582 qdep = dev_data->ats.qdep;
3583 iommu = amd_iommu_rlookup_table[dev_data->devid];
3584
3585 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3586 qdep, address, size);
3587
3588 ret = iommu_queue_command(iommu, &cmd);
3589 if (ret != 0)
3590 goto out;
3591 }
3592
3593 /* Wait until all device TLBs are flushed */
3594 domain_flush_complete(domain);
3595
3596 ret = 0;
3597
3598 out:
3599
3600 return ret;
3601 }
3602
3603 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3604 u64 address)
3605 {
3606 INC_STATS_COUNTER(invalidate_iotlb);
3607
3608 return __flush_pasid(domain, pasid, address, false);
3609 }
3610
3611 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3612 u64 address)
3613 {
3614 struct protection_domain *domain = to_pdomain(dom);
3615 unsigned long flags;
3616 int ret;
3617
3618 spin_lock_irqsave(&domain->lock, flags);
3619 ret = __amd_iommu_flush_page(domain, pasid, address);
3620 spin_unlock_irqrestore(&domain->lock, flags);
3621
3622 return ret;
3623 }
3624 EXPORT_SYMBOL(amd_iommu_flush_page);
3625
3626 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3627 {
3628 INC_STATS_COUNTER(invalidate_iotlb_all);
3629
3630 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3631 true);
3632 }
3633
3634 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3635 {
3636 struct protection_domain *domain = to_pdomain(dom);
3637 unsigned long flags;
3638 int ret;
3639
3640 spin_lock_irqsave(&domain->lock, flags);
3641 ret = __amd_iommu_flush_tlb(domain, pasid);
3642 spin_unlock_irqrestore(&domain->lock, flags);
3643
3644 return ret;
3645 }
3646 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3647
3648 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3649 {
3650 int index;
3651 u64 *pte;
3652
3653 while (true) {
3654
3655 index = (pasid >> (9 * level)) & 0x1ff;
3656 pte = &root[index];
3657
3658 if (level == 0)
3659 break;
3660
3661 if (!(*pte & GCR3_VALID)) {
3662 if (!alloc)
3663 return NULL;
3664
3665 root = (void *)get_zeroed_page(GFP_ATOMIC);
3666 if (root == NULL)
3667 return NULL;
3668
3669 *pte = __pa(root) | GCR3_VALID;
3670 }
3671
3672 root = __va(*pte & PAGE_MASK);
3673
3674 level -= 1;
3675 }
3676
3677 return pte;
3678 }
3679
3680 static int __set_gcr3(struct protection_domain *domain, int pasid,
3681 unsigned long cr3)
3682 {
3683 u64 *pte;
3684
3685 if (domain->mode != PAGE_MODE_NONE)
3686 return -EINVAL;
3687
3688 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3689 if (pte == NULL)
3690 return -ENOMEM;
3691
3692 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3693
3694 return __amd_iommu_flush_tlb(domain, pasid);
3695 }
3696
3697 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3698 {
3699 u64 *pte;
3700
3701 if (domain->mode != PAGE_MODE_NONE)
3702 return -EINVAL;
3703
3704 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3705 if (pte == NULL)
3706 return 0;
3707
3708 *pte = 0;
3709
3710 return __amd_iommu_flush_tlb(domain, pasid);
3711 }
3712
3713 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3714 unsigned long cr3)
3715 {
3716 struct protection_domain *domain = to_pdomain(dom);
3717 unsigned long flags;
3718 int ret;
3719
3720 spin_lock_irqsave(&domain->lock, flags);
3721 ret = __set_gcr3(domain, pasid, cr3);
3722 spin_unlock_irqrestore(&domain->lock, flags);
3723
3724 return ret;
3725 }
3726 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3727
3728 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3729 {
3730 struct protection_domain *domain = to_pdomain(dom);
3731 unsigned long flags;
3732 int ret;
3733
3734 spin_lock_irqsave(&domain->lock, flags);
3735 ret = __clear_gcr3(domain, pasid);
3736 spin_unlock_irqrestore(&domain->lock, flags);
3737
3738 return ret;
3739 }
3740 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3741
3742 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3743 int status, int tag)
3744 {
3745 struct iommu_dev_data *dev_data;
3746 struct amd_iommu *iommu;
3747 struct iommu_cmd cmd;
3748
3749 INC_STATS_COUNTER(complete_ppr);
3750
3751 dev_data = get_dev_data(&pdev->dev);
3752 iommu = amd_iommu_rlookup_table[dev_data->devid];
3753
3754 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3755 tag, dev_data->pri_tlp);
3756
3757 return iommu_queue_command(iommu, &cmd);
3758 }
3759 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3760
3761 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3762 {
3763 struct protection_domain *pdomain;
3764
3765 pdomain = get_domain(&pdev->dev);
3766 if (IS_ERR(pdomain))
3767 return NULL;
3768
3769 /* Only return IOMMUv2 domains */
3770 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3771 return NULL;
3772
3773 return &pdomain->domain;
3774 }
3775 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3776
3777 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3778 {
3779 struct iommu_dev_data *dev_data;
3780
3781 if (!amd_iommu_v2_supported())
3782 return;
3783
3784 dev_data = get_dev_data(&pdev->dev);
3785 dev_data->errata |= (1 << erratum);
3786 }
3787 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3788
3789 int amd_iommu_device_info(struct pci_dev *pdev,
3790 struct amd_iommu_device_info *info)
3791 {
3792 int max_pasids;
3793 int pos;
3794
3795 if (pdev == NULL || info == NULL)
3796 return -EINVAL;
3797
3798 if (!amd_iommu_v2_supported())
3799 return -EINVAL;
3800
3801 memset(info, 0, sizeof(*info));
3802
3803 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3804 if (pos)
3805 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3806
3807 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3808 if (pos)
3809 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3810
3811 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3812 if (pos) {
3813 int features;
3814
3815 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3816 max_pasids = min(max_pasids, (1 << 20));
3817
3818 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3819 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3820
3821 features = pci_pasid_features(pdev);
3822 if (features & PCI_PASID_CAP_EXEC)
3823 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3824 if (features & PCI_PASID_CAP_PRIV)
3825 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3826 }
3827
3828 return 0;
3829 }
3830 EXPORT_SYMBOL(amd_iommu_device_info);
3831
3832 #ifdef CONFIG_IRQ_REMAP
3833
3834 /*****************************************************************************
3835 *
3836 * Interrupt Remapping Implementation
3837 *
3838 *****************************************************************************/
3839
3840 union irte {
3841 u32 val;
3842 struct {
3843 u32 valid : 1,
3844 no_fault : 1,
3845 int_type : 3,
3846 rq_eoi : 1,
3847 dm : 1,
3848 rsvd_1 : 1,
3849 destination : 8,
3850 vector : 8,
3851 rsvd_2 : 8;
3852 } fields;
3853 };
3854
3855 struct irq_2_irte {
3856 u16 devid; /* Device ID for IRTE table */
3857 u16 index; /* Index into IRTE table*/
3858 };
3859
3860 struct amd_ir_data {
3861 struct irq_2_irte irq_2_irte;
3862 union irte irte_entry;
3863 union {
3864 struct msi_msg msi_entry;
3865 };
3866 };
3867
3868 static struct irq_chip amd_ir_chip;
3869
3870 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3871 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3872 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3873 #define DTE_IRQ_REMAP_ENABLE 1ULL
3874
3875 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3876 {
3877 u64 dte;
3878
3879 dte = amd_iommu_dev_table[devid].data[2];
3880 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3881 dte |= virt_to_phys(table->table);
3882 dte |= DTE_IRQ_REMAP_INTCTL;
3883 dte |= DTE_IRQ_TABLE_LEN;
3884 dte |= DTE_IRQ_REMAP_ENABLE;
3885
3886 amd_iommu_dev_table[devid].data[2] = dte;
3887 }
3888
3889 #define IRTE_ALLOCATED (~1U)
3890
3891 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3892 {
3893 struct irq_remap_table *table = NULL;
3894 struct amd_iommu *iommu;
3895 unsigned long flags;
3896 u16 alias;
3897
3898 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3899
3900 iommu = amd_iommu_rlookup_table[devid];
3901 if (!iommu)
3902 goto out_unlock;
3903
3904 table = irq_lookup_table[devid];
3905 if (table)
3906 goto out;
3907
3908 alias = amd_iommu_alias_table[devid];
3909 table = irq_lookup_table[alias];
3910 if (table) {
3911 irq_lookup_table[devid] = table;
3912 set_dte_irq_entry(devid, table);
3913 iommu_flush_dte(iommu, devid);
3914 goto out;
3915 }
3916
3917 /* Nothing there yet, allocate new irq remapping table */
3918 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3919 if (!table)
3920 goto out;
3921
3922 /* Initialize table spin-lock */
3923 spin_lock_init(&table->lock);
3924
3925 if (ioapic)
3926 /* Keep the first 32 indexes free for IOAPIC interrupts */
3927 table->min_index = 32;
3928
3929 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3930 if (!table->table) {
3931 kfree(table);
3932 table = NULL;
3933 goto out;
3934 }
3935
3936 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3937
3938 if (ioapic) {
3939 int i;
3940
3941 for (i = 0; i < 32; ++i)
3942 table->table[i] = IRTE_ALLOCATED;
3943 }
3944
3945 irq_lookup_table[devid] = table;
3946 set_dte_irq_entry(devid, table);
3947 iommu_flush_dte(iommu, devid);
3948 if (devid != alias) {
3949 irq_lookup_table[alias] = table;
3950 set_dte_irq_entry(alias, table);
3951 iommu_flush_dte(iommu, alias);
3952 }
3953
3954 out:
3955 iommu_completion_wait(iommu);
3956
3957 out_unlock:
3958 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3959
3960 return table;
3961 }
3962
3963 static int alloc_irq_index(u16 devid, int count)
3964 {
3965 struct irq_remap_table *table;
3966 unsigned long flags;
3967 int index, c;
3968
3969 table = get_irq_table(devid, false);
3970 if (!table)
3971 return -ENODEV;
3972
3973 spin_lock_irqsave(&table->lock, flags);
3974
3975 /* Scan table for free entries */
3976 for (c = 0, index = table->min_index;
3977 index < MAX_IRQS_PER_TABLE;
3978 ++index) {
3979 if (table->table[index] == 0)
3980 c += 1;
3981 else
3982 c = 0;
3983
3984 if (c == count) {
3985 for (; c != 0; --c)
3986 table->table[index - c + 1] = IRTE_ALLOCATED;
3987
3988 index -= count - 1;
3989 goto out;
3990 }
3991 }
3992
3993 index = -ENOSPC;
3994
3995 out:
3996 spin_unlock_irqrestore(&table->lock, flags);
3997
3998 return index;
3999 }
4000
4001 static int modify_irte(u16 devid, int index, union irte irte)
4002 {
4003 struct irq_remap_table *table;
4004 struct amd_iommu *iommu;
4005 unsigned long flags;
4006
4007 iommu = amd_iommu_rlookup_table[devid];
4008 if (iommu == NULL)
4009 return -EINVAL;
4010
4011 table = get_irq_table(devid, false);
4012 if (!table)
4013 return -ENOMEM;
4014
4015 spin_lock_irqsave(&table->lock, flags);
4016 table->table[index] = irte.val;
4017 spin_unlock_irqrestore(&table->lock, flags);
4018
4019 iommu_flush_irt(iommu, devid);
4020 iommu_completion_wait(iommu);
4021
4022 return 0;
4023 }
4024
4025 static void free_irte(u16 devid, int index)
4026 {
4027 struct irq_remap_table *table;
4028 struct amd_iommu *iommu;
4029 unsigned long flags;
4030
4031 iommu = amd_iommu_rlookup_table[devid];
4032 if (iommu == NULL)
4033 return;
4034
4035 table = get_irq_table(devid, false);
4036 if (!table)
4037 return;
4038
4039 spin_lock_irqsave(&table->lock, flags);
4040 table->table[index] = 0;
4041 spin_unlock_irqrestore(&table->lock, flags);
4042
4043 iommu_flush_irt(iommu, devid);
4044 iommu_completion_wait(iommu);
4045 }
4046
4047 static int get_devid(struct irq_alloc_info *info)
4048 {
4049 int devid = -1;
4050
4051 switch (info->type) {
4052 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4053 devid = get_ioapic_devid(info->ioapic_id);
4054 break;
4055 case X86_IRQ_ALLOC_TYPE_HPET:
4056 devid = get_hpet_devid(info->hpet_id);
4057 break;
4058 case X86_IRQ_ALLOC_TYPE_MSI:
4059 case X86_IRQ_ALLOC_TYPE_MSIX:
4060 devid = get_device_id(&info->msi_dev->dev);
4061 break;
4062 default:
4063 BUG_ON(1);
4064 break;
4065 }
4066
4067 return devid;
4068 }
4069
4070 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4071 {
4072 struct amd_iommu *iommu;
4073 int devid;
4074
4075 if (!info)
4076 return NULL;
4077
4078 devid = get_devid(info);
4079 if (devid >= 0) {
4080 iommu = amd_iommu_rlookup_table[devid];
4081 if (iommu)
4082 return iommu->ir_domain;
4083 }
4084
4085 return NULL;
4086 }
4087
4088 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4089 {
4090 struct amd_iommu *iommu;
4091 int devid;
4092
4093 if (!info)
4094 return NULL;
4095
4096 switch (info->type) {
4097 case X86_IRQ_ALLOC_TYPE_MSI:
4098 case X86_IRQ_ALLOC_TYPE_MSIX:
4099 devid = get_device_id(&info->msi_dev->dev);
4100 if (devid >= 0) {
4101 iommu = amd_iommu_rlookup_table[devid];
4102 if (iommu)
4103 return iommu->msi_domain;
4104 }
4105 break;
4106 default:
4107 break;
4108 }
4109
4110 return NULL;
4111 }
4112
4113 struct irq_remap_ops amd_iommu_irq_ops = {
4114 .prepare = amd_iommu_prepare,
4115 .enable = amd_iommu_enable,
4116 .disable = amd_iommu_disable,
4117 .reenable = amd_iommu_reenable,
4118 .enable_faulting = amd_iommu_enable_faulting,
4119 .get_ir_irq_domain = get_ir_irq_domain,
4120 .get_irq_domain = get_irq_domain,
4121 };
4122
4123 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4124 struct irq_cfg *irq_cfg,
4125 struct irq_alloc_info *info,
4126 int devid, int index, int sub_handle)
4127 {
4128 struct irq_2_irte *irte_info = &data->irq_2_irte;
4129 struct msi_msg *msg = &data->msi_entry;
4130 union irte *irte = &data->irte_entry;
4131 struct IO_APIC_route_entry *entry;
4132
4133 data->irq_2_irte.devid = devid;
4134 data->irq_2_irte.index = index + sub_handle;
4135
4136 /* Setup IRTE for IOMMU */
4137 irte->val = 0;
4138 irte->fields.vector = irq_cfg->vector;
4139 irte->fields.int_type = apic->irq_delivery_mode;
4140 irte->fields.destination = irq_cfg->dest_apicid;
4141 irte->fields.dm = apic->irq_dest_mode;
4142 irte->fields.valid = 1;
4143
4144 switch (info->type) {
4145 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4146 /* Setup IOAPIC entry */
4147 entry = info->ioapic_entry;
4148 info->ioapic_entry = NULL;
4149 memset(entry, 0, sizeof(*entry));
4150 entry->vector = index;
4151 entry->mask = 0;
4152 entry->trigger = info->ioapic_trigger;
4153 entry->polarity = info->ioapic_polarity;
4154 /* Mask level triggered irqs. */
4155 if (info->ioapic_trigger)
4156 entry->mask = 1;
4157 break;
4158
4159 case X86_IRQ_ALLOC_TYPE_HPET:
4160 case X86_IRQ_ALLOC_TYPE_MSI:
4161 case X86_IRQ_ALLOC_TYPE_MSIX:
4162 msg->address_hi = MSI_ADDR_BASE_HI;
4163 msg->address_lo = MSI_ADDR_BASE_LO;
4164 msg->data = irte_info->index;
4165 break;
4166
4167 default:
4168 BUG_ON(1);
4169 break;
4170 }
4171 }
4172
4173 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4174 unsigned int nr_irqs, void *arg)
4175 {
4176 struct irq_alloc_info *info = arg;
4177 struct irq_data *irq_data;
4178 struct amd_ir_data *data;
4179 struct irq_cfg *cfg;
4180 int i, ret, devid;
4181 int index = -1;
4182
4183 if (!info)
4184 return -EINVAL;
4185 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4186 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4187 return -EINVAL;
4188
4189 /*
4190 * With IRQ remapping enabled, don't need contiguous CPU vectors
4191 * to support multiple MSI interrupts.
4192 */
4193 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4194 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4195
4196 devid = get_devid(info);
4197 if (devid < 0)
4198 return -EINVAL;
4199
4200 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4201 if (ret < 0)
4202 return ret;
4203
4204 ret = -ENOMEM;
4205 data = kzalloc(sizeof(*data), GFP_KERNEL);
4206 if (!data)
4207 goto out_free_parent;
4208
4209 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4210 if (get_irq_table(devid, true))
4211 index = info->ioapic_pin;
4212 else
4213 ret = -ENOMEM;
4214 } else {
4215 index = alloc_irq_index(devid, nr_irqs);
4216 }
4217 if (index < 0) {
4218 pr_warn("Failed to allocate IRTE\n");
4219 kfree(data);
4220 goto out_free_parent;
4221 }
4222
4223 for (i = 0; i < nr_irqs; i++) {
4224 irq_data = irq_domain_get_irq_data(domain, virq + i);
4225 cfg = irqd_cfg(irq_data);
4226 if (!irq_data || !cfg) {
4227 ret = -EINVAL;
4228 goto out_free_data;
4229 }
4230
4231 if (i > 0) {
4232 data = kzalloc(sizeof(*data), GFP_KERNEL);
4233 if (!data)
4234 goto out_free_data;
4235 }
4236 irq_data->hwirq = (devid << 16) + i;
4237 irq_data->chip_data = data;
4238 irq_data->chip = &amd_ir_chip;
4239 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4240 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4241 }
4242 return 0;
4243
4244 out_free_data:
4245 for (i--; i >= 0; i--) {
4246 irq_data = irq_domain_get_irq_data(domain, virq + i);
4247 if (irq_data)
4248 kfree(irq_data->chip_data);
4249 }
4250 for (i = 0; i < nr_irqs; i++)
4251 free_irte(devid, index + i);
4252 out_free_parent:
4253 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4254 return ret;
4255 }
4256
4257 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4258 unsigned int nr_irqs)
4259 {
4260 struct irq_2_irte *irte_info;
4261 struct irq_data *irq_data;
4262 struct amd_ir_data *data;
4263 int i;
4264
4265 for (i = 0; i < nr_irqs; i++) {
4266 irq_data = irq_domain_get_irq_data(domain, virq + i);
4267 if (irq_data && irq_data->chip_data) {
4268 data = irq_data->chip_data;
4269 irte_info = &data->irq_2_irte;
4270 free_irte(irte_info->devid, irte_info->index);
4271 kfree(data);
4272 }
4273 }
4274 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4275 }
4276
4277 static void irq_remapping_activate(struct irq_domain *domain,
4278 struct irq_data *irq_data)
4279 {
4280 struct amd_ir_data *data = irq_data->chip_data;
4281 struct irq_2_irte *irte_info = &data->irq_2_irte;
4282
4283 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
4284 }
4285
4286 static void irq_remapping_deactivate(struct irq_domain *domain,
4287 struct irq_data *irq_data)
4288 {
4289 struct amd_ir_data *data = irq_data->chip_data;
4290 struct irq_2_irte *irte_info = &data->irq_2_irte;
4291 union irte entry;
4292
4293 entry.val = 0;
4294 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
4295 }
4296
4297 static struct irq_domain_ops amd_ir_domain_ops = {
4298 .alloc = irq_remapping_alloc,
4299 .free = irq_remapping_free,
4300 .activate = irq_remapping_activate,
4301 .deactivate = irq_remapping_deactivate,
4302 };
4303
4304 static int amd_ir_set_affinity(struct irq_data *data,
4305 const struct cpumask *mask, bool force)
4306 {
4307 struct amd_ir_data *ir_data = data->chip_data;
4308 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4309 struct irq_cfg *cfg = irqd_cfg(data);
4310 struct irq_data *parent = data->parent_data;
4311 int ret;
4312
4313 ret = parent->chip->irq_set_affinity(parent, mask, force);
4314 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4315 return ret;
4316
4317 /*
4318 * Atomically updates the IRTE with the new destination, vector
4319 * and flushes the interrupt entry cache.
4320 */
4321 ir_data->irte_entry.fields.vector = cfg->vector;
4322 ir_data->irte_entry.fields.destination = cfg->dest_apicid;
4323 modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry);
4324
4325 /*
4326 * After this point, all the interrupts will start arriving
4327 * at the new destination. So, time to cleanup the previous
4328 * vector allocation.
4329 */
4330 send_cleanup_vector(cfg);
4331
4332 return IRQ_SET_MASK_OK_DONE;
4333 }
4334
4335 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4336 {
4337 struct amd_ir_data *ir_data = irq_data->chip_data;
4338
4339 *msg = ir_data->msi_entry;
4340 }
4341
4342 static struct irq_chip amd_ir_chip = {
4343 .irq_ack = ir_ack_apic_edge,
4344 .irq_set_affinity = amd_ir_set_affinity,
4345 .irq_compose_msi_msg = ir_compose_msi_msg,
4346 };
4347
4348 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4349 {
4350 iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
4351 if (!iommu->ir_domain)
4352 return -ENOMEM;
4353
4354 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4355 iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
4356
4357 return 0;
4358 }
4359 #endif
Linux kernel - Deliverables
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