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Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
[deliverable/linux.git] / drivers / iommu / amd_iommu_init.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/export.h>
29 #include <linux/iommu.h>
30 #include <asm/pci-direct.h>
31 #include <asm/iommu.h>
32 #include <asm/gart.h>
33 #include <asm/x86_init.h>
34 #include <asm/iommu_table.h>
35 #include <asm/io_apic.h>
36 #include <asm/irq_remapping.h>
37
38 #include "amd_iommu_proto.h"
39 #include "amd_iommu_types.h"
40 #include "irq_remapping.h"
41
42 /*
43 * definitions for the ACPI scanning code
44 */
45 #define IVRS_HEADER_LENGTH 48
46
47 #define ACPI_IVHD_TYPE 0x10
48 #define ACPI_IVMD_TYPE_ALL 0x20
49 #define ACPI_IVMD_TYPE 0x21
50 #define ACPI_IVMD_TYPE_RANGE 0x22
51
52 #define IVHD_DEV_ALL 0x01
53 #define IVHD_DEV_SELECT 0x02
54 #define IVHD_DEV_SELECT_RANGE_START 0x03
55 #define IVHD_DEV_RANGE_END 0x04
56 #define IVHD_DEV_ALIAS 0x42
57 #define IVHD_DEV_ALIAS_RANGE 0x43
58 #define IVHD_DEV_EXT_SELECT 0x46
59 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
60 #define IVHD_DEV_SPECIAL 0x48
61
62 #define IVHD_SPECIAL_IOAPIC 1
63 #define IVHD_SPECIAL_HPET 2
64
65 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
66 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
67 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
68 #define IVHD_FLAG_ISOC_EN_MASK 0x08
69
70 #define IVMD_FLAG_EXCL_RANGE 0x08
71 #define IVMD_FLAG_UNITY_MAP 0x01
72
73 #define ACPI_DEVFLAG_INITPASS 0x01
74 #define ACPI_DEVFLAG_EXTINT 0x02
75 #define ACPI_DEVFLAG_NMI 0x04
76 #define ACPI_DEVFLAG_SYSMGT1 0x10
77 #define ACPI_DEVFLAG_SYSMGT2 0x20
78 #define ACPI_DEVFLAG_LINT0 0x40
79 #define ACPI_DEVFLAG_LINT1 0x80
80 #define ACPI_DEVFLAG_ATSDIS 0x10000000
81
82 /*
83 * ACPI table definitions
84 *
85 * These data structures are laid over the table to parse the important values
86 * out of it.
87 */
88
89 /*
90 * structure describing one IOMMU in the ACPI table. Typically followed by one
91 * or more ivhd_entrys.
92 */
93 struct ivhd_header {
94 u8 type;
95 u8 flags;
96 u16 length;
97 u16 devid;
98 u16 cap_ptr;
99 u64 mmio_phys;
100 u16 pci_seg;
101 u16 info;
102 u32 efr;
103 } __attribute__((packed));
104
105 /*
106 * A device entry describing which devices a specific IOMMU translates and
107 * which requestor ids they use.
108 */
109 struct ivhd_entry {
110 u8 type;
111 u16 devid;
112 u8 flags;
113 u32 ext;
114 } __attribute__((packed));
115
116 /*
117 * An AMD IOMMU memory definition structure. It defines things like exclusion
118 * ranges for devices and regions that should be unity mapped.
119 */
120 struct ivmd_header {
121 u8 type;
122 u8 flags;
123 u16 length;
124 u16 devid;
125 u16 aux;
126 u64 resv;
127 u64 range_start;
128 u64 range_length;
129 } __attribute__((packed));
130
131 bool amd_iommu_dump;
132 bool amd_iommu_irq_remap __read_mostly;
133
134 static bool amd_iommu_detected;
135 static bool __initdata amd_iommu_disabled;
136
137 u16 amd_iommu_last_bdf; /* largest PCI device id we have
138 to handle */
139 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
140 we find in ACPI */
141 u32 amd_iommu_unmap_flush; /* if true, flush on every unmap */
142
143 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
144 system */
145
146 /* Array to assign indices to IOMMUs*/
147 struct amd_iommu *amd_iommus[MAX_IOMMUS];
148 int amd_iommus_present;
149
150 /* IOMMUs have a non-present cache? */
151 bool amd_iommu_np_cache __read_mostly;
152 bool amd_iommu_iotlb_sup __read_mostly = true;
153
154 u32 amd_iommu_max_pasid __read_mostly = ~0;
155
156 bool amd_iommu_v2_present __read_mostly;
157 bool amd_iommu_pc_present __read_mostly;
158
159 bool amd_iommu_force_isolation __read_mostly;
160
161 /*
162 * List of protection domains - used during resume
163 */
164 LIST_HEAD(amd_iommu_pd_list);
165 spinlock_t amd_iommu_pd_lock;
166
167 /*
168 * Pointer to the device table which is shared by all AMD IOMMUs
169 * it is indexed by the PCI device id or the HT unit id and contains
170 * information about the domain the device belongs to as well as the
171 * page table root pointer.
172 */
173 struct dev_table_entry *amd_iommu_dev_table;
174
175 /*
176 * The alias table is a driver specific data structure which contains the
177 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
178 * More than one device can share the same requestor id.
179 */
180 u16 *amd_iommu_alias_table;
181
182 /*
183 * The rlookup table is used to find the IOMMU which is responsible
184 * for a specific device. It is also indexed by the PCI device id.
185 */
186 struct amd_iommu **amd_iommu_rlookup_table;
187
188 /*
189 * This table is used to find the irq remapping table for a given device id
190 * quickly.
191 */
192 struct irq_remap_table **irq_lookup_table;
193
194 /*
195 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
196 * to know which ones are already in use.
197 */
198 unsigned long *amd_iommu_pd_alloc_bitmap;
199
200 static u32 dev_table_size; /* size of the device table */
201 static u32 alias_table_size; /* size of the alias table */
202 static u32 rlookup_table_size; /* size if the rlookup table */
203
204 enum iommu_init_state {
205 IOMMU_START_STATE,
206 IOMMU_IVRS_DETECTED,
207 IOMMU_ACPI_FINISHED,
208 IOMMU_ENABLED,
209 IOMMU_PCI_INIT,
210 IOMMU_INTERRUPTS_EN,
211 IOMMU_DMA_OPS,
212 IOMMU_INITIALIZED,
213 IOMMU_NOT_FOUND,
214 IOMMU_INIT_ERROR,
215 };
216
217 /* Early ioapic and hpet maps from kernel command line */
218 #define EARLY_MAP_SIZE 4
219 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
220 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
221 static int __initdata early_ioapic_map_size;
222 static int __initdata early_hpet_map_size;
223 static bool __initdata cmdline_maps;
224
225 static enum iommu_init_state init_state = IOMMU_START_STATE;
226
227 static int amd_iommu_enable_interrupts(void);
228 static int __init iommu_go_to_state(enum iommu_init_state state);
229
230 static inline void update_last_devid(u16 devid)
231 {
232 if (devid > amd_iommu_last_bdf)
233 amd_iommu_last_bdf = devid;
234 }
235
236 static inline unsigned long tbl_size(int entry_size)
237 {
238 unsigned shift = PAGE_SHIFT +
239 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
240
241 return 1UL << shift;
242 }
243
244 /* Access to l1 and l2 indexed register spaces */
245
246 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
247 {
248 u32 val;
249
250 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
251 pci_read_config_dword(iommu->dev, 0xfc, &val);
252 return val;
253 }
254
255 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
256 {
257 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
258 pci_write_config_dword(iommu->dev, 0xfc, val);
259 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
260 }
261
262 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
263 {
264 u32 val;
265
266 pci_write_config_dword(iommu->dev, 0xf0, address);
267 pci_read_config_dword(iommu->dev, 0xf4, &val);
268 return val;
269 }
270
271 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
272 {
273 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
274 pci_write_config_dword(iommu->dev, 0xf4, val);
275 }
276
277 /****************************************************************************
278 *
279 * AMD IOMMU MMIO register space handling functions
280 *
281 * These functions are used to program the IOMMU device registers in
282 * MMIO space required for that driver.
283 *
284 ****************************************************************************/
285
286 /*
287 * This function set the exclusion range in the IOMMU. DMA accesses to the
288 * exclusion range are passed through untranslated
289 */
290 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
291 {
292 u64 start = iommu->exclusion_start & PAGE_MASK;
293 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
294 u64 entry;
295
296 if (!iommu->exclusion_start)
297 return;
298
299 entry = start | MMIO_EXCL_ENABLE_MASK;
300 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
301 &entry, sizeof(entry));
302
303 entry = limit;
304 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
305 &entry, sizeof(entry));
306 }
307
308 /* Programs the physical address of the device table into the IOMMU hardware */
309 static void iommu_set_device_table(struct amd_iommu *iommu)
310 {
311 u64 entry;
312
313 BUG_ON(iommu->mmio_base == NULL);
314
315 entry = virt_to_phys(amd_iommu_dev_table);
316 entry |= (dev_table_size >> 12) - 1;
317 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
318 &entry, sizeof(entry));
319 }
320
321 /* Generic functions to enable/disable certain features of the IOMMU. */
322 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
323 {
324 u32 ctrl;
325
326 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
327 ctrl |= (1 << bit);
328 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
329 }
330
331 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
332 {
333 u32 ctrl;
334
335 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
336 ctrl &= ~(1 << bit);
337 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
338 }
339
340 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
341 {
342 u32 ctrl;
343
344 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
345 ctrl &= ~CTRL_INV_TO_MASK;
346 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
347 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
348 }
349
350 /* Function to enable the hardware */
351 static void iommu_enable(struct amd_iommu *iommu)
352 {
353 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
354 }
355
356 static void iommu_disable(struct amd_iommu *iommu)
357 {
358 /* Disable command buffer */
359 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
360
361 /* Disable event logging and event interrupts */
362 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
363 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
364
365 /* Disable IOMMU hardware itself */
366 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
367 }
368
369 /*
370 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
371 * the system has one.
372 */
373 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
374 {
375 if (!request_mem_region(address, end, "amd_iommu")) {
376 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
377 address, end);
378 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
379 return NULL;
380 }
381
382 return (u8 __iomem *)ioremap_nocache(address, end);
383 }
384
385 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
386 {
387 if (iommu->mmio_base)
388 iounmap(iommu->mmio_base);
389 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
390 }
391
392 /****************************************************************************
393 *
394 * The functions below belong to the first pass of AMD IOMMU ACPI table
395 * parsing. In this pass we try to find out the highest device id this
396 * code has to handle. Upon this information the size of the shared data
397 * structures is determined later.
398 *
399 ****************************************************************************/
400
401 /*
402 * This function calculates the length of a given IVHD entry
403 */
404 static inline int ivhd_entry_length(u8 *ivhd)
405 {
406 return 0x04 << (*ivhd >> 6);
407 }
408
409 /*
410 * This function reads the last device id the IOMMU has to handle from the PCI
411 * capability header for this IOMMU
412 */
413 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
414 {
415 u32 cap;
416
417 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
418 update_last_devid(PCI_DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
419
420 return 0;
421 }
422
423 /*
424 * After reading the highest device id from the IOMMU PCI capability header
425 * this function looks if there is a higher device id defined in the ACPI table
426 */
427 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
428 {
429 u8 *p = (void *)h, *end = (void *)h;
430 struct ivhd_entry *dev;
431
432 p += sizeof(*h);
433 end += h->length;
434
435 find_last_devid_on_pci(PCI_BUS_NUM(h->devid),
436 PCI_SLOT(h->devid),
437 PCI_FUNC(h->devid),
438 h->cap_ptr);
439
440 while (p < end) {
441 dev = (struct ivhd_entry *)p;
442 switch (dev->type) {
443 case IVHD_DEV_SELECT:
444 case IVHD_DEV_RANGE_END:
445 case IVHD_DEV_ALIAS:
446 case IVHD_DEV_EXT_SELECT:
447 /* all the above subfield types refer to device ids */
448 update_last_devid(dev->devid);
449 break;
450 default:
451 break;
452 }
453 p += ivhd_entry_length(p);
454 }
455
456 WARN_ON(p != end);
457
458 return 0;
459 }
460
461 /*
462 * Iterate over all IVHD entries in the ACPI table and find the highest device
463 * id which we need to handle. This is the first of three functions which parse
464 * the ACPI table. So we check the checksum here.
465 */
466 static int __init find_last_devid_acpi(struct acpi_table_header *table)
467 {
468 int i;
469 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
470 struct ivhd_header *h;
471
472 /*
473 * Validate checksum here so we don't need to do it when
474 * we actually parse the table
475 */
476 for (i = 0; i < table->length; ++i)
477 checksum += p[i];
478 if (checksum != 0)
479 /* ACPI table corrupt */
480 return -ENODEV;
481
482 p += IVRS_HEADER_LENGTH;
483
484 end += table->length;
485 while (p < end) {
486 h = (struct ivhd_header *)p;
487 switch (h->type) {
488 case ACPI_IVHD_TYPE:
489 find_last_devid_from_ivhd(h);
490 break;
491 default:
492 break;
493 }
494 p += h->length;
495 }
496 WARN_ON(p != end);
497
498 return 0;
499 }
500
501 /****************************************************************************
502 *
503 * The following functions belong to the code path which parses the ACPI table
504 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
505 * data structures, initialize the device/alias/rlookup table and also
506 * basically initialize the hardware.
507 *
508 ****************************************************************************/
509
510 /*
511 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
512 * write commands to that buffer later and the IOMMU will execute them
513 * asynchronously
514 */
515 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
516 {
517 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
518 get_order(CMD_BUFFER_SIZE));
519
520 if (cmd_buf == NULL)
521 return NULL;
522
523 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
524
525 return cmd_buf;
526 }
527
528 /*
529 * This function resets the command buffer if the IOMMU stopped fetching
530 * commands from it.
531 */
532 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
533 {
534 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
535
536 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
537 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
538
539 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
540 }
541
542 /*
543 * This function writes the command buffer address to the hardware and
544 * enables it.
545 */
546 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
547 {
548 u64 entry;
549
550 BUG_ON(iommu->cmd_buf == NULL);
551
552 entry = (u64)virt_to_phys(iommu->cmd_buf);
553 entry |= MMIO_CMD_SIZE_512;
554
555 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
556 &entry, sizeof(entry));
557
558 amd_iommu_reset_cmd_buffer(iommu);
559 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
560 }
561
562 static void __init free_command_buffer(struct amd_iommu *iommu)
563 {
564 free_pages((unsigned long)iommu->cmd_buf,
565 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
566 }
567
568 /* allocates the memory where the IOMMU will log its events to */
569 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
570 {
571 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
572 get_order(EVT_BUFFER_SIZE));
573
574 if (iommu->evt_buf == NULL)
575 return NULL;
576
577 iommu->evt_buf_size = EVT_BUFFER_SIZE;
578
579 return iommu->evt_buf;
580 }
581
582 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
583 {
584 u64 entry;
585
586 BUG_ON(iommu->evt_buf == NULL);
587
588 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
589
590 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
591 &entry, sizeof(entry));
592
593 /* set head and tail to zero manually */
594 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
595 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
596
597 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
598 }
599
600 static void __init free_event_buffer(struct amd_iommu *iommu)
601 {
602 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
603 }
604
605 /* allocates the memory where the IOMMU will log its events to */
606 static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
607 {
608 iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
609 get_order(PPR_LOG_SIZE));
610
611 if (iommu->ppr_log == NULL)
612 return NULL;
613
614 return iommu->ppr_log;
615 }
616
617 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
618 {
619 u64 entry;
620
621 if (iommu->ppr_log == NULL)
622 return;
623
624 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
625
626 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
627 &entry, sizeof(entry));
628
629 /* set head and tail to zero manually */
630 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
631 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
632
633 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
634 iommu_feature_enable(iommu, CONTROL_PPR_EN);
635 }
636
637 static void __init free_ppr_log(struct amd_iommu *iommu)
638 {
639 if (iommu->ppr_log == NULL)
640 return;
641
642 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
643 }
644
645 static void iommu_enable_gt(struct amd_iommu *iommu)
646 {
647 if (!iommu_feature(iommu, FEATURE_GT))
648 return;
649
650 iommu_feature_enable(iommu, CONTROL_GT_EN);
651 }
652
653 /* sets a specific bit in the device table entry. */
654 static void set_dev_entry_bit(u16 devid, u8 bit)
655 {
656 int i = (bit >> 6) & 0x03;
657 int _bit = bit & 0x3f;
658
659 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
660 }
661
662 static int get_dev_entry_bit(u16 devid, u8 bit)
663 {
664 int i = (bit >> 6) & 0x03;
665 int _bit = bit & 0x3f;
666
667 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
668 }
669
670
671 void amd_iommu_apply_erratum_63(u16 devid)
672 {
673 int sysmgt;
674
675 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
676 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
677
678 if (sysmgt == 0x01)
679 set_dev_entry_bit(devid, DEV_ENTRY_IW);
680 }
681
682 /* Writes the specific IOMMU for a device into the rlookup table */
683 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
684 {
685 amd_iommu_rlookup_table[devid] = iommu;
686 }
687
688 /*
689 * This function takes the device specific flags read from the ACPI
690 * table and sets up the device table entry with that information
691 */
692 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
693 u16 devid, u32 flags, u32 ext_flags)
694 {
695 if (flags & ACPI_DEVFLAG_INITPASS)
696 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
697 if (flags & ACPI_DEVFLAG_EXTINT)
698 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
699 if (flags & ACPI_DEVFLAG_NMI)
700 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
701 if (flags & ACPI_DEVFLAG_SYSMGT1)
702 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
703 if (flags & ACPI_DEVFLAG_SYSMGT2)
704 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
705 if (flags & ACPI_DEVFLAG_LINT0)
706 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
707 if (flags & ACPI_DEVFLAG_LINT1)
708 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
709
710 amd_iommu_apply_erratum_63(devid);
711
712 set_iommu_for_device(iommu, devid);
713 }
714
715 static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
716 {
717 struct devid_map *entry;
718 struct list_head *list;
719
720 if (type == IVHD_SPECIAL_IOAPIC)
721 list = &ioapic_map;
722 else if (type == IVHD_SPECIAL_HPET)
723 list = &hpet_map;
724 else
725 return -EINVAL;
726
727 list_for_each_entry(entry, list, list) {
728 if (!(entry->id == id && entry->cmd_line))
729 continue;
730
731 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
732 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
733
734 *devid = entry->devid;
735
736 return 0;
737 }
738
739 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
740 if (!entry)
741 return -ENOMEM;
742
743 entry->id = id;
744 entry->devid = *devid;
745 entry->cmd_line = cmd_line;
746
747 list_add_tail(&entry->list, list);
748
749 return 0;
750 }
751
752 static int __init add_early_maps(void)
753 {
754 int i, ret;
755
756 for (i = 0; i < early_ioapic_map_size; ++i) {
757 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
758 early_ioapic_map[i].id,
759 &early_ioapic_map[i].devid,
760 early_ioapic_map[i].cmd_line);
761 if (ret)
762 return ret;
763 }
764
765 for (i = 0; i < early_hpet_map_size; ++i) {
766 ret = add_special_device(IVHD_SPECIAL_HPET,
767 early_hpet_map[i].id,
768 &early_hpet_map[i].devid,
769 early_hpet_map[i].cmd_line);
770 if (ret)
771 return ret;
772 }
773
774 return 0;
775 }
776
777 /*
778 * Reads the device exclusion range from ACPI and initializes the IOMMU with
779 * it
780 */
781 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
782 {
783 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
784
785 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
786 return;
787
788 if (iommu) {
789 /*
790 * We only can configure exclusion ranges per IOMMU, not
791 * per device. But we can enable the exclusion range per
792 * device. This is done here
793 */
794 set_dev_entry_bit(devid, DEV_ENTRY_EX);
795 iommu->exclusion_start = m->range_start;
796 iommu->exclusion_length = m->range_length;
797 }
798 }
799
800 /*
801 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
802 * initializes the hardware and our data structures with it.
803 */
804 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
805 struct ivhd_header *h)
806 {
807 u8 *p = (u8 *)h;
808 u8 *end = p, flags = 0;
809 u16 devid = 0, devid_start = 0, devid_to = 0;
810 u32 dev_i, ext_flags = 0;
811 bool alias = false;
812 struct ivhd_entry *e;
813 int ret;
814
815
816 ret = add_early_maps();
817 if (ret)
818 return ret;
819
820 /*
821 * First save the recommended feature enable bits from ACPI
822 */
823 iommu->acpi_flags = h->flags;
824
825 /*
826 * Done. Now parse the device entries
827 */
828 p += sizeof(struct ivhd_header);
829 end += h->length;
830
831
832 while (p < end) {
833 e = (struct ivhd_entry *)p;
834 switch (e->type) {
835 case IVHD_DEV_ALL:
836
837 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
838 " last device %02x:%02x.%x flags: %02x\n",
839 PCI_BUS_NUM(iommu->first_device),
840 PCI_SLOT(iommu->first_device),
841 PCI_FUNC(iommu->first_device),
842 PCI_BUS_NUM(iommu->last_device),
843 PCI_SLOT(iommu->last_device),
844 PCI_FUNC(iommu->last_device),
845 e->flags);
846
847 for (dev_i = iommu->first_device;
848 dev_i <= iommu->last_device; ++dev_i)
849 set_dev_entry_from_acpi(iommu, dev_i,
850 e->flags, 0);
851 break;
852 case IVHD_DEV_SELECT:
853
854 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
855 "flags: %02x\n",
856 PCI_BUS_NUM(e->devid),
857 PCI_SLOT(e->devid),
858 PCI_FUNC(e->devid),
859 e->flags);
860
861 devid = e->devid;
862 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
863 break;
864 case IVHD_DEV_SELECT_RANGE_START:
865
866 DUMP_printk(" DEV_SELECT_RANGE_START\t "
867 "devid: %02x:%02x.%x flags: %02x\n",
868 PCI_BUS_NUM(e->devid),
869 PCI_SLOT(e->devid),
870 PCI_FUNC(e->devid),
871 e->flags);
872
873 devid_start = e->devid;
874 flags = e->flags;
875 ext_flags = 0;
876 alias = false;
877 break;
878 case IVHD_DEV_ALIAS:
879
880 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
881 "flags: %02x devid_to: %02x:%02x.%x\n",
882 PCI_BUS_NUM(e->devid),
883 PCI_SLOT(e->devid),
884 PCI_FUNC(e->devid),
885 e->flags,
886 PCI_BUS_NUM(e->ext >> 8),
887 PCI_SLOT(e->ext >> 8),
888 PCI_FUNC(e->ext >> 8));
889
890 devid = e->devid;
891 devid_to = e->ext >> 8;
892 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
893 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
894 amd_iommu_alias_table[devid] = devid_to;
895 break;
896 case IVHD_DEV_ALIAS_RANGE:
897
898 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
899 "devid: %02x:%02x.%x flags: %02x "
900 "devid_to: %02x:%02x.%x\n",
901 PCI_BUS_NUM(e->devid),
902 PCI_SLOT(e->devid),
903 PCI_FUNC(e->devid),
904 e->flags,
905 PCI_BUS_NUM(e->ext >> 8),
906 PCI_SLOT(e->ext >> 8),
907 PCI_FUNC(e->ext >> 8));
908
909 devid_start = e->devid;
910 flags = e->flags;
911 devid_to = e->ext >> 8;
912 ext_flags = 0;
913 alias = true;
914 break;
915 case IVHD_DEV_EXT_SELECT:
916
917 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
918 "flags: %02x ext: %08x\n",
919 PCI_BUS_NUM(e->devid),
920 PCI_SLOT(e->devid),
921 PCI_FUNC(e->devid),
922 e->flags, e->ext);
923
924 devid = e->devid;
925 set_dev_entry_from_acpi(iommu, devid, e->flags,
926 e->ext);
927 break;
928 case IVHD_DEV_EXT_SELECT_RANGE:
929
930 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
931 "%02x:%02x.%x flags: %02x ext: %08x\n",
932 PCI_BUS_NUM(e->devid),
933 PCI_SLOT(e->devid),
934 PCI_FUNC(e->devid),
935 e->flags, e->ext);
936
937 devid_start = e->devid;
938 flags = e->flags;
939 ext_flags = e->ext;
940 alias = false;
941 break;
942 case IVHD_DEV_RANGE_END:
943
944 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
945 PCI_BUS_NUM(e->devid),
946 PCI_SLOT(e->devid),
947 PCI_FUNC(e->devid));
948
949 devid = e->devid;
950 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
951 if (alias) {
952 amd_iommu_alias_table[dev_i] = devid_to;
953 set_dev_entry_from_acpi(iommu,
954 devid_to, flags, ext_flags);
955 }
956 set_dev_entry_from_acpi(iommu, dev_i,
957 flags, ext_flags);
958 }
959 break;
960 case IVHD_DEV_SPECIAL: {
961 u8 handle, type;
962 const char *var;
963 u16 devid;
964 int ret;
965
966 handle = e->ext & 0xff;
967 devid = (e->ext >> 8) & 0xffff;
968 type = (e->ext >> 24) & 0xff;
969
970 if (type == IVHD_SPECIAL_IOAPIC)
971 var = "IOAPIC";
972 else if (type == IVHD_SPECIAL_HPET)
973 var = "HPET";
974 else
975 var = "UNKNOWN";
976
977 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
978 var, (int)handle,
979 PCI_BUS_NUM(devid),
980 PCI_SLOT(devid),
981 PCI_FUNC(devid));
982
983 ret = add_special_device(type, handle, &devid, false);
984 if (ret)
985 return ret;
986
987 /*
988 * add_special_device might update the devid in case a
989 * command-line override is present. So call
990 * set_dev_entry_from_acpi after add_special_device.
991 */
992 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
993
994 break;
995 }
996 default:
997 break;
998 }
999
1000 p += ivhd_entry_length(p);
1001 }
1002
1003 return 0;
1004 }
1005
1006 /* Initializes the device->iommu mapping for the driver */
1007 static int __init init_iommu_devices(struct amd_iommu *iommu)
1008 {
1009 u32 i;
1010
1011 for (i = iommu->first_device; i <= iommu->last_device; ++i)
1012 set_iommu_for_device(iommu, i);
1013
1014 return 0;
1015 }
1016
1017 static void __init free_iommu_one(struct amd_iommu *iommu)
1018 {
1019 free_command_buffer(iommu);
1020 free_event_buffer(iommu);
1021 free_ppr_log(iommu);
1022 iommu_unmap_mmio_space(iommu);
1023 }
1024
1025 static void __init free_iommu_all(void)
1026 {
1027 struct amd_iommu *iommu, *next;
1028
1029 for_each_iommu_safe(iommu, next) {
1030 list_del(&iommu->list);
1031 free_iommu_one(iommu);
1032 kfree(iommu);
1033 }
1034 }
1035
1036 /*
1037 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1038 * Workaround:
1039 * BIOS should disable L2B micellaneous clock gating by setting
1040 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1041 */
1042 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1043 {
1044 u32 value;
1045
1046 if ((boot_cpu_data.x86 != 0x15) ||
1047 (boot_cpu_data.x86_model < 0x10) ||
1048 (boot_cpu_data.x86_model > 0x1f))
1049 return;
1050
1051 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1052 pci_read_config_dword(iommu->dev, 0xf4, &value);
1053
1054 if (value & BIT(2))
1055 return;
1056
1057 /* Select NB indirect register 0x90 and enable writing */
1058 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1059
1060 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1061 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1062 dev_name(&iommu->dev->dev));
1063
1064 /* Clear the enable writing bit */
1065 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1066 }
1067
1068 /*
1069 * This function clues the initialization function for one IOMMU
1070 * together and also allocates the command buffer and programs the
1071 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1072 */
1073 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1074 {
1075 int ret;
1076
1077 spin_lock_init(&iommu->lock);
1078
1079 /* Add IOMMU to internal data structures */
1080 list_add_tail(&iommu->list, &amd_iommu_list);
1081 iommu->index = amd_iommus_present++;
1082
1083 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1084 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1085 return -ENOSYS;
1086 }
1087
1088 /* Index is fine - add IOMMU to the array */
1089 amd_iommus[iommu->index] = iommu;
1090
1091 /*
1092 * Copy data from ACPI table entry to the iommu struct
1093 */
1094 iommu->devid = h->devid;
1095 iommu->cap_ptr = h->cap_ptr;
1096 iommu->pci_seg = h->pci_seg;
1097 iommu->mmio_phys = h->mmio_phys;
1098
1099 /* Check if IVHD EFR contains proper max banks/counters */
1100 if ((h->efr != 0) &&
1101 ((h->efr & (0xF << 13)) != 0) &&
1102 ((h->efr & (0x3F << 17)) != 0)) {
1103 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1104 } else {
1105 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1106 }
1107
1108 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1109 iommu->mmio_phys_end);
1110 if (!iommu->mmio_base)
1111 return -ENOMEM;
1112
1113 iommu->cmd_buf = alloc_command_buffer(iommu);
1114 if (!iommu->cmd_buf)
1115 return -ENOMEM;
1116
1117 iommu->evt_buf = alloc_event_buffer(iommu);
1118 if (!iommu->evt_buf)
1119 return -ENOMEM;
1120
1121 iommu->int_enabled = false;
1122
1123 ret = init_iommu_from_acpi(iommu, h);
1124 if (ret)
1125 return ret;
1126
1127 ret = amd_iommu_create_irq_domain(iommu);
1128 if (ret)
1129 return ret;
1130
1131 /*
1132 * Make sure IOMMU is not considered to translate itself. The IVRS
1133 * table tells us so, but this is a lie!
1134 */
1135 amd_iommu_rlookup_table[iommu->devid] = NULL;
1136
1137 init_iommu_devices(iommu);
1138
1139 return 0;
1140 }
1141
1142 /*
1143 * Iterates over all IOMMU entries in the ACPI table, allocates the
1144 * IOMMU structure and initializes it with init_iommu_one()
1145 */
1146 static int __init init_iommu_all(struct acpi_table_header *table)
1147 {
1148 u8 *p = (u8 *)table, *end = (u8 *)table;
1149 struct ivhd_header *h;
1150 struct amd_iommu *iommu;
1151 int ret;
1152
1153 end += table->length;
1154 p += IVRS_HEADER_LENGTH;
1155
1156 while (p < end) {
1157 h = (struct ivhd_header *)p;
1158 switch (*p) {
1159 case ACPI_IVHD_TYPE:
1160
1161 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1162 "seg: %d flags: %01x info %04x\n",
1163 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1164 PCI_FUNC(h->devid), h->cap_ptr,
1165 h->pci_seg, h->flags, h->info);
1166 DUMP_printk(" mmio-addr: %016llx\n",
1167 h->mmio_phys);
1168
1169 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1170 if (iommu == NULL)
1171 return -ENOMEM;
1172
1173 ret = init_iommu_one(iommu, h);
1174 if (ret)
1175 return ret;
1176 break;
1177 default:
1178 break;
1179 }
1180 p += h->length;
1181
1182 }
1183 WARN_ON(p != end);
1184
1185 return 0;
1186 }
1187
1188
1189 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1190 {
1191 u64 val = 0xabcd, val2 = 0;
1192
1193 if (!iommu_feature(iommu, FEATURE_PC))
1194 return;
1195
1196 amd_iommu_pc_present = true;
1197
1198 /* Check if the performance counters can be written to */
1199 if ((0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val, true)) ||
1200 (0 != amd_iommu_pc_get_set_reg_val(0, 0, 0, 0, &val2, false)) ||
1201 (val != val2)) {
1202 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1203 amd_iommu_pc_present = false;
1204 return;
1205 }
1206
1207 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1208
1209 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1210 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1211 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1212 }
1213
1214 static ssize_t amd_iommu_show_cap(struct device *dev,
1215 struct device_attribute *attr,
1216 char *buf)
1217 {
1218 struct amd_iommu *iommu = dev_get_drvdata(dev);
1219 return sprintf(buf, "%x\n", iommu->cap);
1220 }
1221 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1222
1223 static ssize_t amd_iommu_show_features(struct device *dev,
1224 struct device_attribute *attr,
1225 char *buf)
1226 {
1227 struct amd_iommu *iommu = dev_get_drvdata(dev);
1228 return sprintf(buf, "%llx\n", iommu->features);
1229 }
1230 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1231
1232 static struct attribute *amd_iommu_attrs[] = {
1233 &dev_attr_cap.attr,
1234 &dev_attr_features.attr,
1235 NULL,
1236 };
1237
1238 static struct attribute_group amd_iommu_group = {
1239 .name = "amd-iommu",
1240 .attrs = amd_iommu_attrs,
1241 };
1242
1243 static const struct attribute_group *amd_iommu_groups[] = {
1244 &amd_iommu_group,
1245 NULL,
1246 };
1247
1248 static int iommu_init_pci(struct amd_iommu *iommu)
1249 {
1250 int cap_ptr = iommu->cap_ptr;
1251 u32 range, misc, low, high;
1252
1253 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1254 iommu->devid & 0xff);
1255 if (!iommu->dev)
1256 return -ENODEV;
1257
1258 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1259 &iommu->cap);
1260 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1261 &range);
1262 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1263 &misc);
1264
1265 iommu->first_device = PCI_DEVID(MMIO_GET_BUS(range),
1266 MMIO_GET_FD(range));
1267 iommu->last_device = PCI_DEVID(MMIO_GET_BUS(range),
1268 MMIO_GET_LD(range));
1269
1270 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1271 amd_iommu_iotlb_sup = false;
1272
1273 /* read extended feature bits */
1274 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1275 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1276
1277 iommu->features = ((u64)high << 32) | low;
1278
1279 if (iommu_feature(iommu, FEATURE_GT)) {
1280 int glxval;
1281 u32 max_pasid;
1282 u64 pasmax;
1283
1284 pasmax = iommu->features & FEATURE_PASID_MASK;
1285 pasmax >>= FEATURE_PASID_SHIFT;
1286 max_pasid = (1 << (pasmax + 1)) - 1;
1287
1288 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1289
1290 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1291
1292 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1293 glxval >>= FEATURE_GLXVAL_SHIFT;
1294
1295 if (amd_iommu_max_glx_val == -1)
1296 amd_iommu_max_glx_val = glxval;
1297 else
1298 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1299 }
1300
1301 if (iommu_feature(iommu, FEATURE_GT) &&
1302 iommu_feature(iommu, FEATURE_PPR)) {
1303 iommu->is_iommu_v2 = true;
1304 amd_iommu_v2_present = true;
1305 }
1306
1307 if (iommu_feature(iommu, FEATURE_PPR)) {
1308 iommu->ppr_log = alloc_ppr_log(iommu);
1309 if (!iommu->ppr_log)
1310 return -ENOMEM;
1311 }
1312
1313 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1314 amd_iommu_np_cache = true;
1315
1316 init_iommu_perf_ctr(iommu);
1317
1318 if (is_rd890_iommu(iommu->dev)) {
1319 int i, j;
1320
1321 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1322 PCI_DEVFN(0, 0));
1323
1324 /*
1325 * Some rd890 systems may not be fully reconfigured by the
1326 * BIOS, so it's necessary for us to store this information so
1327 * it can be reprogrammed on resume
1328 */
1329 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1330 &iommu->stored_addr_lo);
1331 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1332 &iommu->stored_addr_hi);
1333
1334 /* Low bit locks writes to configuration space */
1335 iommu->stored_addr_lo &= ~1;
1336
1337 for (i = 0; i < 6; i++)
1338 for (j = 0; j < 0x12; j++)
1339 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1340
1341 for (i = 0; i < 0x83; i++)
1342 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1343 }
1344
1345 amd_iommu_erratum_746_workaround(iommu);
1346
1347 iommu->iommu_dev = iommu_device_create(&iommu->dev->dev, iommu,
1348 amd_iommu_groups, "ivhd%d",
1349 iommu->index);
1350
1351 return pci_enable_device(iommu->dev);
1352 }
1353
1354 static void print_iommu_info(void)
1355 {
1356 static const char * const feat_str[] = {
1357 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1358 "IA", "GA", "HE", "PC"
1359 };
1360 struct amd_iommu *iommu;
1361
1362 for_each_iommu(iommu) {
1363 int i;
1364
1365 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1366 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1367
1368 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1369 pr_info("AMD-Vi: Extended features: ");
1370 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1371 if (iommu_feature(iommu, (1ULL << i)))
1372 pr_cont(" %s", feat_str[i]);
1373 }
1374 pr_cont("\n");
1375 }
1376 }
1377 if (irq_remapping_enabled)
1378 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1379 }
1380
1381 static int __init amd_iommu_init_pci(void)
1382 {
1383 struct amd_iommu *iommu;
1384 int ret = 0;
1385
1386 for_each_iommu(iommu) {
1387 ret = iommu_init_pci(iommu);
1388 if (ret)
1389 break;
1390 }
1391
1392 ret = amd_iommu_init_devices();
1393
1394 print_iommu_info();
1395
1396 return ret;
1397 }
1398
1399 /****************************************************************************
1400 *
1401 * The following functions initialize the MSI interrupts for all IOMMUs
1402 * in the system. It's a bit challenging because there could be multiple
1403 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1404 * pci_dev.
1405 *
1406 ****************************************************************************/
1407
1408 static int iommu_setup_msi(struct amd_iommu *iommu)
1409 {
1410 int r;
1411
1412 r = pci_enable_msi(iommu->dev);
1413 if (r)
1414 return r;
1415
1416 r = request_threaded_irq(iommu->dev->irq,
1417 amd_iommu_int_handler,
1418 amd_iommu_int_thread,
1419 0, "AMD-Vi",
1420 iommu);
1421
1422 if (r) {
1423 pci_disable_msi(iommu->dev);
1424 return r;
1425 }
1426
1427 iommu->int_enabled = true;
1428
1429 return 0;
1430 }
1431
1432 static int iommu_init_msi(struct amd_iommu *iommu)
1433 {
1434 int ret;
1435
1436 if (iommu->int_enabled)
1437 goto enable_faults;
1438
1439 if (iommu->dev->msi_cap)
1440 ret = iommu_setup_msi(iommu);
1441 else
1442 ret = -ENODEV;
1443
1444 if (ret)
1445 return ret;
1446
1447 enable_faults:
1448 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1449
1450 if (iommu->ppr_log != NULL)
1451 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1452
1453 return 0;
1454 }
1455
1456 /****************************************************************************
1457 *
1458 * The next functions belong to the third pass of parsing the ACPI
1459 * table. In this last pass the memory mapping requirements are
1460 * gathered (like exclusion and unity mapping ranges).
1461 *
1462 ****************************************************************************/
1463
1464 static void __init free_unity_maps(void)
1465 {
1466 struct unity_map_entry *entry, *next;
1467
1468 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1469 list_del(&entry->list);
1470 kfree(entry);
1471 }
1472 }
1473
1474 /* called when we find an exclusion range definition in ACPI */
1475 static int __init init_exclusion_range(struct ivmd_header *m)
1476 {
1477 int i;
1478
1479 switch (m->type) {
1480 case ACPI_IVMD_TYPE:
1481 set_device_exclusion_range(m->devid, m);
1482 break;
1483 case ACPI_IVMD_TYPE_ALL:
1484 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1485 set_device_exclusion_range(i, m);
1486 break;
1487 case ACPI_IVMD_TYPE_RANGE:
1488 for (i = m->devid; i <= m->aux; ++i)
1489 set_device_exclusion_range(i, m);
1490 break;
1491 default:
1492 break;
1493 }
1494
1495 return 0;
1496 }
1497
1498 /* called for unity map ACPI definition */
1499 static int __init init_unity_map_range(struct ivmd_header *m)
1500 {
1501 struct unity_map_entry *e = NULL;
1502 char *s;
1503
1504 e = kzalloc(sizeof(*e), GFP_KERNEL);
1505 if (e == NULL)
1506 return -ENOMEM;
1507
1508 switch (m->type) {
1509 default:
1510 kfree(e);
1511 return 0;
1512 case ACPI_IVMD_TYPE:
1513 s = "IVMD_TYPEi\t\t\t";
1514 e->devid_start = e->devid_end = m->devid;
1515 break;
1516 case ACPI_IVMD_TYPE_ALL:
1517 s = "IVMD_TYPE_ALL\t\t";
1518 e->devid_start = 0;
1519 e->devid_end = amd_iommu_last_bdf;
1520 break;
1521 case ACPI_IVMD_TYPE_RANGE:
1522 s = "IVMD_TYPE_RANGE\t\t";
1523 e->devid_start = m->devid;
1524 e->devid_end = m->aux;
1525 break;
1526 }
1527 e->address_start = PAGE_ALIGN(m->range_start);
1528 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1529 e->prot = m->flags >> 1;
1530
1531 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1532 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1533 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1534 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
1535 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1536 e->address_start, e->address_end, m->flags);
1537
1538 list_add_tail(&e->list, &amd_iommu_unity_map);
1539
1540 return 0;
1541 }
1542
1543 /* iterates over all memory definitions we find in the ACPI table */
1544 static int __init init_memory_definitions(struct acpi_table_header *table)
1545 {
1546 u8 *p = (u8 *)table, *end = (u8 *)table;
1547 struct ivmd_header *m;
1548
1549 end += table->length;
1550 p += IVRS_HEADER_LENGTH;
1551
1552 while (p < end) {
1553 m = (struct ivmd_header *)p;
1554 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1555 init_exclusion_range(m);
1556 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1557 init_unity_map_range(m);
1558
1559 p += m->length;
1560 }
1561
1562 return 0;
1563 }
1564
1565 /*
1566 * Init the device table to not allow DMA access for devices and
1567 * suppress all page faults
1568 */
1569 static void init_device_table_dma(void)
1570 {
1571 u32 devid;
1572
1573 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1574 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1575 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1576 }
1577 }
1578
1579 static void __init uninit_device_table_dma(void)
1580 {
1581 u32 devid;
1582
1583 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1584 amd_iommu_dev_table[devid].data[0] = 0ULL;
1585 amd_iommu_dev_table[devid].data[1] = 0ULL;
1586 }
1587 }
1588
1589 static void init_device_table(void)
1590 {
1591 u32 devid;
1592
1593 if (!amd_iommu_irq_remap)
1594 return;
1595
1596 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1597 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1598 }
1599
1600 static void iommu_init_flags(struct amd_iommu *iommu)
1601 {
1602 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1603 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1604 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1605
1606 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1607 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1608 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1609
1610 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1611 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1612 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1613
1614 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1615 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1616 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1617
1618 /*
1619 * make IOMMU memory accesses cache coherent
1620 */
1621 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1622
1623 /* Set IOTLB invalidation timeout to 1s */
1624 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1625 }
1626
1627 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1628 {
1629 int i, j;
1630 u32 ioc_feature_control;
1631 struct pci_dev *pdev = iommu->root_pdev;
1632
1633 /* RD890 BIOSes may not have completely reconfigured the iommu */
1634 if (!is_rd890_iommu(iommu->dev) || !pdev)
1635 return;
1636
1637 /*
1638 * First, we need to ensure that the iommu is enabled. This is
1639 * controlled by a register in the northbridge
1640 */
1641
1642 /* Select Northbridge indirect register 0x75 and enable writing */
1643 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1644 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1645
1646 /* Enable the iommu */
1647 if (!(ioc_feature_control & 0x1))
1648 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1649
1650 /* Restore the iommu BAR */
1651 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1652 iommu->stored_addr_lo);
1653 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1654 iommu->stored_addr_hi);
1655
1656 /* Restore the l1 indirect regs for each of the 6 l1s */
1657 for (i = 0; i < 6; i++)
1658 for (j = 0; j < 0x12; j++)
1659 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1660
1661 /* Restore the l2 indirect regs */
1662 for (i = 0; i < 0x83; i++)
1663 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1664
1665 /* Lock PCI setup registers */
1666 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1667 iommu->stored_addr_lo | 1);
1668 }
1669
1670 /*
1671 * This function finally enables all IOMMUs found in the system after
1672 * they have been initialized
1673 */
1674 static void early_enable_iommus(void)
1675 {
1676 struct amd_iommu *iommu;
1677
1678 for_each_iommu(iommu) {
1679 iommu_disable(iommu);
1680 iommu_init_flags(iommu);
1681 iommu_set_device_table(iommu);
1682 iommu_enable_command_buffer(iommu);
1683 iommu_enable_event_buffer(iommu);
1684 iommu_set_exclusion_range(iommu);
1685 iommu_enable(iommu);
1686 iommu_flush_all_caches(iommu);
1687 }
1688 }
1689
1690 static void enable_iommus_v2(void)
1691 {
1692 struct amd_iommu *iommu;
1693
1694 for_each_iommu(iommu) {
1695 iommu_enable_ppr_log(iommu);
1696 iommu_enable_gt(iommu);
1697 }
1698 }
1699
1700 static void enable_iommus(void)
1701 {
1702 early_enable_iommus();
1703
1704 enable_iommus_v2();
1705 }
1706
1707 static void disable_iommus(void)
1708 {
1709 struct amd_iommu *iommu;
1710
1711 for_each_iommu(iommu)
1712 iommu_disable(iommu);
1713 }
1714
1715 /*
1716 * Suspend/Resume support
1717 * disable suspend until real resume implemented
1718 */
1719
1720 static void amd_iommu_resume(void)
1721 {
1722 struct amd_iommu *iommu;
1723
1724 for_each_iommu(iommu)
1725 iommu_apply_resume_quirks(iommu);
1726
1727 /* re-load the hardware */
1728 enable_iommus();
1729
1730 amd_iommu_enable_interrupts();
1731 }
1732
1733 static int amd_iommu_suspend(void)
1734 {
1735 /* disable IOMMUs to go out of the way for BIOS */
1736 disable_iommus();
1737
1738 return 0;
1739 }
1740
1741 static struct syscore_ops amd_iommu_syscore_ops = {
1742 .suspend = amd_iommu_suspend,
1743 .resume = amd_iommu_resume,
1744 };
1745
1746 static void __init free_on_init_error(void)
1747 {
1748 free_pages((unsigned long)irq_lookup_table,
1749 get_order(rlookup_table_size));
1750
1751 if (amd_iommu_irq_cache) {
1752 kmem_cache_destroy(amd_iommu_irq_cache);
1753 amd_iommu_irq_cache = NULL;
1754
1755 }
1756
1757 free_pages((unsigned long)amd_iommu_rlookup_table,
1758 get_order(rlookup_table_size));
1759
1760 free_pages((unsigned long)amd_iommu_alias_table,
1761 get_order(alias_table_size));
1762
1763 free_pages((unsigned long)amd_iommu_dev_table,
1764 get_order(dev_table_size));
1765
1766 free_iommu_all();
1767
1768 #ifdef CONFIG_GART_IOMMU
1769 /*
1770 * We failed to initialize the AMD IOMMU - try fallback to GART
1771 * if possible.
1772 */
1773 gart_iommu_init();
1774
1775 #endif
1776 }
1777
1778 /* SB IOAPIC is always on this device in AMD systems */
1779 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
1780
1781 static bool __init check_ioapic_information(void)
1782 {
1783 const char *fw_bug = FW_BUG;
1784 bool ret, has_sb_ioapic;
1785 int idx;
1786
1787 has_sb_ioapic = false;
1788 ret = false;
1789
1790 /*
1791 * If we have map overrides on the kernel command line the
1792 * messages in this function might not describe firmware bugs
1793 * anymore - so be careful
1794 */
1795 if (cmdline_maps)
1796 fw_bug = "";
1797
1798 for (idx = 0; idx < nr_ioapics; idx++) {
1799 int devid, id = mpc_ioapic_id(idx);
1800
1801 devid = get_ioapic_devid(id);
1802 if (devid < 0) {
1803 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
1804 fw_bug, id);
1805 ret = false;
1806 } else if (devid == IOAPIC_SB_DEVID) {
1807 has_sb_ioapic = true;
1808 ret = true;
1809 }
1810 }
1811
1812 if (!has_sb_ioapic) {
1813 /*
1814 * We expect the SB IOAPIC to be listed in the IVRS
1815 * table. The system timer is connected to the SB IOAPIC
1816 * and if we don't have it in the list the system will
1817 * panic at boot time. This situation usually happens
1818 * when the BIOS is buggy and provides us the wrong
1819 * device id for the IOAPIC in the system.
1820 */
1821 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
1822 }
1823
1824 if (!ret)
1825 pr_err("AMD-Vi: Disabling interrupt remapping\n");
1826
1827 return ret;
1828 }
1829
1830 static void __init free_dma_resources(void)
1831 {
1832 amd_iommu_uninit_devices();
1833
1834 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1835 get_order(MAX_DOMAIN_ID/8));
1836
1837 free_unity_maps();
1838 }
1839
1840 /*
1841 * This is the hardware init function for AMD IOMMU in the system.
1842 * This function is called either from amd_iommu_init or from the interrupt
1843 * remapping setup code.
1844 *
1845 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1846 * three times:
1847 *
1848 * 1 pass) Find the highest PCI device id the driver has to handle.
1849 * Upon this information the size of the data structures is
1850 * determined that needs to be allocated.
1851 *
1852 * 2 pass) Initialize the data structures just allocated with the
1853 * information in the ACPI table about available AMD IOMMUs
1854 * in the system. It also maps the PCI devices in the
1855 * system to specific IOMMUs
1856 *
1857 * 3 pass) After the basic data structures are allocated and
1858 * initialized we update them with information about memory
1859 * remapping requirements parsed out of the ACPI table in
1860 * this last pass.
1861 *
1862 * After everything is set up the IOMMUs are enabled and the necessary
1863 * hotplug and suspend notifiers are registered.
1864 */
1865 static int __init early_amd_iommu_init(void)
1866 {
1867 struct acpi_table_header *ivrs_base;
1868 acpi_size ivrs_size;
1869 acpi_status status;
1870 int i, ret = 0;
1871
1872 if (!amd_iommu_detected)
1873 return -ENODEV;
1874
1875 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1876 if (status == AE_NOT_FOUND)
1877 return -ENODEV;
1878 else if (ACPI_FAILURE(status)) {
1879 const char *err = acpi_format_exception(status);
1880 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1881 return -EINVAL;
1882 }
1883
1884 /*
1885 * First parse ACPI tables to find the largest Bus/Dev/Func
1886 * we need to handle. Upon this information the shared data
1887 * structures for the IOMMUs in the system will be allocated
1888 */
1889 ret = find_last_devid_acpi(ivrs_base);
1890 if (ret)
1891 goto out;
1892
1893 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1894 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1895 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1896
1897 /* Device table - directly used by all IOMMUs */
1898 ret = -ENOMEM;
1899 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1900 get_order(dev_table_size));
1901 if (amd_iommu_dev_table == NULL)
1902 goto out;
1903
1904 /*
1905 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1906 * IOMMU see for that device
1907 */
1908 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1909 get_order(alias_table_size));
1910 if (amd_iommu_alias_table == NULL)
1911 goto out;
1912
1913 /* IOMMU rlookup table - find the IOMMU for a specific device */
1914 amd_iommu_rlookup_table = (void *)__get_free_pages(
1915 GFP_KERNEL | __GFP_ZERO,
1916 get_order(rlookup_table_size));
1917 if (amd_iommu_rlookup_table == NULL)
1918 goto out;
1919
1920 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1921 GFP_KERNEL | __GFP_ZERO,
1922 get_order(MAX_DOMAIN_ID/8));
1923 if (amd_iommu_pd_alloc_bitmap == NULL)
1924 goto out;
1925
1926 /*
1927 * let all alias entries point to itself
1928 */
1929 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1930 amd_iommu_alias_table[i] = i;
1931
1932 /*
1933 * never allocate domain 0 because its used as the non-allocated and
1934 * error value placeholder
1935 */
1936 amd_iommu_pd_alloc_bitmap[0] = 1;
1937
1938 spin_lock_init(&amd_iommu_pd_lock);
1939
1940 /*
1941 * now the data structures are allocated and basically initialized
1942 * start the real acpi table scan
1943 */
1944 ret = init_iommu_all(ivrs_base);
1945 if (ret)
1946 goto out;
1947
1948 if (amd_iommu_irq_remap)
1949 amd_iommu_irq_remap = check_ioapic_information();
1950
1951 if (amd_iommu_irq_remap) {
1952 /*
1953 * Interrupt remapping enabled, create kmem_cache for the
1954 * remapping tables.
1955 */
1956 ret = -ENOMEM;
1957 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
1958 MAX_IRQS_PER_TABLE * sizeof(u32),
1959 IRQ_TABLE_ALIGNMENT,
1960 0, NULL);
1961 if (!amd_iommu_irq_cache)
1962 goto out;
1963
1964 irq_lookup_table = (void *)__get_free_pages(
1965 GFP_KERNEL | __GFP_ZERO,
1966 get_order(rlookup_table_size));
1967 if (!irq_lookup_table)
1968 goto out;
1969 }
1970
1971 ret = init_memory_definitions(ivrs_base);
1972 if (ret)
1973 goto out;
1974
1975 /* init the device table */
1976 init_device_table();
1977
1978 out:
1979 /* Don't leak any ACPI memory */
1980 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1981 ivrs_base = NULL;
1982
1983 return ret;
1984 }
1985
1986 static int amd_iommu_enable_interrupts(void)
1987 {
1988 struct amd_iommu *iommu;
1989 int ret = 0;
1990
1991 for_each_iommu(iommu) {
1992 ret = iommu_init_msi(iommu);
1993 if (ret)
1994 goto out;
1995 }
1996
1997 out:
1998 return ret;
1999 }
2000
2001 static bool detect_ivrs(void)
2002 {
2003 struct acpi_table_header *ivrs_base;
2004 acpi_size ivrs_size;
2005 acpi_status status;
2006
2007 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
2008 if (status == AE_NOT_FOUND)
2009 return false;
2010 else if (ACPI_FAILURE(status)) {
2011 const char *err = acpi_format_exception(status);
2012 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2013 return false;
2014 }
2015
2016 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
2017
2018 /* Make sure ACS will be enabled during PCI probe */
2019 pci_request_acs();
2020
2021 return true;
2022 }
2023
2024 static int amd_iommu_init_dma(void)
2025 {
2026 struct amd_iommu *iommu;
2027 int ret;
2028
2029 if (iommu_pass_through)
2030 ret = amd_iommu_init_passthrough();
2031 else
2032 ret = amd_iommu_init_dma_ops();
2033
2034 if (ret)
2035 return ret;
2036
2037 init_device_table_dma();
2038
2039 for_each_iommu(iommu)
2040 iommu_flush_all_caches(iommu);
2041
2042 amd_iommu_init_api();
2043
2044 amd_iommu_init_notifier();
2045
2046 return 0;
2047 }
2048
2049 /****************************************************************************
2050 *
2051 * AMD IOMMU Initialization State Machine
2052 *
2053 ****************************************************************************/
2054
2055 static int __init state_next(void)
2056 {
2057 int ret = 0;
2058
2059 switch (init_state) {
2060 case IOMMU_START_STATE:
2061 if (!detect_ivrs()) {
2062 init_state = IOMMU_NOT_FOUND;
2063 ret = -ENODEV;
2064 } else {
2065 init_state = IOMMU_IVRS_DETECTED;
2066 }
2067 break;
2068 case IOMMU_IVRS_DETECTED:
2069 ret = early_amd_iommu_init();
2070 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2071 break;
2072 case IOMMU_ACPI_FINISHED:
2073 early_enable_iommus();
2074 register_syscore_ops(&amd_iommu_syscore_ops);
2075 x86_platform.iommu_shutdown = disable_iommus;
2076 init_state = IOMMU_ENABLED;
2077 break;
2078 case IOMMU_ENABLED:
2079 ret = amd_iommu_init_pci();
2080 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2081 enable_iommus_v2();
2082 break;
2083 case IOMMU_PCI_INIT:
2084 ret = amd_iommu_enable_interrupts();
2085 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2086 break;
2087 case IOMMU_INTERRUPTS_EN:
2088 ret = amd_iommu_init_dma();
2089 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2090 break;
2091 case IOMMU_DMA_OPS:
2092 init_state = IOMMU_INITIALIZED;
2093 break;
2094 case IOMMU_INITIALIZED:
2095 /* Nothing to do */
2096 break;
2097 case IOMMU_NOT_FOUND:
2098 case IOMMU_INIT_ERROR:
2099 /* Error states => do nothing */
2100 ret = -EINVAL;
2101 break;
2102 default:
2103 /* Unknown state */
2104 BUG();
2105 }
2106
2107 return ret;
2108 }
2109
2110 static int __init iommu_go_to_state(enum iommu_init_state state)
2111 {
2112 int ret = 0;
2113
2114 while (init_state != state) {
2115 ret = state_next();
2116 if (init_state == IOMMU_NOT_FOUND ||
2117 init_state == IOMMU_INIT_ERROR)
2118 break;
2119 }
2120
2121 return ret;
2122 }
2123
2124 #ifdef CONFIG_IRQ_REMAP
2125 int __init amd_iommu_prepare(void)
2126 {
2127 int ret;
2128
2129 amd_iommu_irq_remap = true;
2130
2131 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2132 if (ret)
2133 return ret;
2134 return amd_iommu_irq_remap ? 0 : -ENODEV;
2135 }
2136
2137 int __init amd_iommu_enable(void)
2138 {
2139 int ret;
2140
2141 ret = iommu_go_to_state(IOMMU_ENABLED);
2142 if (ret)
2143 return ret;
2144
2145 irq_remapping_enabled = 1;
2146
2147 return 0;
2148 }
2149
2150 void amd_iommu_disable(void)
2151 {
2152 amd_iommu_suspend();
2153 }
2154
2155 int amd_iommu_reenable(int mode)
2156 {
2157 amd_iommu_resume();
2158
2159 return 0;
2160 }
2161
2162 int __init amd_iommu_enable_faulting(void)
2163 {
2164 /* We enable MSI later when PCI is initialized */
2165 return 0;
2166 }
2167 #endif
2168
2169 /*
2170 * This is the core init function for AMD IOMMU hardware in the system.
2171 * This function is called from the generic x86 DMA layer initialization
2172 * code.
2173 */
2174 static int __init amd_iommu_init(void)
2175 {
2176 int ret;
2177
2178 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2179 if (ret) {
2180 free_dma_resources();
2181 if (!irq_remapping_enabled) {
2182 disable_iommus();
2183 free_on_init_error();
2184 } else {
2185 struct amd_iommu *iommu;
2186
2187 uninit_device_table_dma();
2188 for_each_iommu(iommu)
2189 iommu_flush_all_caches(iommu);
2190 }
2191 }
2192
2193 return ret;
2194 }
2195
2196 /****************************************************************************
2197 *
2198 * Early detect code. This code runs at IOMMU detection time in the DMA
2199 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2200 * IOMMUs
2201 *
2202 ****************************************************************************/
2203 int __init amd_iommu_detect(void)
2204 {
2205 int ret;
2206
2207 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2208 return -ENODEV;
2209
2210 if (amd_iommu_disabled)
2211 return -ENODEV;
2212
2213 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2214 if (ret)
2215 return ret;
2216
2217 amd_iommu_detected = true;
2218 iommu_detected = 1;
2219 x86_init.iommu.iommu_init = amd_iommu_init;
2220
2221 return 0;
2222 }
2223
2224 /****************************************************************************
2225 *
2226 * Parsing functions for the AMD IOMMU specific kernel command line
2227 * options.
2228 *
2229 ****************************************************************************/
2230
2231 static int __init parse_amd_iommu_dump(char *str)
2232 {
2233 amd_iommu_dump = true;
2234
2235 return 1;
2236 }
2237
2238 static int __init parse_amd_iommu_options(char *str)
2239 {
2240 for (; *str; ++str) {
2241 if (strncmp(str, "fullflush", 9) == 0)
2242 amd_iommu_unmap_flush = true;
2243 if (strncmp(str, "off", 3) == 0)
2244 amd_iommu_disabled = true;
2245 if (strncmp(str, "force_isolation", 15) == 0)
2246 amd_iommu_force_isolation = true;
2247 }
2248
2249 return 1;
2250 }
2251
2252 static int __init parse_ivrs_ioapic(char *str)
2253 {
2254 unsigned int bus, dev, fn;
2255 int ret, id, i;
2256 u16 devid;
2257
2258 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2259
2260 if (ret != 4) {
2261 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2262 return 1;
2263 }
2264
2265 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2266 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2267 str);
2268 return 1;
2269 }
2270
2271 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2272
2273 cmdline_maps = true;
2274 i = early_ioapic_map_size++;
2275 early_ioapic_map[i].id = id;
2276 early_ioapic_map[i].devid = devid;
2277 early_ioapic_map[i].cmd_line = true;
2278
2279 return 1;
2280 }
2281
2282 static int __init parse_ivrs_hpet(char *str)
2283 {
2284 unsigned int bus, dev, fn;
2285 int ret, id, i;
2286 u16 devid;
2287
2288 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2289
2290 if (ret != 4) {
2291 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2292 return 1;
2293 }
2294
2295 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2296 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2297 str);
2298 return 1;
2299 }
2300
2301 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2302
2303 cmdline_maps = true;
2304 i = early_hpet_map_size++;
2305 early_hpet_map[i].id = id;
2306 early_hpet_map[i].devid = devid;
2307 early_hpet_map[i].cmd_line = true;
2308
2309 return 1;
2310 }
2311
2312 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2313 __setup("amd_iommu=", parse_amd_iommu_options);
2314 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2315 __setup("ivrs_hpet", parse_ivrs_hpet);
2316
2317 IOMMU_INIT_FINISH(amd_iommu_detect,
2318 gart_iommu_hole_init,
2319 NULL,
2320 NULL);
2321
2322 bool amd_iommu_v2_supported(void)
2323 {
2324 return amd_iommu_v2_present;
2325 }
2326 EXPORT_SYMBOL(amd_iommu_v2_supported);
2327
2328 /****************************************************************************
2329 *
2330 * IOMMU EFR Performance Counter support functionality. This code allows
2331 * access to the IOMMU PC functionality.
2332 *
2333 ****************************************************************************/
2334
2335 u8 amd_iommu_pc_get_max_banks(u16 devid)
2336 {
2337 struct amd_iommu *iommu;
2338 u8 ret = 0;
2339
2340 /* locate the iommu governing the devid */
2341 iommu = amd_iommu_rlookup_table[devid];
2342 if (iommu)
2343 ret = iommu->max_banks;
2344
2345 return ret;
2346 }
2347 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2348
2349 bool amd_iommu_pc_supported(void)
2350 {
2351 return amd_iommu_pc_present;
2352 }
2353 EXPORT_SYMBOL(amd_iommu_pc_supported);
2354
2355 u8 amd_iommu_pc_get_max_counters(u16 devid)
2356 {
2357 struct amd_iommu *iommu;
2358 u8 ret = 0;
2359
2360 /* locate the iommu governing the devid */
2361 iommu = amd_iommu_rlookup_table[devid];
2362 if (iommu)
2363 ret = iommu->max_counters;
2364
2365 return ret;
2366 }
2367 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2368
2369 int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
2370 u64 *value, bool is_write)
2371 {
2372 struct amd_iommu *iommu;
2373 u32 offset;
2374 u32 max_offset_lim;
2375
2376 /* Make sure the IOMMU PC resource is available */
2377 if (!amd_iommu_pc_present)
2378 return -ENODEV;
2379
2380 /* Locate the iommu associated with the device ID */
2381 iommu = amd_iommu_rlookup_table[devid];
2382
2383 /* Check for valid iommu and pc register indexing */
2384 if (WARN_ON((iommu == NULL) || (fxn > 0x28) || (fxn & 7)))
2385 return -ENODEV;
2386
2387 offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
2388
2389 /* Limit the offset to the hw defined mmio region aperture */
2390 max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) |
2391 (iommu->max_counters << 8) | 0x28);
2392 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2393 (offset > max_offset_lim))
2394 return -EINVAL;
2395
2396 if (is_write) {
2397 writel((u32)*value, iommu->mmio_base + offset);
2398 writel((*value >> 32), iommu->mmio_base + offset + 4);
2399 } else {
2400 *value = readl(iommu->mmio_base + offset + 4);
2401 *value <<= 32;
2402 *value = readl(iommu->mmio_base + offset);
2403 }
2404
2405 return 0;
2406 }
2407 EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
Linux kernel - Deliverables
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