drivers/iommu/amd_iommu_types.h

   1 /*
   2  * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <joerg.roedel@amd.com>
   4  *         Leo Duran <leo.duran@amd.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
  21 #define _ASM_X86_AMD_IOMMU_TYPES_H
  22
  23 #include <linux/types.h>
  24 #include <linux/mutex.h>
  25 #include <linux/list.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/pci.h>
  28
  29 /*
  30  * Maximum number of IOMMUs supported
  31  */
  32 #define MAX_IOMMUS      32
  33
  34 /*
  35  * some size calculation constants
  36  */
  37 #define DEV_TABLE_ENTRY_SIZE            32
  38 #define ALIAS_TABLE_ENTRY_SIZE          2
  39 #define RLOOKUP_TABLE_ENTRY_SIZE        (sizeof(void *))
  40
  41 /* Capability offsets used by the driver */
  42 #define MMIO_CAP_HDR_OFFSET     0x00
  43 #define MMIO_RANGE_OFFSET       0x0c
  44 #define MMIO_MISC_OFFSET        0x10
  45
  46 /* Masks, shifts and macros to parse the device range capability */
  47 #define MMIO_RANGE_LD_MASK      0xff000000
  48 #define MMIO_RANGE_FD_MASK      0x00ff0000
  49 #define MMIO_RANGE_BUS_MASK     0x0000ff00
  50 #define MMIO_RANGE_LD_SHIFT     24
  51 #define MMIO_RANGE_FD_SHIFT     16
  52 #define MMIO_RANGE_BUS_SHIFT    8
  53 #define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
  54 #define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
  55 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
  56 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
  57
  58 /* Flag masks for the AMD IOMMU exclusion range */
  59 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
  60 #define MMIO_EXCL_ALLOW_MASK  0x02ULL
  61
  62 /* Used offsets into the MMIO space */
  63 #define MMIO_DEV_TABLE_OFFSET   0x0000
  64 #define MMIO_CMD_BUF_OFFSET     0x0008
  65 #define MMIO_EVT_BUF_OFFSET     0x0010
  66 #define MMIO_CONTROL_OFFSET     0x0018
  67 #define MMIO_EXCL_BASE_OFFSET   0x0020
  68 #define MMIO_EXCL_LIMIT_OFFSET  0x0028
  69 #define MMIO_EXT_FEATURES       0x0030
  70 #define MMIO_PPR_LOG_OFFSET     0x0038
  71 #define MMIO_CMD_HEAD_OFFSET    0x2000
  72 #define MMIO_CMD_TAIL_OFFSET    0x2008
  73 #define MMIO_EVT_HEAD_OFFSET    0x2010
  74 #define MMIO_EVT_TAIL_OFFSET    0x2018
  75 #define MMIO_STATUS_OFFSET      0x2020
  76 #define MMIO_PPR_HEAD_OFFSET    0x2030
  77 #define MMIO_PPR_TAIL_OFFSET    0x2038
  78 #define MMIO_CNTR_CONF_OFFSET   0x4000
  79 #define MMIO_CNTR_REG_OFFSET    0x40000
  80 #define MMIO_REG_END_OFFSET     0x80000
  81
  82
  83
  84 /* Extended Feature Bits */
  85 #define FEATURE_PREFETCH        (1ULL<<0)
  86 #define FEATURE_PPR             (1ULL<<1)
  87 #define FEATURE_X2APIC          (1ULL<<2)
  88 #define FEATURE_NX              (1ULL<<3)
  89 #define FEATURE_GT              (1ULL<<4)
  90 #define FEATURE_IA              (1ULL<<6)
  91 #define FEATURE_GA              (1ULL<<7)
  92 #define FEATURE_HE              (1ULL<<8)
  93 #define FEATURE_PC              (1ULL<<9)
  94
  95 #define FEATURE_PASID_SHIFT     32
  96 #define FEATURE_PASID_MASK      (0x1fULL << FEATURE_PASID_SHIFT)
  97
  98 #define FEATURE_GLXVAL_SHIFT    14
  99 #define FEATURE_GLXVAL_MASK     (0x03ULL << FEATURE_GLXVAL_SHIFT)
 100
 101 #define PASID_MASK              0x000fffff
 102
 103 /* MMIO status bits */
 104 #define MMIO_STATUS_EVT_INT_MASK        (1 << 1)
 105 #define MMIO_STATUS_COM_WAIT_INT_MASK   (1 << 2)
 106 #define MMIO_STATUS_PPR_INT_MASK        (1 << 6)
 107
 108 /* event logging constants */
 109 #define EVENT_ENTRY_SIZE        0x10
 110 #define EVENT_TYPE_SHIFT        28
 111 #define EVENT_TYPE_MASK         0xf
 112 #define EVENT_TYPE_ILL_DEV      0x1
 113 #define EVENT_TYPE_IO_FAULT     0x2
 114 #define EVENT_TYPE_DEV_TAB_ERR  0x3
 115 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
 116 #define EVENT_TYPE_ILL_CMD      0x5
 117 #define EVENT_TYPE_CMD_HARD_ERR 0x6
 118 #define EVENT_TYPE_IOTLB_INV_TO 0x7
 119 #define EVENT_TYPE_INV_DEV_REQ  0x8
 120 #define EVENT_DEVID_MASK        0xffff
 121 #define EVENT_DEVID_SHIFT       0
 122 #define EVENT_DOMID_MASK        0xffff
 123 #define EVENT_DOMID_SHIFT       0
 124 #define EVENT_FLAGS_MASK        0xfff
 125 #define EVENT_FLAGS_SHIFT       0x10
 126
 127 /* feature control bits */
 128 #define CONTROL_IOMMU_EN        0x00ULL
 129 #define CONTROL_HT_TUN_EN       0x01ULL
 130 #define CONTROL_EVT_LOG_EN      0x02ULL
 131 #define CONTROL_EVT_INT_EN      0x03ULL
 132 #define CONTROL_COMWAIT_EN      0x04ULL
 133 #define CONTROL_INV_TIMEOUT     0x05ULL
 134 #define CONTROL_PASSPW_EN       0x08ULL
 135 #define CONTROL_RESPASSPW_EN    0x09ULL
 136 #define CONTROL_COHERENT_EN     0x0aULL
 137 #define CONTROL_ISOC_EN         0x0bULL
 138 #define CONTROL_CMDBUF_EN       0x0cULL
 139 #define CONTROL_PPFLOG_EN       0x0dULL
 140 #define CONTROL_PPFINT_EN       0x0eULL
 141 #define CONTROL_PPR_EN          0x0fULL
 142 #define CONTROL_GT_EN           0x10ULL
 143
 144 #define CTRL_INV_TO_MASK        (7 << CONTROL_INV_TIMEOUT)
 145 #define CTRL_INV_TO_NONE        0
 146 #define CTRL_INV_TO_1MS         1
 147 #define CTRL_INV_TO_10MS        2
 148 #define CTRL_INV_TO_100MS       3
 149 #define CTRL_INV_TO_1S          4
 150 #define CTRL_INV_TO_10S         5
 151 #define CTRL_INV_TO_100S        6
 152
 153 /* command specific defines */
 154 #define CMD_COMPL_WAIT          0x01
 155 #define CMD_INV_DEV_ENTRY       0x02
 156 #define CMD_INV_IOMMU_PAGES     0x03
 157 #define CMD_INV_IOTLB_PAGES     0x04
 158 #define CMD_INV_IRT             0x05
 159 #define CMD_COMPLETE_PPR        0x07
 160 #define CMD_INV_ALL             0x08
 161
 162 #define CMD_COMPL_WAIT_STORE_MASK       0x01
 163 #define CMD_COMPL_WAIT_INT_MASK         0x02
 164 #define CMD_INV_IOMMU_PAGES_SIZE_MASK   0x01
 165 #define CMD_INV_IOMMU_PAGES_PDE_MASK    0x02
 166 #define CMD_INV_IOMMU_PAGES_GN_MASK     0x04
 167
 168 #define PPR_STATUS_MASK                 0xf
 169 #define PPR_STATUS_SHIFT                12
 170
 171 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
 172
 173 /* macros and definitions for device table entries */
 174 #define DEV_ENTRY_VALID         0x00
 175 #define DEV_ENTRY_TRANSLATION   0x01
 176 #define DEV_ENTRY_IR            0x3d
 177 #define DEV_ENTRY_IW            0x3e
 178 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
 179 #define DEV_ENTRY_EX            0x67
 180 #define DEV_ENTRY_SYSMGT1       0x68
 181 #define DEV_ENTRY_SYSMGT2       0x69
 182 #define DEV_ENTRY_IRQ_TBL_EN    0x80
 183 #define DEV_ENTRY_INIT_PASS     0xb8
 184 #define DEV_ENTRY_EINT_PASS     0xb9
 185 #define DEV_ENTRY_NMI_PASS      0xba
 186 #define DEV_ENTRY_LINT0_PASS    0xbe
 187 #define DEV_ENTRY_LINT1_PASS    0xbf
 188 #define DEV_ENTRY_MODE_MASK     0x07
 189 #define DEV_ENTRY_MODE_SHIFT    0x09
 190
 191 #define MAX_DEV_TABLE_ENTRIES   0xffff
 192
 193 /* constants to configure the command buffer */
 194 #define CMD_BUFFER_SIZE    8192
 195 #define CMD_BUFFER_UNINITIALIZED 1
 196 #define CMD_BUFFER_ENTRIES 512
 197 #define MMIO_CMD_SIZE_SHIFT 56
 198 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
 199
 200 /* constants for event buffer handling */
 201 #define EVT_BUFFER_SIZE         8192 /* 512 entries */
 202 #define EVT_LEN_MASK            (0x9ULL << 56)
 203
 204 /* Constants for PPR Log handling */
 205 #define PPR_LOG_ENTRIES         512
 206 #define PPR_LOG_SIZE_SHIFT      56
 207 #define PPR_LOG_SIZE_512        (0x9ULL << PPR_LOG_SIZE_SHIFT)
 208 #define PPR_ENTRY_SIZE          16
 209 #define PPR_LOG_SIZE            (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
 210
 211 #define PPR_REQ_TYPE(x)         (((x) >> 60) & 0xfULL)
 212 #define PPR_FLAGS(x)            (((x) >> 48) & 0xfffULL)
 213 #define PPR_DEVID(x)            ((x) & 0xffffULL)
 214 #define PPR_TAG(x)              (((x) >> 32) & 0x3ffULL)
 215 #define PPR_PASID1(x)           (((x) >> 16) & 0xffffULL)
 216 #define PPR_PASID2(x)           (((x) >> 42) & 0xfULL)
 217 #define PPR_PASID(x)            ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
 218
 219 #define PPR_REQ_FAULT           0x01
 220
 221 #define PAGE_MODE_NONE    0x00
 222 #define PAGE_MODE_1_LEVEL 0x01
 223 #define PAGE_MODE_2_LEVEL 0x02
 224 #define PAGE_MODE_3_LEVEL 0x03
 225 #define PAGE_MODE_4_LEVEL 0x04
 226 #define PAGE_MODE_5_LEVEL 0x05
 227 #define PAGE_MODE_6_LEVEL 0x06
 228
 229 #define PM_LEVEL_SHIFT(x)       (12 + ((x) * 9))
 230 #define PM_LEVEL_SIZE(x)        (((x) < 6) ? \
 231                                   ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
 232                                    (0xffffffffffffffffULL))
 233 #define PM_LEVEL_INDEX(x, a)    (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
 234 #define PM_LEVEL_ENC(x)         (((x) << 9) & 0xe00ULL)
 235 #define PM_LEVEL_PDE(x, a)      ((a) | PM_LEVEL_ENC((x)) | \
 236                                  IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
 237 #define PM_PTE_LEVEL(pte)       (((pte) >> 9) & 0x7ULL)
 238
 239 #define PM_MAP_4k               0
 240 #define PM_ADDR_MASK            0x000ffffffffff000ULL
 241 #define PM_MAP_MASK(lvl)        (PM_ADDR_MASK & \
 242                                 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
 243 #define PM_ALIGNED(lvl, addr)   ((PM_MAP_MASK(lvl) & (addr)) == (addr))
 244
 245 /*
 246  * Returns the page table level to use for a given page size
 247  * Pagesize is expected to be a power-of-two
 248  */
 249 #define PAGE_SIZE_LEVEL(pagesize) \
 250                 ((__ffs(pagesize) - 12) / 9)
 251 /*
 252  * Returns the number of ptes to use for a given page size
 253  * Pagesize is expected to be a power-of-two
 254  */
 255 #define PAGE_SIZE_PTE_COUNT(pagesize) \
 256                 (1ULL << ((__ffs(pagesize) - 12) % 9))
 257
 258 /*
 259  * Aligns a given io-virtual address to a given page size
 260  * Pagesize is expected to be a power-of-two
 261  */
 262 #define PAGE_SIZE_ALIGN(address, pagesize) \
 263                 ((address) & ~((pagesize) - 1))
 264 /*
 265  * Creates an IOMMU PTE for an address and a given pagesize
 266  * The PTE has no permission bits set
 267  * Pagesize is expected to be a power-of-two larger than 4096
 268  */
 269 #define PAGE_SIZE_PTE(address, pagesize)                \
 270                 (((address) | ((pagesize) - 1)) &       \
 271                  (~(pagesize >> 1)) & PM_ADDR_MASK)
 272
 273 /*
 274  * Takes a PTE value with mode=0x07 and returns the page size it maps
 275  */
 276 #define PTE_PAGE_SIZE(pte) \
 277         (1ULL << (1 + ffz(((pte) | 0xfffULL))))
 278
 279 #define IOMMU_PTE_P  (1ULL << 0)
 280 #define IOMMU_PTE_TV (1ULL << 1)
 281 #define IOMMU_PTE_U  (1ULL << 59)
 282 #define IOMMU_PTE_FC (1ULL << 60)
 283 #define IOMMU_PTE_IR (1ULL << 61)
 284 #define IOMMU_PTE_IW (1ULL << 62)
 285
 286 #define DTE_FLAG_IOTLB  (0x01UL << 32)
 287 #define DTE_FLAG_GV     (0x01ULL << 55)
 288 #define DTE_GLX_SHIFT   (56)
 289 #define DTE_GLX_MASK    (3)
 290
 291 #define DTE_GCR3_VAL_A(x)       (((x) >> 12) & 0x00007ULL)
 292 #define DTE_GCR3_VAL_B(x)       (((x) >> 15) & 0x0ffffULL)
 293 #define DTE_GCR3_VAL_C(x)       (((x) >> 31) & 0xfffffULL)
 294
 295 #define DTE_GCR3_INDEX_A        0
 296 #define DTE_GCR3_INDEX_B        1
 297 #define DTE_GCR3_INDEX_C        1
 298
 299 #define DTE_GCR3_SHIFT_A        58
 300 #define DTE_GCR3_SHIFT_B        16
 301 #define DTE_GCR3_SHIFT_C        43
 302
 303 #define GCR3_VALID              0x01ULL
 304
 305 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
 306 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
 307 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
 308 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
 309
 310 #define IOMMU_PROT_MASK 0x03
 311 #define IOMMU_PROT_IR 0x01
 312 #define IOMMU_PROT_IW 0x02
 313
 314 /* IOMMU capabilities */
 315 #define IOMMU_CAP_IOTLB   24
 316 #define IOMMU_CAP_NPCACHE 26
 317 #define IOMMU_CAP_EFR     27
 318
 319 #define MAX_DOMAIN_ID 65536
 320
 321 /* Protection domain flags */
 322 #define PD_DMA_OPS_MASK         (1UL << 0) /* domain used for dma_ops */
 323 #define PD_DEFAULT_MASK         (1UL << 1) /* domain is a default dma_ops
 324                                               domain for an IOMMU */
 325 #define PD_PASSTHROUGH_MASK     (1UL << 2) /* domain has no page
 326                                               translation */
 327 #define PD_IOMMUV2_MASK         (1UL << 3) /* domain has gcr3 table */
 328
 329 extern bool amd_iommu_dump;
 330 #define DUMP_printk(format, arg...)                                     \
 331         do {                                                            \
 332                 if (amd_iommu_dump)                                             \
 333                         printk(KERN_INFO "AMD-Vi: " format, ## arg);    \
 334         } while(0);
 335
 336 /* global flag if IOMMUs cache non-present entries */
 337 extern bool amd_iommu_np_cache;
 338 /* Only true if all IOMMUs support device IOTLBs */
 339 extern bool amd_iommu_iotlb_sup;
 340
 341 #define MAX_IRQS_PER_TABLE      256
 342 #define IRQ_TABLE_ALIGNMENT     128
 343
 344 struct irq_remap_table {
 345         spinlock_t lock;
 346         unsigned min_index;
 347         u32 *table;
 348 };
 349
 350 extern struct irq_remap_table **irq_lookup_table;
 351
 352 /* Interrupt remapping feature used? */
 353 extern bool amd_iommu_irq_remap;
 354
 355 /* kmem_cache to get tables with 128 byte alignement */
 356 extern struct kmem_cache *amd_iommu_irq_cache;
 357
 358 /*
 359  * Make iterating over all IOMMUs easier
 360  */
 361 #define for_each_iommu(iommu) \
 362         list_for_each_entry((iommu), &amd_iommu_list, list)
 363 #define for_each_iommu_safe(iommu, next) \
 364         list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
 365
 366 #define APERTURE_RANGE_SHIFT    27      /* 128 MB */
 367 #define APERTURE_RANGE_SIZE     (1ULL << APERTURE_RANGE_SHIFT)
 368 #define APERTURE_RANGE_PAGES    (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
 369 #define APERTURE_MAX_RANGES     32      /* allows 4GB of DMA address space */
 370 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
 371 #define APERTURE_PAGE_INDEX(a)  (((a) >> 21) & 0x3fULL)
 372
 373
 374 /*
 375  * This struct is used to pass information about
 376  * incoming PPR faults around.
 377  */
 378 struct amd_iommu_fault {
 379         u64 address;    /* IO virtual address of the fault*/
 380         u32 pasid;      /* Address space identifier */
 381         u16 device_id;  /* Originating PCI device id */
 382         u16 tag;        /* PPR tag */
 383         u16 flags;      /* Fault flags */
 384
 385 };
 386
 387 #define PPR_FAULT_EXEC  (1 << 1)
 388 #define PPR_FAULT_READ  (1 << 2)
 389 #define PPR_FAULT_WRITE (1 << 5)
 390 #define PPR_FAULT_USER  (1 << 6)
 391 #define PPR_FAULT_RSVD  (1 << 7)
 392 #define PPR_FAULT_GN    (1 << 8)
 393
 394 struct iommu_domain;
 395
 396 /*
 397  * This structure contains generic data for  IOMMU protection domains
 398  * independent of their use.
 399  */
 400 struct protection_domain {
 401         struct list_head list;  /* for list of all protection domains */
 402         struct list_head dev_list; /* List of all devices in this domain */
 403         spinlock_t lock;        /* mostly used to lock the page table*/
 404         struct mutex api_lock;  /* protect page tables in the iommu-api path */
 405         u16 id;                 /* the domain id written to the device table */
 406         int mode;               /* paging mode (0-6 levels) */
 407         u64 *pt_root;           /* page table root pointer */
 408         int glx;                /* Number of levels for GCR3 table */
 409         u64 *gcr3_tbl;          /* Guest CR3 table */
 410         unsigned long flags;    /* flags to find out type of domain */
 411         bool updated;           /* complete domain flush required */
 412         unsigned dev_cnt;       /* devices assigned to this domain */
 413         unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
 414         void *priv;             /* private data */
 415         struct iommu_domain *iommu_domain; /* Pointer to generic
 416                                               domain structure */
 417
 418 };
 419
 420 /*
 421  * This struct contains device specific data for the IOMMU
 422  */
 423 struct iommu_dev_data {
 424         struct list_head list;            /* For domain->dev_list */
 425         struct list_head dev_data_list;   /* For global dev_data_list */
 426         struct iommu_dev_data *alias_data;/* The alias dev_data */
 427         struct protection_domain *domain; /* Domain the device is bound to */
 428         atomic_t bind;                    /* Domain attach reference count */
 429         struct iommu_group *group;        /* IOMMU group for virtual aliases */
 430         u16 devid;                        /* PCI Device ID */
 431         bool iommu_v2;                    /* Device can make use of IOMMUv2 */
 432         bool passthrough;                 /* Default for device is pt_domain */
 433         struct {
 434                 bool enabled;
 435                 int qdep;
 436         } ats;                            /* ATS state */
 437         bool pri_tlp;                     /* PASID TLB required for
 438                                              PPR completions */
 439         u32 errata;                       /* Bitmap for errata to apply */
 440 };
 441
 442 /*
 443  * For dynamic growth the aperture size is split into ranges of 128MB of
 444  * DMA address space each. This struct represents one such range.
 445  */
 446 struct aperture_range {
 447
 448         /* address allocation bitmap */
 449         unsigned long *bitmap;
 450
 451         /*
 452          * Array of PTE pages for the aperture. In this array we save all the
 453          * leaf pages of the domain page table used for the aperture. This way
 454          * we don't need to walk the page table to find a specific PTE. We can
 455          * just calculate its address in constant time.
 456          */
 457         u64 *pte_pages[64];
 458
 459         unsigned long offset;
 460 };
 461
 462 /*
 463  * Data container for a dma_ops specific protection domain
 464  */
 465 struct dma_ops_domain {
 466         struct list_head list;
 467
 468         /* generic protection domain information */
 469         struct protection_domain domain;
 470
 471         /* size of the aperture for the mappings */
 472         unsigned long aperture_size;
 473
 474         /* address we start to search for free addresses */
 475         unsigned long next_address;
 476
 477         /* address space relevant data */
 478         struct aperture_range *aperture[APERTURE_MAX_RANGES];
 479
 480         /* This will be set to true when TLB needs to be flushed */
 481         bool need_flush;
 482
 483         /*
 484          * if this is a preallocated domain, keep the device for which it was
 485          * preallocated in this variable
 486          */
 487         u16 target_dev;
 488 };
 489
 490 /*
 491  * Structure where we save information about one hardware AMD IOMMU in the
 492  * system.
 493  */
 494 struct amd_iommu {
 495         struct list_head list;
 496
 497         /* Index within the IOMMU array */
 498         int index;
 499
 500         /* locks the accesses to the hardware */
 501         spinlock_t lock;
 502
 503         /* Pointer to PCI device of this IOMMU */
 504         struct pci_dev *dev;
 505
 506         /* Cache pdev to root device for resume quirks */
 507         struct pci_dev *root_pdev;
 508
 509         /* physical address of MMIO space */
 510         u64 mmio_phys;
 511
 512         /* physical end address of MMIO space */
 513         u64 mmio_phys_end;
 514
 515         /* virtual address of MMIO space */
 516         u8 __iomem *mmio_base;
 517
 518         /* capabilities of that IOMMU read from ACPI */
 519         u32 cap;
 520
 521         /* flags read from acpi table */
 522         u8 acpi_flags;
 523
 524         /* Extended features */
 525         u64 features;
 526
 527         /* IOMMUv2 */
 528         bool is_iommu_v2;
 529
 530         /* PCI device id of the IOMMU device */
 531         u16 devid;
 532
 533         /*
 534          * Capability pointer. There could be more than one IOMMU per PCI
 535          * device function if there are more than one AMD IOMMU capability
 536          * pointers.
 537          */
 538         u16 cap_ptr;
 539
 540         /* pci domain of this IOMMU */
 541         u16 pci_seg;
 542
 543         /* first device this IOMMU handles. read from PCI */
 544         u16 first_device;
 545         /* last device this IOMMU handles. read from PCI */
 546         u16 last_device;
 547
 548         /* start of exclusion range of that IOMMU */
 549         u64 exclusion_start;
 550         /* length of exclusion range of that IOMMU */
 551         u64 exclusion_length;
 552
 553         /* command buffer virtual address */
 554         u8 *cmd_buf;
 555         /* size of command buffer */
 556         u32 cmd_buf_size;
 557
 558         /* size of event buffer */
 559         u32 evt_buf_size;
 560         /* event buffer virtual address */
 561         u8 *evt_buf;
 562
 563         /* Base of the PPR log, if present */
 564         u8 *ppr_log;
 565
 566         /* true if interrupts for this IOMMU are already enabled */
 567         bool int_enabled;
 568
 569         /* if one, we need to send a completion wait command */
 570         bool need_sync;
 571
 572         /* default dma_ops domain for that IOMMU */
 573         struct dma_ops_domain *default_dom;
 574
 575         /*
 576          * We can't rely on the BIOS to restore all values on reinit, so we
 577          * need to stash them
 578          */
 579
 580         /* The iommu BAR */
 581         u32 stored_addr_lo;
 582         u32 stored_addr_hi;
 583
 584         /*
 585          * Each iommu has 6 l1s, each of which is documented as having 0x12
 586          * registers
 587          */
 588         u32 stored_l1[6][0x12];
 589
 590         /* The l2 indirect registers */
 591         u32 stored_l2[0x83];
 592
 593         /* The maximum PC banks and counters/bank (PCSup=1) */
 594         u8 max_banks;
 595         u8 max_counters;
 596 };
 597
 598 struct devid_map {
 599         struct list_head list;
 600         u8 id;
 601         u16 devid;
 602         bool cmd_line;
 603 };
 604
 605 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
 606 extern struct list_head ioapic_map;
 607 extern struct list_head hpet_map;
 608
 609 /*
 610  * List with all IOMMUs in the system. This list is not locked because it is
 611  * only written and read at driver initialization or suspend time
 612  */
 613 extern struct list_head amd_iommu_list;
 614
 615 /*
 616  * Array with pointers to each IOMMU struct
 617  * The indices are referenced in the protection domains
 618  */
 619 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
 620
 621 /* Number of IOMMUs present in the system */
 622 extern int amd_iommus_present;
 623
 624 /*
 625  * Declarations for the global list of all protection domains
 626  */
 627 extern spinlock_t amd_iommu_pd_lock;
 628 extern struct list_head amd_iommu_pd_list;
 629
 630 /*
 631  * Structure defining one entry in the device table
 632  */
 633 struct dev_table_entry {
 634         u64 data[4];
 635 };
 636
 637 /*
 638  * One entry for unity mappings parsed out of the ACPI table.
 639  */
 640 struct unity_map_entry {
 641         struct list_head list;
 642
 643         /* starting device id this entry is used for (including) */
 644         u16 devid_start;
 645         /* end device id this entry is used for (including) */
 646         u16 devid_end;
 647
 648         /* start address to unity map (including) */
 649         u64 address_start;
 650         /* end address to unity map (including) */
 651         u64 address_end;
 652
 653         /* required protection */
 654         int prot;
 655 };
 656
 657 /*
 658  * List of all unity mappings. It is not locked because as runtime it is only
 659  * read. It is created at ACPI table parsing time.
 660  */
 661 extern struct list_head amd_iommu_unity_map;
 662
 663 /*
 664  * Data structures for device handling
 665  */
 666
 667 /*
 668  * Device table used by hardware. Read and write accesses by software are
 669  * locked with the amd_iommu_pd_table lock.
 670  */
 671 extern struct dev_table_entry *amd_iommu_dev_table;
 672
 673 /*
 674  * Alias table to find requestor ids to device ids. Not locked because only
 675  * read on runtime.
 676  */
 677 extern u16 *amd_iommu_alias_table;
 678
 679 /*
 680  * Reverse lookup table to find the IOMMU which translates a specific device.
 681  */
 682 extern struct amd_iommu **amd_iommu_rlookup_table;
 683
 684 /* size of the dma_ops aperture as power of 2 */
 685 extern unsigned amd_iommu_aperture_order;
 686
 687 /* largest PCI device id we expect translation requests for */
 688 extern u16 amd_iommu_last_bdf;
 689
 690 /* allocation bitmap for domain ids */
 691 extern unsigned long *amd_iommu_pd_alloc_bitmap;
 692
 693 /*
 694  * If true, the addresses will be flushed on unmap time, not when
 695  * they are reused
 696  */
 697 extern u32 amd_iommu_unmap_flush;
 698
 699 /* Smallest number of PASIDs supported by any IOMMU in the system */
 700 extern u32 amd_iommu_max_pasids;
 701
 702 extern bool amd_iommu_v2_present;
 703
 704 extern bool amd_iommu_force_isolation;
 705
 706 /* Max levels of glxval supported */
 707 extern int amd_iommu_max_glx_val;
 708
 709 /*
 710  * This function flushes all internal caches of
 711  * the IOMMU used by this driver.
 712  */
 713 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
 714
 715 static inline int get_ioapic_devid(int id)
 716 {
 717         struct devid_map *entry;
 718
 719         list_for_each_entry(entry, &ioapic_map, list) {
 720                 if (entry->id == id)
 721                         return entry->devid;
 722         }
 723
 724         return -EINVAL;
 725 }
 726
 727 static inline int get_hpet_devid(int id)
 728 {
 729         struct devid_map *entry;
 730
 731         list_for_each_entry(entry, &hpet_map, list) {
 732                 if (entry->id == id)
 733                         return entry->devid;
 734         }
 735
 736         return -EINVAL;
 737 }
 738
 739 #ifdef CONFIG_AMD_IOMMU_STATS
 740
 741 struct __iommu_counter {
 742         char *name;
 743         struct dentry *dent;
 744         u64 value;
 745 };
 746
 747 #define DECLARE_STATS_COUNTER(nm) \
 748         static struct __iommu_counter nm = {    \
 749                 .name = #nm,                    \
 750         }
 751
 752 #define INC_STATS_COUNTER(name)         name.value += 1
 753 #define ADD_STATS_COUNTER(name, x)      name.value += (x)
 754 #define SUB_STATS_COUNTER(name, x)      name.value -= (x)
 755
 756 #else /* CONFIG_AMD_IOMMU_STATS */
 757
 758 #define DECLARE_STATS_COUNTER(name)
 759 #define INC_STATS_COUNTER(name)
 760 #define ADD_STATS_COUNTER(name, x)
 761 #define SUB_STATS_COUNTER(name, x)
 762
 763 #endif /* CONFIG_AMD_IOMMU_STATS */
 764
 765 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */