drivers/iommu/amd_iommu_v2.c

   1 /*
   2  * Copyright (C) 2010-2012 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <joerg.roedel@amd.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  17  */
  18
  19 #include <linux/mmu_notifier.h>
  20 #include <linux/amd-iommu.h>
  21 #include <linux/mm_types.h>
  22 #include <linux/profile.h>
  23 #include <linux/module.h>
  24 #include <linux/sched.h>
  25 #include <linux/iommu.h>
  26 #include <linux/wait.h>
  27 #include <linux/pci.h>
  28 #include <linux/gfp.h>
  29
  30 #include "amd_iommu_types.h"
  31 #include "amd_iommu_proto.h"
  32
  33 MODULE_LICENSE("GPL v2");
  34 MODULE_AUTHOR("Joerg Roedel <joerg.roedel@amd.com>");
  35
  36 #define MAX_DEVICES             0x10000
  37 #define PRI_QUEUE_SIZE          512
  38
  39 struct pri_queue {
  40         atomic_t inflight;
  41         bool finish;
  42         int status;
  43 };
  44
  45 struct pasid_state {
  46         struct list_head list;                  /* For global state-list */
  47         atomic_t count;                         /* Reference count */
  48         atomic_t mmu_notifier_count;            /* Counting nested mmu_notifier
  49                                                    calls */
  50         struct task_struct *task;               /* Task bound to this PASID */
  51         struct mm_struct *mm;                   /* mm_struct for the faults */
  52         struct mmu_notifier mn;                 /* mmu_otifier handle */
  53         struct pri_queue pri[PRI_QUEUE_SIZE];   /* PRI tag states */
  54         struct device_state *device_state;      /* Link to our device_state */
  55         int pasid;                              /* PASID index */
  56         spinlock_t lock;                        /* Protect pri_queues */
  57         wait_queue_head_t wq;                   /* To wait for count == 0 */
  58 };
  59
  60 struct device_state {
  61         struct list_head list;
  62         u16 devid;
  63         atomic_t count;
  64         struct pci_dev *pdev;
  65         struct pasid_state **states;
  66         struct iommu_domain *domain;
  67         int pasid_levels;
  68         int max_pasids;
  69         amd_iommu_invalid_ppr_cb inv_ppr_cb;
  70         amd_iommu_invalidate_ctx inv_ctx_cb;
  71         spinlock_t lock;
  72         wait_queue_head_t wq;
  73 };
  74
  75 struct fault {
  76         struct work_struct work;
  77         struct device_state *dev_state;
  78         struct pasid_state *state;
  79         struct mm_struct *mm;
  80         u64 address;
  81         u16 devid;
  82         u16 pasid;
  83         u16 tag;
  84         u16 finish;
  85         u16 flags;
  86 };
  87
  88 static LIST_HEAD(state_list);
  89 static spinlock_t state_lock;
  90
  91 static struct workqueue_struct *iommu_wq;
  92
  93 /*
  94  * Empty page table - Used between
  95  * mmu_notifier_invalidate_range_start and
  96  * mmu_notifier_invalidate_range_end
  97  */
  98 static u64 *empty_page_table;
  99
 100 static void free_pasid_states(struct device_state *dev_state);
 101 static void unbind_pasid(struct device_state *dev_state, int pasid);
 102
 103 static u16 device_id(struct pci_dev *pdev)
 104 {
 105         u16 devid;
 106
 107         devid = pdev->bus->number;
 108         devid = (devid << 8) | pdev->devfn;
 109
 110         return devid;
 111 }
 112
 113 static struct device_state *__get_device_state(u16 devid)
 114 {
 115         struct device_state *dev_state;
 116
 117         list_for_each_entry(dev_state, &state_list, list) {
 118                 if (dev_state->devid == devid)
 119                         return dev_state;
 120         }
 121
 122         return NULL;
 123 }
 124
 125 static struct device_state *get_device_state(u16 devid)
 126 {
 127         struct device_state *dev_state;
 128         unsigned long flags;
 129
 130         spin_lock_irqsave(&state_lock, flags);
 131         dev_state = __get_device_state(devid);
 132         if (dev_state != NULL)
 133                 atomic_inc(&dev_state->count);
 134         spin_unlock_irqrestore(&state_lock, flags);
 135
 136         return dev_state;
 137 }
 138
 139 static void free_device_state(struct device_state *dev_state)
 140 {
 141         /*
 142          * First detach device from domain - No more PRI requests will arrive
 143          * from that device after it is unbound from the IOMMUv2 domain.
 144          */
 145         iommu_detach_device(dev_state->domain, &dev_state->pdev->dev);
 146
 147         /* Everything is down now, free the IOMMUv2 domain */
 148         iommu_domain_free(dev_state->domain);
 149
 150         /* Finally get rid of the device-state */
 151         kfree(dev_state);
 152 }
 153
 154 static void put_device_state(struct device_state *dev_state)
 155 {
 156         if (atomic_dec_and_test(&dev_state->count))
 157                 wake_up(&dev_state->wq);
 158 }
 159
 160 static void put_device_state_wait(struct device_state *dev_state)
 161 {
 162         DEFINE_WAIT(wait);
 163
 164         prepare_to_wait(&dev_state->wq, &wait, TASK_UNINTERRUPTIBLE);
 165         if (!atomic_dec_and_test(&dev_state->count))
 166                 schedule();
 167         finish_wait(&dev_state->wq, &wait);
 168
 169         free_device_state(dev_state);
 170 }
 171
 172 /* Must be called under dev_state->lock */
 173 static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state,
 174                                                   int pasid, bool alloc)
 175 {
 176         struct pasid_state **root, **ptr;
 177         int level, index;
 178
 179         level = dev_state->pasid_levels;
 180         root  = dev_state->states;
 181
 182         while (true) {
 183
 184                 index = (pasid >> (9 * level)) & 0x1ff;
 185                 ptr   = &root[index];
 186
 187                 if (level == 0)
 188                         break;
 189
 190                 if (*ptr == NULL) {
 191                         if (!alloc)
 192                                 return NULL;
 193
 194                         *ptr = (void *)get_zeroed_page(GFP_ATOMIC);
 195                         if (*ptr == NULL)
 196                                 return NULL;
 197                 }
 198
 199                 root   = (struct pasid_state **)*ptr;
 200                 level -= 1;
 201         }
 202
 203         return ptr;
 204 }
 205
 206 static int set_pasid_state(struct device_state *dev_state,
 207                            struct pasid_state *pasid_state,
 208                            int pasid)
 209 {
 210         struct pasid_state **ptr;
 211         unsigned long flags;
 212         int ret;
 213
 214         spin_lock_irqsave(&dev_state->lock, flags);
 215         ptr = __get_pasid_state_ptr(dev_state, pasid, true);
 216
 217         ret = -ENOMEM;
 218         if (ptr == NULL)
 219                 goto out_unlock;
 220
 221         ret = -ENOMEM;
 222         if (*ptr != NULL)
 223                 goto out_unlock;
 224
 225         *ptr = pasid_state;
 226
 227         ret = 0;
 228
 229 out_unlock:
 230         spin_unlock_irqrestore(&dev_state->lock, flags);
 231
 232         return ret;
 233 }
 234
 235 static void clear_pasid_state(struct device_state *dev_state, int pasid)
 236 {
 237         struct pasid_state **ptr;
 238         unsigned long flags;
 239
 240         spin_lock_irqsave(&dev_state->lock, flags);
 241         ptr = __get_pasid_state_ptr(dev_state, pasid, true);
 242
 243         if (ptr == NULL)
 244                 goto out_unlock;
 245
 246         *ptr = NULL;
 247
 248 out_unlock:
 249         spin_unlock_irqrestore(&dev_state->lock, flags);
 250 }
 251
 252 static struct pasid_state *get_pasid_state(struct device_state *dev_state,
 253                                            int pasid)
 254 {
 255         struct pasid_state **ptr, *ret = NULL;
 256         unsigned long flags;
 257
 258         spin_lock_irqsave(&dev_state->lock, flags);
 259         ptr = __get_pasid_state_ptr(dev_state, pasid, false);
 260
 261         if (ptr == NULL)
 262                 goto out_unlock;
 263
 264         ret = *ptr;
 265         if (ret)
 266                 atomic_inc(&ret->count);
 267
 268 out_unlock:
 269         spin_unlock_irqrestore(&dev_state->lock, flags);
 270
 271         return ret;
 272 }
 273
 274 static void free_pasid_state(struct pasid_state *pasid_state)
 275 {
 276         kfree(pasid_state);
 277 }
 278
 279 static void put_pasid_state(struct pasid_state *pasid_state)
 280 {
 281         if (atomic_dec_and_test(&pasid_state->count)) {
 282                 put_device_state(pasid_state->device_state);
 283                 wake_up(&pasid_state->wq);
 284         }
 285 }
 286
 287 static void put_pasid_state_wait(struct pasid_state *pasid_state)
 288 {
 289         DEFINE_WAIT(wait);
 290
 291         prepare_to_wait(&pasid_state->wq, &wait, TASK_UNINTERRUPTIBLE);
 292
 293         if (atomic_dec_and_test(&pasid_state->count))
 294                 put_device_state(pasid_state->device_state);
 295         else
 296                 schedule();
 297
 298         finish_wait(&pasid_state->wq, &wait);
 299         mmput(pasid_state->mm);
 300         free_pasid_state(pasid_state);
 301 }
 302
 303 static void __unbind_pasid(struct pasid_state *pasid_state)
 304 {
 305         struct iommu_domain *domain;
 306
 307         domain = pasid_state->device_state->domain;
 308
 309         amd_iommu_domain_clear_gcr3(domain, pasid_state->pasid);
 310         clear_pasid_state(pasid_state->device_state, pasid_state->pasid);
 311
 312         /* Make sure no more pending faults are in the queue */
 313         flush_workqueue(iommu_wq);
 314
 315         mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
 316
 317         put_pasid_state(pasid_state); /* Reference taken in bind() function */
 318 }
 319
 320 static void unbind_pasid(struct device_state *dev_state, int pasid)
 321 {
 322         struct pasid_state *pasid_state;
 323
 324         pasid_state = get_pasid_state(dev_state, pasid);
 325         if (pasid_state == NULL)
 326                 return;
 327
 328         __unbind_pasid(pasid_state);
 329         put_pasid_state_wait(pasid_state); /* Reference taken in this function */
 330 }
 331
 332 static void free_pasid_states_level1(struct pasid_state **tbl)
 333 {
 334         int i;
 335
 336         for (i = 0; i < 512; ++i) {
 337                 if (tbl[i] == NULL)
 338                         continue;
 339
 340                 free_page((unsigned long)tbl[i]);
 341         }
 342 }
 343
 344 static void free_pasid_states_level2(struct pasid_state **tbl)
 345 {
 346         struct pasid_state **ptr;
 347         int i;
 348
 349         for (i = 0; i < 512; ++i) {
 350                 if (tbl[i] == NULL)
 351                         continue;
 352
 353                 ptr = (struct pasid_state **)tbl[i];
 354                 free_pasid_states_level1(ptr);
 355         }
 356 }
 357
 358 static void free_pasid_states(struct device_state *dev_state)
 359 {
 360         struct pasid_state *pasid_state;
 361         int i;
 362
 363         for (i = 0; i < dev_state->max_pasids; ++i) {
 364                 pasid_state = get_pasid_state(dev_state, i);
 365                 if (pasid_state == NULL)
 366                         continue;
 367
 368                 put_pasid_state(pasid_state);
 369
 370                 /*
 371                  * This will call the mn_release function and
 372                  * unbind the PASID
 373                  */
 374                 mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
 375         }
 376
 377         if (dev_state->pasid_levels == 2)
 378                 free_pasid_states_level2(dev_state->states);
 379         else if (dev_state->pasid_levels == 1)
 380                 free_pasid_states_level1(dev_state->states);
 381         else if (dev_state->pasid_levels != 0)
 382                 BUG();
 383
 384         free_page((unsigned long)dev_state->states);
 385 }
 386
 387 static struct pasid_state *mn_to_state(struct mmu_notifier *mn)
 388 {
 389         return container_of(mn, struct pasid_state, mn);
 390 }
 391
 392 static void __mn_flush_page(struct mmu_notifier *mn,
 393                             unsigned long address)
 394 {
 395         struct pasid_state *pasid_state;
 396         struct device_state *dev_state;
 397
 398         pasid_state = mn_to_state(mn);
 399         dev_state   = pasid_state->device_state;
 400
 401         amd_iommu_flush_page(dev_state->domain, pasid_state->pasid, address);
 402 }
 403
 404 static int mn_clear_flush_young(struct mmu_notifier *mn,
 405                                 struct mm_struct *mm,
 406                                 unsigned long address)
 407 {
 408         __mn_flush_page(mn, address);
 409
 410         return 0;
 411 }
 412
 413 static void mn_change_pte(struct mmu_notifier *mn,
 414                           struct mm_struct *mm,
 415                           unsigned long address,
 416                           pte_t pte)
 417 {
 418         __mn_flush_page(mn, address);
 419 }
 420
 421 static void mn_invalidate_page(struct mmu_notifier *mn,
 422                                struct mm_struct *mm,
 423                                unsigned long address)
 424 {
 425         __mn_flush_page(mn, address);
 426 }
 427
 428 static void mn_invalidate_range_start(struct mmu_notifier *mn,
 429                                       struct mm_struct *mm,
 430                                       unsigned long start, unsigned long end)
 431 {
 432         struct pasid_state *pasid_state;
 433         struct device_state *dev_state;
 434
 435         pasid_state = mn_to_state(mn);
 436         dev_state   = pasid_state->device_state;
 437
 438         if (atomic_add_return(1, &pasid_state->mmu_notifier_count) == 1) {
 439                 amd_iommu_domain_set_gcr3(dev_state->domain,
 440                                           pasid_state->pasid,
 441                                           __pa(empty_page_table));
 442         }
 443 }
 444
 445 static void mn_invalidate_range_end(struct mmu_notifier *mn,
 446                                     struct mm_struct *mm,
 447                                     unsigned long start, unsigned long end)
 448 {
 449         struct pasid_state *pasid_state;
 450         struct device_state *dev_state;
 451
 452         pasid_state = mn_to_state(mn);
 453         dev_state   = pasid_state->device_state;
 454
 455         if (atomic_dec_and_test(&pasid_state->mmu_notifier_count)) {
 456                 amd_iommu_domain_set_gcr3(dev_state->domain,
 457                                           pasid_state->pasid,
 458                                           __pa(pasid_state->mm->pgd));
 459         }
 460 }
 461
 462 static void mn_release(struct mmu_notifier *mn, struct mm_struct *mm)
 463 {
 464         struct pasid_state *pasid_state;
 465         struct device_state *dev_state;
 466
 467         might_sleep();
 468
 469         pasid_state = mn_to_state(mn);
 470         dev_state   = pasid_state->device_state;
 471
 472         if (pasid_state->device_state->inv_ctx_cb)
 473                 dev_state->inv_ctx_cb(dev_state->pdev, pasid_state->pasid);
 474
 475         unbind_pasid(dev_state, pasid_state->pasid);
 476 }
 477
 478 static struct mmu_notifier_ops iommu_mn = {
 479         .release                = mn_release,
 480         .clear_flush_young      = mn_clear_flush_young,
 481         .change_pte             = mn_change_pte,
 482         .invalidate_page        = mn_invalidate_page,
 483         .invalidate_range_start = mn_invalidate_range_start,
 484         .invalidate_range_end   = mn_invalidate_range_end,
 485 };
 486
 487 static void set_pri_tag_status(struct pasid_state *pasid_state,
 488                                u16 tag, int status)
 489 {
 490         unsigned long flags;
 491
 492         spin_lock_irqsave(&pasid_state->lock, flags);
 493         pasid_state->pri[tag].status = status;
 494         spin_unlock_irqrestore(&pasid_state->lock, flags);
 495 }
 496
 497 static void finish_pri_tag(struct device_state *dev_state,
 498                            struct pasid_state *pasid_state,
 499                            u16 tag)
 500 {
 501         unsigned long flags;
 502
 503         spin_lock_irqsave(&pasid_state->lock, flags);
 504         if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) &&
 505             pasid_state->pri[tag].finish) {
 506                 amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid,
 507                                        pasid_state->pri[tag].status, tag);
 508                 pasid_state->pri[tag].finish = false;
 509                 pasid_state->pri[tag].status = PPR_SUCCESS;
 510         }
 511         spin_unlock_irqrestore(&pasid_state->lock, flags);
 512 }
 513
 514 static void do_fault(struct work_struct *work)
 515 {
 516         struct fault *fault = container_of(work, struct fault, work);
 517         int npages, write;
 518         struct page *page;
 519
 520         write = !!(fault->flags & PPR_FAULT_WRITE);
 521
 522         down_read(&fault->state->mm->mmap_sem);
 523         npages = get_user_pages(fault->state->task, fault->state->mm,
 524                                 fault->address, 1, write, 0, &page, NULL);
 525         up_read(&fault->state->mm->mmap_sem);
 526
 527         if (npages == 1) {
 528                 put_page(page);
 529         } else if (fault->dev_state->inv_ppr_cb) {
 530                 int status;
 531
 532                 status = fault->dev_state->inv_ppr_cb(fault->dev_state->pdev,
 533                                                       fault->pasid,
 534                                                       fault->address,
 535                                                       fault->flags);
 536                 switch (status) {
 537                 case AMD_IOMMU_INV_PRI_RSP_SUCCESS:
 538                         set_pri_tag_status(fault->state, fault->tag, PPR_SUCCESS);
 539                         break;
 540                 case AMD_IOMMU_INV_PRI_RSP_INVALID:
 541                         set_pri_tag_status(fault->state, fault->tag, PPR_INVALID);
 542                         break;
 543                 case AMD_IOMMU_INV_PRI_RSP_FAIL:
 544                         set_pri_tag_status(fault->state, fault->tag, PPR_FAILURE);
 545                         break;
 546                 default:
 547                         BUG();
 548                 }
 549         } else {
 550                 set_pri_tag_status(fault->state, fault->tag, PPR_INVALID);
 551         }
 552
 553         finish_pri_tag(fault->dev_state, fault->state, fault->tag);
 554
 555         put_pasid_state(fault->state);
 556
 557         kfree(fault);
 558 }
 559
 560 static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data)
 561 {
 562         struct amd_iommu_fault *iommu_fault;
 563         struct pasid_state *pasid_state;
 564         struct device_state *dev_state;
 565         unsigned long flags;
 566         struct fault *fault;
 567         bool finish;
 568         u16 tag;
 569         int ret;
 570
 571         iommu_fault = data;
 572         tag         = iommu_fault->tag & 0x1ff;
 573         finish      = (iommu_fault->tag >> 9) & 1;
 574
 575         ret = NOTIFY_DONE;
 576         dev_state = get_device_state(iommu_fault->device_id);
 577         if (dev_state == NULL)
 578                 goto out;
 579
 580         pasid_state = get_pasid_state(dev_state, iommu_fault->pasid);
 581         if (pasid_state == NULL) {
 582                 /* We know the device but not the PASID -> send INVALID */
 583                 amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid,
 584                                        PPR_INVALID, tag);
 585                 goto out_drop_state;
 586         }
 587
 588         spin_lock_irqsave(&pasid_state->lock, flags);
 589         atomic_inc(&pasid_state->pri[tag].inflight);
 590         if (finish)
 591                 pasid_state->pri[tag].finish = true;
 592         spin_unlock_irqrestore(&pasid_state->lock, flags);
 593
 594         fault = kzalloc(sizeof(*fault), GFP_ATOMIC);
 595         if (fault == NULL) {
 596                 /* We are OOM - send success and let the device re-fault */
 597                 finish_pri_tag(dev_state, pasid_state, tag);
 598                 goto out_drop_state;
 599         }
 600
 601         fault->dev_state = dev_state;
 602         fault->address   = iommu_fault->address;
 603         fault->state     = pasid_state;
 604         fault->tag       = tag;
 605         fault->finish    = finish;
 606         fault->flags     = iommu_fault->flags;
 607         INIT_WORK(&fault->work, do_fault);
 608
 609         queue_work(iommu_wq, &fault->work);
 610
 611         ret = NOTIFY_OK;
 612
 613 out_drop_state:
 614         put_device_state(dev_state);
 615
 616 out:
 617         return ret;
 618 }
 619
 620 static struct notifier_block ppr_nb = {
 621         .notifier_call = ppr_notifier,
 622 };
 623
 624 int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid,
 625                          struct task_struct *task)
 626 {
 627         struct pasid_state *pasid_state;
 628         struct device_state *dev_state;
 629         u16 devid;
 630         int ret;
 631
 632         might_sleep();
 633
 634         if (!amd_iommu_v2_supported())
 635                 return -ENODEV;
 636
 637         devid     = device_id(pdev);
 638         dev_state = get_device_state(devid);
 639
 640         if (dev_state == NULL)
 641                 return -EINVAL;
 642
 643         ret = -EINVAL;
 644         if (pasid < 0 || pasid >= dev_state->max_pasids)
 645                 goto out;
 646
 647         ret = -ENOMEM;
 648         pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL);
 649         if (pasid_state == NULL)
 650                 goto out;
 651
 652         atomic_set(&pasid_state->count, 1);
 653         atomic_set(&pasid_state->mmu_notifier_count, 0);
 654         init_waitqueue_head(&pasid_state->wq);
 655         spin_lock_init(&pasid_state->lock);
 656
 657         pasid_state->task         = task;
 658         pasid_state->mm           = get_task_mm(task);
 659         pasid_state->device_state = dev_state;
 660         pasid_state->pasid        = pasid;
 661         pasid_state->mn.ops       = &iommu_mn;
 662
 663         if (pasid_state->mm == NULL)
 664                 goto out_free;
 665
 666         mmu_notifier_register(&pasid_state->mn, pasid_state->mm);
 667
 668         ret = set_pasid_state(dev_state, pasid_state, pasid);
 669         if (ret)
 670                 goto out_unregister;
 671
 672         ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid,
 673                                         __pa(pasid_state->mm->pgd));
 674         if (ret)
 675                 goto out_clear_state;
 676
 677         return 0;
 678
 679 out_clear_state:
 680         clear_pasid_state(dev_state, pasid);
 681
 682 out_unregister:
 683         mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
 684
 685 out_free:
 686         free_pasid_state(pasid_state);
 687
 688 out:
 689         put_device_state(dev_state);
 690
 691         return ret;
 692 }
 693 EXPORT_SYMBOL(amd_iommu_bind_pasid);
 694
 695 void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid)
 696 {
 697         struct pasid_state *pasid_state;
 698         struct device_state *dev_state;
 699         u16 devid;
 700
 701         might_sleep();
 702
 703         if (!amd_iommu_v2_supported())
 704                 return;
 705
 706         devid = device_id(pdev);
 707         dev_state = get_device_state(devid);
 708         if (dev_state == NULL)
 709                 return;
 710
 711         if (pasid < 0 || pasid >= dev_state->max_pasids)
 712                 goto out;
 713
 714         pasid_state = get_pasid_state(dev_state, pasid);
 715         if (pasid_state == NULL)
 716                 goto out;
 717         /*
 718          * Drop reference taken here. We are safe because we still hold
 719          * the reference taken in the amd_iommu_bind_pasid function.
 720          */
 721         put_pasid_state(pasid_state);
 722
 723         /* This will call the mn_release function and unbind the PASID */
 724         mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm);
 725
 726 out:
 727         put_device_state(dev_state);
 728 }
 729 EXPORT_SYMBOL(amd_iommu_unbind_pasid);
 730
 731 int amd_iommu_init_device(struct pci_dev *pdev, int pasids)
 732 {
 733         struct device_state *dev_state;
 734         unsigned long flags;
 735         int ret, tmp;
 736         u16 devid;
 737
 738         might_sleep();
 739
 740         if (!amd_iommu_v2_supported())
 741                 return -ENODEV;
 742
 743         if (pasids <= 0 || pasids > (PASID_MASK + 1))
 744                 return -EINVAL;
 745
 746         devid = device_id(pdev);
 747
 748         dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL);
 749         if (dev_state == NULL)
 750                 return -ENOMEM;
 751
 752         spin_lock_init(&dev_state->lock);
 753         init_waitqueue_head(&dev_state->wq);
 754         dev_state->pdev  = pdev;
 755         dev_state->devid = devid;
 756
 757         tmp = pasids;
 758         for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9)
 759                 dev_state->pasid_levels += 1;
 760
 761         atomic_set(&dev_state->count, 1);
 762         dev_state->max_pasids = pasids;
 763
 764         ret = -ENOMEM;
 765         dev_state->states = (void *)get_zeroed_page(GFP_KERNEL);
 766         if (dev_state->states == NULL)
 767                 goto out_free_dev_state;
 768
 769         dev_state->domain = iommu_domain_alloc(&pci_bus_type);
 770         if (dev_state->domain == NULL)
 771                 goto out_free_states;
 772
 773         amd_iommu_domain_direct_map(dev_state->domain);
 774
 775         ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids);
 776         if (ret)
 777                 goto out_free_domain;
 778
 779         ret = iommu_attach_device(dev_state->domain, &pdev->dev);
 780         if (ret != 0)
 781                 goto out_free_domain;
 782
 783         spin_lock_irqsave(&state_lock, flags);
 784
 785         if (__get_device_state(devid) != NULL) {
 786                 spin_unlock_irqrestore(&state_lock, flags);
 787                 ret = -EBUSY;
 788                 goto out_free_domain;
 789         }
 790
 791         list_add_tail(&dev_state->list, &state_list);
 792
 793         spin_unlock_irqrestore(&state_lock, flags);
 794
 795         return 0;
 796
 797 out_free_domain:
 798         iommu_domain_free(dev_state->domain);
 799
 800 out_free_states:
 801         free_page((unsigned long)dev_state->states);
 802
 803 out_free_dev_state:
 804         kfree(dev_state);
 805
 806         return ret;
 807 }
 808 EXPORT_SYMBOL(amd_iommu_init_device);
 809
 810 void amd_iommu_free_device(struct pci_dev *pdev)
 811 {
 812         struct device_state *dev_state;
 813         unsigned long flags;
 814         u16 devid;
 815
 816         if (!amd_iommu_v2_supported())
 817                 return;
 818
 819         devid = device_id(pdev);
 820
 821         spin_lock_irqsave(&state_lock, flags);
 822
 823         dev_state = __get_device_state(devid);
 824         if (dev_state == NULL) {
 825                 spin_unlock_irqrestore(&state_lock, flags);
 826                 return;
 827         }
 828
 829         list_del(&dev_state->list);
 830
 831         spin_unlock_irqrestore(&state_lock, flags);
 832
 833         /* Get rid of any remaining pasid states */
 834         free_pasid_states(dev_state);
 835
 836         put_device_state_wait(dev_state);
 837 }
 838 EXPORT_SYMBOL(amd_iommu_free_device);
 839
 840 int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
 841                                  amd_iommu_invalid_ppr_cb cb)
 842 {
 843         struct device_state *dev_state;
 844         unsigned long flags;
 845         u16 devid;
 846         int ret;
 847
 848         if (!amd_iommu_v2_supported())
 849                 return -ENODEV;
 850
 851         devid = device_id(pdev);
 852
 853         spin_lock_irqsave(&state_lock, flags);
 854
 855         ret = -EINVAL;
 856         dev_state = __get_device_state(devid);
 857         if (dev_state == NULL)
 858                 goto out_unlock;
 859
 860         dev_state->inv_ppr_cb = cb;
 861
 862         ret = 0;
 863
 864 out_unlock:
 865         spin_unlock_irqrestore(&state_lock, flags);
 866
 867         return ret;
 868 }
 869 EXPORT_SYMBOL(amd_iommu_set_invalid_ppr_cb);
 870
 871 int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
 872                                     amd_iommu_invalidate_ctx cb)
 873 {
 874         struct device_state *dev_state;
 875         unsigned long flags;
 876         u16 devid;
 877         int ret;
 878
 879         if (!amd_iommu_v2_supported())
 880                 return -ENODEV;
 881
 882         devid = device_id(pdev);
 883
 884         spin_lock_irqsave(&state_lock, flags);
 885
 886         ret = -EINVAL;
 887         dev_state = __get_device_state(devid);
 888         if (dev_state == NULL)
 889                 goto out_unlock;
 890
 891         dev_state->inv_ctx_cb = cb;
 892
 893         ret = 0;
 894
 895 out_unlock:
 896         spin_unlock_irqrestore(&state_lock, flags);
 897
 898         return ret;
 899 }
 900 EXPORT_SYMBOL(amd_iommu_set_invalidate_ctx_cb);
 901
 902 static int __init amd_iommu_v2_init(void)
 903 {
 904         int ret;
 905
 906         pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>\n");
 907
 908         if (!amd_iommu_v2_supported()) {
 909                 pr_info("AMD IOMMUv2 functionality not available on this system\n");
 910                 /*
 911                  * Load anyway to provide the symbols to other modules
 912                  * which may use AMD IOMMUv2 optionally.
 913                  */
 914                 return 0;
 915         }
 916
 917         spin_lock_init(&state_lock);
 918
 919         ret = -ENOMEM;
 920         iommu_wq = create_workqueue("amd_iommu_v2");
 921         if (iommu_wq == NULL)
 922                 goto out;
 923
 924         ret = -ENOMEM;
 925         empty_page_table = (u64 *)get_zeroed_page(GFP_KERNEL);
 926         if (empty_page_table == NULL)
 927                 goto out_destroy_wq;
 928
 929         amd_iommu_register_ppr_notifier(&ppr_nb);
 930
 931         return 0;
 932
 933 out_destroy_wq:
 934         destroy_workqueue(iommu_wq);
 935
 936 out:
 937         return ret;
 938 }
 939
 940 static void __exit amd_iommu_v2_exit(void)
 941 {
 942         struct device_state *dev_state;
 943         int i;
 944
 945         if (!amd_iommu_v2_supported())
 946                 return;
 947
 948         amd_iommu_unregister_ppr_notifier(&ppr_nb);
 949
 950         flush_workqueue(iommu_wq);
 951
 952         /*
 953          * The loop below might call flush_workqueue(), so call
 954          * destroy_workqueue() after it
 955          */
 956         for (i = 0; i < MAX_DEVICES; ++i) {
 957                 dev_state = get_device_state(i);
 958
 959                 if (dev_state == NULL)
 960                         continue;
 961
 962                 WARN_ON_ONCE(1);
 963
 964                 put_device_state(dev_state);
 965                 amd_iommu_free_device(dev_state->pdev);
 966         }
 967
 968         destroy_workqueue(iommu_wq);
 969
 970         free_page((unsigned long)empty_page_table);
 971 }
 972
 973 module_init(amd_iommu_v2_init);
 974 module_exit(amd_iommu_v2_exit);