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Merge tag 'v4.1-rockchip-socfixes2' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / iommu / arm-smmu.c
1 /*
2 * IOMMU API for ARM architected SMMU implementations.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 *
17 * Copyright (C) 2013 ARM Limited
18 *
19 * Author: Will Deacon <will.deacon@arm.com>
20 *
21 * This driver currently supports:
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
26 * - Context fault reporting
27 */
28
29 #define pr_fmt(fmt) "arm-smmu: " fmt
30
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/interrupt.h>
35 #include <linux/io.h>
36 #include <linux/iommu.h>
37 #include <linux/iopoll.h>
38 #include <linux/module.h>
39 #include <linux/of.h>
40 #include <linux/pci.h>
41 #include <linux/platform_device.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
44
45 #include <linux/amba/bus.h>
46
47 #include "io-pgtable.h"
48
49 /* Maximum number of stream IDs assigned to a single device */
50 #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
51
52 /* Maximum number of context banks per SMMU */
53 #define ARM_SMMU_MAX_CBS 128
54
55 /* Maximum number of mapping groups per SMMU */
56 #define ARM_SMMU_MAX_SMRS 128
57
58 /* SMMU global address space */
59 #define ARM_SMMU_GR0(smmu) ((smmu)->base)
60 #define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift))
61
62 /*
63 * SMMU global address space with conditional offset to access secure
64 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
65 * nsGFSYNR0: 0x450)
66 */
67 #define ARM_SMMU_GR0_NS(smmu) \
68 ((smmu)->base + \
69 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
70 ? 0x400 : 0))
71
72 /* Configuration registers */
73 #define ARM_SMMU_GR0_sCR0 0x0
74 #define sCR0_CLIENTPD (1 << 0)
75 #define sCR0_GFRE (1 << 1)
76 #define sCR0_GFIE (1 << 2)
77 #define sCR0_GCFGFRE (1 << 4)
78 #define sCR0_GCFGFIE (1 << 5)
79 #define sCR0_USFCFG (1 << 10)
80 #define sCR0_VMIDPNE (1 << 11)
81 #define sCR0_PTM (1 << 12)
82 #define sCR0_FB (1 << 13)
83 #define sCR0_BSU_SHIFT 14
84 #define sCR0_BSU_MASK 0x3
85
86 /* Identification registers */
87 #define ARM_SMMU_GR0_ID0 0x20
88 #define ARM_SMMU_GR0_ID1 0x24
89 #define ARM_SMMU_GR0_ID2 0x28
90 #define ARM_SMMU_GR0_ID3 0x2c
91 #define ARM_SMMU_GR0_ID4 0x30
92 #define ARM_SMMU_GR0_ID5 0x34
93 #define ARM_SMMU_GR0_ID6 0x38
94 #define ARM_SMMU_GR0_ID7 0x3c
95 #define ARM_SMMU_GR0_sGFSR 0x48
96 #define ARM_SMMU_GR0_sGFSYNR0 0x50
97 #define ARM_SMMU_GR0_sGFSYNR1 0x54
98 #define ARM_SMMU_GR0_sGFSYNR2 0x58
99
100 #define ID0_S1TS (1 << 30)
101 #define ID0_S2TS (1 << 29)
102 #define ID0_NTS (1 << 28)
103 #define ID0_SMS (1 << 27)
104 #define ID0_ATOSNS (1 << 26)
105 #define ID0_CTTW (1 << 14)
106 #define ID0_NUMIRPT_SHIFT 16
107 #define ID0_NUMIRPT_MASK 0xff
108 #define ID0_NUMSIDB_SHIFT 9
109 #define ID0_NUMSIDB_MASK 0xf
110 #define ID0_NUMSMRG_SHIFT 0
111 #define ID0_NUMSMRG_MASK 0xff
112
113 #define ID1_PAGESIZE (1 << 31)
114 #define ID1_NUMPAGENDXB_SHIFT 28
115 #define ID1_NUMPAGENDXB_MASK 7
116 #define ID1_NUMS2CB_SHIFT 16
117 #define ID1_NUMS2CB_MASK 0xff
118 #define ID1_NUMCB_SHIFT 0
119 #define ID1_NUMCB_MASK 0xff
120
121 #define ID2_OAS_SHIFT 4
122 #define ID2_OAS_MASK 0xf
123 #define ID2_IAS_SHIFT 0
124 #define ID2_IAS_MASK 0xf
125 #define ID2_UBS_SHIFT 8
126 #define ID2_UBS_MASK 0xf
127 #define ID2_PTFS_4K (1 << 12)
128 #define ID2_PTFS_16K (1 << 13)
129 #define ID2_PTFS_64K (1 << 14)
130
131 /* Global TLB invalidation */
132 #define ARM_SMMU_GR0_TLBIVMID 0x64
133 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
134 #define ARM_SMMU_GR0_TLBIALLH 0x6c
135 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
136 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
137 #define sTLBGSTATUS_GSACTIVE (1 << 0)
138 #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
139
140 /* Stream mapping registers */
141 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
142 #define SMR_VALID (1 << 31)
143 #define SMR_MASK_SHIFT 16
144 #define SMR_MASK_MASK 0x7fff
145 #define SMR_ID_SHIFT 0
146 #define SMR_ID_MASK 0x7fff
147
148 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
149 #define S2CR_CBNDX_SHIFT 0
150 #define S2CR_CBNDX_MASK 0xff
151 #define S2CR_TYPE_SHIFT 16
152 #define S2CR_TYPE_MASK 0x3
153 #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
154 #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
155 #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
156
157 /* Context bank attribute registers */
158 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
159 #define CBAR_VMID_SHIFT 0
160 #define CBAR_VMID_MASK 0xff
161 #define CBAR_S1_BPSHCFG_SHIFT 8
162 #define CBAR_S1_BPSHCFG_MASK 3
163 #define CBAR_S1_BPSHCFG_NSH 3
164 #define CBAR_S1_MEMATTR_SHIFT 12
165 #define CBAR_S1_MEMATTR_MASK 0xf
166 #define CBAR_S1_MEMATTR_WB 0xf
167 #define CBAR_TYPE_SHIFT 16
168 #define CBAR_TYPE_MASK 0x3
169 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
170 #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
171 #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
172 #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
173 #define CBAR_IRPTNDX_SHIFT 24
174 #define CBAR_IRPTNDX_MASK 0xff
175
176 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
177 #define CBA2R_RW64_32BIT (0 << 0)
178 #define CBA2R_RW64_64BIT (1 << 0)
179
180 /* Translation context bank */
181 #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
182 #define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift))
183
184 #define ARM_SMMU_CB_SCTLR 0x0
185 #define ARM_SMMU_CB_RESUME 0x8
186 #define ARM_SMMU_CB_TTBCR2 0x10
187 #define ARM_SMMU_CB_TTBR0_LO 0x20
188 #define ARM_SMMU_CB_TTBR0_HI 0x24
189 #define ARM_SMMU_CB_TTBR1_LO 0x28
190 #define ARM_SMMU_CB_TTBR1_HI 0x2c
191 #define ARM_SMMU_CB_TTBCR 0x30
192 #define ARM_SMMU_CB_S1_MAIR0 0x38
193 #define ARM_SMMU_CB_S1_MAIR1 0x3c
194 #define ARM_SMMU_CB_PAR_LO 0x50
195 #define ARM_SMMU_CB_PAR_HI 0x54
196 #define ARM_SMMU_CB_FSR 0x58
197 #define ARM_SMMU_CB_FAR_LO 0x60
198 #define ARM_SMMU_CB_FAR_HI 0x64
199 #define ARM_SMMU_CB_FSYNR0 0x68
200 #define ARM_SMMU_CB_S1_TLBIVA 0x600
201 #define ARM_SMMU_CB_S1_TLBIASID 0x610
202 #define ARM_SMMU_CB_S1_TLBIVAL 0x620
203 #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
204 #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
205 #define ARM_SMMU_CB_ATS1PR_LO 0x800
206 #define ARM_SMMU_CB_ATS1PR_HI 0x804
207 #define ARM_SMMU_CB_ATSR 0x8f0
208
209 #define SCTLR_S1_ASIDPNE (1 << 12)
210 #define SCTLR_CFCFG (1 << 7)
211 #define SCTLR_CFIE (1 << 6)
212 #define SCTLR_CFRE (1 << 5)
213 #define SCTLR_E (1 << 4)
214 #define SCTLR_AFE (1 << 2)
215 #define SCTLR_TRE (1 << 1)
216 #define SCTLR_M (1 << 0)
217 #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
218
219 #define CB_PAR_F (1 << 0)
220
221 #define ATSR_ACTIVE (1 << 0)
222
223 #define RESUME_RETRY (0 << 0)
224 #define RESUME_TERMINATE (1 << 0)
225
226 #define TTBCR2_SEP_SHIFT 15
227 #define TTBCR2_SEP_MASK 0x7
228
229 #define TTBCR2_ADDR_32 0
230 #define TTBCR2_ADDR_36 1
231 #define TTBCR2_ADDR_40 2
232 #define TTBCR2_ADDR_42 3
233 #define TTBCR2_ADDR_44 4
234 #define TTBCR2_ADDR_48 5
235
236 #define TTBRn_HI_ASID_SHIFT 16
237
238 #define FSR_MULTI (1 << 31)
239 #define FSR_SS (1 << 30)
240 #define FSR_UUT (1 << 8)
241 #define FSR_ASF (1 << 7)
242 #define FSR_TLBLKF (1 << 6)
243 #define FSR_TLBMCF (1 << 5)
244 #define FSR_EF (1 << 4)
245 #define FSR_PF (1 << 3)
246 #define FSR_AFF (1 << 2)
247 #define FSR_TF (1 << 1)
248
249 #define FSR_IGN (FSR_AFF | FSR_ASF | \
250 FSR_TLBMCF | FSR_TLBLKF)
251 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
252 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
253
254 #define FSYNR0_WNR (1 << 4)
255
256 static int force_stage;
257 module_param_named(force_stage, force_stage, int, S_IRUGO | S_IWUSR);
258 MODULE_PARM_DESC(force_stage,
259 "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
260
261 enum arm_smmu_arch_version {
262 ARM_SMMU_V1 = 1,
263 ARM_SMMU_V2,
264 };
265
266 struct arm_smmu_smr {
267 u8 idx;
268 u16 mask;
269 u16 id;
270 };
271
272 struct arm_smmu_master_cfg {
273 int num_streamids;
274 u16 streamids[MAX_MASTER_STREAMIDS];
275 struct arm_smmu_smr *smrs;
276 };
277
278 struct arm_smmu_master {
279 struct device_node *of_node;
280 struct rb_node node;
281 struct arm_smmu_master_cfg cfg;
282 };
283
284 struct arm_smmu_device {
285 struct device *dev;
286
287 void __iomem *base;
288 unsigned long size;
289 unsigned long pgshift;
290
291 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
292 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
293 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
294 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
295 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
296 #define ARM_SMMU_FEAT_TRANS_OPS (1 << 5)
297 u32 features;
298
299 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
300 u32 options;
301 enum arm_smmu_arch_version version;
302
303 u32 num_context_banks;
304 u32 num_s2_context_banks;
305 DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
306 atomic_t irptndx;
307
308 u32 num_mapping_groups;
309 DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
310
311 unsigned long va_size;
312 unsigned long ipa_size;
313 unsigned long pa_size;
314
315 u32 num_global_irqs;
316 u32 num_context_irqs;
317 unsigned int *irqs;
318
319 struct list_head list;
320 struct rb_root masters;
321 };
322
323 struct arm_smmu_cfg {
324 u8 cbndx;
325 u8 irptndx;
326 u32 cbar;
327 };
328 #define INVALID_IRPTNDX 0xff
329
330 #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)
331 #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)
332
333 enum arm_smmu_domain_stage {
334 ARM_SMMU_DOMAIN_S1 = 0,
335 ARM_SMMU_DOMAIN_S2,
336 ARM_SMMU_DOMAIN_NESTED,
337 };
338
339 struct arm_smmu_domain {
340 struct arm_smmu_device *smmu;
341 struct io_pgtable_ops *pgtbl_ops;
342 spinlock_t pgtbl_lock;
343 struct arm_smmu_cfg cfg;
344 enum arm_smmu_domain_stage stage;
345 struct mutex init_mutex; /* Protects smmu pointer */
346 struct iommu_domain domain;
347 };
348
349 static struct iommu_ops arm_smmu_ops;
350
351 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
352 static LIST_HEAD(arm_smmu_devices);
353
354 struct arm_smmu_option_prop {
355 u32 opt;
356 const char *prop;
357 };
358
359 static struct arm_smmu_option_prop arm_smmu_options[] = {
360 { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
361 { 0, NULL},
362 };
363
364 static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
365 {
366 return container_of(dom, struct arm_smmu_domain, domain);
367 }
368
369 static void parse_driver_options(struct arm_smmu_device *smmu)
370 {
371 int i = 0;
372
373 do {
374 if (of_property_read_bool(smmu->dev->of_node,
375 arm_smmu_options[i].prop)) {
376 smmu->options |= arm_smmu_options[i].opt;
377 dev_notice(smmu->dev, "option %s\n",
378 arm_smmu_options[i].prop);
379 }
380 } while (arm_smmu_options[++i].opt);
381 }
382
383 static struct device_node *dev_get_dev_node(struct device *dev)
384 {
385 if (dev_is_pci(dev)) {
386 struct pci_bus *bus = to_pci_dev(dev)->bus;
387
388 while (!pci_is_root_bus(bus))
389 bus = bus->parent;
390 return bus->bridge->parent->of_node;
391 }
392
393 return dev->of_node;
394 }
395
396 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
397 struct device_node *dev_node)
398 {
399 struct rb_node *node = smmu->masters.rb_node;
400
401 while (node) {
402 struct arm_smmu_master *master;
403
404 master = container_of(node, struct arm_smmu_master, node);
405
406 if (dev_node < master->of_node)
407 node = node->rb_left;
408 else if (dev_node > master->of_node)
409 node = node->rb_right;
410 else
411 return master;
412 }
413
414 return NULL;
415 }
416
417 static struct arm_smmu_master_cfg *
418 find_smmu_master_cfg(struct device *dev)
419 {
420 struct arm_smmu_master_cfg *cfg = NULL;
421 struct iommu_group *group = iommu_group_get(dev);
422
423 if (group) {
424 cfg = iommu_group_get_iommudata(group);
425 iommu_group_put(group);
426 }
427
428 return cfg;
429 }
430
431 static int insert_smmu_master(struct arm_smmu_device *smmu,
432 struct arm_smmu_master *master)
433 {
434 struct rb_node **new, *parent;
435
436 new = &smmu->masters.rb_node;
437 parent = NULL;
438 while (*new) {
439 struct arm_smmu_master *this
440 = container_of(*new, struct arm_smmu_master, node);
441
442 parent = *new;
443 if (master->of_node < this->of_node)
444 new = &((*new)->rb_left);
445 else if (master->of_node > this->of_node)
446 new = &((*new)->rb_right);
447 else
448 return -EEXIST;
449 }
450
451 rb_link_node(&master->node, parent, new);
452 rb_insert_color(&master->node, &smmu->masters);
453 return 0;
454 }
455
456 static int register_smmu_master(struct arm_smmu_device *smmu,
457 struct device *dev,
458 struct of_phandle_args *masterspec)
459 {
460 int i;
461 struct arm_smmu_master *master;
462
463 master = find_smmu_master(smmu, masterspec->np);
464 if (master) {
465 dev_err(dev,
466 "rejecting multiple registrations for master device %s\n",
467 masterspec->np->name);
468 return -EBUSY;
469 }
470
471 if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
472 dev_err(dev,
473 "reached maximum number (%d) of stream IDs for master device %s\n",
474 MAX_MASTER_STREAMIDS, masterspec->np->name);
475 return -ENOSPC;
476 }
477
478 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
479 if (!master)
480 return -ENOMEM;
481
482 master->of_node = masterspec->np;
483 master->cfg.num_streamids = masterspec->args_count;
484
485 for (i = 0; i < master->cfg.num_streamids; ++i) {
486 u16 streamid = masterspec->args[i];
487
488 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) &&
489 (streamid >= smmu->num_mapping_groups)) {
490 dev_err(dev,
491 "stream ID for master device %s greater than maximum allowed (%d)\n",
492 masterspec->np->name, smmu->num_mapping_groups);
493 return -ERANGE;
494 }
495 master->cfg.streamids[i] = streamid;
496 }
497 return insert_smmu_master(smmu, master);
498 }
499
500 static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
501 {
502 struct arm_smmu_device *smmu;
503 struct arm_smmu_master *master = NULL;
504 struct device_node *dev_node = dev_get_dev_node(dev);
505
506 spin_lock(&arm_smmu_devices_lock);
507 list_for_each_entry(smmu, &arm_smmu_devices, list) {
508 master = find_smmu_master(smmu, dev_node);
509 if (master)
510 break;
511 }
512 spin_unlock(&arm_smmu_devices_lock);
513
514 return master ? smmu : NULL;
515 }
516
517 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
518 {
519 int idx;
520
521 do {
522 idx = find_next_zero_bit(map, end, start);
523 if (idx == end)
524 return -ENOSPC;
525 } while (test_and_set_bit(idx, map));
526
527 return idx;
528 }
529
530 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
531 {
532 clear_bit(idx, map);
533 }
534
535 /* Wait for any pending TLB invalidations to complete */
536 static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
537 {
538 int count = 0;
539 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
540
541 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
542 while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
543 & sTLBGSTATUS_GSACTIVE) {
544 cpu_relax();
545 if (++count == TLB_LOOP_TIMEOUT) {
546 dev_err_ratelimited(smmu->dev,
547 "TLB sync timed out -- SMMU may be deadlocked\n");
548 return;
549 }
550 udelay(1);
551 }
552 }
553
554 static void arm_smmu_tlb_sync(void *cookie)
555 {
556 struct arm_smmu_domain *smmu_domain = cookie;
557 __arm_smmu_tlb_sync(smmu_domain->smmu);
558 }
559
560 static void arm_smmu_tlb_inv_context(void *cookie)
561 {
562 struct arm_smmu_domain *smmu_domain = cookie;
563 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
564 struct arm_smmu_device *smmu = smmu_domain->smmu;
565 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
566 void __iomem *base;
567
568 if (stage1) {
569 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
570 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
571 base + ARM_SMMU_CB_S1_TLBIASID);
572 } else {
573 base = ARM_SMMU_GR0(smmu);
574 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
575 base + ARM_SMMU_GR0_TLBIVMID);
576 }
577
578 __arm_smmu_tlb_sync(smmu);
579 }
580
581 static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
582 bool leaf, void *cookie)
583 {
584 struct arm_smmu_domain *smmu_domain = cookie;
585 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
586 struct arm_smmu_device *smmu = smmu_domain->smmu;
587 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
588 void __iomem *reg;
589
590 if (stage1) {
591 reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
592 reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
593
594 if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) {
595 iova &= ~12UL;
596 iova |= ARM_SMMU_CB_ASID(cfg);
597 writel_relaxed(iova, reg);
598 #ifdef CONFIG_64BIT
599 } else {
600 iova >>= 12;
601 iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48;
602 writeq_relaxed(iova, reg);
603 #endif
604 }
605 #ifdef CONFIG_64BIT
606 } else if (smmu->version == ARM_SMMU_V2) {
607 reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
608 reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L :
609 ARM_SMMU_CB_S2_TLBIIPAS2;
610 writeq_relaxed(iova >> 12, reg);
611 #endif
612 } else {
613 reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
614 writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);
615 }
616 }
617
618 static void arm_smmu_flush_pgtable(void *addr, size_t size, void *cookie)
619 {
620 struct arm_smmu_domain *smmu_domain = cookie;
621 struct arm_smmu_device *smmu = smmu_domain->smmu;
622 unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
623
624
625 /* Ensure new page tables are visible to the hardware walker */
626 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
627 dsb(ishst);
628 } else {
629 /*
630 * If the SMMU can't walk tables in the CPU caches, treat them
631 * like non-coherent DMA since we need to flush the new entries
632 * all the way out to memory. There's no possibility of
633 * recursion here as the SMMU table walker will not be wired
634 * through another SMMU.
635 */
636 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
637 DMA_TO_DEVICE);
638 }
639 }
640
641 static struct iommu_gather_ops arm_smmu_gather_ops = {
642 .tlb_flush_all = arm_smmu_tlb_inv_context,
643 .tlb_add_flush = arm_smmu_tlb_inv_range_nosync,
644 .tlb_sync = arm_smmu_tlb_sync,
645 .flush_pgtable = arm_smmu_flush_pgtable,
646 };
647
648 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
649 {
650 int flags, ret;
651 u32 fsr, far, fsynr, resume;
652 unsigned long iova;
653 struct iommu_domain *domain = dev;
654 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
655 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
656 struct arm_smmu_device *smmu = smmu_domain->smmu;
657 void __iomem *cb_base;
658
659 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
660 fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
661
662 if (!(fsr & FSR_FAULT))
663 return IRQ_NONE;
664
665 if (fsr & FSR_IGN)
666 dev_err_ratelimited(smmu->dev,
667 "Unexpected context fault (fsr 0x%x)\n",
668 fsr);
669
670 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
671 flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
672
673 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
674 iova = far;
675 #ifdef CONFIG_64BIT
676 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
677 iova |= ((unsigned long)far << 32);
678 #endif
679
680 if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
681 ret = IRQ_HANDLED;
682 resume = RESUME_RETRY;
683 } else {
684 dev_err_ratelimited(smmu->dev,
685 "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
686 iova, fsynr, cfg->cbndx);
687 ret = IRQ_NONE;
688 resume = RESUME_TERMINATE;
689 }
690
691 /* Clear the faulting FSR */
692 writel(fsr, cb_base + ARM_SMMU_CB_FSR);
693
694 /* Retry or terminate any stalled transactions */
695 if (fsr & FSR_SS)
696 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
697
698 return ret;
699 }
700
701 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
702 {
703 u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
704 struct arm_smmu_device *smmu = dev;
705 void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
706
707 gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
708 gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
709 gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
710 gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
711
712 if (!gfsr)
713 return IRQ_NONE;
714
715 dev_err_ratelimited(smmu->dev,
716 "Unexpected global fault, this could be serious\n");
717 dev_err_ratelimited(smmu->dev,
718 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
719 gfsr, gfsynr0, gfsynr1, gfsynr2);
720
721 writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
722 return IRQ_HANDLED;
723 }
724
725 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
726 struct io_pgtable_cfg *pgtbl_cfg)
727 {
728 u32 reg;
729 bool stage1;
730 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
731 struct arm_smmu_device *smmu = smmu_domain->smmu;
732 void __iomem *cb_base, *gr0_base, *gr1_base;
733
734 gr0_base = ARM_SMMU_GR0(smmu);
735 gr1_base = ARM_SMMU_GR1(smmu);
736 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
737 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
738
739 if (smmu->version > ARM_SMMU_V1) {
740 /*
741 * CBA2R.
742 * *Must* be initialised before CBAR thanks to VMID16
743 * architectural oversight affected some implementations.
744 */
745 #ifdef CONFIG_64BIT
746 reg = CBA2R_RW64_64BIT;
747 #else
748 reg = CBA2R_RW64_32BIT;
749 #endif
750 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
751 }
752
753 /* CBAR */
754 reg = cfg->cbar;
755 if (smmu->version == ARM_SMMU_V1)
756 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
757
758 /*
759 * Use the weakest shareability/memory types, so they are
760 * overridden by the ttbcr/pte.
761 */
762 if (stage1) {
763 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
764 (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
765 } else {
766 reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
767 }
768 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
769
770 /* TTBRs */
771 if (stage1) {
772 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
773 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
774 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0] >> 32;
775 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
776 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
777
778 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
779 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_LO);
780 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1] >> 32;
781 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
782 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_HI);
783 } else {
784 reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
785 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
786 reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr >> 32;
787 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
788 }
789
790 /* TTBCR */
791 if (stage1) {
792 reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
793 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
794 if (smmu->version > ARM_SMMU_V1) {
795 reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
796 switch (smmu->va_size) {
797 case 32:
798 reg |= (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
799 break;
800 case 36:
801 reg |= (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
802 break;
803 case 40:
804 reg |= (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
805 break;
806 case 42:
807 reg |= (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
808 break;
809 case 44:
810 reg |= (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
811 break;
812 case 48:
813 reg |= (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
814 break;
815 }
816 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
817 }
818 } else {
819 reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
820 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
821 }
822
823 /* MAIRs (stage-1 only) */
824 if (stage1) {
825 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
826 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
827 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
828 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1);
829 }
830
831 /* SCTLR */
832 reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
833 if (stage1)
834 reg |= SCTLR_S1_ASIDPNE;
835 #ifdef __BIG_ENDIAN
836 reg |= SCTLR_E;
837 #endif
838 writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
839 }
840
841 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
842 struct arm_smmu_device *smmu)
843 {
844 int irq, start, ret = 0;
845 unsigned long ias, oas;
846 struct io_pgtable_ops *pgtbl_ops;
847 struct io_pgtable_cfg pgtbl_cfg;
848 enum io_pgtable_fmt fmt;
849 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
850 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
851
852 mutex_lock(&smmu_domain->init_mutex);
853 if (smmu_domain->smmu)
854 goto out_unlock;
855
856 /*
857 * Mapping the requested stage onto what we support is surprisingly
858 * complicated, mainly because the spec allows S1+S2 SMMUs without
859 * support for nested translation. That means we end up with the
860 * following table:
861 *
862 * Requested Supported Actual
863 * S1 N S1
864 * S1 S1+S2 S1
865 * S1 S2 S2
866 * S1 S1 S1
867 * N N N
868 * N S1+S2 S2
869 * N S2 S2
870 * N S1 S1
871 *
872 * Note that you can't actually request stage-2 mappings.
873 */
874 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
875 smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
876 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
877 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
878
879 switch (smmu_domain->stage) {
880 case ARM_SMMU_DOMAIN_S1:
881 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
882 start = smmu->num_s2_context_banks;
883 ias = smmu->va_size;
884 oas = smmu->ipa_size;
885 if (IS_ENABLED(CONFIG_64BIT))
886 fmt = ARM_64_LPAE_S1;
887 else
888 fmt = ARM_32_LPAE_S1;
889 break;
890 case ARM_SMMU_DOMAIN_NESTED:
891 /*
892 * We will likely want to change this if/when KVM gets
893 * involved.
894 */
895 case ARM_SMMU_DOMAIN_S2:
896 cfg->cbar = CBAR_TYPE_S2_TRANS;
897 start = 0;
898 ias = smmu->ipa_size;
899 oas = smmu->pa_size;
900 if (IS_ENABLED(CONFIG_64BIT))
901 fmt = ARM_64_LPAE_S2;
902 else
903 fmt = ARM_32_LPAE_S2;
904 break;
905 default:
906 ret = -EINVAL;
907 goto out_unlock;
908 }
909
910 ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
911 smmu->num_context_banks);
912 if (IS_ERR_VALUE(ret))
913 goto out_unlock;
914
915 cfg->cbndx = ret;
916 if (smmu->version == ARM_SMMU_V1) {
917 cfg->irptndx = atomic_inc_return(&smmu->irptndx);
918 cfg->irptndx %= smmu->num_context_irqs;
919 } else {
920 cfg->irptndx = cfg->cbndx;
921 }
922
923 pgtbl_cfg = (struct io_pgtable_cfg) {
924 .pgsize_bitmap = arm_smmu_ops.pgsize_bitmap,
925 .ias = ias,
926 .oas = oas,
927 .tlb = &arm_smmu_gather_ops,
928 };
929
930 smmu_domain->smmu = smmu;
931 pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
932 if (!pgtbl_ops) {
933 ret = -ENOMEM;
934 goto out_clear_smmu;
935 }
936
937 /* Update our support page sizes to reflect the page table format */
938 arm_smmu_ops.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
939
940 /* Initialise the context bank with our page table cfg */
941 arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg);
942
943 /*
944 * Request context fault interrupt. Do this last to avoid the
945 * handler seeing a half-initialised domain state.
946 */
947 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
948 ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
949 "arm-smmu-context-fault", domain);
950 if (IS_ERR_VALUE(ret)) {
951 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
952 cfg->irptndx, irq);
953 cfg->irptndx = INVALID_IRPTNDX;
954 }
955
956 mutex_unlock(&smmu_domain->init_mutex);
957
958 /* Publish page table ops for map/unmap */
959 smmu_domain->pgtbl_ops = pgtbl_ops;
960 return 0;
961
962 out_clear_smmu:
963 smmu_domain->smmu = NULL;
964 out_unlock:
965 mutex_unlock(&smmu_domain->init_mutex);
966 return ret;
967 }
968
969 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
970 {
971 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
972 struct arm_smmu_device *smmu = smmu_domain->smmu;
973 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
974 void __iomem *cb_base;
975 int irq;
976
977 if (!smmu)
978 return;
979
980 /*
981 * Disable the context bank and free the page tables before freeing
982 * it.
983 */
984 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
985 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
986
987 if (cfg->irptndx != INVALID_IRPTNDX) {
988 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
989 free_irq(irq, domain);
990 }
991
992 if (smmu_domain->pgtbl_ops)
993 free_io_pgtable_ops(smmu_domain->pgtbl_ops);
994
995 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
996 }
997
998 static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
999 {
1000 struct arm_smmu_domain *smmu_domain;
1001
1002 if (type != IOMMU_DOMAIN_UNMANAGED)
1003 return NULL;
1004 /*
1005 * Allocate the domain and initialise some of its data structures.
1006 * We can't really do anything meaningful until we've added a
1007 * master.
1008 */
1009 smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
1010 if (!smmu_domain)
1011 return NULL;
1012
1013 mutex_init(&smmu_domain->init_mutex);
1014 spin_lock_init(&smmu_domain->pgtbl_lock);
1015
1016 return &smmu_domain->domain;
1017 }
1018
1019 static void arm_smmu_domain_free(struct iommu_domain *domain)
1020 {
1021 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1022
1023 /*
1024 * Free the domain resources. We assume that all devices have
1025 * already been detached.
1026 */
1027 arm_smmu_destroy_domain_context(domain);
1028 kfree(smmu_domain);
1029 }
1030
1031 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1032 struct arm_smmu_master_cfg *cfg)
1033 {
1034 int i;
1035 struct arm_smmu_smr *smrs;
1036 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1037
1038 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1039 return 0;
1040
1041 if (cfg->smrs)
1042 return -EEXIST;
1043
1044 smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
1045 if (!smrs) {
1046 dev_err(smmu->dev, "failed to allocate %d SMRs\n",
1047 cfg->num_streamids);
1048 return -ENOMEM;
1049 }
1050
1051 /* Allocate the SMRs on the SMMU */
1052 for (i = 0; i < cfg->num_streamids; ++i) {
1053 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1054 smmu->num_mapping_groups);
1055 if (IS_ERR_VALUE(idx)) {
1056 dev_err(smmu->dev, "failed to allocate free SMR\n");
1057 goto err_free_smrs;
1058 }
1059
1060 smrs[i] = (struct arm_smmu_smr) {
1061 .idx = idx,
1062 .mask = 0, /* We don't currently share SMRs */
1063 .id = cfg->streamids[i],
1064 };
1065 }
1066
1067 /* It worked! Now, poke the actual hardware */
1068 for (i = 0; i < cfg->num_streamids; ++i) {
1069 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1070 smrs[i].mask << SMR_MASK_SHIFT;
1071 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1072 }
1073
1074 cfg->smrs = smrs;
1075 return 0;
1076
1077 err_free_smrs:
1078 while (--i >= 0)
1079 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1080 kfree(smrs);
1081 return -ENOSPC;
1082 }
1083
1084 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1085 struct arm_smmu_master_cfg *cfg)
1086 {
1087 int i;
1088 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1089 struct arm_smmu_smr *smrs = cfg->smrs;
1090
1091 if (!smrs)
1092 return;
1093
1094 /* Invalidate the SMRs before freeing back to the allocator */
1095 for (i = 0; i < cfg->num_streamids; ++i) {
1096 u8 idx = smrs[i].idx;
1097
1098 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1099 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1100 }
1101
1102 cfg->smrs = NULL;
1103 kfree(smrs);
1104 }
1105
1106 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1107 struct arm_smmu_master_cfg *cfg)
1108 {
1109 int i, ret;
1110 struct arm_smmu_device *smmu = smmu_domain->smmu;
1111 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1112
1113 /* Devices in an IOMMU group may already be configured */
1114 ret = arm_smmu_master_configure_smrs(smmu, cfg);
1115 if (ret)
1116 return ret == -EEXIST ? 0 : ret;
1117
1118 for (i = 0; i < cfg->num_streamids; ++i) {
1119 u32 idx, s2cr;
1120
1121 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1122 s2cr = S2CR_TYPE_TRANS |
1123 (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
1124 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1125 }
1126
1127 return 0;
1128 }
1129
1130 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1131 struct arm_smmu_master_cfg *cfg)
1132 {
1133 int i;
1134 struct arm_smmu_device *smmu = smmu_domain->smmu;
1135 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1136
1137 /* An IOMMU group is torn down by the first device to be removed */
1138 if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs)
1139 return;
1140
1141 /*
1142 * We *must* clear the S2CR first, because freeing the SMR means
1143 * that it can be re-allocated immediately.
1144 */
1145 for (i = 0; i < cfg->num_streamids; ++i) {
1146 u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1147
1148 writel_relaxed(S2CR_TYPE_BYPASS,
1149 gr0_base + ARM_SMMU_GR0_S2CR(idx));
1150 }
1151
1152 arm_smmu_master_free_smrs(smmu, cfg);
1153 }
1154
1155 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1156 {
1157 int ret;
1158 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1159 struct arm_smmu_device *smmu;
1160 struct arm_smmu_master_cfg *cfg;
1161
1162 smmu = find_smmu_for_device(dev);
1163 if (!smmu) {
1164 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1165 return -ENXIO;
1166 }
1167
1168 if (dev->archdata.iommu) {
1169 dev_err(dev, "already attached to IOMMU domain\n");
1170 return -EEXIST;
1171 }
1172
1173 /* Ensure that the domain is finalised */
1174 ret = arm_smmu_init_domain_context(domain, smmu);
1175 if (IS_ERR_VALUE(ret))
1176 return ret;
1177
1178 /*
1179 * Sanity check the domain. We don't support domains across
1180 * different SMMUs.
1181 */
1182 if (smmu_domain->smmu != smmu) {
1183 dev_err(dev,
1184 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1185 dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
1186 return -EINVAL;
1187 }
1188
1189 /* Looks ok, so add the device to the domain */
1190 cfg = find_smmu_master_cfg(dev);
1191 if (!cfg)
1192 return -ENODEV;
1193
1194 ret = arm_smmu_domain_add_master(smmu_domain, cfg);
1195 if (!ret)
1196 dev->archdata.iommu = domain;
1197 return ret;
1198 }
1199
1200 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1201 {
1202 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1203 struct arm_smmu_master_cfg *cfg;
1204
1205 cfg = find_smmu_master_cfg(dev);
1206 if (!cfg)
1207 return;
1208
1209 dev->archdata.iommu = NULL;
1210 arm_smmu_domain_remove_master(smmu_domain, cfg);
1211 }
1212
1213 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1214 phys_addr_t paddr, size_t size, int prot)
1215 {
1216 int ret;
1217 unsigned long flags;
1218 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1219 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1220
1221 if (!ops)
1222 return -ENODEV;
1223
1224 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1225 ret = ops->map(ops, iova, paddr, size, prot);
1226 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1227 return ret;
1228 }
1229
1230 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1231 size_t size)
1232 {
1233 size_t ret;
1234 unsigned long flags;
1235 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1236 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1237
1238 if (!ops)
1239 return 0;
1240
1241 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1242 ret = ops->unmap(ops, iova, size);
1243 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1244 return ret;
1245 }
1246
1247 static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
1248 dma_addr_t iova)
1249 {
1250 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1251 struct arm_smmu_device *smmu = smmu_domain->smmu;
1252 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1253 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1254 struct device *dev = smmu->dev;
1255 void __iomem *cb_base;
1256 u32 tmp;
1257 u64 phys;
1258
1259 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
1260
1261 if (smmu->version == 1) {
1262 u32 reg = iova & ~0xfff;
1263 writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);
1264 } else {
1265 u32 reg = iova & ~0xfff;
1266 writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);
1267 reg = ((u64)iova & ~0xfff) >> 32;
1268 writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_HI);
1269 }
1270
1271 if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,
1272 !(tmp & ATSR_ACTIVE), 5, 50)) {
1273 dev_err(dev,
1274 "iova to phys timed out on 0x%pad. Falling back to software table walk.\n",
1275 &iova);
1276 return ops->iova_to_phys(ops, iova);
1277 }
1278
1279 phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO);
1280 phys |= ((u64)readl_relaxed(cb_base + ARM_SMMU_CB_PAR_HI)) << 32;
1281
1282 if (phys & CB_PAR_F) {
1283 dev_err(dev, "translation fault!\n");
1284 dev_err(dev, "PAR = 0x%llx\n", phys);
1285 return 0;
1286 }
1287
1288 return (phys & GENMASK_ULL(39, 12)) | (iova & 0xfff);
1289 }
1290
1291 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1292 dma_addr_t iova)
1293 {
1294 phys_addr_t ret;
1295 unsigned long flags;
1296 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1297 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1298
1299 if (!ops)
1300 return 0;
1301
1302 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1303 if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS &&
1304 smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1305 ret = arm_smmu_iova_to_phys_hard(domain, iova);
1306 } else {
1307 ret = ops->iova_to_phys(ops, iova);
1308 }
1309
1310 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1311
1312 return ret;
1313 }
1314
1315 static bool arm_smmu_capable(enum iommu_cap cap)
1316 {
1317 switch (cap) {
1318 case IOMMU_CAP_CACHE_COHERENCY:
1319 /*
1320 * Return true here as the SMMU can always send out coherent
1321 * requests.
1322 */
1323 return true;
1324 case IOMMU_CAP_INTR_REMAP:
1325 return true; /* MSIs are just memory writes */
1326 case IOMMU_CAP_NOEXEC:
1327 return true;
1328 default:
1329 return false;
1330 }
1331 }
1332
1333 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
1334 {
1335 *((u16 *)data) = alias;
1336 return 0; /* Continue walking */
1337 }
1338
1339 static void __arm_smmu_release_pci_iommudata(void *data)
1340 {
1341 kfree(data);
1342 }
1343
1344 static int arm_smmu_add_pci_device(struct pci_dev *pdev)
1345 {
1346 int i, ret;
1347 u16 sid;
1348 struct iommu_group *group;
1349 struct arm_smmu_master_cfg *cfg;
1350
1351 group = iommu_group_get_for_dev(&pdev->dev);
1352 if (IS_ERR(group))
1353 return PTR_ERR(group);
1354
1355 cfg = iommu_group_get_iommudata(group);
1356 if (!cfg) {
1357 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1358 if (!cfg) {
1359 ret = -ENOMEM;
1360 goto out_put_group;
1361 }
1362
1363 iommu_group_set_iommudata(group, cfg,
1364 __arm_smmu_release_pci_iommudata);
1365 }
1366
1367 if (cfg->num_streamids >= MAX_MASTER_STREAMIDS) {
1368 ret = -ENOSPC;
1369 goto out_put_group;
1370 }
1371
1372 /*
1373 * Assume Stream ID == Requester ID for now.
1374 * We need a way to describe the ID mappings in FDT.
1375 */
1376 pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid);
1377 for (i = 0; i < cfg->num_streamids; ++i)
1378 if (cfg->streamids[i] == sid)
1379 break;
1380
1381 /* Avoid duplicate SIDs, as this can lead to SMR conflicts */
1382 if (i == cfg->num_streamids)
1383 cfg->streamids[cfg->num_streamids++] = sid;
1384
1385 return 0;
1386 out_put_group:
1387 iommu_group_put(group);
1388 return ret;
1389 }
1390
1391 static int arm_smmu_add_platform_device(struct device *dev)
1392 {
1393 struct iommu_group *group;
1394 struct arm_smmu_master *master;
1395 struct arm_smmu_device *smmu = find_smmu_for_device(dev);
1396
1397 if (!smmu)
1398 return -ENODEV;
1399
1400 master = find_smmu_master(smmu, dev->of_node);
1401 if (!master)
1402 return -ENODEV;
1403
1404 /* No automatic group creation for platform devices */
1405 group = iommu_group_alloc();
1406 if (IS_ERR(group))
1407 return PTR_ERR(group);
1408
1409 iommu_group_set_iommudata(group, &master->cfg, NULL);
1410 return iommu_group_add_device(group, dev);
1411 }
1412
1413 static int arm_smmu_add_device(struct device *dev)
1414 {
1415 if (dev_is_pci(dev))
1416 return arm_smmu_add_pci_device(to_pci_dev(dev));
1417
1418 return arm_smmu_add_platform_device(dev);
1419 }
1420
1421 static void arm_smmu_remove_device(struct device *dev)
1422 {
1423 iommu_group_remove_device(dev);
1424 }
1425
1426 static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
1427 enum iommu_attr attr, void *data)
1428 {
1429 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1430
1431 switch (attr) {
1432 case DOMAIN_ATTR_NESTING:
1433 *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
1434 return 0;
1435 default:
1436 return -ENODEV;
1437 }
1438 }
1439
1440 static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
1441 enum iommu_attr attr, void *data)
1442 {
1443 int ret = 0;
1444 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1445
1446 mutex_lock(&smmu_domain->init_mutex);
1447
1448 switch (attr) {
1449 case DOMAIN_ATTR_NESTING:
1450 if (smmu_domain->smmu) {
1451 ret = -EPERM;
1452 goto out_unlock;
1453 }
1454
1455 if (*(int *)data)
1456 smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED;
1457 else
1458 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
1459
1460 break;
1461 default:
1462 ret = -ENODEV;
1463 }
1464
1465 out_unlock:
1466 mutex_unlock(&smmu_domain->init_mutex);
1467 return ret;
1468 }
1469
1470 static struct iommu_ops arm_smmu_ops = {
1471 .capable = arm_smmu_capable,
1472 .domain_alloc = arm_smmu_domain_alloc,
1473 .domain_free = arm_smmu_domain_free,
1474 .attach_dev = arm_smmu_attach_dev,
1475 .detach_dev = arm_smmu_detach_dev,
1476 .map = arm_smmu_map,
1477 .unmap = arm_smmu_unmap,
1478 .map_sg = default_iommu_map_sg,
1479 .iova_to_phys = arm_smmu_iova_to_phys,
1480 .add_device = arm_smmu_add_device,
1481 .remove_device = arm_smmu_remove_device,
1482 .domain_get_attr = arm_smmu_domain_get_attr,
1483 .domain_set_attr = arm_smmu_domain_set_attr,
1484 .pgsize_bitmap = -1UL, /* Restricted during device attach */
1485 };
1486
1487 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1488 {
1489 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1490 void __iomem *cb_base;
1491 int i = 0;
1492 u32 reg;
1493
1494 /* clear global FSR */
1495 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1496 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1497
1498 /* Mark all SMRn as invalid and all S2CRn as bypass */
1499 for (i = 0; i < smmu->num_mapping_groups; ++i) {
1500 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
1501 writel_relaxed(S2CR_TYPE_BYPASS,
1502 gr0_base + ARM_SMMU_GR0_S2CR(i));
1503 }
1504
1505 /* Make sure all context banks are disabled and clear CB_FSR */
1506 for (i = 0; i < smmu->num_context_banks; ++i) {
1507 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1508 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1509 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1510 }
1511
1512 /* Invalidate the TLB, just in case */
1513 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1514 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1515
1516 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1517
1518 /* Enable fault reporting */
1519 reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1520
1521 /* Disable TLB broadcasting. */
1522 reg |= (sCR0_VMIDPNE | sCR0_PTM);
1523
1524 /* Enable client access, but bypass when no mapping is found */
1525 reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1526
1527 /* Disable forced broadcasting */
1528 reg &= ~sCR0_FB;
1529
1530 /* Don't upgrade barriers */
1531 reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1532
1533 /* Push the button */
1534 __arm_smmu_tlb_sync(smmu);
1535 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1536 }
1537
1538 static int arm_smmu_id_size_to_bits(int size)
1539 {
1540 switch (size) {
1541 case 0:
1542 return 32;
1543 case 1:
1544 return 36;
1545 case 2:
1546 return 40;
1547 case 3:
1548 return 42;
1549 case 4:
1550 return 44;
1551 case 5:
1552 default:
1553 return 48;
1554 }
1555 }
1556
1557 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1558 {
1559 unsigned long size;
1560 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1561 u32 id;
1562
1563 dev_notice(smmu->dev, "probing hardware configuration...\n");
1564 dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1565
1566 /* ID0 */
1567 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1568
1569 /* Restrict available stages based on module parameter */
1570 if (force_stage == 1)
1571 id &= ~(ID0_S2TS | ID0_NTS);
1572 else if (force_stage == 2)
1573 id &= ~(ID0_S1TS | ID0_NTS);
1574
1575 if (id & ID0_S1TS) {
1576 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1577 dev_notice(smmu->dev, "\tstage 1 translation\n");
1578 }
1579
1580 if (id & ID0_S2TS) {
1581 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1582 dev_notice(smmu->dev, "\tstage 2 translation\n");
1583 }
1584
1585 if (id & ID0_NTS) {
1586 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1587 dev_notice(smmu->dev, "\tnested translation\n");
1588 }
1589
1590 if (!(smmu->features &
1591 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) {
1592 dev_err(smmu->dev, "\tno translation support!\n");
1593 return -ENODEV;
1594 }
1595
1596 if ((id & ID0_S1TS) && ((smmu->version == 1) || (id & ID0_ATOSNS))) {
1597 smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
1598 dev_notice(smmu->dev, "\taddress translation ops\n");
1599 }
1600
1601 if (id & ID0_CTTW) {
1602 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1603 dev_notice(smmu->dev, "\tcoherent table walk\n");
1604 }
1605
1606 if (id & ID0_SMS) {
1607 u32 smr, sid, mask;
1608
1609 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1610 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1611 ID0_NUMSMRG_MASK;
1612 if (smmu->num_mapping_groups == 0) {
1613 dev_err(smmu->dev,
1614 "stream-matching supported, but no SMRs present!\n");
1615 return -ENODEV;
1616 }
1617
1618 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1619 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1620 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1621 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1622
1623 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1624 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1625 if ((mask & sid) != sid) {
1626 dev_err(smmu->dev,
1627 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1628 mask, sid);
1629 return -ENODEV;
1630 }
1631
1632 dev_notice(smmu->dev,
1633 "\tstream matching with %u register groups, mask 0x%x",
1634 smmu->num_mapping_groups, mask);
1635 } else {
1636 smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) &
1637 ID0_NUMSIDB_MASK;
1638 }
1639
1640 /* ID1 */
1641 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1642 smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12;
1643
1644 /* Check for size mismatch of SMMU address space from mapped region */
1645 size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1646 size *= 2 << smmu->pgshift;
1647 if (smmu->size != size)
1648 dev_warn(smmu->dev,
1649 "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1650 size, smmu->size);
1651
1652 smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK;
1653 smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1654 if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1655 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1656 return -ENODEV;
1657 }
1658 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1659 smmu->num_context_banks, smmu->num_s2_context_banks);
1660
1661 /* ID2 */
1662 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1663 size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1664 smmu->ipa_size = size;
1665
1666 /* The output mask is also applied for bypass */
1667 size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1668 smmu->pa_size = size;
1669
1670 /*
1671 * What the page table walker can address actually depends on which
1672 * descriptor format is in use, but since a) we don't know that yet,
1673 * and b) it can vary per context bank, this will have to do...
1674 */
1675 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(size)))
1676 dev_warn(smmu->dev,
1677 "failed to set DMA mask for table walker\n");
1678
1679 if (smmu->version == ARM_SMMU_V1) {
1680 smmu->va_size = smmu->ipa_size;
1681 size = SZ_4K | SZ_2M | SZ_1G;
1682 } else {
1683 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1684 smmu->va_size = arm_smmu_id_size_to_bits(size);
1685 #ifndef CONFIG_64BIT
1686 smmu->va_size = min(32UL, smmu->va_size);
1687 #endif
1688 size = 0;
1689 if (id & ID2_PTFS_4K)
1690 size |= SZ_4K | SZ_2M | SZ_1G;
1691 if (id & ID2_PTFS_16K)
1692 size |= SZ_16K | SZ_32M;
1693 if (id & ID2_PTFS_64K)
1694 size |= SZ_64K | SZ_512M;
1695 }
1696
1697 arm_smmu_ops.pgsize_bitmap &= size;
1698 dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", size);
1699
1700 if (smmu->features & ARM_SMMU_FEAT_TRANS_S1)
1701 dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n",
1702 smmu->va_size, smmu->ipa_size);
1703
1704 if (smmu->features & ARM_SMMU_FEAT_TRANS_S2)
1705 dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
1706 smmu->ipa_size, smmu->pa_size);
1707
1708 return 0;
1709 }
1710
1711 static const struct of_device_id arm_smmu_of_match[] = {
1712 { .compatible = "arm,smmu-v1", .data = (void *)ARM_SMMU_V1 },
1713 { .compatible = "arm,smmu-v2", .data = (void *)ARM_SMMU_V2 },
1714 { .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 },
1715 { .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 },
1716 { .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 },
1717 { },
1718 };
1719 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
1720
1721 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1722 {
1723 const struct of_device_id *of_id;
1724 struct resource *res;
1725 struct arm_smmu_device *smmu;
1726 struct device *dev = &pdev->dev;
1727 struct rb_node *node;
1728 struct of_phandle_args masterspec;
1729 int num_irqs, i, err;
1730
1731 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1732 if (!smmu) {
1733 dev_err(dev, "failed to allocate arm_smmu_device\n");
1734 return -ENOMEM;
1735 }
1736 smmu->dev = dev;
1737
1738 of_id = of_match_node(arm_smmu_of_match, dev->of_node);
1739 smmu->version = (enum arm_smmu_arch_version)of_id->data;
1740
1741 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1742 smmu->base = devm_ioremap_resource(dev, res);
1743 if (IS_ERR(smmu->base))
1744 return PTR_ERR(smmu->base);
1745 smmu->size = resource_size(res);
1746
1747 if (of_property_read_u32(dev->of_node, "#global-interrupts",
1748 &smmu->num_global_irqs)) {
1749 dev_err(dev, "missing #global-interrupts property\n");
1750 return -ENODEV;
1751 }
1752
1753 num_irqs = 0;
1754 while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1755 num_irqs++;
1756 if (num_irqs > smmu->num_global_irqs)
1757 smmu->num_context_irqs++;
1758 }
1759
1760 if (!smmu->num_context_irqs) {
1761 dev_err(dev, "found %d interrupts but expected at least %d\n",
1762 num_irqs, smmu->num_global_irqs + 1);
1763 return -ENODEV;
1764 }
1765
1766 smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1767 GFP_KERNEL);
1768 if (!smmu->irqs) {
1769 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1770 return -ENOMEM;
1771 }
1772
1773 for (i = 0; i < num_irqs; ++i) {
1774 int irq = platform_get_irq(pdev, i);
1775
1776 if (irq < 0) {
1777 dev_err(dev, "failed to get irq index %d\n", i);
1778 return -ENODEV;
1779 }
1780 smmu->irqs[i] = irq;
1781 }
1782
1783 err = arm_smmu_device_cfg_probe(smmu);
1784 if (err)
1785 return err;
1786
1787 i = 0;
1788 smmu->masters = RB_ROOT;
1789 while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1790 "#stream-id-cells", i,
1791 &masterspec)) {
1792 err = register_smmu_master(smmu, dev, &masterspec);
1793 if (err) {
1794 dev_err(dev, "failed to add master %s\n",
1795 masterspec.np->name);
1796 goto out_put_masters;
1797 }
1798
1799 i++;
1800 }
1801 dev_notice(dev, "registered %d master devices\n", i);
1802
1803 parse_driver_options(smmu);
1804
1805 if (smmu->version > ARM_SMMU_V1 &&
1806 smmu->num_context_banks != smmu->num_context_irqs) {
1807 dev_err(dev,
1808 "found only %d context interrupt(s) but %d required\n",
1809 smmu->num_context_irqs, smmu->num_context_banks);
1810 err = -ENODEV;
1811 goto out_put_masters;
1812 }
1813
1814 for (i = 0; i < smmu->num_global_irqs; ++i) {
1815 err = request_irq(smmu->irqs[i],
1816 arm_smmu_global_fault,
1817 IRQF_SHARED,
1818 "arm-smmu global fault",
1819 smmu);
1820 if (err) {
1821 dev_err(dev, "failed to request global IRQ %d (%u)\n",
1822 i, smmu->irqs[i]);
1823 goto out_free_irqs;
1824 }
1825 }
1826
1827 INIT_LIST_HEAD(&smmu->list);
1828 spin_lock(&arm_smmu_devices_lock);
1829 list_add(&smmu->list, &arm_smmu_devices);
1830 spin_unlock(&arm_smmu_devices_lock);
1831
1832 arm_smmu_device_reset(smmu);
1833 return 0;
1834
1835 out_free_irqs:
1836 while (i--)
1837 free_irq(smmu->irqs[i], smmu);
1838
1839 out_put_masters:
1840 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1841 struct arm_smmu_master *master
1842 = container_of(node, struct arm_smmu_master, node);
1843 of_node_put(master->of_node);
1844 }
1845
1846 return err;
1847 }
1848
1849 static int arm_smmu_device_remove(struct platform_device *pdev)
1850 {
1851 int i;
1852 struct device *dev = &pdev->dev;
1853 struct arm_smmu_device *curr, *smmu = NULL;
1854 struct rb_node *node;
1855
1856 spin_lock(&arm_smmu_devices_lock);
1857 list_for_each_entry(curr, &arm_smmu_devices, list) {
1858 if (curr->dev == dev) {
1859 smmu = curr;
1860 list_del(&smmu->list);
1861 break;
1862 }
1863 }
1864 spin_unlock(&arm_smmu_devices_lock);
1865
1866 if (!smmu)
1867 return -ENODEV;
1868
1869 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1870 struct arm_smmu_master *master
1871 = container_of(node, struct arm_smmu_master, node);
1872 of_node_put(master->of_node);
1873 }
1874
1875 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
1876 dev_err(dev, "removing device with active domains!\n");
1877
1878 for (i = 0; i < smmu->num_global_irqs; ++i)
1879 free_irq(smmu->irqs[i], smmu);
1880
1881 /* Turn the thing off */
1882 writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1883 return 0;
1884 }
1885
1886 static struct platform_driver arm_smmu_driver = {
1887 .driver = {
1888 .name = "arm-smmu",
1889 .of_match_table = of_match_ptr(arm_smmu_of_match),
1890 },
1891 .probe = arm_smmu_device_dt_probe,
1892 .remove = arm_smmu_device_remove,
1893 };
1894
1895 static int __init arm_smmu_init(void)
1896 {
1897 struct device_node *np;
1898 int ret;
1899
1900 /*
1901 * Play nice with systems that don't have an ARM SMMU by checking that
1902 * an ARM SMMU exists in the system before proceeding with the driver
1903 * and IOMMU bus operation registration.
1904 */
1905 np = of_find_matching_node(NULL, arm_smmu_of_match);
1906 if (!np)
1907 return 0;
1908
1909 of_node_put(np);
1910
1911 ret = platform_driver_register(&arm_smmu_driver);
1912 if (ret)
1913 return ret;
1914
1915 /* Oh, for a proper bus abstraction */
1916 if (!iommu_present(&platform_bus_type))
1917 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
1918
1919 #ifdef CONFIG_ARM_AMBA
1920 if (!iommu_present(&amba_bustype))
1921 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
1922 #endif
1923
1924 #ifdef CONFIG_PCI
1925 if (!iommu_present(&pci_bus_type))
1926 bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
1927 #endif
1928
1929 return 0;
1930 }
1931
1932 static void __exit arm_smmu_exit(void)
1933 {
1934 return platform_driver_unregister(&arm_smmu_driver);
1935 }
1936
1937 subsys_initcall(arm_smmu_init);
1938 module_exit(arm_smmu_exit);
1939
1940 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
1941 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1942 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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