projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
iommu/vt-d: Honour intel_iommu=sp_off for non-VMM domains
[deliverable/linux.git] / drivers / iommu / intel-iommu.c
1 /*
2 * Copyright © 2006-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * Authors: David Woodhouse <dwmw2@infradead.org>,
14 * Ashok Raj <ashok.raj@intel.com>,
15 * Shaohua Li <shaohua.li@intel.com>,
16 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
17 * Fenghua Yu <fenghua.yu@intel.com>
18 */
19
20 #include <linux/init.h>
21 #include <linux/bitmap.h>
22 #include <linux/debugfs.h>
23 #include <linux/export.h>
24 #include <linux/slab.h>
25 #include <linux/irq.h>
26 #include <linux/interrupt.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29 #include <linux/dmar.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/mempool.h>
32 #include <linux/memory.h>
33 #include <linux/timer.h>
34 #include <linux/iova.h>
35 #include <linux/iommu.h>
36 #include <linux/intel-iommu.h>
37 #include <linux/syscore_ops.h>
38 #include <linux/tboot.h>
39 #include <linux/dmi.h>
40 #include <linux/pci-ats.h>
41 #include <linux/memblock.h>
42 #include <asm/irq_remapping.h>
43 #include <asm/cacheflush.h>
44 #include <asm/iommu.h>
45
46 #include "irq_remapping.h"
47 #include "pci.h"
48
49 #define ROOT_SIZE VTD_PAGE_SIZE
50 #define CONTEXT_SIZE VTD_PAGE_SIZE
51
52 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
53 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
54 #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
55
56 #define IOAPIC_RANGE_START (0xfee00000)
57 #define IOAPIC_RANGE_END (0xfeefffff)
58 #define IOVA_START_ADDR (0x1000)
59
60 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
61
62 #define MAX_AGAW_WIDTH 64
63 #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
64
65 #define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
66 #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
67
68 /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
69 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
70 #define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
71 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
72 #define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
73
74 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
75 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
76 #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
77
78 /* page table handling */
79 #define LEVEL_STRIDE (9)
80 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
81
82 /*
83 * This bitmap is used to advertise the page sizes our hardware support
84 * to the IOMMU core, which will then use this information to split
85 * physically contiguous memory regions it is mapping into page sizes
86 * that we support.
87 *
88 * Traditionally the IOMMU core just handed us the mappings directly,
89 * after making sure the size is an order of a 4KiB page and that the
90 * mapping has natural alignment.
91 *
92 * To retain this behavior, we currently advertise that we support
93 * all page sizes that are an order of 4KiB.
94 *
95 * If at some point we'd like to utilize the IOMMU core's new behavior,
96 * we could change this to advertise the real page sizes we support.
97 */
98 #define INTEL_IOMMU_PGSIZES (~0xFFFUL)
99
100 static inline int agaw_to_level(int agaw)
101 {
102 return agaw + 2;
103 }
104
105 static inline int agaw_to_width(int agaw)
106 {
107 return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
108 }
109
110 static inline int width_to_agaw(int width)
111 {
112 return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
113 }
114
115 static inline unsigned int level_to_offset_bits(int level)
116 {
117 return (level - 1) * LEVEL_STRIDE;
118 }
119
120 static inline int pfn_level_offset(unsigned long pfn, int level)
121 {
122 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
123 }
124
125 static inline unsigned long level_mask(int level)
126 {
127 return -1UL << level_to_offset_bits(level);
128 }
129
130 static inline unsigned long level_size(int level)
131 {
132 return 1UL << level_to_offset_bits(level);
133 }
134
135 static inline unsigned long align_to_level(unsigned long pfn, int level)
136 {
137 return (pfn + level_size(level) - 1) & level_mask(level);
138 }
139
140 static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
141 {
142 return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
143 }
144
145 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
146 are never going to work. */
147 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
148 {
149 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
150 }
151
152 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
153 {
154 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
155 }
156 static inline unsigned long page_to_dma_pfn(struct page *pg)
157 {
158 return mm_to_dma_pfn(page_to_pfn(pg));
159 }
160 static inline unsigned long virt_to_dma_pfn(void *p)
161 {
162 return page_to_dma_pfn(virt_to_page(p));
163 }
164
165 /* global iommu list, set NULL for ignored DMAR units */
166 static struct intel_iommu **g_iommus;
167
168 static void __init check_tylersburg_isoch(void);
169 static int rwbf_quirk;
170
171 /*
172 * set to 1 to panic kernel if can't successfully enable VT-d
173 * (used when kernel is launched w/ TXT)
174 */
175 static int force_on = 0;
176
177 /*
178 * 0: Present
179 * 1-11: Reserved
180 * 12-63: Context Ptr (12 - (haw-1))
181 * 64-127: Reserved
182 */
183 struct root_entry {
184 u64 val;
185 u64 rsvd1;
186 };
187 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
188 static inline bool root_present(struct root_entry *root)
189 {
190 return (root->val & 1);
191 }
192 static inline void set_root_present(struct root_entry *root)
193 {
194 root->val |= 1;
195 }
196 static inline void set_root_value(struct root_entry *root, unsigned long value)
197 {
198 root->val |= value & VTD_PAGE_MASK;
199 }
200
201 static inline struct context_entry *
202 get_context_addr_from_root(struct root_entry *root)
203 {
204 return (struct context_entry *)
205 (root_present(root)?phys_to_virt(
206 root->val & VTD_PAGE_MASK) :
207 NULL);
208 }
209
210 /*
211 * low 64 bits:
212 * 0: present
213 * 1: fault processing disable
214 * 2-3: translation type
215 * 12-63: address space root
216 * high 64 bits:
217 * 0-2: address width
218 * 3-6: aval
219 * 8-23: domain id
220 */
221 struct context_entry {
222 u64 lo;
223 u64 hi;
224 };
225
226 static inline bool context_present(struct context_entry *context)
227 {
228 return (context->lo & 1);
229 }
230 static inline void context_set_present(struct context_entry *context)
231 {
232 context->lo |= 1;
233 }
234
235 static inline void context_set_fault_enable(struct context_entry *context)
236 {
237 context->lo &= (((u64)-1) << 2) | 1;
238 }
239
240 static inline void context_set_translation_type(struct context_entry *context,
241 unsigned long value)
242 {
243 context->lo &= (((u64)-1) << 4) | 3;
244 context->lo |= (value & 3) << 2;
245 }
246
247 static inline void context_set_address_root(struct context_entry *context,
248 unsigned long value)
249 {
250 context->lo |= value & VTD_PAGE_MASK;
251 }
252
253 static inline void context_set_address_width(struct context_entry *context,
254 unsigned long value)
255 {
256 context->hi |= value & 7;
257 }
258
259 static inline void context_set_domain_id(struct context_entry *context,
260 unsigned long value)
261 {
262 context->hi |= (value & ((1 << 16) - 1)) << 8;
263 }
264
265 static inline void context_clear_entry(struct context_entry *context)
266 {
267 context->lo = 0;
268 context->hi = 0;
269 }
270
271 /*
272 * 0: readable
273 * 1: writable
274 * 2-6: reserved
275 * 7: super page
276 * 8-10: available
277 * 11: snoop behavior
278 * 12-63: Host physcial address
279 */
280 struct dma_pte {
281 u64 val;
282 };
283
284 static inline void dma_clear_pte(struct dma_pte *pte)
285 {
286 pte->val = 0;
287 }
288
289 static inline u64 dma_pte_addr(struct dma_pte *pte)
290 {
291 #ifdef CONFIG_64BIT
292 return pte->val & VTD_PAGE_MASK;
293 #else
294 /* Must have a full atomic 64-bit read */
295 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
296 #endif
297 }
298
299 static inline bool dma_pte_present(struct dma_pte *pte)
300 {
301 return (pte->val & 3) != 0;
302 }
303
304 static inline bool dma_pte_superpage(struct dma_pte *pte)
305 {
306 return (pte->val & (1 << 7));
307 }
308
309 static inline int first_pte_in_page(struct dma_pte *pte)
310 {
311 return !((unsigned long)pte & ~VTD_PAGE_MASK);
312 }
313
314 /*
315 * This domain is a statically identity mapping domain.
316 * 1. This domain creats a static 1:1 mapping to all usable memory.
317 * 2. It maps to each iommu if successful.
318 * 3. Each iommu mapps to this domain if successful.
319 */
320 static struct dmar_domain *si_domain;
321 static int hw_pass_through = 1;
322
323 /* devices under the same p2p bridge are owned in one domain */
324 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
325
326 /* domain represents a virtual machine, more than one devices
327 * across iommus may be owned in one domain, e.g. kvm guest.
328 */
329 #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
330
331 /* si_domain contains mulitple devices */
332 #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
333
334 /* define the limit of IOMMUs supported in each domain */
335 #ifdef CONFIG_X86
336 # define IOMMU_UNITS_SUPPORTED MAX_IO_APICS
337 #else
338 # define IOMMU_UNITS_SUPPORTED 64
339 #endif
340
341 struct dmar_domain {
342 int id; /* domain id */
343 int nid; /* node id */
344 DECLARE_BITMAP(iommu_bmp, IOMMU_UNITS_SUPPORTED);
345 /* bitmap of iommus this domain uses*/
346
347 struct list_head devices; /* all devices' list */
348 struct iova_domain iovad; /* iova's that belong to this domain */
349
350 struct dma_pte *pgd; /* virtual address */
351 int gaw; /* max guest address width */
352
353 /* adjusted guest address width, 0 is level 2 30-bit */
354 int agaw;
355
356 int flags; /* flags to find out type of domain */
357
358 int iommu_coherency;/* indicate coherency of iommu access */
359 int iommu_snooping; /* indicate snooping control feature*/
360 int iommu_count; /* reference count of iommu */
361 int iommu_superpage;/* Level of superpages supported:
362 0 == 4KiB (no superpages), 1 == 2MiB,
363 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
364 spinlock_t iommu_lock; /* protect iommu set in domain */
365 u64 max_addr; /* maximum mapped address */
366 };
367
368 /* PCI domain-device relationship */
369 struct device_domain_info {
370 struct list_head link; /* link to domain siblings */
371 struct list_head global; /* link to global list */
372 int segment; /* PCI domain */
373 u8 bus; /* PCI bus number */
374 u8 devfn; /* PCI devfn number */
375 struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */
376 struct intel_iommu *iommu; /* IOMMU used by this device */
377 struct dmar_domain *domain; /* pointer to domain */
378 };
379
380 struct dmar_rmrr_unit {
381 struct list_head list; /* list of rmrr units */
382 struct acpi_dmar_header *hdr; /* ACPI header */
383 u64 base_address; /* reserved base address*/
384 u64 end_address; /* reserved end address */
385 struct pci_dev __rcu **devices; /* target devices */
386 int devices_cnt; /* target device count */
387 };
388
389 struct dmar_atsr_unit {
390 struct list_head list; /* list of ATSR units */
391 struct acpi_dmar_header *hdr; /* ACPI header */
392 struct pci_dev __rcu **devices; /* target devices */
393 int devices_cnt; /* target device count */
394 u8 include_all:1; /* include all ports */
395 };
396
397 static LIST_HEAD(dmar_atsr_units);
398 static LIST_HEAD(dmar_rmrr_units);
399
400 #define for_each_rmrr_units(rmrr) \
401 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
402
403 static void flush_unmaps_timeout(unsigned long data);
404
405 static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
406
407 #define HIGH_WATER_MARK 250
408 struct deferred_flush_tables {
409 int next;
410 struct iova *iova[HIGH_WATER_MARK];
411 struct dmar_domain *domain[HIGH_WATER_MARK];
412 struct page *freelist[HIGH_WATER_MARK];
413 };
414
415 static struct deferred_flush_tables *deferred_flush;
416
417 /* bitmap for indexing intel_iommus */
418 static int g_num_of_iommus;
419
420 static DEFINE_SPINLOCK(async_umap_flush_lock);
421 static LIST_HEAD(unmaps_to_do);
422
423 static int timer_on;
424 static long list_size;
425
426 static void domain_exit(struct dmar_domain *domain);
427 static void domain_remove_dev_info(struct dmar_domain *domain);
428 static void domain_remove_one_dev_info(struct dmar_domain *domain,
429 struct pci_dev *pdev);
430 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
431 struct pci_dev *pdev);
432
433 #ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
434 int dmar_disabled = 0;
435 #else
436 int dmar_disabled = 1;
437 #endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
438
439 int intel_iommu_enabled = 0;
440 EXPORT_SYMBOL_GPL(intel_iommu_enabled);
441
442 static int dmar_map_gfx = 1;
443 static int dmar_forcedac;
444 static int intel_iommu_strict;
445 static int intel_iommu_superpage = 1;
446
447 int intel_iommu_gfx_mapped;
448 EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
449
450 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
451 static DEFINE_SPINLOCK(device_domain_lock);
452 static LIST_HEAD(device_domain_list);
453
454 static struct iommu_ops intel_iommu_ops;
455
456 static int __init intel_iommu_setup(char *str)
457 {
458 if (!str)
459 return -EINVAL;
460 while (*str) {
461 if (!strncmp(str, "on", 2)) {
462 dmar_disabled = 0;
463 printk(KERN_INFO "Intel-IOMMU: enabled\n");
464 } else if (!strncmp(str, "off", 3)) {
465 dmar_disabled = 1;
466 printk(KERN_INFO "Intel-IOMMU: disabled\n");
467 } else if (!strncmp(str, "igfx_off", 8)) {
468 dmar_map_gfx = 0;
469 printk(KERN_INFO
470 "Intel-IOMMU: disable GFX device mapping\n");
471 } else if (!strncmp(str, "forcedac", 8)) {
472 printk(KERN_INFO
473 "Intel-IOMMU: Forcing DAC for PCI devices\n");
474 dmar_forcedac = 1;
475 } else if (!strncmp(str, "strict", 6)) {
476 printk(KERN_INFO
477 "Intel-IOMMU: disable batched IOTLB flush\n");
478 intel_iommu_strict = 1;
479 } else if (!strncmp(str, "sp_off", 6)) {
480 printk(KERN_INFO
481 "Intel-IOMMU: disable supported super page\n");
482 intel_iommu_superpage = 0;
483 }
484
485 str += strcspn(str, ",");
486 while (*str == ',')
487 str++;
488 }
489 return 0;
490 }
491 __setup("intel_iommu=", intel_iommu_setup);
492
493 static struct kmem_cache *iommu_domain_cache;
494 static struct kmem_cache *iommu_devinfo_cache;
495 static struct kmem_cache *iommu_iova_cache;
496
497 static inline void *alloc_pgtable_page(int node)
498 {
499 struct page *page;
500 void *vaddr = NULL;
501
502 page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
503 if (page)
504 vaddr = page_address(page);
505 return vaddr;
506 }
507
508 static inline void free_pgtable_page(void *vaddr)
509 {
510 free_page((unsigned long)vaddr);
511 }
512
513 static inline void *alloc_domain_mem(void)
514 {
515 return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
516 }
517
518 static void free_domain_mem(void *vaddr)
519 {
520 kmem_cache_free(iommu_domain_cache, vaddr);
521 }
522
523 static inline void * alloc_devinfo_mem(void)
524 {
525 return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
526 }
527
528 static inline void free_devinfo_mem(void *vaddr)
529 {
530 kmem_cache_free(iommu_devinfo_cache, vaddr);
531 }
532
533 struct iova *alloc_iova_mem(void)
534 {
535 return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC);
536 }
537
538 void free_iova_mem(struct iova *iova)
539 {
540 kmem_cache_free(iommu_iova_cache, iova);
541 }
542
543
544 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
545 {
546 unsigned long sagaw;
547 int agaw = -1;
548
549 sagaw = cap_sagaw(iommu->cap);
550 for (agaw = width_to_agaw(max_gaw);
551 agaw >= 0; agaw--) {
552 if (test_bit(agaw, &sagaw))
553 break;
554 }
555
556 return agaw;
557 }
558
559 /*
560 * Calculate max SAGAW for each iommu.
561 */
562 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
563 {
564 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
565 }
566
567 /*
568 * calculate agaw for each iommu.
569 * "SAGAW" may be different across iommus, use a default agaw, and
570 * get a supported less agaw for iommus that don't support the default agaw.
571 */
572 int iommu_calculate_agaw(struct intel_iommu *iommu)
573 {
574 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
575 }
576
577 /* This functionin only returns single iommu in a domain */
578 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
579 {
580 int iommu_id;
581
582 /* si_domain and vm domain should not get here. */
583 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
584 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
585
586 iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
587 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
588 return NULL;
589
590 return g_iommus[iommu_id];
591 }
592
593 static void domain_update_iommu_coherency(struct dmar_domain *domain)
594 {
595 int i;
596
597 i = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
598
599 domain->iommu_coherency = i < g_num_of_iommus ? 1 : 0;
600
601 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
602 if (!ecap_coherent(g_iommus[i]->ecap)) {
603 domain->iommu_coherency = 0;
604 break;
605 }
606 }
607 }
608
609 static void domain_update_iommu_snooping(struct dmar_domain *domain)
610 {
611 int i;
612
613 domain->iommu_snooping = 1;
614
615 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
616 if (!ecap_sc_support(g_iommus[i]->ecap)) {
617 domain->iommu_snooping = 0;
618 break;
619 }
620 }
621 }
622
623 static void domain_update_iommu_superpage(struct dmar_domain *domain)
624 {
625 struct dmar_drhd_unit *drhd;
626 struct intel_iommu *iommu = NULL;
627 int mask = 0xf;
628
629 if (!intel_iommu_superpage) {
630 domain->iommu_superpage = 0;
631 return;
632 }
633
634 /* set iommu_superpage to the smallest common denominator */
635 rcu_read_lock();
636 for_each_active_iommu(iommu, drhd) {
637 mask &= cap_super_page_val(iommu->cap);
638 if (!mask) {
639 break;
640 }
641 }
642 rcu_read_unlock();
643
644 domain->iommu_superpage = fls(mask);
645 }
646
647 /* Some capabilities may be different across iommus */
648 static void domain_update_iommu_cap(struct dmar_domain *domain)
649 {
650 domain_update_iommu_coherency(domain);
651 domain_update_iommu_snooping(domain);
652 domain_update_iommu_superpage(domain);
653 }
654
655 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
656 {
657 struct dmar_drhd_unit *drhd = NULL;
658 struct intel_iommu *iommu;
659 struct pci_dev *dev;
660 int i;
661
662 rcu_read_lock();
663 for_each_active_iommu(iommu, drhd) {
664 if (segment != drhd->segment)
665 continue;
666
667 for_each_active_dev_scope(drhd->devices,
668 drhd->devices_cnt, i, dev) {
669 if (dev->bus->number == bus && dev->devfn == devfn)
670 goto out;
671 if (dev->subordinate &&
672 dev->subordinate->number <= bus &&
673 dev->subordinate->busn_res.end >= bus)
674 goto out;
675 }
676
677 if (drhd->include_all)
678 goto out;
679 }
680 iommu = NULL;
681 out:
682 rcu_read_unlock();
683
684 return iommu;
685 }
686
687 static void domain_flush_cache(struct dmar_domain *domain,
688 void *addr, int size)
689 {
690 if (!domain->iommu_coherency)
691 clflush_cache_range(addr, size);
692 }
693
694 /* Gets context entry for a given bus and devfn */
695 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
696 u8 bus, u8 devfn)
697 {
698 struct root_entry *root;
699 struct context_entry *context;
700 unsigned long phy_addr;
701 unsigned long flags;
702
703 spin_lock_irqsave(&iommu->lock, flags);
704 root = &iommu->root_entry[bus];
705 context = get_context_addr_from_root(root);
706 if (!context) {
707 context = (struct context_entry *)
708 alloc_pgtable_page(iommu->node);
709 if (!context) {
710 spin_unlock_irqrestore(&iommu->lock, flags);
711 return NULL;
712 }
713 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
714 phy_addr = virt_to_phys((void *)context);
715 set_root_value(root, phy_addr);
716 set_root_present(root);
717 __iommu_flush_cache(iommu, root, sizeof(*root));
718 }
719 spin_unlock_irqrestore(&iommu->lock, flags);
720 return &context[devfn];
721 }
722
723 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
724 {
725 struct root_entry *root;
726 struct context_entry *context;
727 int ret;
728 unsigned long flags;
729
730 spin_lock_irqsave(&iommu->lock, flags);
731 root = &iommu->root_entry[bus];
732 context = get_context_addr_from_root(root);
733 if (!context) {
734 ret = 0;
735 goto out;
736 }
737 ret = context_present(&context[devfn]);
738 out:
739 spin_unlock_irqrestore(&iommu->lock, flags);
740 return ret;
741 }
742
743 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
744 {
745 struct root_entry *root;
746 struct context_entry *context;
747 unsigned long flags;
748
749 spin_lock_irqsave(&iommu->lock, flags);
750 root = &iommu->root_entry[bus];
751 context = get_context_addr_from_root(root);
752 if (context) {
753 context_clear_entry(&context[devfn]);
754 __iommu_flush_cache(iommu, &context[devfn], \
755 sizeof(*context));
756 }
757 spin_unlock_irqrestore(&iommu->lock, flags);
758 }
759
760 static void free_context_table(struct intel_iommu *iommu)
761 {
762 struct root_entry *root;
763 int i;
764 unsigned long flags;
765 struct context_entry *context;
766
767 spin_lock_irqsave(&iommu->lock, flags);
768 if (!iommu->root_entry) {
769 goto out;
770 }
771 for (i = 0; i < ROOT_ENTRY_NR; i++) {
772 root = &iommu->root_entry[i];
773 context = get_context_addr_from_root(root);
774 if (context)
775 free_pgtable_page(context);
776 }
777 free_pgtable_page(iommu->root_entry);
778 iommu->root_entry = NULL;
779 out:
780 spin_unlock_irqrestore(&iommu->lock, flags);
781 }
782
783 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
784 unsigned long pfn, int *target_level)
785 {
786 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
787 struct dma_pte *parent, *pte = NULL;
788 int level = agaw_to_level(domain->agaw);
789 int offset;
790
791 BUG_ON(!domain->pgd);
792
793 if (addr_width < BITS_PER_LONG && pfn >> addr_width)
794 /* Address beyond IOMMU's addressing capabilities. */
795 return NULL;
796
797 parent = domain->pgd;
798
799 while (1) {
800 void *tmp_page;
801
802 offset = pfn_level_offset(pfn, level);
803 pte = &parent[offset];
804 if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
805 break;
806 if (level == *target_level)
807 break;
808
809 if (!dma_pte_present(pte)) {
810 uint64_t pteval;
811
812 tmp_page = alloc_pgtable_page(domain->nid);
813
814 if (!tmp_page)
815 return NULL;
816
817 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
818 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
819 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
820 /* Someone else set it while we were thinking; use theirs. */
821 free_pgtable_page(tmp_page);
822 } else {
823 dma_pte_addr(pte);
824 domain_flush_cache(domain, pte, sizeof(*pte));
825 }
826 }
827 if (level == 1)
828 break;
829
830 parent = phys_to_virt(dma_pte_addr(pte));
831 level--;
832 }
833
834 if (!*target_level)
835 *target_level = level;
836
837 return pte;
838 }
839
840
841 /* return address's pte at specific level */
842 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
843 unsigned long pfn,
844 int level, int *large_page)
845 {
846 struct dma_pte *parent, *pte = NULL;
847 int total = agaw_to_level(domain->agaw);
848 int offset;
849
850 parent = domain->pgd;
851 while (level <= total) {
852 offset = pfn_level_offset(pfn, total);
853 pte = &parent[offset];
854 if (level == total)
855 return pte;
856
857 if (!dma_pte_present(pte)) {
858 *large_page = total;
859 break;
860 }
861
862 if (pte->val & DMA_PTE_LARGE_PAGE) {
863 *large_page = total;
864 return pte;
865 }
866
867 parent = phys_to_virt(dma_pte_addr(pte));
868 total--;
869 }
870 return NULL;
871 }
872
873 /* clear last level pte, a tlb flush should be followed */
874 static void dma_pte_clear_range(struct dmar_domain *domain,
875 unsigned long start_pfn,
876 unsigned long last_pfn)
877 {
878 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
879 unsigned int large_page = 1;
880 struct dma_pte *first_pte, *pte;
881
882 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
883 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
884 BUG_ON(start_pfn > last_pfn);
885
886 /* we don't need lock here; nobody else touches the iova range */
887 do {
888 large_page = 1;
889 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
890 if (!pte) {
891 start_pfn = align_to_level(start_pfn + 1, large_page + 1);
892 continue;
893 }
894 do {
895 dma_clear_pte(pte);
896 start_pfn += lvl_to_nr_pages(large_page);
897 pte++;
898 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
899
900 domain_flush_cache(domain, first_pte,
901 (void *)pte - (void *)first_pte);
902
903 } while (start_pfn && start_pfn <= last_pfn);
904 }
905
906 static void dma_pte_free_level(struct dmar_domain *domain, int level,
907 struct dma_pte *pte, unsigned long pfn,
908 unsigned long start_pfn, unsigned long last_pfn)
909 {
910 pfn = max(start_pfn, pfn);
911 pte = &pte[pfn_level_offset(pfn, level)];
912
913 do {
914 unsigned long level_pfn;
915 struct dma_pte *level_pte;
916
917 if (!dma_pte_present(pte) || dma_pte_superpage(pte))
918 goto next;
919
920 level_pfn = pfn & level_mask(level - 1);
921 level_pte = phys_to_virt(dma_pte_addr(pte));
922
923 if (level > 2)
924 dma_pte_free_level(domain, level - 1, level_pte,
925 level_pfn, start_pfn, last_pfn);
926
927 /* If range covers entire pagetable, free it */
928 if (!(start_pfn > level_pfn ||
929 last_pfn < level_pfn + level_size(level) - 1)) {
930 dma_clear_pte(pte);
931 domain_flush_cache(domain, pte, sizeof(*pte));
932 free_pgtable_page(level_pte);
933 }
934 next:
935 pfn += level_size(level);
936 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
937 }
938
939 /* free page table pages. last level pte should already be cleared */
940 static void dma_pte_free_pagetable(struct dmar_domain *domain,
941 unsigned long start_pfn,
942 unsigned long last_pfn)
943 {
944 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
945
946 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
947 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
948 BUG_ON(start_pfn > last_pfn);
949
950 /* We don't need lock here; nobody else touches the iova range */
951 dma_pte_free_level(domain, agaw_to_level(domain->agaw),
952 domain->pgd, 0, start_pfn, last_pfn);
953
954 /* free pgd */
955 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
956 free_pgtable_page(domain->pgd);
957 domain->pgd = NULL;
958 }
959 }
960
961 /* When a page at a given level is being unlinked from its parent, we don't
962 need to *modify* it at all. All we need to do is make a list of all the
963 pages which can be freed just as soon as we've flushed the IOTLB and we
964 know the hardware page-walk will no longer touch them.
965 The 'pte' argument is the *parent* PTE, pointing to the page that is to
966 be freed. */
967 static struct page *dma_pte_list_pagetables(struct dmar_domain *domain,
968 int level, struct dma_pte *pte,
969 struct page *freelist)
970 {
971 struct page *pg;
972
973 pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT);
974 pg->freelist = freelist;
975 freelist = pg;
976
977 if (level == 1)
978 return freelist;
979
980 for (pte = page_address(pg); !first_pte_in_page(pte); pte++) {
981 if (dma_pte_present(pte) && !dma_pte_superpage(pte))
982 freelist = dma_pte_list_pagetables(domain, level - 1,
983 pte, freelist);
984 }
985
986 return freelist;
987 }
988
989 static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
990 struct dma_pte *pte, unsigned long pfn,
991 unsigned long start_pfn,
992 unsigned long last_pfn,
993 struct page *freelist)
994 {
995 struct dma_pte *first_pte = NULL, *last_pte = NULL;
996
997 pfn = max(start_pfn, pfn);
998 pte = &pte[pfn_level_offset(pfn, level)];
999
1000 do {
1001 unsigned long level_pfn;
1002
1003 if (!dma_pte_present(pte))
1004 goto next;
1005
1006 level_pfn = pfn & level_mask(level);
1007
1008 /* If range covers entire pagetable, free it */
1009 if (start_pfn <= level_pfn &&
1010 last_pfn >= level_pfn + level_size(level) - 1) {
1011 /* These suborbinate page tables are going away entirely. Don't
1012 bother to clear them; we're just going to *free* them. */
1013 if (level > 1 && !dma_pte_superpage(pte))
1014 freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist);
1015
1016 dma_clear_pte(pte);
1017 if (!first_pte)
1018 first_pte = pte;
1019 last_pte = pte;
1020 } else if (level > 1) {
1021 /* Recurse down into a level that isn't *entirely* obsolete */
1022 freelist = dma_pte_clear_level(domain, level - 1,
1023 phys_to_virt(dma_pte_addr(pte)),
1024 level_pfn, start_pfn, last_pfn,
1025 freelist);
1026 }
1027 next:
1028 pfn += level_size(level);
1029 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
1030
1031 if (first_pte)
1032 domain_flush_cache(domain, first_pte,
1033 (void *)++last_pte - (void *)first_pte);
1034
1035 return freelist;
1036 }
1037
1038 /* We can't just free the pages because the IOMMU may still be walking
1039 the page tables, and may have cached the intermediate levels. The
1040 pages can only be freed after the IOTLB flush has been done. */
1041 struct page *domain_unmap(struct dmar_domain *domain,
1042 unsigned long start_pfn,
1043 unsigned long last_pfn)
1044 {
1045 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1046 struct page *freelist = NULL;
1047
1048 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
1049 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
1050 BUG_ON(start_pfn > last_pfn);
1051
1052 /* we don't need lock here; nobody else touches the iova range */
1053 freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw),
1054 domain->pgd, 0, start_pfn, last_pfn, NULL);
1055
1056 /* free pgd */
1057 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1058 struct page *pgd_page = virt_to_page(domain->pgd);
1059 pgd_page->freelist = freelist;
1060 freelist = pgd_page;
1061
1062 domain->pgd = NULL;
1063 }
1064
1065 return freelist;
1066 }
1067
1068 void dma_free_pagelist(struct page *freelist)
1069 {
1070 struct page *pg;
1071
1072 while ((pg = freelist)) {
1073 freelist = pg->freelist;
1074 free_pgtable_page(page_address(pg));
1075 }
1076 }
1077
1078 /* iommu handling */
1079 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
1080 {
1081 struct root_entry *root;
1082 unsigned long flags;
1083
1084 root = (struct root_entry *)alloc_pgtable_page(iommu->node);
1085 if (!root)
1086 return -ENOMEM;
1087
1088 __iommu_flush_cache(iommu, root, ROOT_SIZE);
1089
1090 spin_lock_irqsave(&iommu->lock, flags);
1091 iommu->root_entry = root;
1092 spin_unlock_irqrestore(&iommu->lock, flags);
1093
1094 return 0;
1095 }
1096
1097 static void iommu_set_root_entry(struct intel_iommu *iommu)
1098 {
1099 void *addr;
1100 u32 sts;
1101 unsigned long flag;
1102
1103 addr = iommu->root_entry;
1104
1105 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1106 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
1107
1108 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
1109
1110 /* Make sure hardware complete it */
1111 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1112 readl, (sts & DMA_GSTS_RTPS), sts);
1113
1114 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1115 }
1116
1117 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
1118 {
1119 u32 val;
1120 unsigned long flag;
1121
1122 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
1123 return;
1124
1125 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1126 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
1127
1128 /* Make sure hardware complete it */
1129 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1130 readl, (!(val & DMA_GSTS_WBFS)), val);
1131
1132 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1133 }
1134
1135 /* return value determine if we need a write buffer flush */
1136 static void __iommu_flush_context(struct intel_iommu *iommu,
1137 u16 did, u16 source_id, u8 function_mask,
1138 u64 type)
1139 {
1140 u64 val = 0;
1141 unsigned long flag;
1142
1143 switch (type) {
1144 case DMA_CCMD_GLOBAL_INVL:
1145 val = DMA_CCMD_GLOBAL_INVL;
1146 break;
1147 case DMA_CCMD_DOMAIN_INVL:
1148 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
1149 break;
1150 case DMA_CCMD_DEVICE_INVL:
1151 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
1152 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
1153 break;
1154 default:
1155 BUG();
1156 }
1157 val |= DMA_CCMD_ICC;
1158
1159 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1160 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
1161
1162 /* Make sure hardware complete it */
1163 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
1164 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
1165
1166 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1167 }
1168
1169 /* return value determine if we need a write buffer flush */
1170 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
1171 u64 addr, unsigned int size_order, u64 type)
1172 {
1173 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
1174 u64 val = 0, val_iva = 0;
1175 unsigned long flag;
1176
1177 switch (type) {
1178 case DMA_TLB_GLOBAL_FLUSH:
1179 /* global flush doesn't need set IVA_REG */
1180 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
1181 break;
1182 case DMA_TLB_DSI_FLUSH:
1183 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1184 break;
1185 case DMA_TLB_PSI_FLUSH:
1186 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1187 /* IH bit is passed in as part of address */
1188 val_iva = size_order | addr;
1189 break;
1190 default:
1191 BUG();
1192 }
1193 /* Note: set drain read/write */
1194 #if 0
1195 /*
1196 * This is probably to be super secure.. Looks like we can
1197 * ignore it without any impact.
1198 */
1199 if (cap_read_drain(iommu->cap))
1200 val |= DMA_TLB_READ_DRAIN;
1201 #endif
1202 if (cap_write_drain(iommu->cap))
1203 val |= DMA_TLB_WRITE_DRAIN;
1204
1205 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1206 /* Note: Only uses first TLB reg currently */
1207 if (val_iva)
1208 dmar_writeq(iommu->reg + tlb_offset, val_iva);
1209 dmar_writeq(iommu->reg + tlb_offset + 8, val);
1210
1211 /* Make sure hardware complete it */
1212 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
1213 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1214
1215 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1216
1217 /* check IOTLB invalidation granularity */
1218 if (DMA_TLB_IAIG(val) == 0)
1219 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
1220 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1221 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
1222 (unsigned long long)DMA_TLB_IIRG(type),
1223 (unsigned long long)DMA_TLB_IAIG(val));
1224 }
1225
1226 static struct device_domain_info *iommu_support_dev_iotlb(
1227 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1228 {
1229 int found = 0;
1230 unsigned long flags;
1231 struct device_domain_info *info;
1232 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1233
1234 if (!ecap_dev_iotlb_support(iommu->ecap))
1235 return NULL;
1236
1237 if (!iommu->qi)
1238 return NULL;
1239
1240 spin_lock_irqsave(&device_domain_lock, flags);
1241 list_for_each_entry(info, &domain->devices, link)
1242 if (info->bus == bus && info->devfn == devfn) {
1243 found = 1;
1244 break;
1245 }
1246 spin_unlock_irqrestore(&device_domain_lock, flags);
1247
1248 if (!found || !info->dev)
1249 return NULL;
1250
1251 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1252 return NULL;
1253
1254 if (!dmar_find_matched_atsr_unit(info->dev))
1255 return NULL;
1256
1257 info->iommu = iommu;
1258
1259 return info;
1260 }
1261
1262 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1263 {
1264 if (!info)
1265 return;
1266
1267 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1268 }
1269
1270 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1271 {
1272 if (!info->dev || !pci_ats_enabled(info->dev))
1273 return;
1274
1275 pci_disable_ats(info->dev);
1276 }
1277
1278 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1279 u64 addr, unsigned mask)
1280 {
1281 u16 sid, qdep;
1282 unsigned long flags;
1283 struct device_domain_info *info;
1284
1285 spin_lock_irqsave(&device_domain_lock, flags);
1286 list_for_each_entry(info, &domain->devices, link) {
1287 if (!info->dev || !pci_ats_enabled(info->dev))
1288 continue;
1289
1290 sid = info->bus << 8 | info->devfn;
1291 qdep = pci_ats_queue_depth(info->dev);
1292 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1293 }
1294 spin_unlock_irqrestore(&device_domain_lock, flags);
1295 }
1296
1297 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1298 unsigned long pfn, unsigned int pages, int ih, int map)
1299 {
1300 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1301 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1302
1303 BUG_ON(pages == 0);
1304
1305 if (ih)
1306 ih = 1 << 6;
1307 /*
1308 * Fallback to domain selective flush if no PSI support or the size is
1309 * too big.
1310 * PSI requires page size to be 2 ^ x, and the base address is naturally
1311 * aligned to the size
1312 */
1313 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1314 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1315 DMA_TLB_DSI_FLUSH);
1316 else
1317 iommu->flush.flush_iotlb(iommu, did, addr | ih, mask,
1318 DMA_TLB_PSI_FLUSH);
1319
1320 /*
1321 * In caching mode, changes of pages from non-present to present require
1322 * flush. However, device IOTLB doesn't need to be flushed in this case.
1323 */
1324 if (!cap_caching_mode(iommu->cap) || !map)
1325 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1326 }
1327
1328 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1329 {
1330 u32 pmen;
1331 unsigned long flags;
1332
1333 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1334 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1335 pmen &= ~DMA_PMEN_EPM;
1336 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1337
1338 /* wait for the protected region status bit to clear */
1339 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1340 readl, !(pmen & DMA_PMEN_PRS), pmen);
1341
1342 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1343 }
1344
1345 static int iommu_enable_translation(struct intel_iommu *iommu)
1346 {
1347 u32 sts;
1348 unsigned long flags;
1349
1350 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1351 iommu->gcmd |= DMA_GCMD_TE;
1352 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1353
1354 /* Make sure hardware complete it */
1355 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1356 readl, (sts & DMA_GSTS_TES), sts);
1357
1358 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1359 return 0;
1360 }
1361
1362 static int iommu_disable_translation(struct intel_iommu *iommu)
1363 {
1364 u32 sts;
1365 unsigned long flag;
1366
1367 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1368 iommu->gcmd &= ~DMA_GCMD_TE;
1369 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1370
1371 /* Make sure hardware complete it */
1372 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1373 readl, (!(sts & DMA_GSTS_TES)), sts);
1374
1375 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1376 return 0;
1377 }
1378
1379
1380 static int iommu_init_domains(struct intel_iommu *iommu)
1381 {
1382 unsigned long ndomains;
1383 unsigned long nlongs;
1384
1385 ndomains = cap_ndoms(iommu->cap);
1386 pr_debug("IOMMU%d: Number of Domains supported <%ld>\n",
1387 iommu->seq_id, ndomains);
1388 nlongs = BITS_TO_LONGS(ndomains);
1389
1390 spin_lock_init(&iommu->lock);
1391
1392 /* TBD: there might be 64K domains,
1393 * consider other allocation for future chip
1394 */
1395 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1396 if (!iommu->domain_ids) {
1397 pr_err("IOMMU%d: allocating domain id array failed\n",
1398 iommu->seq_id);
1399 return -ENOMEM;
1400 }
1401 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1402 GFP_KERNEL);
1403 if (!iommu->domains) {
1404 pr_err("IOMMU%d: allocating domain array failed\n",
1405 iommu->seq_id);
1406 kfree(iommu->domain_ids);
1407 iommu->domain_ids = NULL;
1408 return -ENOMEM;
1409 }
1410
1411 /*
1412 * if Caching mode is set, then invalid translations are tagged
1413 * with domainid 0. Hence we need to pre-allocate it.
1414 */
1415 if (cap_caching_mode(iommu->cap))
1416 set_bit(0, iommu->domain_ids);
1417 return 0;
1418 }
1419
1420 static void free_dmar_iommu(struct intel_iommu *iommu)
1421 {
1422 struct dmar_domain *domain;
1423 int i, count;
1424 unsigned long flags;
1425
1426 if ((iommu->domains) && (iommu->domain_ids)) {
1427 for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
1428 /*
1429 * Domain id 0 is reserved for invalid translation
1430 * if hardware supports caching mode.
1431 */
1432 if (cap_caching_mode(iommu->cap) && i == 0)
1433 continue;
1434
1435 domain = iommu->domains[i];
1436 clear_bit(i, iommu->domain_ids);
1437
1438 spin_lock_irqsave(&domain->iommu_lock, flags);
1439 count = --domain->iommu_count;
1440 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1441 if (count == 0)
1442 domain_exit(domain);
1443 }
1444 }
1445
1446 if (iommu->gcmd & DMA_GCMD_TE)
1447 iommu_disable_translation(iommu);
1448
1449 kfree(iommu->domains);
1450 kfree(iommu->domain_ids);
1451 iommu->domains = NULL;
1452 iommu->domain_ids = NULL;
1453
1454 g_iommus[iommu->seq_id] = NULL;
1455
1456 /* free context mapping */
1457 free_context_table(iommu);
1458 }
1459
1460 static struct dmar_domain *alloc_domain(bool vm)
1461 {
1462 /* domain id for virtual machine, it won't be set in context */
1463 static atomic_t vm_domid = ATOMIC_INIT(0);
1464 struct dmar_domain *domain;
1465
1466 domain = alloc_domain_mem();
1467 if (!domain)
1468 return NULL;
1469
1470 domain->nid = -1;
1471 domain->iommu_count = 0;
1472 memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp));
1473 domain->flags = 0;
1474 spin_lock_init(&domain->iommu_lock);
1475 INIT_LIST_HEAD(&domain->devices);
1476 if (vm) {
1477 domain->id = atomic_inc_return(&vm_domid);
1478 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
1479 }
1480
1481 return domain;
1482 }
1483
1484 static int iommu_attach_domain(struct dmar_domain *domain,
1485 struct intel_iommu *iommu)
1486 {
1487 int num;
1488 unsigned long ndomains;
1489 unsigned long flags;
1490
1491 ndomains = cap_ndoms(iommu->cap);
1492
1493 spin_lock_irqsave(&iommu->lock, flags);
1494
1495 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1496 if (num >= ndomains) {
1497 spin_unlock_irqrestore(&iommu->lock, flags);
1498 printk(KERN_ERR "IOMMU: no free domain ids\n");
1499 return -ENOMEM;
1500 }
1501
1502 domain->id = num;
1503 domain->iommu_count++;
1504 set_bit(num, iommu->domain_ids);
1505 set_bit(iommu->seq_id, domain->iommu_bmp);
1506 iommu->domains[num] = domain;
1507 spin_unlock_irqrestore(&iommu->lock, flags);
1508
1509 return 0;
1510 }
1511
1512 static void iommu_detach_domain(struct dmar_domain *domain,
1513 struct intel_iommu *iommu)
1514 {
1515 unsigned long flags;
1516 int num, ndomains;
1517
1518 spin_lock_irqsave(&iommu->lock, flags);
1519 ndomains = cap_ndoms(iommu->cap);
1520 for_each_set_bit(num, iommu->domain_ids, ndomains) {
1521 if (iommu->domains[num] == domain) {
1522 clear_bit(num, iommu->domain_ids);
1523 iommu->domains[num] = NULL;
1524 break;
1525 }
1526 }
1527 spin_unlock_irqrestore(&iommu->lock, flags);
1528 }
1529
1530 static struct iova_domain reserved_iova_list;
1531 static struct lock_class_key reserved_rbtree_key;
1532
1533 static int dmar_init_reserved_ranges(void)
1534 {
1535 struct pci_dev *pdev = NULL;
1536 struct iova *iova;
1537 int i;
1538
1539 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1540
1541 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1542 &reserved_rbtree_key);
1543
1544 /* IOAPIC ranges shouldn't be accessed by DMA */
1545 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1546 IOVA_PFN(IOAPIC_RANGE_END));
1547 if (!iova) {
1548 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1549 return -ENODEV;
1550 }
1551
1552 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1553 for_each_pci_dev(pdev) {
1554 struct resource *r;
1555
1556 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1557 r = &pdev->resource[i];
1558 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1559 continue;
1560 iova = reserve_iova(&reserved_iova_list,
1561 IOVA_PFN(r->start),
1562 IOVA_PFN(r->end));
1563 if (!iova) {
1564 printk(KERN_ERR "Reserve iova failed\n");
1565 return -ENODEV;
1566 }
1567 }
1568 }
1569 return 0;
1570 }
1571
1572 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1573 {
1574 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1575 }
1576
1577 static inline int guestwidth_to_adjustwidth(int gaw)
1578 {
1579 int agaw;
1580 int r = (gaw - 12) % 9;
1581
1582 if (r == 0)
1583 agaw = gaw;
1584 else
1585 agaw = gaw + 9 - r;
1586 if (agaw > 64)
1587 agaw = 64;
1588 return agaw;
1589 }
1590
1591 static int domain_init(struct dmar_domain *domain, int guest_width)
1592 {
1593 struct intel_iommu *iommu;
1594 int adjust_width, agaw;
1595 unsigned long sagaw;
1596
1597 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1598 domain_reserve_special_ranges(domain);
1599
1600 /* calculate AGAW */
1601 iommu = domain_get_iommu(domain);
1602 if (guest_width > cap_mgaw(iommu->cap))
1603 guest_width = cap_mgaw(iommu->cap);
1604 domain->gaw = guest_width;
1605 adjust_width = guestwidth_to_adjustwidth(guest_width);
1606 agaw = width_to_agaw(adjust_width);
1607 sagaw = cap_sagaw(iommu->cap);
1608 if (!test_bit(agaw, &sagaw)) {
1609 /* hardware doesn't support it, choose a bigger one */
1610 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1611 agaw = find_next_bit(&sagaw, 5, agaw);
1612 if (agaw >= 5)
1613 return -ENODEV;
1614 }
1615 domain->agaw = agaw;
1616
1617 if (ecap_coherent(iommu->ecap))
1618 domain->iommu_coherency = 1;
1619 else
1620 domain->iommu_coherency = 0;
1621
1622 if (ecap_sc_support(iommu->ecap))
1623 domain->iommu_snooping = 1;
1624 else
1625 domain->iommu_snooping = 0;
1626
1627 if (intel_iommu_superpage)
1628 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1629 else
1630 domain->iommu_superpage = 0;
1631
1632 domain->nid = iommu->node;
1633
1634 /* always allocate the top pgd */
1635 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
1636 if (!domain->pgd)
1637 return -ENOMEM;
1638 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1639 return 0;
1640 }
1641
1642 static void domain_exit(struct dmar_domain *domain)
1643 {
1644 struct dmar_drhd_unit *drhd;
1645 struct intel_iommu *iommu;
1646 struct page *freelist = NULL;
1647
1648 /* Domain 0 is reserved, so dont process it */
1649 if (!domain)
1650 return;
1651
1652 /* Flush any lazy unmaps that may reference this domain */
1653 if (!intel_iommu_strict)
1654 flush_unmaps_timeout(0);
1655
1656 /* remove associated devices */
1657 domain_remove_dev_info(domain);
1658
1659 /* destroy iovas */
1660 put_iova_domain(&domain->iovad);
1661
1662 freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1663
1664 /* clear attached or cached domains */
1665 rcu_read_lock();
1666 for_each_active_iommu(iommu, drhd)
1667 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1668 test_bit(iommu->seq_id, domain->iommu_bmp))
1669 iommu_detach_domain(domain, iommu);
1670 rcu_read_unlock();
1671
1672 dma_free_pagelist(freelist);
1673
1674 free_domain_mem(domain);
1675 }
1676
1677 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1678 u8 bus, u8 devfn, int translation)
1679 {
1680 struct context_entry *context;
1681 unsigned long flags;
1682 struct intel_iommu *iommu;
1683 struct dma_pte *pgd;
1684 unsigned long num;
1685 unsigned long ndomains;
1686 int id;
1687 int agaw;
1688 struct device_domain_info *info = NULL;
1689
1690 pr_debug("Set context mapping for %02x:%02x.%d\n",
1691 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1692
1693 BUG_ON(!domain->pgd);
1694 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1695 translation != CONTEXT_TT_MULTI_LEVEL);
1696
1697 iommu = device_to_iommu(segment, bus, devfn);
1698 if (!iommu)
1699 return -ENODEV;
1700
1701 context = device_to_context_entry(iommu, bus, devfn);
1702 if (!context)
1703 return -ENOMEM;
1704 spin_lock_irqsave(&iommu->lock, flags);
1705 if (context_present(context)) {
1706 spin_unlock_irqrestore(&iommu->lock, flags);
1707 return 0;
1708 }
1709
1710 id = domain->id;
1711 pgd = domain->pgd;
1712
1713 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1714 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1715 int found = 0;
1716
1717 /* find an available domain id for this device in iommu */
1718 ndomains = cap_ndoms(iommu->cap);
1719 for_each_set_bit(num, iommu->domain_ids, ndomains) {
1720 if (iommu->domains[num] == domain) {
1721 id = num;
1722 found = 1;
1723 break;
1724 }
1725 }
1726
1727 if (found == 0) {
1728 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1729 if (num >= ndomains) {
1730 spin_unlock_irqrestore(&iommu->lock, flags);
1731 printk(KERN_ERR "IOMMU: no free domain ids\n");
1732 return -EFAULT;
1733 }
1734
1735 set_bit(num, iommu->domain_ids);
1736 iommu->domains[num] = domain;
1737 id = num;
1738 }
1739
1740 /* Skip top levels of page tables for
1741 * iommu which has less agaw than default.
1742 * Unnecessary for PT mode.
1743 */
1744 if (translation != CONTEXT_TT_PASS_THROUGH) {
1745 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1746 pgd = phys_to_virt(dma_pte_addr(pgd));
1747 if (!dma_pte_present(pgd)) {
1748 spin_unlock_irqrestore(&iommu->lock, flags);
1749 return -ENOMEM;
1750 }
1751 }
1752 }
1753 }
1754
1755 context_set_domain_id(context, id);
1756
1757 if (translation != CONTEXT_TT_PASS_THROUGH) {
1758 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1759 translation = info ? CONTEXT_TT_DEV_IOTLB :
1760 CONTEXT_TT_MULTI_LEVEL;
1761 }
1762 /*
1763 * In pass through mode, AW must be programmed to indicate the largest
1764 * AGAW value supported by hardware. And ASR is ignored by hardware.
1765 */
1766 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1767 context_set_address_width(context, iommu->msagaw);
1768 else {
1769 context_set_address_root(context, virt_to_phys(pgd));
1770 context_set_address_width(context, iommu->agaw);
1771 }
1772
1773 context_set_translation_type(context, translation);
1774 context_set_fault_enable(context);
1775 context_set_present(context);
1776 domain_flush_cache(domain, context, sizeof(*context));
1777
1778 /*
1779 * It's a non-present to present mapping. If hardware doesn't cache
1780 * non-present entry we only need to flush the write-buffer. If the
1781 * _does_ cache non-present entries, then it does so in the special
1782 * domain #0, which we have to flush:
1783 */
1784 if (cap_caching_mode(iommu->cap)) {
1785 iommu->flush.flush_context(iommu, 0,
1786 (((u16)bus) << 8) | devfn,
1787 DMA_CCMD_MASK_NOBIT,
1788 DMA_CCMD_DEVICE_INVL);
1789 iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH);
1790 } else {
1791 iommu_flush_write_buffer(iommu);
1792 }
1793 iommu_enable_dev_iotlb(info);
1794 spin_unlock_irqrestore(&iommu->lock, flags);
1795
1796 spin_lock_irqsave(&domain->iommu_lock, flags);
1797 if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) {
1798 domain->iommu_count++;
1799 if (domain->iommu_count == 1)
1800 domain->nid = iommu->node;
1801 domain_update_iommu_cap(domain);
1802 }
1803 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1804 return 0;
1805 }
1806
1807 static int
1808 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1809 int translation)
1810 {
1811 int ret;
1812 struct pci_dev *tmp, *parent;
1813
1814 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1815 pdev->bus->number, pdev->devfn,
1816 translation);
1817 if (ret)
1818 return ret;
1819
1820 /* dependent device mapping */
1821 tmp = pci_find_upstream_pcie_bridge(pdev);
1822 if (!tmp)
1823 return 0;
1824 /* Secondary interface's bus number and devfn 0 */
1825 parent = pdev->bus->self;
1826 while (parent != tmp) {
1827 ret = domain_context_mapping_one(domain,
1828 pci_domain_nr(parent->bus),
1829 parent->bus->number,
1830 parent->devfn, translation);
1831 if (ret)
1832 return ret;
1833 parent = parent->bus->self;
1834 }
1835 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
1836 return domain_context_mapping_one(domain,
1837 pci_domain_nr(tmp->subordinate),
1838 tmp->subordinate->number, 0,
1839 translation);
1840 else /* this is a legacy PCI bridge */
1841 return domain_context_mapping_one(domain,
1842 pci_domain_nr(tmp->bus),
1843 tmp->bus->number,
1844 tmp->devfn,
1845 translation);
1846 }
1847
1848 static int domain_context_mapped(struct pci_dev *pdev)
1849 {
1850 int ret;
1851 struct pci_dev *tmp, *parent;
1852 struct intel_iommu *iommu;
1853
1854 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1855 pdev->devfn);
1856 if (!iommu)
1857 return -ENODEV;
1858
1859 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1860 if (!ret)
1861 return ret;
1862 /* dependent device mapping */
1863 tmp = pci_find_upstream_pcie_bridge(pdev);
1864 if (!tmp)
1865 return ret;
1866 /* Secondary interface's bus number and devfn 0 */
1867 parent = pdev->bus->self;
1868 while (parent != tmp) {
1869 ret = device_context_mapped(iommu, parent->bus->number,
1870 parent->devfn);
1871 if (!ret)
1872 return ret;
1873 parent = parent->bus->self;
1874 }
1875 if (pci_is_pcie(tmp))
1876 return device_context_mapped(iommu, tmp->subordinate->number,
1877 0);
1878 else
1879 return device_context_mapped(iommu, tmp->bus->number,
1880 tmp->devfn);
1881 }
1882
1883 /* Returns a number of VTD pages, but aligned to MM page size */
1884 static inline unsigned long aligned_nrpages(unsigned long host_addr,
1885 size_t size)
1886 {
1887 host_addr &= ~PAGE_MASK;
1888 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1889 }
1890
1891 /* Return largest possible superpage level for a given mapping */
1892 static inline int hardware_largepage_caps(struct dmar_domain *domain,
1893 unsigned long iov_pfn,
1894 unsigned long phy_pfn,
1895 unsigned long pages)
1896 {
1897 int support, level = 1;
1898 unsigned long pfnmerge;
1899
1900 support = domain->iommu_superpage;
1901
1902 /* To use a large page, the virtual *and* physical addresses
1903 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
1904 of them will mean we have to use smaller pages. So just
1905 merge them and check both at once. */
1906 pfnmerge = iov_pfn | phy_pfn;
1907
1908 while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
1909 pages >>= VTD_STRIDE_SHIFT;
1910 if (!pages)
1911 break;
1912 pfnmerge >>= VTD_STRIDE_SHIFT;
1913 level++;
1914 support--;
1915 }
1916 return level;
1917 }
1918
1919 static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1920 struct scatterlist *sg, unsigned long phys_pfn,
1921 unsigned long nr_pages, int prot)
1922 {
1923 struct dma_pte *first_pte = NULL, *pte = NULL;
1924 phys_addr_t uninitialized_var(pteval);
1925 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1926 unsigned long sg_res;
1927 unsigned int largepage_lvl = 0;
1928 unsigned long lvl_pages = 0;
1929
1930 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1931
1932 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1933 return -EINVAL;
1934
1935 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1936
1937 if (sg)
1938 sg_res = 0;
1939 else {
1940 sg_res = nr_pages + 1;
1941 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1942 }
1943
1944 while (nr_pages > 0) {
1945 uint64_t tmp;
1946
1947 if (!sg_res) {
1948 sg_res = aligned_nrpages(sg->offset, sg->length);
1949 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1950 sg->dma_length = sg->length;
1951 pteval = page_to_phys(sg_page(sg)) | prot;
1952 phys_pfn = pteval >> VTD_PAGE_SHIFT;
1953 }
1954
1955 if (!pte) {
1956 largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
1957
1958 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl);
1959 if (!pte)
1960 return -ENOMEM;
1961 /* It is large page*/
1962 if (largepage_lvl > 1) {
1963 pteval |= DMA_PTE_LARGE_PAGE;
1964 /* Ensure that old small page tables are removed to make room
1965 for superpage, if they exist. */
1966 dma_pte_clear_range(domain, iov_pfn,
1967 iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
1968 dma_pte_free_pagetable(domain, iov_pfn,
1969 iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
1970 } else {
1971 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
1972 }
1973
1974 }
1975 /* We don't need lock here, nobody else
1976 * touches the iova range
1977 */
1978 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
1979 if (tmp) {
1980 static int dumps = 5;
1981 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1982 iov_pfn, tmp, (unsigned long long)pteval);
1983 if (dumps) {
1984 dumps--;
1985 debug_dma_dump_mappings(NULL);
1986 }
1987 WARN_ON(1);
1988 }
1989
1990 lvl_pages = lvl_to_nr_pages(largepage_lvl);
1991
1992 BUG_ON(nr_pages < lvl_pages);
1993 BUG_ON(sg_res < lvl_pages);
1994
1995 nr_pages -= lvl_pages;
1996 iov_pfn += lvl_pages;
1997 phys_pfn += lvl_pages;
1998 pteval += lvl_pages * VTD_PAGE_SIZE;
1999 sg_res -= lvl_pages;
2000
2001 /* If the next PTE would be the first in a new page, then we
2002 need to flush the cache on the entries we've just written.
2003 And then we'll need to recalculate 'pte', so clear it and
2004 let it get set again in the if (!pte) block above.
2005
2006 If we're done (!nr_pages) we need to flush the cache too.
2007
2008 Also if we've been setting superpages, we may need to
2009 recalculate 'pte' and switch back to smaller pages for the
2010 end of the mapping, if the trailing size is not enough to
2011 use another superpage (i.e. sg_res < lvl_pages). */
2012 pte++;
2013 if (!nr_pages || first_pte_in_page(pte) ||
2014 (largepage_lvl > 1 && sg_res < lvl_pages)) {
2015 domain_flush_cache(domain, first_pte,
2016 (void *)pte - (void *)first_pte);
2017 pte = NULL;
2018 }
2019
2020 if (!sg_res && nr_pages)
2021 sg = sg_next(sg);
2022 }
2023 return 0;
2024 }
2025
2026 static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2027 struct scatterlist *sg, unsigned long nr_pages,
2028 int prot)
2029 {
2030 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
2031 }
2032
2033 static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2034 unsigned long phys_pfn, unsigned long nr_pages,
2035 int prot)
2036 {
2037 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
2038 }
2039
2040 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
2041 {
2042 if (!iommu)
2043 return;
2044
2045 clear_context_table(iommu, bus, devfn);
2046 iommu->flush.flush_context(iommu, 0, 0, 0,
2047 DMA_CCMD_GLOBAL_INVL);
2048 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2049 }
2050
2051 static inline void unlink_domain_info(struct device_domain_info *info)
2052 {
2053 assert_spin_locked(&device_domain_lock);
2054 list_del(&info->link);
2055 list_del(&info->global);
2056 if (info->dev)
2057 info->dev->dev.archdata.iommu = NULL;
2058 }
2059
2060 static void domain_remove_dev_info(struct dmar_domain *domain)
2061 {
2062 struct device_domain_info *info;
2063 unsigned long flags, flags2;
2064 struct intel_iommu *iommu;
2065
2066 spin_lock_irqsave(&device_domain_lock, flags);
2067 while (!list_empty(&domain->devices)) {
2068 info = list_entry(domain->devices.next,
2069 struct device_domain_info, link);
2070 unlink_domain_info(info);
2071 spin_unlock_irqrestore(&device_domain_lock, flags);
2072
2073 iommu_disable_dev_iotlb(info);
2074 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
2075 iommu_detach_dev(iommu, info->bus, info->devfn);
2076
2077 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) {
2078 iommu_detach_dependent_devices(iommu, info->dev);
2079 /* clear this iommu in iommu_bmp, update iommu count
2080 * and capabilities
2081 */
2082 spin_lock_irqsave(&domain->iommu_lock, flags2);
2083 if (test_and_clear_bit(iommu->seq_id,
2084 domain->iommu_bmp)) {
2085 domain->iommu_count--;
2086 domain_update_iommu_cap(domain);
2087 }
2088 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
2089 }
2090
2091 free_devinfo_mem(info);
2092 spin_lock_irqsave(&device_domain_lock, flags);
2093 }
2094 spin_unlock_irqrestore(&device_domain_lock, flags);
2095 }
2096
2097 /*
2098 * find_domain
2099 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
2100 */
2101 static struct dmar_domain *
2102 find_domain(struct pci_dev *pdev)
2103 {
2104 struct device_domain_info *info;
2105
2106 /* No lock here, assumes no domain exit in normal case */
2107 info = pdev->dev.archdata.iommu;
2108 if (info)
2109 return info->domain;
2110 return NULL;
2111 }
2112
2113 static inline struct dmar_domain *
2114 dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
2115 {
2116 struct device_domain_info *info;
2117
2118 list_for_each_entry(info, &device_domain_list, global)
2119 if (info->segment == segment && info->bus == bus &&
2120 info->devfn == devfn)
2121 return info->domain;
2122
2123 return NULL;
2124 }
2125
2126 static int dmar_insert_dev_info(int segment, int bus, int devfn,
2127 struct pci_dev *dev, struct dmar_domain **domp)
2128 {
2129 struct dmar_domain *found, *domain = *domp;
2130 struct device_domain_info *info;
2131 unsigned long flags;
2132
2133 info = alloc_devinfo_mem();
2134 if (!info)
2135 return -ENOMEM;
2136
2137 info->segment = segment;
2138 info->bus = bus;
2139 info->devfn = devfn;
2140 info->dev = dev;
2141 info->domain = domain;
2142 if (!dev)
2143 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
2144
2145 spin_lock_irqsave(&device_domain_lock, flags);
2146 if (dev)
2147 found = find_domain(dev);
2148 else
2149 found = dmar_search_domain_by_dev_info(segment, bus, devfn);
2150 if (found) {
2151 spin_unlock_irqrestore(&device_domain_lock, flags);
2152 free_devinfo_mem(info);
2153 if (found != domain) {
2154 domain_exit(domain);
2155 *domp = found;
2156 }
2157 } else {
2158 list_add(&info->link, &domain->devices);
2159 list_add(&info->global, &device_domain_list);
2160 if (dev)
2161 dev->dev.archdata.iommu = info;
2162 spin_unlock_irqrestore(&device_domain_lock, flags);
2163 }
2164
2165 return 0;
2166 }
2167
2168 /* domain is initialized */
2169 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
2170 {
2171 struct dmar_domain *domain, *free = NULL;
2172 struct intel_iommu *iommu;
2173 struct dmar_drhd_unit *drhd;
2174 struct pci_dev *dev_tmp;
2175 unsigned long flags;
2176 int bus = 0, devfn = 0;
2177 int segment;
2178
2179 domain = find_domain(pdev);
2180 if (domain)
2181 return domain;
2182
2183 segment = pci_domain_nr(pdev->bus);
2184
2185 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
2186 if (dev_tmp) {
2187 if (pci_is_pcie(dev_tmp)) {
2188 bus = dev_tmp->subordinate->number;
2189 devfn = 0;
2190 } else {
2191 bus = dev_tmp->bus->number;
2192 devfn = dev_tmp->devfn;
2193 }
2194 spin_lock_irqsave(&device_domain_lock, flags);
2195 domain = dmar_search_domain_by_dev_info(segment, bus, devfn);
2196 spin_unlock_irqrestore(&device_domain_lock, flags);
2197 /* pcie-pci bridge already has a domain, uses it */
2198 if (domain)
2199 goto found_domain;
2200 }
2201
2202 drhd = dmar_find_matched_drhd_unit(pdev);
2203 if (!drhd) {
2204 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
2205 pci_name(pdev));
2206 return NULL;
2207 }
2208 iommu = drhd->iommu;
2209
2210 /* Allocate and intialize new domain for the device */
2211 domain = alloc_domain(false);
2212 if (!domain)
2213 goto error;
2214 if (iommu_attach_domain(domain, iommu)) {
2215 free_domain_mem(domain);
2216 goto error;
2217 }
2218 free = domain;
2219 if (domain_init(domain, gaw))
2220 goto error;
2221
2222 /* register pcie-to-pci device */
2223 if (dev_tmp) {
2224 if (dmar_insert_dev_info(segment, bus, devfn, NULL, &domain))
2225 goto error;
2226 else
2227 free = NULL;
2228 }
2229
2230 found_domain:
2231 if (dmar_insert_dev_info(segment, pdev->bus->number, pdev->devfn,
2232 pdev, &domain) == 0)
2233 return domain;
2234 error:
2235 if (free)
2236 domain_exit(free);
2237 /* recheck it here, maybe others set it */
2238 return find_domain(pdev);
2239 }
2240
2241 static int iommu_identity_mapping;
2242 #define IDENTMAP_ALL 1
2243 #define IDENTMAP_GFX 2
2244 #define IDENTMAP_AZALIA 4
2245
2246 static int iommu_domain_identity_map(struct dmar_domain *domain,
2247 unsigned long long start,
2248 unsigned long long end)
2249 {
2250 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
2251 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
2252
2253 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
2254 dma_to_mm_pfn(last_vpfn))) {
2255 printk(KERN_ERR "IOMMU: reserve iova failed\n");
2256 return -ENOMEM;
2257 }
2258
2259 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
2260 start, end, domain->id);
2261 /*
2262 * RMRR range might have overlap with physical memory range,
2263 * clear it first
2264 */
2265 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
2266
2267 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
2268 last_vpfn - first_vpfn + 1,
2269 DMA_PTE_READ|DMA_PTE_WRITE);
2270 }
2271
2272 static int iommu_prepare_identity_map(struct pci_dev *pdev,
2273 unsigned long long start,
2274 unsigned long long end)
2275 {
2276 struct dmar_domain *domain;
2277 int ret;
2278
2279 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2280 if (!domain)
2281 return -ENOMEM;
2282
2283 /* For _hardware_ passthrough, don't bother. But for software
2284 passthrough, we do it anyway -- it may indicate a memory
2285 range which is reserved in E820, so which didn't get set
2286 up to start with in si_domain */
2287 if (domain == si_domain && hw_pass_through) {
2288 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
2289 pci_name(pdev), start, end);
2290 return 0;
2291 }
2292
2293 printk(KERN_INFO
2294 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
2295 pci_name(pdev), start, end);
2296
2297 if (end < start) {
2298 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2299 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2300 dmi_get_system_info(DMI_BIOS_VENDOR),
2301 dmi_get_system_info(DMI_BIOS_VERSION),
2302 dmi_get_system_info(DMI_PRODUCT_VERSION));
2303 ret = -EIO;
2304 goto error;
2305 }
2306
2307 if (end >> agaw_to_width(domain->agaw)) {
2308 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2309 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2310 agaw_to_width(domain->agaw),
2311 dmi_get_system_info(DMI_BIOS_VENDOR),
2312 dmi_get_system_info(DMI_BIOS_VERSION),
2313 dmi_get_system_info(DMI_PRODUCT_VERSION));
2314 ret = -EIO;
2315 goto error;
2316 }
2317
2318 ret = iommu_domain_identity_map(domain, start, end);
2319 if (ret)
2320 goto error;
2321
2322 /* context entry init */
2323 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
2324 if (ret)
2325 goto error;
2326
2327 return 0;
2328
2329 error:
2330 domain_exit(domain);
2331 return ret;
2332 }
2333
2334 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2335 struct pci_dev *pdev)
2336 {
2337 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2338 return 0;
2339 return iommu_prepare_identity_map(pdev, rmrr->base_address,
2340 rmrr->end_address);
2341 }
2342
2343 #ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
2344 static inline void iommu_prepare_isa(void)
2345 {
2346 struct pci_dev *pdev;
2347 int ret;
2348
2349 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2350 if (!pdev)
2351 return;
2352
2353 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
2354 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024 - 1);
2355
2356 if (ret)
2357 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2358 "floppy might not work\n");
2359
2360 }
2361 #else
2362 static inline void iommu_prepare_isa(void)
2363 {
2364 return;
2365 }
2366 #endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
2367
2368 static int md_domain_init(struct dmar_domain *domain, int guest_width);
2369
2370 static int __init si_domain_init(int hw)
2371 {
2372 struct dmar_drhd_unit *drhd;
2373 struct intel_iommu *iommu;
2374 int nid, ret = 0;
2375
2376 si_domain = alloc_domain(false);
2377 if (!si_domain)
2378 return -EFAULT;
2379
2380 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2381
2382 for_each_active_iommu(iommu, drhd) {
2383 ret = iommu_attach_domain(si_domain, iommu);
2384 if (ret) {
2385 domain_exit(si_domain);
2386 return -EFAULT;
2387 }
2388 }
2389
2390 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2391 domain_exit(si_domain);
2392 return -EFAULT;
2393 }
2394
2395 pr_debug("IOMMU: identity mapping domain is domain %d\n",
2396 si_domain->id);
2397
2398 if (hw)
2399 return 0;
2400
2401 for_each_online_node(nid) {
2402 unsigned long start_pfn, end_pfn;
2403 int i;
2404
2405 for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
2406 ret = iommu_domain_identity_map(si_domain,
2407 PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
2408 if (ret)
2409 return ret;
2410 }
2411 }
2412
2413 return 0;
2414 }
2415
2416 static int identity_mapping(struct pci_dev *pdev)
2417 {
2418 struct device_domain_info *info;
2419
2420 if (likely(!iommu_identity_mapping))
2421 return 0;
2422
2423 info = pdev->dev.archdata.iommu;
2424 if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2425 return (info->domain == si_domain);
2426
2427 return 0;
2428 }
2429
2430 static int domain_add_dev_info(struct dmar_domain *domain,
2431 struct pci_dev *pdev,
2432 int translation)
2433 {
2434 struct device_domain_info *info;
2435 unsigned long flags;
2436 int ret;
2437
2438 info = alloc_devinfo_mem();
2439 if (!info)
2440 return -ENOMEM;
2441
2442 info->segment = pci_domain_nr(pdev->bus);
2443 info->bus = pdev->bus->number;
2444 info->devfn = pdev->devfn;
2445 info->dev = pdev;
2446 info->domain = domain;
2447
2448 spin_lock_irqsave(&device_domain_lock, flags);
2449 list_add(&info->link, &domain->devices);
2450 list_add(&info->global, &device_domain_list);
2451 pdev->dev.archdata.iommu = info;
2452 spin_unlock_irqrestore(&device_domain_lock, flags);
2453
2454 ret = domain_context_mapping(domain, pdev, translation);
2455 if (ret) {
2456 spin_lock_irqsave(&device_domain_lock, flags);
2457 unlink_domain_info(info);
2458 spin_unlock_irqrestore(&device_domain_lock, flags);
2459 free_devinfo_mem(info);
2460 return ret;
2461 }
2462
2463 return 0;
2464 }
2465
2466 static bool device_has_rmrr(struct pci_dev *dev)
2467 {
2468 struct dmar_rmrr_unit *rmrr;
2469 struct pci_dev *tmp;
2470 int i;
2471
2472 rcu_read_lock();
2473 for_each_rmrr_units(rmrr) {
2474 /*
2475 * Return TRUE if this RMRR contains the device that
2476 * is passed in.
2477 */
2478 for_each_active_dev_scope(rmrr->devices,
2479 rmrr->devices_cnt, i, tmp)
2480 if (tmp == dev) {
2481 rcu_read_unlock();
2482 return true;
2483 }
2484 }
2485 rcu_read_unlock();
2486 return false;
2487 }
2488
2489 static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2490 {
2491
2492 /*
2493 * We want to prevent any device associated with an RMRR from
2494 * getting placed into the SI Domain. This is done because
2495 * problems exist when devices are moved in and out of domains
2496 * and their respective RMRR info is lost. We exempt USB devices
2497 * from this process due to their usage of RMRRs that are known
2498 * to not be needed after BIOS hand-off to OS.
2499 */
2500 if (device_has_rmrr(pdev) &&
2501 (pdev->class >> 8) != PCI_CLASS_SERIAL_USB)
2502 return 0;
2503
2504 if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
2505 return 1;
2506
2507 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
2508 return 1;
2509
2510 if (!(iommu_identity_mapping & IDENTMAP_ALL))
2511 return 0;
2512
2513 /*
2514 * We want to start off with all devices in the 1:1 domain, and
2515 * take them out later if we find they can't access all of memory.
2516 *
2517 * However, we can't do this for PCI devices behind bridges,
2518 * because all PCI devices behind the same bridge will end up
2519 * with the same source-id on their transactions.
2520 *
2521 * Practically speaking, we can't change things around for these
2522 * devices at run-time, because we can't be sure there'll be no
2523 * DMA transactions in flight for any of their siblings.
2524 *
2525 * So PCI devices (unless they're on the root bus) as well as
2526 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2527 * the 1:1 domain, just in _case_ one of their siblings turns out
2528 * not to be able to map all of memory.
2529 */
2530 if (!pci_is_pcie(pdev)) {
2531 if (!pci_is_root_bus(pdev->bus))
2532 return 0;
2533 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2534 return 0;
2535 } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
2536 return 0;
2537
2538 /*
2539 * At boot time, we don't yet know if devices will be 64-bit capable.
2540 * Assume that they will -- if they turn out not to be, then we can
2541 * take them out of the 1:1 domain later.
2542 */
2543 if (!startup) {
2544 /*
2545 * If the device's dma_mask is less than the system's memory
2546 * size then this is not a candidate for identity mapping.
2547 */
2548 u64 dma_mask = pdev->dma_mask;
2549
2550 if (pdev->dev.coherent_dma_mask &&
2551 pdev->dev.coherent_dma_mask < dma_mask)
2552 dma_mask = pdev->dev.coherent_dma_mask;
2553
2554 return dma_mask >= dma_get_required_mask(&pdev->dev);
2555 }
2556
2557 return 1;
2558 }
2559
2560 static int __init iommu_prepare_static_identity_mapping(int hw)
2561 {
2562 struct pci_dev *pdev = NULL;
2563 int ret;
2564
2565 ret = si_domain_init(hw);
2566 if (ret)
2567 return -EFAULT;
2568
2569 for_each_pci_dev(pdev) {
2570 if (iommu_should_identity_map(pdev, 1)) {
2571 ret = domain_add_dev_info(si_domain, pdev,
2572 hw ? CONTEXT_TT_PASS_THROUGH :
2573 CONTEXT_TT_MULTI_LEVEL);
2574 if (ret) {
2575 /* device not associated with an iommu */
2576 if (ret == -ENODEV)
2577 continue;
2578 return ret;
2579 }
2580 pr_info("IOMMU: %s identity mapping for device %s\n",
2581 hw ? "hardware" : "software", pci_name(pdev));
2582 }
2583 }
2584
2585 return 0;
2586 }
2587
2588 static int __init init_dmars(void)
2589 {
2590 struct dmar_drhd_unit *drhd;
2591 struct dmar_rmrr_unit *rmrr;
2592 struct pci_dev *pdev;
2593 struct intel_iommu *iommu;
2594 int i, ret;
2595
2596 /*
2597 * for each drhd
2598 * allocate root
2599 * initialize and program root entry to not present
2600 * endfor
2601 */
2602 for_each_drhd_unit(drhd) {
2603 /*
2604 * lock not needed as this is only incremented in the single
2605 * threaded kernel __init code path all other access are read
2606 * only
2607 */
2608 if (g_num_of_iommus < IOMMU_UNITS_SUPPORTED) {
2609 g_num_of_iommus++;
2610 continue;
2611 }
2612 printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n",
2613 IOMMU_UNITS_SUPPORTED);
2614 }
2615
2616 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2617 GFP_KERNEL);
2618 if (!g_iommus) {
2619 printk(KERN_ERR "Allocating global iommu array failed\n");
2620 ret = -ENOMEM;
2621 goto error;
2622 }
2623
2624 deferred_flush = kzalloc(g_num_of_iommus *
2625 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2626 if (!deferred_flush) {
2627 ret = -ENOMEM;
2628 goto free_g_iommus;
2629 }
2630
2631 for_each_active_iommu(iommu, drhd) {
2632 g_iommus[iommu->seq_id] = iommu;
2633
2634 ret = iommu_init_domains(iommu);
2635 if (ret)
2636 goto free_iommu;
2637
2638 /*
2639 * TBD:
2640 * we could share the same root & context tables
2641 * among all IOMMU's. Need to Split it later.
2642 */
2643 ret = iommu_alloc_root_entry(iommu);
2644 if (ret) {
2645 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2646 goto free_iommu;
2647 }
2648 if (!ecap_pass_through(iommu->ecap))
2649 hw_pass_through = 0;
2650 }
2651
2652 /*
2653 * Start from the sane iommu hardware state.
2654 */
2655 for_each_active_iommu(iommu, drhd) {
2656 /*
2657 * If the queued invalidation is already initialized by us
2658 * (for example, while enabling interrupt-remapping) then
2659 * we got the things already rolling from a sane state.
2660 */
2661 if (iommu->qi)
2662 continue;
2663
2664 /*
2665 * Clear any previous faults.
2666 */
2667 dmar_fault(-1, iommu);
2668 /*
2669 * Disable queued invalidation if supported and already enabled
2670 * before OS handover.
2671 */
2672 dmar_disable_qi(iommu);
2673 }
2674
2675 for_each_active_iommu(iommu, drhd) {
2676 if (dmar_enable_qi(iommu)) {
2677 /*
2678 * Queued Invalidate not enabled, use Register Based
2679 * Invalidate
2680 */
2681 iommu->flush.flush_context = __iommu_flush_context;
2682 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2683 printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
2684 "invalidation\n",
2685 iommu->seq_id,
2686 (unsigned long long)drhd->reg_base_addr);
2687 } else {
2688 iommu->flush.flush_context = qi_flush_context;
2689 iommu->flush.flush_iotlb = qi_flush_iotlb;
2690 printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
2691 "invalidation\n",
2692 iommu->seq_id,
2693 (unsigned long long)drhd->reg_base_addr);
2694 }
2695 }
2696
2697 if (iommu_pass_through)
2698 iommu_identity_mapping |= IDENTMAP_ALL;
2699
2700 #ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
2701 iommu_identity_mapping |= IDENTMAP_GFX;
2702 #endif
2703
2704 check_tylersburg_isoch();
2705
2706 /*
2707 * If pass through is not set or not enabled, setup context entries for
2708 * identity mappings for rmrr, gfx, and isa and may fall back to static
2709 * identity mapping if iommu_identity_mapping is set.
2710 */
2711 if (iommu_identity_mapping) {
2712 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
2713 if (ret) {
2714 printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
2715 goto free_iommu;
2716 }
2717 }
2718 /*
2719 * For each rmrr
2720 * for each dev attached to rmrr
2721 * do
2722 * locate drhd for dev, alloc domain for dev
2723 * allocate free domain
2724 * allocate page table entries for rmrr
2725 * if context not allocated for bus
2726 * allocate and init context
2727 * set present in root table for this bus
2728 * init context with domain, translation etc
2729 * endfor
2730 * endfor
2731 */
2732 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2733 for_each_rmrr_units(rmrr) {
2734 /* some BIOS lists non-exist devices in DMAR table. */
2735 for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
2736 i, pdev) {
2737 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2738 if (ret)
2739 printk(KERN_ERR
2740 "IOMMU: mapping reserved region failed\n");
2741 }
2742 }
2743
2744 iommu_prepare_isa();
2745
2746 /*
2747 * for each drhd
2748 * enable fault log
2749 * global invalidate context cache
2750 * global invalidate iotlb
2751 * enable translation
2752 */
2753 for_each_iommu(iommu, drhd) {
2754 if (drhd->ignored) {
2755 /*
2756 * we always have to disable PMRs or DMA may fail on
2757 * this device
2758 */
2759 if (force_on)
2760 iommu_disable_protect_mem_regions(iommu);
2761 continue;
2762 }
2763
2764 iommu_flush_write_buffer(iommu);
2765
2766 ret = dmar_set_interrupt(iommu);
2767 if (ret)
2768 goto free_iommu;
2769
2770 iommu_set_root_entry(iommu);
2771
2772 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2773 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2774
2775 ret = iommu_enable_translation(iommu);
2776 if (ret)
2777 goto free_iommu;
2778
2779 iommu_disable_protect_mem_regions(iommu);
2780 }
2781
2782 return 0;
2783
2784 free_iommu:
2785 for_each_active_iommu(iommu, drhd)
2786 free_dmar_iommu(iommu);
2787 kfree(deferred_flush);
2788 free_g_iommus:
2789 kfree(g_iommus);
2790 error:
2791 return ret;
2792 }
2793
2794 /* This takes a number of _MM_ pages, not VTD pages */
2795 static struct iova *intel_alloc_iova(struct device *dev,
2796 struct dmar_domain *domain,
2797 unsigned long nrpages, uint64_t dma_mask)
2798 {
2799 struct pci_dev *pdev = to_pci_dev(dev);
2800 struct iova *iova = NULL;
2801
2802 /* Restrict dma_mask to the width that the iommu can handle */
2803 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2804
2805 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2806 /*
2807 * First try to allocate an io virtual address in
2808 * DMA_BIT_MASK(32) and if that fails then try allocating
2809 * from higher range
2810 */
2811 iova = alloc_iova(&domain->iovad, nrpages,
2812 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2813 if (iova)
2814 return iova;
2815 }
2816 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2817 if (unlikely(!iova)) {
2818 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2819 nrpages, pci_name(pdev));
2820 return NULL;
2821 }
2822
2823 return iova;
2824 }
2825
2826 static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
2827 {
2828 struct dmar_domain *domain;
2829 int ret;
2830
2831 domain = get_domain_for_dev(pdev,
2832 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2833 if (!domain) {
2834 printk(KERN_ERR
2835 "Allocating domain for %s failed", pci_name(pdev));
2836 return NULL;
2837 }
2838
2839 /* make sure context mapping is ok */
2840 if (unlikely(!domain_context_mapped(pdev))) {
2841 ret = domain_context_mapping(domain, pdev,
2842 CONTEXT_TT_MULTI_LEVEL);
2843 if (ret) {
2844 printk(KERN_ERR
2845 "Domain context map for %s failed",
2846 pci_name(pdev));
2847 return NULL;
2848 }
2849 }
2850
2851 return domain;
2852 }
2853
2854 static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2855 {
2856 struct device_domain_info *info;
2857
2858 /* No lock here, assumes no domain exit in normal case */
2859 info = dev->dev.archdata.iommu;
2860 if (likely(info))
2861 return info->domain;
2862
2863 return __get_valid_domain_for_dev(dev);
2864 }
2865
2866 static int iommu_dummy(struct pci_dev *pdev)
2867 {
2868 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2869 }
2870
2871 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2872 static int iommu_no_mapping(struct device *dev)
2873 {
2874 struct pci_dev *pdev;
2875 int found;
2876
2877 if (unlikely(!dev_is_pci(dev)))
2878 return 1;
2879
2880 pdev = to_pci_dev(dev);
2881 if (iommu_dummy(pdev))
2882 return 1;
2883
2884 if (!iommu_identity_mapping)
2885 return 0;
2886
2887 found = identity_mapping(pdev);
2888 if (found) {
2889 if (iommu_should_identity_map(pdev, 0))
2890 return 1;
2891 else {
2892 /*
2893 * 32 bit DMA is removed from si_domain and fall back
2894 * to non-identity mapping.
2895 */
2896 domain_remove_one_dev_info(si_domain, pdev);
2897 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2898 pci_name(pdev));
2899 return 0;
2900 }
2901 } else {
2902 /*
2903 * In case of a detached 64 bit DMA device from vm, the device
2904 * is put into si_domain for identity mapping.
2905 */
2906 if (iommu_should_identity_map(pdev, 0)) {
2907 int ret;
2908 ret = domain_add_dev_info(si_domain, pdev,
2909 hw_pass_through ?
2910 CONTEXT_TT_PASS_THROUGH :
2911 CONTEXT_TT_MULTI_LEVEL);
2912 if (!ret) {
2913 printk(KERN_INFO "64bit %s uses identity mapping\n",
2914 pci_name(pdev));
2915 return 1;
2916 }
2917 }
2918 }
2919
2920 return 0;
2921 }
2922
2923 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2924 size_t size, int dir, u64 dma_mask)
2925 {
2926 struct pci_dev *pdev = to_pci_dev(hwdev);
2927 struct dmar_domain *domain;
2928 phys_addr_t start_paddr;
2929 struct iova *iova;
2930 int prot = 0;
2931 int ret;
2932 struct intel_iommu *iommu;
2933 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
2934
2935 BUG_ON(dir == DMA_NONE);
2936
2937 if (iommu_no_mapping(hwdev))
2938 return paddr;
2939
2940 domain = get_valid_domain_for_dev(pdev);
2941 if (!domain)
2942 return 0;
2943
2944 iommu = domain_get_iommu(domain);
2945 size = aligned_nrpages(paddr, size);
2946
2947 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), dma_mask);
2948 if (!iova)
2949 goto error;
2950
2951 /*
2952 * Check if DMAR supports zero-length reads on write only
2953 * mappings..
2954 */
2955 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2956 !cap_zlr(iommu->cap))
2957 prot |= DMA_PTE_READ;
2958 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2959 prot |= DMA_PTE_WRITE;
2960 /*
2961 * paddr - (paddr + size) might be partial page, we should map the whole
2962 * page. Note: if two part of one page are separately mapped, we
2963 * might have two guest_addr mapping to the same host paddr, but this
2964 * is not a big problem
2965 */
2966 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2967 mm_to_dma_pfn(paddr_pfn), size, prot);
2968 if (ret)
2969 goto error;
2970
2971 /* it's a non-present to present mapping. Only flush if caching mode */
2972 if (cap_caching_mode(iommu->cap))
2973 iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1);
2974 else
2975 iommu_flush_write_buffer(iommu);
2976
2977 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2978 start_paddr += paddr & ~PAGE_MASK;
2979 return start_paddr;
2980
2981 error:
2982 if (iova)
2983 __free_iova(&domain->iovad, iova);
2984 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2985 pci_name(pdev), size, (unsigned long long)paddr, dir);
2986 return 0;
2987 }
2988
2989 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2990 unsigned long offset, size_t size,
2991 enum dma_data_direction dir,
2992 struct dma_attrs *attrs)
2993 {
2994 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2995 dir, to_pci_dev(dev)->dma_mask);
2996 }
2997
2998 static void flush_unmaps(void)
2999 {
3000 int i, j;
3001
3002 timer_on = 0;
3003
3004 /* just flush them all */
3005 for (i = 0; i < g_num_of_iommus; i++) {
3006 struct intel_iommu *iommu = g_iommus[i];
3007 if (!iommu)
3008 continue;
3009
3010 if (!deferred_flush[i].next)
3011 continue;
3012
3013 /* In caching mode, global flushes turn emulation expensive */
3014 if (!cap_caching_mode(iommu->cap))
3015 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3016 DMA_TLB_GLOBAL_FLUSH);
3017 for (j = 0; j < deferred_flush[i].next; j++) {
3018 unsigned long mask;
3019 struct iova *iova = deferred_flush[i].iova[j];
3020 struct dmar_domain *domain = deferred_flush[i].domain[j];
3021
3022 /* On real hardware multiple invalidations are expensive */
3023 if (cap_caching_mode(iommu->cap))
3024 iommu_flush_iotlb_psi(iommu, domain->id,
3025 iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1,
3026 !deferred_flush[i].freelist[j], 0);
3027 else {
3028 mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
3029 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
3030 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
3031 }
3032 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
3033 if (deferred_flush[i].freelist[j])
3034 dma_free_pagelist(deferred_flush[i].freelist[j]);
3035 }
3036 deferred_flush[i].next = 0;
3037 }
3038
3039 list_size = 0;
3040 }
3041
3042 static void flush_unmaps_timeout(unsigned long data)
3043 {
3044 unsigned long flags;
3045
3046 spin_lock_irqsave(&async_umap_flush_lock, flags);
3047 flush_unmaps();
3048 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
3049 }
3050
3051 static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist)
3052 {
3053 unsigned long flags;
3054 int next, iommu_id;
3055 struct intel_iommu *iommu;
3056
3057 spin_lock_irqsave(&async_umap_flush_lock, flags);
3058 if (list_size == HIGH_WATER_MARK)
3059 flush_unmaps();
3060
3061 iommu = domain_get_iommu(dom);
3062 iommu_id = iommu->seq_id;
3063
3064 next = deferred_flush[iommu_id].next;
3065 deferred_flush[iommu_id].domain[next] = dom;
3066 deferred_flush[iommu_id].iova[next] = iova;
3067 deferred_flush[iommu_id].freelist[next] = freelist;
3068 deferred_flush[iommu_id].next++;
3069
3070 if (!timer_on) {
3071 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
3072 timer_on = 1;
3073 }
3074 list_size++;
3075 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
3076 }
3077
3078 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
3079 size_t size, enum dma_data_direction dir,
3080 struct dma_attrs *attrs)
3081 {
3082 struct pci_dev *pdev = to_pci_dev(dev);
3083 struct dmar_domain *domain;
3084 unsigned long start_pfn, last_pfn;
3085 struct iova *iova;
3086 struct intel_iommu *iommu;
3087 struct page *freelist;
3088
3089 if (iommu_no_mapping(dev))
3090 return;
3091
3092 domain = find_domain(pdev);
3093 BUG_ON(!domain);
3094
3095 iommu = domain_get_iommu(domain);
3096
3097 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
3098 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
3099 (unsigned long long)dev_addr))
3100 return;
3101
3102 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3103 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
3104
3105 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
3106 pci_name(pdev), start_pfn, last_pfn);
3107
3108 freelist = domain_unmap(domain, start_pfn, last_pfn);
3109
3110 if (intel_iommu_strict) {
3111 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
3112 last_pfn - start_pfn + 1, !freelist, 0);
3113 /* free iova */
3114 __free_iova(&domain->iovad, iova);
3115 dma_free_pagelist(freelist);
3116 } else {
3117 add_unmap(domain, iova, freelist);
3118 /*
3119 * queue up the release of the unmap to save the 1/6th of the
3120 * cpu used up by the iotlb flush operation...
3121 */
3122 }
3123 }
3124
3125 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
3126 dma_addr_t *dma_handle, gfp_t flags,
3127 struct dma_attrs *attrs)
3128 {
3129 void *vaddr;
3130 int order;
3131
3132 size = PAGE_ALIGN(size);
3133 order = get_order(size);
3134
3135 if (!iommu_no_mapping(hwdev))
3136 flags &= ~(GFP_DMA | GFP_DMA32);
3137 else if (hwdev->coherent_dma_mask < dma_get_required_mask(hwdev)) {
3138 if (hwdev->coherent_dma_mask < DMA_BIT_MASK(32))
3139 flags |= GFP_DMA;
3140 else
3141 flags |= GFP_DMA32;
3142 }
3143
3144 vaddr = (void *)__get_free_pages(flags, order);
3145 if (!vaddr)
3146 return NULL;
3147 memset(vaddr, 0, size);
3148
3149 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
3150 DMA_BIDIRECTIONAL,
3151 hwdev->coherent_dma_mask);
3152 if (*dma_handle)
3153 return vaddr;
3154 free_pages((unsigned long)vaddr, order);
3155 return NULL;
3156 }
3157
3158 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
3159 dma_addr_t dma_handle, struct dma_attrs *attrs)
3160 {
3161 int order;
3162
3163 size = PAGE_ALIGN(size);
3164 order = get_order(size);
3165
3166 intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
3167 free_pages((unsigned long)vaddr, order);
3168 }
3169
3170 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
3171 int nelems, enum dma_data_direction dir,
3172 struct dma_attrs *attrs)
3173 {
3174 struct pci_dev *pdev = to_pci_dev(hwdev);
3175 struct dmar_domain *domain;
3176 unsigned long start_pfn, last_pfn;
3177 struct iova *iova;
3178 struct intel_iommu *iommu;
3179 struct page *freelist;
3180
3181 if (iommu_no_mapping(hwdev))
3182 return;
3183
3184 domain = find_domain(pdev);
3185 BUG_ON(!domain);
3186
3187 iommu = domain_get_iommu(domain);
3188
3189 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
3190 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
3191 (unsigned long long)sglist[0].dma_address))
3192 return;
3193
3194 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3195 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
3196
3197 freelist = domain_unmap(domain, start_pfn, last_pfn);
3198
3199 if (intel_iommu_strict) {
3200 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
3201 last_pfn - start_pfn + 1, !freelist, 0);
3202 /* free iova */
3203 __free_iova(&domain->iovad, iova);
3204 dma_free_pagelist(freelist);
3205 } else {
3206 add_unmap(domain, iova, freelist);
3207 /*
3208 * queue up the release of the unmap to save the 1/6th of the
3209 * cpu used up by the iotlb flush operation...
3210 */
3211 }
3212 }
3213
3214 static int intel_nontranslate_map_sg(struct device *hddev,
3215 struct scatterlist *sglist, int nelems, int dir)
3216 {
3217 int i;
3218 struct scatterlist *sg;
3219
3220 for_each_sg(sglist, sg, nelems, i) {
3221 BUG_ON(!sg_page(sg));
3222 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
3223 sg->dma_length = sg->length;
3224 }
3225 return nelems;
3226 }
3227
3228 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
3229 enum dma_data_direction dir, struct dma_attrs *attrs)
3230 {
3231 int i;
3232 struct pci_dev *pdev = to_pci_dev(hwdev);
3233 struct dmar_domain *domain;
3234 size_t size = 0;
3235 int prot = 0;
3236 struct iova *iova = NULL;
3237 int ret;
3238 struct scatterlist *sg;
3239 unsigned long start_vpfn;
3240 struct intel_iommu *iommu;
3241
3242 BUG_ON(dir == DMA_NONE);
3243 if (iommu_no_mapping(hwdev))
3244 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
3245
3246 domain = get_valid_domain_for_dev(pdev);
3247 if (!domain)
3248 return 0;
3249
3250 iommu = domain_get_iommu(domain);
3251
3252 for_each_sg(sglist, sg, nelems, i)
3253 size += aligned_nrpages(sg->offset, sg->length);
3254
3255 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
3256 pdev->dma_mask);
3257 if (!iova) {
3258 sglist->dma_length = 0;
3259 return 0;
3260 }
3261
3262 /*
3263 * Check if DMAR supports zero-length reads on write only
3264 * mappings..
3265 */
3266 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
3267 !cap_zlr(iommu->cap))
3268 prot |= DMA_PTE_READ;
3269 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3270 prot |= DMA_PTE_WRITE;
3271
3272 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
3273
3274 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
3275 if (unlikely(ret)) {
3276 /* clear the page */
3277 dma_pte_clear_range(domain, start_vpfn,
3278 start_vpfn + size - 1);
3279 /* free page tables */
3280 dma_pte_free_pagetable(domain, start_vpfn,
3281 start_vpfn + size - 1);
3282 /* free iova */
3283 __free_iova(&domain->iovad, iova);
3284 return 0;
3285 }
3286
3287 /* it's a non-present to present mapping. Only flush if caching mode */
3288 if (cap_caching_mode(iommu->cap))
3289 iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1);
3290 else
3291 iommu_flush_write_buffer(iommu);
3292
3293 return nelems;
3294 }
3295
3296 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
3297 {
3298 return !dma_addr;
3299 }
3300
3301 struct dma_map_ops intel_dma_ops = {
3302 .alloc = intel_alloc_coherent,
3303 .free = intel_free_coherent,
3304 .map_sg = intel_map_sg,
3305 .unmap_sg = intel_unmap_sg,
3306 .map_page = intel_map_page,
3307 .unmap_page = intel_unmap_page,
3308 .mapping_error = intel_mapping_error,
3309 };
3310
3311 static inline int iommu_domain_cache_init(void)
3312 {
3313 int ret = 0;
3314
3315 iommu_domain_cache = kmem_cache_create("iommu_domain",
3316 sizeof(struct dmar_domain),
3317 0,
3318 SLAB_HWCACHE_ALIGN,
3319
3320 NULL);
3321 if (!iommu_domain_cache) {
3322 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
3323 ret = -ENOMEM;
3324 }
3325
3326 return ret;
3327 }
3328
3329 static inline int iommu_devinfo_cache_init(void)
3330 {
3331 int ret = 0;
3332
3333 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
3334 sizeof(struct device_domain_info),
3335 0,
3336 SLAB_HWCACHE_ALIGN,
3337 NULL);
3338 if (!iommu_devinfo_cache) {
3339 printk(KERN_ERR "Couldn't create devinfo cache\n");
3340 ret = -ENOMEM;
3341 }
3342
3343 return ret;
3344 }
3345
3346 static inline int iommu_iova_cache_init(void)
3347 {
3348 int ret = 0;
3349
3350 iommu_iova_cache = kmem_cache_create("iommu_iova",
3351 sizeof(struct iova),
3352 0,
3353 SLAB_HWCACHE_ALIGN,
3354 NULL);
3355 if (!iommu_iova_cache) {
3356 printk(KERN_ERR "Couldn't create iova cache\n");
3357 ret = -ENOMEM;
3358 }
3359
3360 return ret;
3361 }
3362
3363 static int __init iommu_init_mempool(void)
3364 {
3365 int ret;
3366 ret = iommu_iova_cache_init();
3367 if (ret)
3368 return ret;
3369
3370 ret = iommu_domain_cache_init();
3371 if (ret)
3372 goto domain_error;
3373
3374 ret = iommu_devinfo_cache_init();
3375 if (!ret)
3376 return ret;
3377
3378 kmem_cache_destroy(iommu_domain_cache);
3379 domain_error:
3380 kmem_cache_destroy(iommu_iova_cache);
3381
3382 return -ENOMEM;
3383 }
3384
3385 static void __init iommu_exit_mempool(void)
3386 {
3387 kmem_cache_destroy(iommu_devinfo_cache);
3388 kmem_cache_destroy(iommu_domain_cache);
3389 kmem_cache_destroy(iommu_iova_cache);
3390
3391 }
3392
3393 static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3394 {
3395 struct dmar_drhd_unit *drhd;
3396 u32 vtbar;
3397 int rc;
3398
3399 /* We know that this device on this chipset has its own IOMMU.
3400 * If we find it under a different IOMMU, then the BIOS is lying
3401 * to us. Hope that the IOMMU for this device is actually
3402 * disabled, and it needs no translation...
3403 */
3404 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
3405 if (rc) {
3406 /* "can't" happen */
3407 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
3408 return;
3409 }
3410 vtbar &= 0xffff0000;
3411
3412 /* we know that the this iommu should be at offset 0xa000 from vtbar */
3413 drhd = dmar_find_matched_drhd_unit(pdev);
3414 if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
3415 TAINT_FIRMWARE_WORKAROUND,
3416 "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3417 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3418 }
3419 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
3420
3421 static void __init init_no_remapping_devices(void)
3422 {
3423 struct dmar_drhd_unit *drhd;
3424 struct pci_dev *dev;
3425 int i;
3426
3427 for_each_drhd_unit(drhd) {
3428 if (!drhd->include_all) {
3429 for_each_active_dev_scope(drhd->devices,
3430 drhd->devices_cnt, i, dev)
3431 break;
3432 /* ignore DMAR unit if no pci devices exist */
3433 if (i == drhd->devices_cnt)
3434 drhd->ignored = 1;
3435 }
3436 }
3437
3438 for_each_active_drhd_unit(drhd) {
3439 if (drhd->include_all)
3440 continue;
3441
3442 for_each_active_dev_scope(drhd->devices,
3443 drhd->devices_cnt, i, dev)
3444 if (!IS_GFX_DEVICE(dev))
3445 break;
3446 if (i < drhd->devices_cnt)
3447 continue;
3448
3449 /* This IOMMU has *only* gfx devices. Either bypass it or
3450 set the gfx_mapped flag, as appropriate */
3451 if (dmar_map_gfx) {
3452 intel_iommu_gfx_mapped = 1;
3453 } else {
3454 drhd->ignored = 1;
3455 for_each_active_dev_scope(drhd->devices,
3456 drhd->devices_cnt, i, dev)
3457 dev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3458 }
3459 }
3460 }
3461
3462 #ifdef CONFIG_SUSPEND
3463 static int init_iommu_hw(void)
3464 {
3465 struct dmar_drhd_unit *drhd;
3466 struct intel_iommu *iommu = NULL;
3467
3468 for_each_active_iommu(iommu, drhd)
3469 if (iommu->qi)
3470 dmar_reenable_qi(iommu);
3471
3472 for_each_iommu(iommu, drhd) {
3473 if (drhd->ignored) {
3474 /*
3475 * we always have to disable PMRs or DMA may fail on
3476 * this device
3477 */
3478 if (force_on)
3479 iommu_disable_protect_mem_regions(iommu);
3480 continue;
3481 }
3482
3483 iommu_flush_write_buffer(iommu);
3484
3485 iommu_set_root_entry(iommu);
3486
3487 iommu->flush.flush_context(iommu, 0, 0, 0,
3488 DMA_CCMD_GLOBAL_INVL);
3489 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3490 DMA_TLB_GLOBAL_FLUSH);
3491 if (iommu_enable_translation(iommu))
3492 return 1;
3493 iommu_disable_protect_mem_regions(iommu);
3494 }
3495
3496 return 0;
3497 }
3498
3499 static void iommu_flush_all(void)
3500 {
3501 struct dmar_drhd_unit *drhd;
3502 struct intel_iommu *iommu;
3503
3504 for_each_active_iommu(iommu, drhd) {
3505 iommu->flush.flush_context(iommu, 0, 0, 0,
3506 DMA_CCMD_GLOBAL_INVL);
3507 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3508 DMA_TLB_GLOBAL_FLUSH);
3509 }
3510 }
3511
3512 static int iommu_suspend(void)
3513 {
3514 struct dmar_drhd_unit *drhd;
3515 struct intel_iommu *iommu = NULL;
3516 unsigned long flag;
3517
3518 for_each_active_iommu(iommu, drhd) {
3519 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3520 GFP_ATOMIC);
3521 if (!iommu->iommu_state)
3522 goto nomem;
3523 }
3524
3525 iommu_flush_all();
3526
3527 for_each_active_iommu(iommu, drhd) {
3528 iommu_disable_translation(iommu);
3529
3530 raw_spin_lock_irqsave(&iommu->register_lock, flag);
3531
3532 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3533 readl(iommu->reg + DMAR_FECTL_REG);
3534 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3535 readl(iommu->reg + DMAR_FEDATA_REG);
3536 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3537 readl(iommu->reg + DMAR_FEADDR_REG);
3538 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3539 readl(iommu->reg + DMAR_FEUADDR_REG);
3540
3541 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3542 }
3543 return 0;
3544
3545 nomem:
3546 for_each_active_iommu(iommu, drhd)
3547 kfree(iommu->iommu_state);
3548
3549 return -ENOMEM;
3550 }
3551
3552 static void iommu_resume(void)
3553 {
3554 struct dmar_drhd_unit *drhd;
3555 struct intel_iommu *iommu = NULL;
3556 unsigned long flag;
3557
3558 if (init_iommu_hw()) {
3559 if (force_on)
3560 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3561 else
3562 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3563 return;
3564 }
3565
3566 for_each_active_iommu(iommu, drhd) {
3567
3568 raw_spin_lock_irqsave(&iommu->register_lock, flag);
3569
3570 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3571 iommu->reg + DMAR_FECTL_REG);
3572 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3573 iommu->reg + DMAR_FEDATA_REG);
3574 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3575 iommu->reg + DMAR_FEADDR_REG);
3576 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3577 iommu->reg + DMAR_FEUADDR_REG);
3578
3579 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3580 }
3581
3582 for_each_active_iommu(iommu, drhd)
3583 kfree(iommu->iommu_state);
3584 }
3585
3586 static struct syscore_ops iommu_syscore_ops = {
3587 .resume = iommu_resume,
3588 .suspend = iommu_suspend,
3589 };
3590
3591 static void __init init_iommu_pm_ops(void)
3592 {
3593 register_syscore_ops(&iommu_syscore_ops);
3594 }
3595
3596 #else
3597 static inline void init_iommu_pm_ops(void) {}
3598 #endif /* CONFIG_PM */
3599
3600
3601 int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header)
3602 {
3603 struct acpi_dmar_reserved_memory *rmrr;
3604 struct dmar_rmrr_unit *rmrru;
3605
3606 rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
3607 if (!rmrru)
3608 return -ENOMEM;
3609
3610 rmrru->hdr = header;
3611 rmrr = (struct acpi_dmar_reserved_memory *)header;
3612 rmrru->base_address = rmrr->base_address;
3613 rmrru->end_address = rmrr->end_address;
3614 rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
3615 ((void *)rmrr) + rmrr->header.length,
3616 &rmrru->devices_cnt);
3617 if (rmrru->devices_cnt && rmrru->devices == NULL) {
3618 kfree(rmrru);
3619 return -ENOMEM;
3620 }
3621
3622 list_add(&rmrru->list, &dmar_rmrr_units);
3623
3624 return 0;
3625 }
3626
3627 int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr)
3628 {
3629 struct acpi_dmar_atsr *atsr;
3630 struct dmar_atsr_unit *atsru;
3631
3632 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
3633 atsru = kzalloc(sizeof(*atsru), GFP_KERNEL);
3634 if (!atsru)
3635 return -ENOMEM;
3636
3637 atsru->hdr = hdr;
3638 atsru->include_all = atsr->flags & 0x1;
3639 if (!atsru->include_all) {
3640 atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1),
3641 (void *)atsr + atsr->header.length,
3642 &atsru->devices_cnt);
3643 if (atsru->devices_cnt && atsru->devices == NULL) {
3644 kfree(atsru);
3645 return -ENOMEM;
3646 }
3647 }
3648
3649 list_add_rcu(&atsru->list, &dmar_atsr_units);
3650
3651 return 0;
3652 }
3653
3654 static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
3655 {
3656 dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
3657 kfree(atsru);
3658 }
3659
3660 static void intel_iommu_free_dmars(void)
3661 {
3662 struct dmar_rmrr_unit *rmrru, *rmrr_n;
3663 struct dmar_atsr_unit *atsru, *atsr_n;
3664
3665 list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
3666 list_del(&rmrru->list);
3667 dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
3668 kfree(rmrru);
3669 }
3670
3671 list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
3672 list_del(&atsru->list);
3673 intel_iommu_free_atsr(atsru);
3674 }
3675 }
3676
3677 int dmar_find_matched_atsr_unit(struct pci_dev *dev)
3678 {
3679 int i, ret = 1;
3680 struct pci_bus *bus;
3681 struct pci_dev *bridge = NULL, *tmp;
3682 struct acpi_dmar_atsr *atsr;
3683 struct dmar_atsr_unit *atsru;
3684
3685 dev = pci_physfn(dev);
3686 for (bus = dev->bus; bus; bus = bus->parent) {
3687 bridge = bus->self;
3688 if (!bridge || !pci_is_pcie(bridge) ||
3689 pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
3690 return 0;
3691 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT)
3692 break;
3693 }
3694 if (!bridge)
3695 return 0;
3696
3697 rcu_read_lock();
3698 list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
3699 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3700 if (atsr->segment != pci_domain_nr(dev->bus))
3701 continue;
3702
3703 for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp)
3704 if (tmp == bridge)
3705 goto out;
3706
3707 if (atsru->include_all)
3708 goto out;
3709 }
3710 ret = 0;
3711 out:
3712 rcu_read_unlock();
3713
3714 return ret;
3715 }
3716
3717 int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
3718 {
3719 int ret = 0;
3720 struct dmar_rmrr_unit *rmrru;
3721 struct dmar_atsr_unit *atsru;
3722 struct acpi_dmar_atsr *atsr;
3723 struct acpi_dmar_reserved_memory *rmrr;
3724
3725 if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING)
3726 return 0;
3727
3728 list_for_each_entry(rmrru, &dmar_rmrr_units, list) {
3729 rmrr = container_of(rmrru->hdr,
3730 struct acpi_dmar_reserved_memory, header);
3731 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
3732 ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1),
3733 ((void *)rmrr) + rmrr->header.length,
3734 rmrr->segment, rmrru->devices,
3735 rmrru->devices_cnt);
3736 if (ret > 0)
3737 break;
3738 else if(ret < 0)
3739 return ret;
3740 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
3741 if (dmar_remove_dev_scope(info, rmrr->segment,
3742 rmrru->devices, rmrru->devices_cnt))
3743 break;
3744 }
3745 }
3746
3747 list_for_each_entry(atsru, &dmar_atsr_units, list) {
3748 if (atsru->include_all)
3749 continue;
3750
3751 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3752 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
3753 ret = dmar_insert_dev_scope(info, (void *)(atsr + 1),
3754 (void *)atsr + atsr->header.length,
3755 atsr->segment, atsru->devices,
3756 atsru->devices_cnt);
3757 if (ret > 0)
3758 break;
3759 else if(ret < 0)
3760 return ret;
3761 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
3762 if (dmar_remove_dev_scope(info, atsr->segment,
3763 atsru->devices, atsru->devices_cnt))
3764 break;
3765 }
3766 }
3767
3768 return 0;
3769 }
3770
3771 /*
3772 * Here we only respond to action of unbound device from driver.
3773 *
3774 * Added device is not attached to its DMAR domain here yet. That will happen
3775 * when mapping the device to iova.
3776 */
3777 static int device_notifier(struct notifier_block *nb,
3778 unsigned long action, void *data)
3779 {
3780 struct device *dev = data;
3781 struct pci_dev *pdev = to_pci_dev(dev);
3782 struct dmar_domain *domain;
3783
3784 if (iommu_dummy(pdev))
3785 return 0;
3786
3787 if (action != BUS_NOTIFY_UNBOUND_DRIVER &&
3788 action != BUS_NOTIFY_DEL_DEVICE)
3789 return 0;
3790
3791 domain = find_domain(pdev);
3792 if (!domain)
3793 return 0;
3794
3795 down_read(&dmar_global_lock);
3796 domain_remove_one_dev_info(domain, pdev);
3797 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
3798 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) &&
3799 list_empty(&domain->devices))
3800 domain_exit(domain);
3801 up_read(&dmar_global_lock);
3802
3803 return 0;
3804 }
3805
3806 static struct notifier_block device_nb = {
3807 .notifier_call = device_notifier,
3808 };
3809
3810 static int intel_iommu_memory_notifier(struct notifier_block *nb,
3811 unsigned long val, void *v)
3812 {
3813 struct memory_notify *mhp = v;
3814 unsigned long long start, end;
3815 unsigned long start_vpfn, last_vpfn;
3816
3817 switch (val) {
3818 case MEM_GOING_ONLINE:
3819 start = mhp->start_pfn << PAGE_SHIFT;
3820 end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
3821 if (iommu_domain_identity_map(si_domain, start, end)) {
3822 pr_warn("dmar: failed to build identity map for [%llx-%llx]\n",
3823 start, end);
3824 return NOTIFY_BAD;
3825 }
3826 break;
3827
3828 case MEM_OFFLINE:
3829 case MEM_CANCEL_ONLINE:
3830 start_vpfn = mm_to_dma_pfn(mhp->start_pfn);
3831 last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1);
3832 while (start_vpfn <= last_vpfn) {
3833 struct iova *iova;
3834 struct dmar_drhd_unit *drhd;
3835 struct intel_iommu *iommu;
3836 struct page *freelist;
3837
3838 iova = find_iova(&si_domain->iovad, start_vpfn);
3839 if (iova == NULL) {
3840 pr_debug("dmar: failed get IOVA for PFN %lx\n",
3841 start_vpfn);
3842 break;
3843 }
3844
3845 iova = split_and_remove_iova(&si_domain->iovad, iova,
3846 start_vpfn, last_vpfn);
3847 if (iova == NULL) {
3848 pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n",
3849 start_vpfn, last_vpfn);
3850 return NOTIFY_BAD;
3851 }
3852
3853 freelist = domain_unmap(si_domain, iova->pfn_lo,
3854 iova->pfn_hi);
3855
3856 rcu_read_lock();
3857 for_each_active_iommu(iommu, drhd)
3858 iommu_flush_iotlb_psi(iommu, si_domain->id,
3859 iova->pfn_lo,
3860 iova->pfn_hi - iova->pfn_lo + 1,
3861 !freelist, 0);
3862 rcu_read_unlock();
3863 dma_free_pagelist(freelist);
3864
3865 start_vpfn = iova->pfn_hi + 1;
3866 free_iova_mem(iova);
3867 }
3868 break;
3869 }
3870
3871 return NOTIFY_OK;
3872 }
3873
3874 static struct notifier_block intel_iommu_memory_nb = {
3875 .notifier_call = intel_iommu_memory_notifier,
3876 .priority = 0
3877 };
3878
3879 int __init intel_iommu_init(void)
3880 {
3881 int ret = -ENODEV;
3882 struct dmar_drhd_unit *drhd;
3883 struct intel_iommu *iommu;
3884
3885 /* VT-d is required for a TXT/tboot launch, so enforce that */
3886 force_on = tboot_force_iommu();
3887
3888 if (iommu_init_mempool()) {
3889 if (force_on)
3890 panic("tboot: Failed to initialize iommu memory\n");
3891 return -ENOMEM;
3892 }
3893
3894 down_write(&dmar_global_lock);
3895 if (dmar_table_init()) {
3896 if (force_on)
3897 panic("tboot: Failed to initialize DMAR table\n");
3898 goto out_free_dmar;
3899 }
3900
3901 /*
3902 * Disable translation if already enabled prior to OS handover.
3903 */
3904 for_each_active_iommu(iommu, drhd)
3905 if (iommu->gcmd & DMA_GCMD_TE)
3906 iommu_disable_translation(iommu);
3907
3908 if (dmar_dev_scope_init() < 0) {
3909 if (force_on)
3910 panic("tboot: Failed to initialize DMAR device scope\n");
3911 goto out_free_dmar;
3912 }
3913
3914 if (no_iommu || dmar_disabled)
3915 goto out_free_dmar;
3916
3917 if (list_empty(&dmar_rmrr_units))
3918 printk(KERN_INFO "DMAR: No RMRR found\n");
3919
3920 if (list_empty(&dmar_atsr_units))
3921 printk(KERN_INFO "DMAR: No ATSR found\n");
3922
3923 if (dmar_init_reserved_ranges()) {
3924 if (force_on)
3925 panic("tboot: Failed to reserve iommu ranges\n");
3926 goto out_free_reserved_range;
3927 }
3928
3929 init_no_remapping_devices();
3930
3931 ret = init_dmars();
3932 if (ret) {
3933 if (force_on)
3934 panic("tboot: Failed to initialize DMARs\n");
3935 printk(KERN_ERR "IOMMU: dmar init failed\n");
3936 goto out_free_reserved_range;
3937 }
3938 up_write(&dmar_global_lock);
3939 printk(KERN_INFO
3940 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3941
3942 init_timer(&unmap_timer);
3943 #ifdef CONFIG_SWIOTLB
3944 swiotlb = 0;
3945 #endif
3946 dma_ops = &intel_dma_ops;
3947
3948 init_iommu_pm_ops();
3949
3950 bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
3951 bus_register_notifier(&pci_bus_type, &device_nb);
3952 if (si_domain && !hw_pass_through)
3953 register_memory_notifier(&intel_iommu_memory_nb);
3954
3955 intel_iommu_enabled = 1;
3956
3957 return 0;
3958
3959 out_free_reserved_range:
3960 put_iova_domain(&reserved_iova_list);
3961 out_free_dmar:
3962 intel_iommu_free_dmars();
3963 up_write(&dmar_global_lock);
3964 iommu_exit_mempool();
3965 return ret;
3966 }
3967
3968 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3969 struct pci_dev *pdev)
3970 {
3971 struct pci_dev *tmp, *parent;
3972
3973 if (!iommu || !pdev)
3974 return;
3975
3976 /* dependent device detach */
3977 tmp = pci_find_upstream_pcie_bridge(pdev);
3978 /* Secondary interface's bus number and devfn 0 */
3979 if (tmp) {
3980 parent = pdev->bus->self;
3981 while (parent != tmp) {
3982 iommu_detach_dev(iommu, parent->bus->number,
3983 parent->devfn);
3984 parent = parent->bus->self;
3985 }
3986 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
3987 iommu_detach_dev(iommu,
3988 tmp->subordinate->number, 0);
3989 else /* this is a legacy PCI bridge */
3990 iommu_detach_dev(iommu, tmp->bus->number,
3991 tmp->devfn);
3992 }
3993 }
3994
3995 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3996 struct pci_dev *pdev)
3997 {
3998 struct device_domain_info *info, *tmp;
3999 struct intel_iommu *iommu;
4000 unsigned long flags;
4001 int found = 0;
4002
4003 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
4004 pdev->devfn);
4005 if (!iommu)
4006 return;
4007
4008 spin_lock_irqsave(&device_domain_lock, flags);
4009 list_for_each_entry_safe(info, tmp, &domain->devices, link) {
4010 if (info->segment == pci_domain_nr(pdev->bus) &&
4011 info->bus == pdev->bus->number &&
4012 info->devfn == pdev->devfn) {
4013 unlink_domain_info(info);
4014 spin_unlock_irqrestore(&device_domain_lock, flags);
4015
4016 iommu_disable_dev_iotlb(info);
4017 iommu_detach_dev(iommu, info->bus, info->devfn);
4018 iommu_detach_dependent_devices(iommu, pdev);
4019 free_devinfo_mem(info);
4020
4021 spin_lock_irqsave(&device_domain_lock, flags);
4022
4023 if (found)
4024 break;
4025 else
4026 continue;
4027 }
4028
4029 /* if there is no other devices under the same iommu
4030 * owned by this domain, clear this iommu in iommu_bmp
4031 * update iommu count and coherency
4032 */
4033 if (iommu == device_to_iommu(info->segment, info->bus,
4034 info->devfn))
4035 found = 1;
4036 }
4037
4038 spin_unlock_irqrestore(&device_domain_lock, flags);
4039
4040 if (found == 0) {
4041 unsigned long tmp_flags;
4042 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
4043 clear_bit(iommu->seq_id, domain->iommu_bmp);
4044 domain->iommu_count--;
4045 domain_update_iommu_cap(domain);
4046 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
4047
4048 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
4049 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) {
4050 spin_lock_irqsave(&iommu->lock, tmp_flags);
4051 clear_bit(domain->id, iommu->domain_ids);
4052 iommu->domains[domain->id] = NULL;
4053 spin_unlock_irqrestore(&iommu->lock, tmp_flags);
4054 }
4055 }
4056 }
4057
4058 static int md_domain_init(struct dmar_domain *domain, int guest_width)
4059 {
4060 int adjust_width;
4061
4062 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
4063 domain_reserve_special_ranges(domain);
4064
4065 /* calculate AGAW */
4066 domain->gaw = guest_width;
4067 adjust_width = guestwidth_to_adjustwidth(guest_width);
4068 domain->agaw = width_to_agaw(adjust_width);
4069
4070 domain->iommu_coherency = 0;
4071 domain->iommu_snooping = 0;
4072 domain->iommu_superpage = 0;
4073 domain->max_addr = 0;
4074 domain->nid = -1;
4075
4076 /* always allocate the top pgd */
4077 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
4078 if (!domain->pgd)
4079 return -ENOMEM;
4080 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
4081 return 0;
4082 }
4083
4084 static int intel_iommu_domain_init(struct iommu_domain *domain)
4085 {
4086 struct dmar_domain *dmar_domain;
4087
4088 dmar_domain = alloc_domain(true);
4089 if (!dmar_domain) {
4090 printk(KERN_ERR
4091 "intel_iommu_domain_init: dmar_domain == NULL\n");
4092 return -ENOMEM;
4093 }
4094 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
4095 printk(KERN_ERR
4096 "intel_iommu_domain_init() failed\n");
4097 domain_exit(dmar_domain);
4098 return -ENOMEM;
4099 }
4100 domain_update_iommu_cap(dmar_domain);
4101 domain->priv = dmar_domain;
4102
4103 domain->geometry.aperture_start = 0;
4104 domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
4105 domain->geometry.force_aperture = true;
4106
4107 return 0;
4108 }
4109
4110 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
4111 {
4112 struct dmar_domain *dmar_domain = domain->priv;
4113
4114 domain->priv = NULL;
4115 domain_exit(dmar_domain);
4116 }
4117
4118 static int intel_iommu_attach_device(struct iommu_domain *domain,
4119 struct device *dev)
4120 {
4121 struct dmar_domain *dmar_domain = domain->priv;
4122 struct pci_dev *pdev = to_pci_dev(dev);
4123 struct intel_iommu *iommu;
4124 int addr_width;
4125
4126 /* normally pdev is not mapped */
4127 if (unlikely(domain_context_mapped(pdev))) {
4128 struct dmar_domain *old_domain;
4129
4130 old_domain = find_domain(pdev);
4131 if (old_domain) {
4132 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
4133 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
4134 domain_remove_one_dev_info(old_domain, pdev);
4135 else
4136 domain_remove_dev_info(old_domain);
4137 }
4138 }
4139
4140 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
4141 pdev->devfn);
4142 if (!iommu)
4143 return -ENODEV;
4144
4145 /* check if this iommu agaw is sufficient for max mapped address */
4146 addr_width = agaw_to_width(iommu->agaw);
4147 if (addr_width > cap_mgaw(iommu->cap))
4148 addr_width = cap_mgaw(iommu->cap);
4149
4150 if (dmar_domain->max_addr > (1LL << addr_width)) {
4151 printk(KERN_ERR "%s: iommu width (%d) is not "
4152 "sufficient for the mapped address (%llx)\n",
4153 __func__, addr_width, dmar_domain->max_addr);
4154 return -EFAULT;
4155 }
4156 dmar_domain->gaw = addr_width;
4157
4158 /*
4159 * Knock out extra levels of page tables if necessary
4160 */
4161 while (iommu->agaw < dmar_domain->agaw) {
4162 struct dma_pte *pte;
4163
4164 pte = dmar_domain->pgd;
4165 if (dma_pte_present(pte)) {
4166 dmar_domain->pgd = (struct dma_pte *)
4167 phys_to_virt(dma_pte_addr(pte));
4168 free_pgtable_page(pte);
4169 }
4170 dmar_domain->agaw--;
4171 }
4172
4173 return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
4174 }
4175
4176 static void intel_iommu_detach_device(struct iommu_domain *domain,
4177 struct device *dev)
4178 {
4179 struct dmar_domain *dmar_domain = domain->priv;
4180 struct pci_dev *pdev = to_pci_dev(dev);
4181
4182 domain_remove_one_dev_info(dmar_domain, pdev);
4183 }
4184
4185 static int intel_iommu_map(struct iommu_domain *domain,
4186 unsigned long iova, phys_addr_t hpa,
4187 size_t size, int iommu_prot)
4188 {
4189 struct dmar_domain *dmar_domain = domain->priv;
4190 u64 max_addr;
4191 int prot = 0;
4192 int ret;
4193
4194 if (iommu_prot & IOMMU_READ)
4195 prot |= DMA_PTE_READ;
4196 if (iommu_prot & IOMMU_WRITE)
4197 prot |= DMA_PTE_WRITE;
4198 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
4199 prot |= DMA_PTE_SNP;
4200
4201 max_addr = iova + size;
4202 if (dmar_domain->max_addr < max_addr) {
4203 u64 end;
4204
4205 /* check if minimum agaw is sufficient for mapped address */
4206 end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
4207 if (end < max_addr) {
4208 printk(KERN_ERR "%s: iommu width (%d) is not "
4209 "sufficient for the mapped address (%llx)\n",
4210 __func__, dmar_domain->gaw, max_addr);
4211 return -EFAULT;
4212 }
4213 dmar_domain->max_addr = max_addr;
4214 }
4215 /* Round up size to next multiple of PAGE_SIZE, if it and
4216 the low bits of hpa would take us onto the next page */
4217 size = aligned_nrpages(hpa, size);
4218 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
4219 hpa >> VTD_PAGE_SHIFT, size, prot);
4220 return ret;
4221 }
4222
4223 static size_t intel_iommu_unmap(struct iommu_domain *domain,
4224 unsigned long iova, size_t size)
4225 {
4226 struct dmar_domain *dmar_domain = domain->priv;
4227 struct page *freelist = NULL;
4228 struct intel_iommu *iommu;
4229 unsigned long start_pfn, last_pfn;
4230 unsigned int npages;
4231 int iommu_id, num, ndomains, level = 0;
4232
4233 /* Cope with horrid API which requires us to unmap more than the
4234 size argument if it happens to be a large-page mapping. */
4235 if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level))
4236 BUG();
4237
4238 if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
4239 size = VTD_PAGE_SIZE << level_to_offset_bits(level);
4240
4241 start_pfn = iova >> VTD_PAGE_SHIFT;
4242 last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT;
4243
4244 freelist = domain_unmap(dmar_domain, start_pfn, last_pfn);
4245
4246 npages = last_pfn - start_pfn + 1;
4247
4248 for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) {
4249 iommu = g_iommus[iommu_id];
4250
4251 /*
4252 * find bit position of dmar_domain
4253 */
4254 ndomains = cap_ndoms(iommu->cap);
4255 for_each_set_bit(num, iommu->domain_ids, ndomains) {
4256 if (iommu->domains[num] == dmar_domain)
4257 iommu_flush_iotlb_psi(iommu, num, start_pfn,
4258 npages, !freelist, 0);
4259 }
4260
4261 }
4262
4263 dma_free_pagelist(freelist);
4264
4265 if (dmar_domain->max_addr == iova + size)
4266 dmar_domain->max_addr = iova;
4267
4268 return size;
4269 }
4270
4271 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
4272 dma_addr_t iova)
4273 {
4274 struct dmar_domain *dmar_domain = domain->priv;
4275 struct dma_pte *pte;
4276 int level = 0;
4277 u64 phys = 0;
4278
4279 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
4280 if (pte)
4281 phys = dma_pte_addr(pte);
4282
4283 return phys;
4284 }
4285
4286 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
4287 unsigned long cap)
4288 {
4289 struct dmar_domain *dmar_domain = domain->priv;
4290
4291 if (cap == IOMMU_CAP_CACHE_COHERENCY)
4292 return dmar_domain->iommu_snooping;
4293 if (cap == IOMMU_CAP_INTR_REMAP)
4294 return irq_remapping_enabled;
4295
4296 return 0;
4297 }
4298
4299 #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
4300
4301 static int intel_iommu_add_device(struct device *dev)
4302 {
4303 struct pci_dev *pdev = to_pci_dev(dev);
4304 struct pci_dev *bridge, *dma_pdev = NULL;
4305 struct iommu_group *group;
4306 int ret;
4307
4308 if (!device_to_iommu(pci_domain_nr(pdev->bus),
4309 pdev->bus->number, pdev->devfn))
4310 return -ENODEV;
4311
4312 bridge = pci_find_upstream_pcie_bridge(pdev);
4313 if (bridge) {
4314 if (pci_is_pcie(bridge))
4315 dma_pdev = pci_get_domain_bus_and_slot(
4316 pci_domain_nr(pdev->bus),
4317 bridge->subordinate->number, 0);
4318 if (!dma_pdev)
4319 dma_pdev = pci_dev_get(bridge);
4320 } else
4321 dma_pdev = pci_dev_get(pdev);
4322
4323 /* Account for quirked devices */
4324 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
4325
4326 /*
4327 * If it's a multifunction device that does not support our
4328 * required ACS flags, add to the same group as lowest numbered
4329 * function that also does not suport the required ACS flags.
4330 */
4331 if (dma_pdev->multifunction &&
4332 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) {
4333 u8 i, slot = PCI_SLOT(dma_pdev->devfn);
4334
4335 for (i = 0; i < 8; i++) {
4336 struct pci_dev *tmp;
4337
4338 tmp = pci_get_slot(dma_pdev->bus, PCI_DEVFN(slot, i));
4339 if (!tmp)
4340 continue;
4341
4342 if (!pci_acs_enabled(tmp, REQ_ACS_FLAGS)) {
4343 swap_pci_ref(&dma_pdev, tmp);
4344 break;
4345 }
4346 pci_dev_put(tmp);
4347 }
4348 }
4349
4350 /*
4351 * Devices on the root bus go through the iommu. If that's not us,
4352 * find the next upstream device and test ACS up to the root bus.
4353 * Finding the next device may require skipping virtual buses.
4354 */
4355 while (!pci_is_root_bus(dma_pdev->bus)) {
4356 struct pci_bus *bus = dma_pdev->bus;
4357
4358 while (!bus->self) {
4359 if (!pci_is_root_bus(bus))
4360 bus = bus->parent;
4361 else
4362 goto root_bus;
4363 }
4364
4365 if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
4366 break;
4367
4368 swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
4369 }
4370
4371 root_bus:
4372 group = iommu_group_get(&dma_pdev->dev);
4373 pci_dev_put(dma_pdev);
4374 if (!group) {
4375 group = iommu_group_alloc();
4376 if (IS_ERR(group))
4377 return PTR_ERR(group);
4378 }
4379
4380 ret = iommu_group_add_device(group, dev);
4381
4382 iommu_group_put(group);
4383 return ret;
4384 }
4385
4386 static void intel_iommu_remove_device(struct device *dev)
4387 {
4388 iommu_group_remove_device(dev);
4389 }
4390
4391 static struct iommu_ops intel_iommu_ops = {
4392 .domain_init = intel_iommu_domain_init,
4393 .domain_destroy = intel_iommu_domain_destroy,
4394 .attach_dev = intel_iommu_attach_device,
4395 .detach_dev = intel_iommu_detach_device,
4396 .map = intel_iommu_map,
4397 .unmap = intel_iommu_unmap,
4398 .iova_to_phys = intel_iommu_iova_to_phys,
4399 .domain_has_cap = intel_iommu_domain_has_cap,
4400 .add_device = intel_iommu_add_device,
4401 .remove_device = intel_iommu_remove_device,
4402 .pgsize_bitmap = INTEL_IOMMU_PGSIZES,
4403 };
4404
4405 static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
4406 {
4407 /* G4x/GM45 integrated gfx dmar support is totally busted. */
4408 printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
4409 dmar_map_gfx = 0;
4410 }
4411
4412 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
4413 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
4414 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
4415 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
4416 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
4417 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
4418 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
4419
4420 static void quirk_iommu_rwbf(struct pci_dev *dev)
4421 {
4422 /*
4423 * Mobile 4 Series Chipset neglects to set RWBF capability,
4424 * but needs it. Same seems to hold for the desktop versions.
4425 */
4426 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
4427 rwbf_quirk = 1;
4428 }
4429
4430 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
4431 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
4432 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
4433 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
4434 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
4435 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
4436 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
4437
4438 #define GGC 0x52
4439 #define GGC_MEMORY_SIZE_MASK (0xf << 8)
4440 #define GGC_MEMORY_SIZE_NONE (0x0 << 8)
4441 #define GGC_MEMORY_SIZE_1M (0x1 << 8)
4442 #define GGC_MEMORY_SIZE_2M (0x3 << 8)
4443 #define GGC_MEMORY_VT_ENABLED (0x8 << 8)
4444 #define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
4445 #define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
4446 #define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
4447
4448 static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
4449 {
4450 unsigned short ggc;
4451
4452 if (pci_read_config_word(dev, GGC, &ggc))
4453 return;
4454
4455 if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
4456 printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
4457 dmar_map_gfx = 0;
4458 } else if (dmar_map_gfx) {
4459 /* we have to ensure the gfx device is idle before we flush */
4460 printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
4461 intel_iommu_strict = 1;
4462 }
4463 }
4464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
4465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
4466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
4467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
4468
4469 /* On Tylersburg chipsets, some BIOSes have been known to enable the
4470 ISOCH DMAR unit for the Azalia sound device, but not give it any
4471 TLB entries, which causes it to deadlock. Check for that. We do
4472 this in a function called from init_dmars(), instead of in a PCI
4473 quirk, because we don't want to print the obnoxious "BIOS broken"
4474 message if VT-d is actually disabled.
4475 */
4476 static void __init check_tylersburg_isoch(void)
4477 {
4478 struct pci_dev *pdev;
4479 uint32_t vtisochctrl;
4480
4481 /* If there's no Azalia in the system anyway, forget it. */
4482 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
4483 if (!pdev)
4484 return;
4485 pci_dev_put(pdev);
4486
4487 /* System Management Registers. Might be hidden, in which case
4488 we can't do the sanity check. But that's OK, because the
4489 known-broken BIOSes _don't_ actually hide it, so far. */
4490 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
4491 if (!pdev)
4492 return;
4493
4494 if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
4495 pci_dev_put(pdev);
4496 return;
4497 }
4498
4499 pci_dev_put(pdev);
4500
4501 /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
4502 if (vtisochctrl & 1)
4503 return;
4504
4505 /* Drop all bits other than the number of TLB entries */
4506 vtisochctrl &= 0x1c;
4507
4508 /* If we have the recommended number of TLB entries (16), fine. */
4509 if (vtisochctrl == 0x10)
4510 return;
4511
4512 /* Zero TLB entries? You get to ride the short bus to school. */
4513 if (!vtisochctrl) {
4514 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
4515 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
4516 dmi_get_system_info(DMI_BIOS_VENDOR),
4517 dmi_get_system_info(DMI_BIOS_VERSION),
4518 dmi_get_system_info(DMI_PRODUCT_VERSION));
4519 iommu_identity_mapping |= IDENTMAP_AZALIA;
4520 return;
4521 }
4522
4523 printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
4524 vtisochctrl);
4525 }
Linux kernel - Deliverables
This page took 0.276931 seconds and 5 git commands to generate.