1 #include <linux/interrupt.h>
2 #include <linux/dmar.h>
3 #include <linux/spinlock.h>
4 #include <linux/slab.h>
5 #include <linux/jiffies.h>
6 #include <linux/hpet.h>
9 #include <linux/intel-iommu.h>
10 #include <linux/acpi.h>
11 #include <asm/io_apic.h>
14 #include <asm/irq_remapping.h>
15 #include <asm/pci-direct.h>
16 #include <asm/msidef.h>
18 #include "irq_remapping.h"
21 struct intel_iommu
*iommu
;
23 unsigned int bus
; /* PCI bus number */
24 unsigned int devfn
; /* PCI devfn number */
28 struct intel_iommu
*iommu
;
34 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
35 #define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
37 static struct ioapic_scope ir_ioapic
[MAX_IO_APICS
];
38 static struct hpet_scope ir_hpet
[MAX_HPET_TBS
];
39 static int ir_ioapic_num
, ir_hpet_num
;
46 * ->iommu->register_lock
48 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
49 * in single-threaded environment with interrupt disabled, so no need to tabke
50 * the dmar_global_lock.
52 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock
);
54 static int __init
parse_ioapics_under_ir(void);
56 static struct irq_2_iommu
*irq_2_iommu(unsigned int irq
)
58 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
59 return cfg
? &cfg
->irq_2_iommu
: NULL
;
62 static int get_irte(int irq
, struct irte
*entry
)
64 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
68 if (!entry
|| !irq_iommu
)
71 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
73 if (unlikely(!irq_iommu
->iommu
)) {
74 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
78 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
79 *entry
= *(irq_iommu
->iommu
->ir_table
->base
+ index
);
81 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
85 static int alloc_irte(struct intel_iommu
*iommu
, int irq
, u16 count
)
87 struct ir_table
*table
= iommu
->ir_table
;
88 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
89 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
90 unsigned int mask
= 0;
94 if (!count
|| !irq_iommu
)
98 count
= __roundup_pow_of_two(count
);
102 if (mask
> ecap_max_handle_mask(iommu
->ecap
)) {
104 "Requested mask %x exceeds the max invalidation handle"
105 " mask value %Lx\n", mask
,
106 ecap_max_handle_mask(iommu
->ecap
));
110 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
111 index
= bitmap_find_free_region(table
->bitmap
,
112 INTR_REMAP_TABLE_ENTRIES
, mask
);
114 pr_warn("IR%d: can't allocate an IRTE\n", iommu
->seq_id
);
117 irq_iommu
->iommu
= iommu
;
118 irq_iommu
->irte_index
= index
;
119 irq_iommu
->sub_handle
= 0;
120 irq_iommu
->irte_mask
= mask
;
122 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
127 static int qi_flush_iec(struct intel_iommu
*iommu
, int index
, int mask
)
131 desc
.low
= QI_IEC_IIDEX(index
) | QI_IEC_TYPE
| QI_IEC_IM(mask
)
135 return qi_submit_sync(&desc
, iommu
);
138 static int map_irq_to_irte_handle(int irq
, u16
*sub_handle
)
140 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
147 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
148 *sub_handle
= irq_iommu
->sub_handle
;
149 index
= irq_iommu
->irte_index
;
150 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
154 static int set_irte_irq(int irq
, struct intel_iommu
*iommu
, u16 index
, u16 subhandle
)
156 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
157 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
163 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
166 irq_iommu
->iommu
= iommu
;
167 irq_iommu
->irte_index
= index
;
168 irq_iommu
->sub_handle
= subhandle
;
169 irq_iommu
->irte_mask
= 0;
171 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
176 static int modify_irte(int irq
, struct irte
*irte_modified
)
178 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
179 struct intel_iommu
*iommu
;
187 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
189 iommu
= irq_iommu
->iommu
;
191 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
192 irte
= &iommu
->ir_table
->base
[index
];
194 set_64bit(&irte
->low
, irte_modified
->low
);
195 set_64bit(&irte
->high
, irte_modified
->high
);
196 __iommu_flush_cache(iommu
, irte
, sizeof(*irte
));
198 rc
= qi_flush_iec(iommu
, index
, 0);
199 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
204 static struct intel_iommu
*map_hpet_to_ir(u8 hpet_id
)
208 for (i
= 0; i
< MAX_HPET_TBS
; i
++)
209 if (ir_hpet
[i
].id
== hpet_id
)
210 return ir_hpet
[i
].iommu
;
214 static struct intel_iommu
*map_ioapic_to_ir(int apic
)
218 for (i
= 0; i
< MAX_IO_APICS
; i
++)
219 if (ir_ioapic
[i
].id
== apic
)
220 return ir_ioapic
[i
].iommu
;
224 static struct intel_iommu
*map_dev_to_ir(struct pci_dev
*dev
)
226 struct dmar_drhd_unit
*drhd
;
228 drhd
= dmar_find_matched_drhd_unit(dev
);
235 static int clear_entries(struct irq_2_iommu
*irq_iommu
)
237 struct irte
*start
, *entry
, *end
;
238 struct intel_iommu
*iommu
;
241 if (irq_iommu
->sub_handle
)
244 iommu
= irq_iommu
->iommu
;
245 index
= irq_iommu
->irte_index
+ irq_iommu
->sub_handle
;
247 start
= iommu
->ir_table
->base
+ index
;
248 end
= start
+ (1 << irq_iommu
->irte_mask
);
250 for (entry
= start
; entry
< end
; entry
++) {
251 set_64bit(&entry
->low
, 0);
252 set_64bit(&entry
->high
, 0);
254 bitmap_release_region(iommu
->ir_table
->bitmap
, index
,
255 irq_iommu
->irte_mask
);
257 return qi_flush_iec(iommu
, index
, irq_iommu
->irte_mask
);
260 static int free_irte(int irq
)
262 struct irq_2_iommu
*irq_iommu
= irq_2_iommu(irq
);
269 raw_spin_lock_irqsave(&irq_2_ir_lock
, flags
);
271 rc
= clear_entries(irq_iommu
);
273 irq_iommu
->iommu
= NULL
;
274 irq_iommu
->irte_index
= 0;
275 irq_iommu
->sub_handle
= 0;
276 irq_iommu
->irte_mask
= 0;
278 raw_spin_unlock_irqrestore(&irq_2_ir_lock
, flags
);
284 * source validation type
286 #define SVT_NO_VERIFY 0x0 /* no verification is required */
287 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
288 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
291 * source-id qualifier
293 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
294 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
295 * the third least significant bit
297 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
298 * the second and third least significant bits
300 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
301 * the least three significant bits
305 * set SVT, SQ and SID fields of irte to verify
306 * source ids of interrupt requests
308 static void set_irte_sid(struct irte
*irte
, unsigned int svt
,
309 unsigned int sq
, unsigned int sid
)
311 if (disable_sourceid_checking
)
318 static int set_ioapic_sid(struct irte
*irte
, int apic
)
326 down_read(&dmar_global_lock
);
327 for (i
= 0; i
< MAX_IO_APICS
; i
++) {
328 if (ir_ioapic
[i
].id
== apic
) {
329 sid
= (ir_ioapic
[i
].bus
<< 8) | ir_ioapic
[i
].devfn
;
333 up_read(&dmar_global_lock
);
336 pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic
);
340 set_irte_sid(irte
, SVT_VERIFY_SID_SQ
, SQ_ALL_16
, sid
);
345 static int set_hpet_sid(struct irte
*irte
, u8 id
)
353 down_read(&dmar_global_lock
);
354 for (i
= 0; i
< MAX_HPET_TBS
; i
++) {
355 if (ir_hpet
[i
].id
== id
) {
356 sid
= (ir_hpet
[i
].bus
<< 8) | ir_hpet
[i
].devfn
;
360 up_read(&dmar_global_lock
);
363 pr_warning("Failed to set source-id of HPET block (%d)\n", id
);
368 * Should really use SQ_ALL_16. Some platforms are broken.
369 * While we figure out the right quirks for these broken platforms, use
370 * SQ_13_IGNORE_3 for now.
372 set_irte_sid(irte
, SVT_VERIFY_SID_SQ
, SQ_13_IGNORE_3
, sid
);
377 struct set_msi_sid_data
{
378 struct pci_dev
*pdev
;
382 static int set_msi_sid_cb(struct pci_dev
*pdev
, u16 alias
, void *opaque
)
384 struct set_msi_sid_data
*data
= opaque
;
392 static int set_msi_sid(struct irte
*irte
, struct pci_dev
*dev
)
394 struct set_msi_sid_data data
;
399 pci_for_each_dma_alias(dev
, set_msi_sid_cb
, &data
);
402 * DMA alias provides us with a PCI device and alias. The only case
403 * where the it will return an alias on a different bus than the
404 * device is the case of a PCIe-to-PCI bridge, where the alias is for
405 * the subordinate bus. In this case we can only verify the bus.
407 * If the alias device is on a different bus than our source device
408 * then we have a topology based alias, use it.
410 * Otherwise, the alias is for a device DMA quirk and we cannot
411 * assume that MSI uses the same requester ID. Therefore use the
414 if (PCI_BUS_NUM(data
.alias
) != data
.pdev
->bus
->number
)
415 set_irte_sid(irte
, SVT_VERIFY_BUS
, SQ_ALL_16
,
416 PCI_DEVID(PCI_BUS_NUM(data
.alias
),
418 else if (data
.pdev
->bus
->number
!= dev
->bus
->number
)
419 set_irte_sid(irte
, SVT_VERIFY_SID_SQ
, SQ_ALL_16
, data
.alias
);
421 set_irte_sid(irte
, SVT_VERIFY_SID_SQ
, SQ_ALL_16
,
422 PCI_DEVID(dev
->bus
->number
, dev
->devfn
));
427 static void iommu_set_irq_remapping(struct intel_iommu
*iommu
, int mode
)
433 addr
= virt_to_phys((void *)iommu
->ir_table
->base
);
435 raw_spin_lock_irqsave(&iommu
->register_lock
, flags
);
437 dmar_writeq(iommu
->reg
+ DMAR_IRTA_REG
,
438 (addr
) | IR_X2APIC_MODE(mode
) | INTR_REMAP_TABLE_REG_SIZE
);
440 /* Set interrupt-remapping table pointer */
441 iommu
->gcmd
|= DMA_GCMD_SIRTP
;
442 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
444 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
445 readl
, (sts
& DMA_GSTS_IRTPS
), sts
);
446 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
449 * global invalidation of interrupt entry cache before enabling
450 * interrupt-remapping.
452 qi_global_iec(iommu
);
454 raw_spin_lock_irqsave(&iommu
->register_lock
, flags
);
456 /* Enable interrupt-remapping */
457 iommu
->gcmd
|= DMA_GCMD_IRE
;
458 iommu
->gcmd
&= ~DMA_GCMD_CFI
; /* Block compatibility-format MSIs */
459 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
461 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
462 readl
, (sts
& DMA_GSTS_IRES
), sts
);
465 * With CFI clear in the Global Command register, we should be
466 * protected from dangerous (i.e. compatibility) interrupts
467 * regardless of x2apic status. Check just to be sure.
469 if (sts
& DMA_GSTS_CFIS
)
471 "Compatibility-format IRQs enabled despite intr remapping;\n"
472 "you are vulnerable to IRQ injection.\n");
474 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
478 static int intel_setup_irq_remapping(struct intel_iommu
*iommu
, int mode
)
480 struct ir_table
*ir_table
;
482 unsigned long *bitmap
;
484 ir_table
= iommu
->ir_table
= kzalloc(sizeof(struct ir_table
),
487 if (!iommu
->ir_table
)
490 pages
= alloc_pages_node(iommu
->node
, GFP_ATOMIC
| __GFP_ZERO
,
491 INTR_REMAP_PAGE_ORDER
);
494 pr_err("IR%d: failed to allocate pages of order %d\n",
495 iommu
->seq_id
, INTR_REMAP_PAGE_ORDER
);
496 kfree(iommu
->ir_table
);
500 bitmap
= kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES
),
501 sizeof(long), GFP_ATOMIC
);
502 if (bitmap
== NULL
) {
503 pr_err("IR%d: failed to allocate bitmap\n", iommu
->seq_id
);
504 __free_pages(pages
, INTR_REMAP_PAGE_ORDER
);
509 ir_table
->base
= page_address(pages
);
510 ir_table
->bitmap
= bitmap
;
512 iommu_set_irq_remapping(iommu
, mode
);
517 * Disable Interrupt Remapping.
519 static void iommu_disable_irq_remapping(struct intel_iommu
*iommu
)
524 if (!ecap_ir_support(iommu
->ecap
))
528 * global invalidation of interrupt entry cache before disabling
529 * interrupt-remapping.
531 qi_global_iec(iommu
);
533 raw_spin_lock_irqsave(&iommu
->register_lock
, flags
);
535 sts
= dmar_readq(iommu
->reg
+ DMAR_GSTS_REG
);
536 if (!(sts
& DMA_GSTS_IRES
))
539 iommu
->gcmd
&= ~DMA_GCMD_IRE
;
540 writel(iommu
->gcmd
, iommu
->reg
+ DMAR_GCMD_REG
);
542 IOMMU_WAIT_OP(iommu
, DMAR_GSTS_REG
,
543 readl
, !(sts
& DMA_GSTS_IRES
), sts
);
546 raw_spin_unlock_irqrestore(&iommu
->register_lock
, flags
);
549 static int __init
dmar_x2apic_optout(void)
551 struct acpi_table_dmar
*dmar
;
552 dmar
= (struct acpi_table_dmar
*)dmar_tbl
;
553 if (!dmar
|| no_x2apic_optout
)
555 return dmar
->flags
& DMAR_X2APIC_OPT_OUT
;
558 static int __init
intel_irq_remapping_supported(void)
560 struct dmar_drhd_unit
*drhd
;
561 struct intel_iommu
*iommu
;
563 if (disable_irq_remap
)
565 if (irq_remap_broken
) {
567 "This system BIOS has enabled interrupt remapping\n"
568 "on a chipset that contains an erratum making that\n"
569 "feature unstable. To maintain system stability\n"
570 "interrupt remapping is being disabled. Please\n"
571 "contact your BIOS vendor for an update\n");
572 add_taint(TAINT_FIRMWARE_WORKAROUND
, LOCKDEP_STILL_OK
);
573 disable_irq_remap
= 1;
577 if (!dmar_ir_support())
580 for_each_iommu(iommu
, drhd
)
581 if (!ecap_ir_support(iommu
->ecap
))
587 static int __init
intel_enable_irq_remapping(void)
589 struct dmar_drhd_unit
*drhd
;
590 struct intel_iommu
*iommu
;
595 x2apic_present
= x2apic_supported();
597 if (parse_ioapics_under_ir() != 1) {
598 printk(KERN_INFO
"Not enable interrupt remapping\n");
602 if (x2apic_present
) {
603 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
605 eim
= !dmar_x2apic_optout();
608 "Your BIOS is broken and requested that x2apic be disabled.\n"
609 "This will slightly decrease performance.\n"
610 "Use 'intremap=no_x2apic_optout' to override BIOS request.\n");
613 for_each_iommu(iommu
, drhd
) {
615 * If the queued invalidation is already initialized,
616 * shouldn't disable it.
622 * Clear previous faults.
624 dmar_fault(-1, iommu
);
627 * Disable intr remapping and queued invalidation, if already
628 * enabled prior to OS handover.
630 iommu_disable_irq_remapping(iommu
);
632 dmar_disable_qi(iommu
);
636 * check for the Interrupt-remapping support
638 for_each_iommu(iommu
, drhd
) {
639 if (!ecap_ir_support(iommu
->ecap
))
642 if (eim
&& !ecap_eim_support(iommu
->ecap
)) {
643 printk(KERN_INFO
"DRHD %Lx: EIM not supported by DRHD, "
644 " ecap %Lx\n", drhd
->reg_base_addr
, iommu
->ecap
);
650 * Enable queued invalidation for all the DRHD's.
652 for_each_iommu(iommu
, drhd
) {
653 int ret
= dmar_enable_qi(iommu
);
656 printk(KERN_ERR
"DRHD %Lx: failed to enable queued, "
657 " invalidation, ecap %Lx, ret %d\n",
658 drhd
->reg_base_addr
, iommu
->ecap
, ret
);
664 * Setup Interrupt-remapping for all the DRHD's now.
666 for_each_iommu(iommu
, drhd
) {
667 if (!ecap_ir_support(iommu
->ecap
))
670 if (intel_setup_irq_remapping(iommu
, eim
))
679 irq_remapping_enabled
= 1;
682 * VT-d has a different layout for IO-APIC entries when
683 * interrupt remapping is enabled. So it needs a special routine
684 * to print IO-APIC entries for debugging purposes too.
686 x86_io_apic_ops
.print_entries
= intel_ir_io_apic_print_entries
;
688 pr_info("Enabled IRQ remapping in %s mode\n", eim
? "x2apic" : "xapic");
690 return eim
? IRQ_REMAP_X2APIC_MODE
: IRQ_REMAP_XAPIC_MODE
;
694 * handle error condition gracefully here!
698 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
703 static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope
*scope
,
704 struct intel_iommu
*iommu
)
706 struct acpi_dmar_pci_path
*path
;
711 path
= (struct acpi_dmar_pci_path
*)(scope
+ 1);
712 count
= (scope
->length
- sizeof(struct acpi_dmar_device_scope
))
713 / sizeof(struct acpi_dmar_pci_path
);
715 while (--count
> 0) {
717 * Access PCI directly due to the PCI
718 * subsystem isn't initialized yet.
720 bus
= read_pci_config_byte(bus
, path
->device
, path
->function
,
724 ir_hpet
[ir_hpet_num
].bus
= bus
;
725 ir_hpet
[ir_hpet_num
].devfn
= PCI_DEVFN(path
->device
, path
->function
);
726 ir_hpet
[ir_hpet_num
].iommu
= iommu
;
727 ir_hpet
[ir_hpet_num
].id
= scope
->enumeration_id
;
731 static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope
*scope
,
732 struct intel_iommu
*iommu
)
734 struct acpi_dmar_pci_path
*path
;
739 path
= (struct acpi_dmar_pci_path
*)(scope
+ 1);
740 count
= (scope
->length
- sizeof(struct acpi_dmar_device_scope
))
741 / sizeof(struct acpi_dmar_pci_path
);
743 while (--count
> 0) {
745 * Access PCI directly due to the PCI
746 * subsystem isn't initialized yet.
748 bus
= read_pci_config_byte(bus
, path
->device
, path
->function
,
753 ir_ioapic
[ir_ioapic_num
].bus
= bus
;
754 ir_ioapic
[ir_ioapic_num
].devfn
= PCI_DEVFN(path
->device
, path
->function
);
755 ir_ioapic
[ir_ioapic_num
].iommu
= iommu
;
756 ir_ioapic
[ir_ioapic_num
].id
= scope
->enumeration_id
;
760 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header
*header
,
761 struct intel_iommu
*iommu
)
763 struct acpi_dmar_hardware_unit
*drhd
;
764 struct acpi_dmar_device_scope
*scope
;
767 drhd
= (struct acpi_dmar_hardware_unit
*)header
;
769 start
= (void *)(drhd
+ 1);
770 end
= ((void *)drhd
) + header
->length
;
772 while (start
< end
) {
774 if (scope
->entry_type
== ACPI_DMAR_SCOPE_TYPE_IOAPIC
) {
775 if (ir_ioapic_num
== MAX_IO_APICS
) {
776 printk(KERN_WARNING
"Exceeded Max IO APICS\n");
780 printk(KERN_INFO
"IOAPIC id %d under DRHD base "
781 " 0x%Lx IOMMU %d\n", scope
->enumeration_id
,
782 drhd
->address
, iommu
->seq_id
);
784 ir_parse_one_ioapic_scope(scope
, iommu
);
785 } else if (scope
->entry_type
== ACPI_DMAR_SCOPE_TYPE_HPET
) {
786 if (ir_hpet_num
== MAX_HPET_TBS
) {
787 printk(KERN_WARNING
"Exceeded Max HPET blocks\n");
791 printk(KERN_INFO
"HPET id %d under DRHD base"
792 " 0x%Lx\n", scope
->enumeration_id
,
795 ir_parse_one_hpet_scope(scope
, iommu
);
797 start
+= scope
->length
;
804 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
807 static int __init
parse_ioapics_under_ir(void)
809 struct dmar_drhd_unit
*drhd
;
810 struct intel_iommu
*iommu
;
811 int ir_supported
= 0;
814 for_each_iommu(iommu
, drhd
)
815 if (ecap_ir_support(iommu
->ecap
)) {
816 if (ir_parse_ioapic_hpet_scope(drhd
->hdr
, iommu
))
825 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++) {
826 int ioapic_id
= mpc_ioapic_id(ioapic_idx
);
827 if (!map_ioapic_to_ir(ioapic_id
)) {
828 pr_err(FW_BUG
"ioapic %d has no mapping iommu, "
829 "interrupt remapping will be disabled\n",
838 static int __init
ir_dev_scope_init(void)
842 if (!irq_remapping_enabled
)
845 down_write(&dmar_global_lock
);
846 ret
= dmar_dev_scope_init();
847 up_write(&dmar_global_lock
);
851 rootfs_initcall(ir_dev_scope_init
);
853 static void disable_irq_remapping(void)
855 struct dmar_drhd_unit
*drhd
;
856 struct intel_iommu
*iommu
= NULL
;
859 * Disable Interrupt-remapping for all the DRHD's now.
861 for_each_iommu(iommu
, drhd
) {
862 if (!ecap_ir_support(iommu
->ecap
))
865 iommu_disable_irq_remapping(iommu
);
869 static int reenable_irq_remapping(int eim
)
871 struct dmar_drhd_unit
*drhd
;
873 struct intel_iommu
*iommu
= NULL
;
875 for_each_iommu(iommu
, drhd
)
877 dmar_reenable_qi(iommu
);
880 * Setup Interrupt-remapping for all the DRHD's now.
882 for_each_iommu(iommu
, drhd
) {
883 if (!ecap_ir_support(iommu
->ecap
))
886 /* Set up interrupt remapping for iommu.*/
887 iommu_set_irq_remapping(iommu
, eim
);
898 * handle error condition gracefully here!
903 static void prepare_irte(struct irte
*irte
, int vector
,
906 memset(irte
, 0, sizeof(*irte
));
909 irte
->dst_mode
= apic
->irq_dest_mode
;
911 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
912 * actual level or edge trigger will be setup in the IO-APIC
913 * RTE. This will help simplify level triggered irq migration.
914 * For more details, see the comments (in io_apic.c) explainig IO-APIC
915 * irq migration in the presence of interrupt-remapping.
917 irte
->trigger_mode
= 0;
918 irte
->dlvry_mode
= apic
->irq_delivery_mode
;
919 irte
->vector
= vector
;
920 irte
->dest_id
= IRTE_DEST(dest
);
921 irte
->redir_hint
= 1;
924 static int intel_setup_ioapic_entry(int irq
,
925 struct IO_APIC_route_entry
*route_entry
,
926 unsigned int destination
, int vector
,
927 struct io_apic_irq_attr
*attr
)
929 int ioapic_id
= mpc_ioapic_id(attr
->ioapic
);
930 struct intel_iommu
*iommu
;
931 struct IR_IO_APIC_route_entry
*entry
;
935 down_read(&dmar_global_lock
);
936 iommu
= map_ioapic_to_ir(ioapic_id
);
938 pr_warn("No mapping iommu for ioapic %d\n", ioapic_id
);
941 index
= alloc_irte(iommu
, irq
, 1);
943 pr_warn("Failed to allocate IRTE for ioapic %d\n",
948 up_read(&dmar_global_lock
);
952 prepare_irte(&irte
, vector
, destination
);
954 /* Set source-id of interrupt request */
955 set_ioapic_sid(&irte
, ioapic_id
);
957 modify_irte(irq
, &irte
);
959 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"IOAPIC[%d]: "
960 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
961 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
962 "Avail:%X Vector:%02X Dest:%08X "
963 "SID:%04X SQ:%X SVT:%X)\n",
964 attr
->ioapic
, irte
.present
, irte
.fpd
, irte
.dst_mode
,
965 irte
.redir_hint
, irte
.trigger_mode
, irte
.dlvry_mode
,
966 irte
.avail
, irte
.vector
, irte
.dest_id
,
967 irte
.sid
, irte
.sq
, irte
.svt
);
969 entry
= (struct IR_IO_APIC_route_entry
*)route_entry
;
970 memset(entry
, 0, sizeof(*entry
));
972 entry
->index2
= (index
>> 15) & 0x1;
975 entry
->index
= (index
& 0x7fff);
977 * IO-APIC RTE will be configured with virtual vector.
978 * irq handler will do the explicit EOI to the io-apic.
980 entry
->vector
= attr
->ioapic_pin
;
981 entry
->mask
= 0; /* enable IRQ */
982 entry
->trigger
= attr
->trigger
;
983 entry
->polarity
= attr
->polarity
;
985 /* Mask level triggered irqs.
986 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
995 * Migrate the IO-APIC irq in the presence of intr-remapping.
997 * For both level and edge triggered, irq migration is a simple atomic
998 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1000 * For level triggered, we eliminate the io-apic RTE modification (with the
1001 * updated vector information), by using a virtual vector (io-apic pin number).
1002 * Real vector that is used for interrupting cpu will be coming from
1003 * the interrupt-remapping table entry.
1005 * As the migration is a simple atomic update of IRTE, the same mechanism
1006 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1009 intel_ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
1012 struct irq_cfg
*cfg
= data
->chip_data
;
1013 unsigned int dest
, irq
= data
->irq
;
1017 if (!config_enabled(CONFIG_SMP
))
1020 if (!cpumask_intersects(mask
, cpu_online_mask
))
1023 if (get_irte(irq
, &irte
))
1026 err
= assign_irq_vector(irq
, cfg
, mask
);
1030 err
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
, &dest
);
1032 if (assign_irq_vector(irq
, cfg
, data
->affinity
))
1033 pr_err("Failed to recover vector for irq %d\n", irq
);
1037 irte
.vector
= cfg
->vector
;
1038 irte
.dest_id
= IRTE_DEST(dest
);
1041 * Atomically updates the IRTE with the new destination, vector
1042 * and flushes the interrupt entry cache.
1044 modify_irte(irq
, &irte
);
1047 * After this point, all the interrupts will start arriving
1048 * at the new destination. So, time to cleanup the previous
1049 * vector allocation.
1051 if (cfg
->move_in_progress
)
1052 send_cleanup_vector(cfg
);
1054 cpumask_copy(data
->affinity
, mask
);
1058 static void intel_compose_msi_msg(struct pci_dev
*pdev
,
1059 unsigned int irq
, unsigned int dest
,
1060 struct msi_msg
*msg
, u8 hpet_id
)
1062 struct irq_cfg
*cfg
;
1067 cfg
= irq_get_chip_data(irq
);
1069 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
1070 BUG_ON(ir_index
== -1);
1072 prepare_irte(&irte
, cfg
->vector
, dest
);
1074 /* Set source-id of interrupt request */
1076 set_msi_sid(&irte
, pdev
);
1078 set_hpet_sid(&irte
, hpet_id
);
1080 modify_irte(irq
, &irte
);
1082 msg
->address_hi
= MSI_ADDR_BASE_HI
;
1083 msg
->data
= sub_handle
;
1084 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
1086 MSI_ADDR_IR_INDEX1(ir_index
) |
1087 MSI_ADDR_IR_INDEX2(ir_index
);
1091 * Map the PCI dev to the corresponding remapping hardware unit
1092 * and allocate 'nvec' consecutive interrupt-remapping table entries
1095 static int intel_msi_alloc_irq(struct pci_dev
*dev
, int irq
, int nvec
)
1097 struct intel_iommu
*iommu
;
1100 down_read(&dmar_global_lock
);
1101 iommu
= map_dev_to_ir(dev
);
1104 "Unable to map PCI %s to iommu\n", pci_name(dev
));
1107 index
= alloc_irte(iommu
, irq
, nvec
);
1110 "Unable to allocate %d IRTE for PCI %s\n",
1111 nvec
, pci_name(dev
));
1115 up_read(&dmar_global_lock
);
1120 static int intel_msi_setup_irq(struct pci_dev
*pdev
, unsigned int irq
,
1121 int index
, int sub_handle
)
1123 struct intel_iommu
*iommu
;
1126 down_read(&dmar_global_lock
);
1127 iommu
= map_dev_to_ir(pdev
);
1130 * setup the mapping between the irq and the IRTE
1131 * base index, the sub_handle pointing to the
1132 * appropriate interrupt remap table entry.
1134 set_irte_irq(irq
, iommu
, index
, sub_handle
);
1137 up_read(&dmar_global_lock
);
1142 static int intel_setup_hpet_msi(unsigned int irq
, unsigned int id
)
1145 struct intel_iommu
*iommu
;
1148 down_read(&dmar_global_lock
);
1149 iommu
= map_hpet_to_ir(id
);
1151 index
= alloc_irte(iommu
, irq
, 1);
1155 up_read(&dmar_global_lock
);
1160 struct irq_remap_ops intel_irq_remap_ops
= {
1161 .supported
= intel_irq_remapping_supported
,
1162 .prepare
= dmar_table_init
,
1163 .enable
= intel_enable_irq_remapping
,
1164 .disable
= disable_irq_remapping
,
1165 .reenable
= reenable_irq_remapping
,
1166 .enable_faulting
= enable_drhd_fault_handling
,
1167 .setup_ioapic_entry
= intel_setup_ioapic_entry
,
1168 .set_affinity
= intel_ioapic_set_affinity
,
1169 .free_irq
= free_irte
,
1170 .compose_msi_msg
= intel_compose_msi_msg
,
1171 .msi_alloc_irq
= intel_msi_alloc_irq
,
1172 .msi_setup_irq
= intel_msi_setup_irq
,
1173 .setup_hpet_msi
= intel_setup_hpet_msi
,