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Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
[deliverable/linux.git] / drivers / iommu / intel_irq_remapping.c
1 #include <linux/interrupt.h>
2 #include <linux/dmar.h>
3 #include <linux/spinlock.h>
4 #include <linux/slab.h>
5 #include <linux/jiffies.h>
6 #include <linux/hpet.h>
7 #include <linux/pci.h>
8 #include <linux/irq.h>
9 #include <linux/intel-iommu.h>
10 #include <linux/acpi.h>
11 #include <linux/irqdomain.h>
12 #include <asm/io_apic.h>
13 #include <asm/smp.h>
14 #include <asm/cpu.h>
15 #include <asm/irq_remapping.h>
16 #include <asm/pci-direct.h>
17 #include <asm/msidef.h>
18
19 #include "irq_remapping.h"
20
21 enum irq_mode {
22 IRQ_REMAPPING,
23 IRQ_POSTING,
24 };
25
26 struct ioapic_scope {
27 struct intel_iommu *iommu;
28 unsigned int id;
29 unsigned int bus; /* PCI bus number */
30 unsigned int devfn; /* PCI devfn number */
31 };
32
33 struct hpet_scope {
34 struct intel_iommu *iommu;
35 u8 id;
36 unsigned int bus;
37 unsigned int devfn;
38 };
39
40 struct irq_2_iommu {
41 struct intel_iommu *iommu;
42 u16 irte_index;
43 u16 sub_handle;
44 u8 irte_mask;
45 enum irq_mode mode;
46 };
47
48 struct intel_ir_data {
49 struct irq_2_iommu irq_2_iommu;
50 struct irte irte_entry;
51 union {
52 struct msi_msg msi_entry;
53 };
54 };
55
56 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
57 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
58
59 static int __read_mostly eim_mode;
60 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
61 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
62
63 /*
64 * Lock ordering:
65 * ->dmar_global_lock
66 * ->irq_2_ir_lock
67 * ->qi->q_lock
68 * ->iommu->register_lock
69 * Note:
70 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
71 * in single-threaded environment with interrupt disabled, so no need to tabke
72 * the dmar_global_lock.
73 */
74 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
75 static struct irq_domain_ops intel_ir_domain_ops;
76
77 static int __init parse_ioapics_under_ir(void);
78
79 static int alloc_irte(struct intel_iommu *iommu, int irq,
80 struct irq_2_iommu *irq_iommu, u16 count)
81 {
82 struct ir_table *table = iommu->ir_table;
83 unsigned int mask = 0;
84 unsigned long flags;
85 int index;
86
87 if (!count || !irq_iommu)
88 return -1;
89
90 if (count > 1) {
91 count = __roundup_pow_of_two(count);
92 mask = ilog2(count);
93 }
94
95 if (mask > ecap_max_handle_mask(iommu->ecap)) {
96 printk(KERN_ERR
97 "Requested mask %x exceeds the max invalidation handle"
98 " mask value %Lx\n", mask,
99 ecap_max_handle_mask(iommu->ecap));
100 return -1;
101 }
102
103 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
104 index = bitmap_find_free_region(table->bitmap,
105 INTR_REMAP_TABLE_ENTRIES, mask);
106 if (index < 0) {
107 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
108 } else {
109 irq_iommu->iommu = iommu;
110 irq_iommu->irte_index = index;
111 irq_iommu->sub_handle = 0;
112 irq_iommu->irte_mask = mask;
113 irq_iommu->mode = IRQ_REMAPPING;
114 }
115 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
116
117 return index;
118 }
119
120 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
121 {
122 struct qi_desc desc;
123
124 desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
125 | QI_IEC_SELECTIVE;
126 desc.high = 0;
127
128 return qi_submit_sync(&desc, iommu);
129 }
130
131 static int modify_irte(struct irq_2_iommu *irq_iommu,
132 struct irte *irte_modified)
133 {
134 struct intel_iommu *iommu;
135 unsigned long flags;
136 struct irte *irte;
137 int rc, index;
138
139 if (!irq_iommu)
140 return -1;
141
142 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
143
144 iommu = irq_iommu->iommu;
145
146 index = irq_iommu->irte_index + irq_iommu->sub_handle;
147 irte = &iommu->ir_table->base[index];
148
149 set_64bit(&irte->low, irte_modified->low);
150 set_64bit(&irte->high, irte_modified->high);
151 __iommu_flush_cache(iommu, irte, sizeof(*irte));
152
153 rc = qi_flush_iec(iommu, index, 0);
154
155 /* Update iommu mode according to the IRTE mode */
156 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
157 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
158
159 return rc;
160 }
161
162 static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
163 {
164 int i;
165
166 for (i = 0; i < MAX_HPET_TBS; i++)
167 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
168 return ir_hpet[i].iommu;
169 return NULL;
170 }
171
172 static struct intel_iommu *map_ioapic_to_ir(int apic)
173 {
174 int i;
175
176 for (i = 0; i < MAX_IO_APICS; i++)
177 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
178 return ir_ioapic[i].iommu;
179 return NULL;
180 }
181
182 static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
183 {
184 struct dmar_drhd_unit *drhd;
185
186 drhd = dmar_find_matched_drhd_unit(dev);
187 if (!drhd)
188 return NULL;
189
190 return drhd->iommu;
191 }
192
193 static int clear_entries(struct irq_2_iommu *irq_iommu)
194 {
195 struct irte *start, *entry, *end;
196 struct intel_iommu *iommu;
197 int index;
198
199 if (irq_iommu->sub_handle)
200 return 0;
201
202 iommu = irq_iommu->iommu;
203 index = irq_iommu->irte_index;
204
205 start = iommu->ir_table->base + index;
206 end = start + (1 << irq_iommu->irte_mask);
207
208 for (entry = start; entry < end; entry++) {
209 set_64bit(&entry->low, 0);
210 set_64bit(&entry->high, 0);
211 }
212 bitmap_release_region(iommu->ir_table->bitmap, index,
213 irq_iommu->irte_mask);
214
215 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
216 }
217
218 /*
219 * source validation type
220 */
221 #define SVT_NO_VERIFY 0x0 /* no verification is required */
222 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
223 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
224
225 /*
226 * source-id qualifier
227 */
228 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
229 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
230 * the third least significant bit
231 */
232 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
233 * the second and third least significant bits
234 */
235 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
236 * the least three significant bits
237 */
238
239 /*
240 * set SVT, SQ and SID fields of irte to verify
241 * source ids of interrupt requests
242 */
243 static void set_irte_sid(struct irte *irte, unsigned int svt,
244 unsigned int sq, unsigned int sid)
245 {
246 if (disable_sourceid_checking)
247 svt = SVT_NO_VERIFY;
248 irte->svt = svt;
249 irte->sq = sq;
250 irte->sid = sid;
251 }
252
253 static int set_ioapic_sid(struct irte *irte, int apic)
254 {
255 int i;
256 u16 sid = 0;
257
258 if (!irte)
259 return -1;
260
261 down_read(&dmar_global_lock);
262 for (i = 0; i < MAX_IO_APICS; i++) {
263 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
264 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
265 break;
266 }
267 }
268 up_read(&dmar_global_lock);
269
270 if (sid == 0) {
271 pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic);
272 return -1;
273 }
274
275 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
276
277 return 0;
278 }
279
280 static int set_hpet_sid(struct irte *irte, u8 id)
281 {
282 int i;
283 u16 sid = 0;
284
285 if (!irte)
286 return -1;
287
288 down_read(&dmar_global_lock);
289 for (i = 0; i < MAX_HPET_TBS; i++) {
290 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
291 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
292 break;
293 }
294 }
295 up_read(&dmar_global_lock);
296
297 if (sid == 0) {
298 pr_warning("Failed to set source-id of HPET block (%d)\n", id);
299 return -1;
300 }
301
302 /*
303 * Should really use SQ_ALL_16. Some platforms are broken.
304 * While we figure out the right quirks for these broken platforms, use
305 * SQ_13_IGNORE_3 for now.
306 */
307 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
308
309 return 0;
310 }
311
312 struct set_msi_sid_data {
313 struct pci_dev *pdev;
314 u16 alias;
315 };
316
317 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
318 {
319 struct set_msi_sid_data *data = opaque;
320
321 data->pdev = pdev;
322 data->alias = alias;
323
324 return 0;
325 }
326
327 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
328 {
329 struct set_msi_sid_data data;
330
331 if (!irte || !dev)
332 return -1;
333
334 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
335
336 /*
337 * DMA alias provides us with a PCI device and alias. The only case
338 * where the it will return an alias on a different bus than the
339 * device is the case of a PCIe-to-PCI bridge, where the alias is for
340 * the subordinate bus. In this case we can only verify the bus.
341 *
342 * If the alias device is on a different bus than our source device
343 * then we have a topology based alias, use it.
344 *
345 * Otherwise, the alias is for a device DMA quirk and we cannot
346 * assume that MSI uses the same requester ID. Therefore use the
347 * original device.
348 */
349 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
350 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
351 PCI_DEVID(PCI_BUS_NUM(data.alias),
352 dev->bus->number));
353 else if (data.pdev->bus->number != dev->bus->number)
354 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
355 else
356 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
357 PCI_DEVID(dev->bus->number, dev->devfn));
358
359 return 0;
360 }
361
362 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
363 {
364 u64 addr;
365 u32 sts;
366 unsigned long flags;
367
368 addr = virt_to_phys((void *)iommu->ir_table->base);
369
370 raw_spin_lock_irqsave(&iommu->register_lock, flags);
371
372 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
373 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
374
375 /* Set interrupt-remapping table pointer */
376 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
377
378 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
379 readl, (sts & DMA_GSTS_IRTPS), sts);
380 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
381
382 /*
383 * global invalidation of interrupt entry cache before enabling
384 * interrupt-remapping.
385 */
386 qi_global_iec(iommu);
387
388 raw_spin_lock_irqsave(&iommu->register_lock, flags);
389
390 /* Enable interrupt-remapping */
391 iommu->gcmd |= DMA_GCMD_IRE;
392 iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
393 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
394
395 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
396 readl, (sts & DMA_GSTS_IRES), sts);
397
398 /*
399 * With CFI clear in the Global Command register, we should be
400 * protected from dangerous (i.e. compatibility) interrupts
401 * regardless of x2apic status. Check just to be sure.
402 */
403 if (sts & DMA_GSTS_CFIS)
404 WARN(1, KERN_WARNING
405 "Compatibility-format IRQs enabled despite intr remapping;\n"
406 "you are vulnerable to IRQ injection.\n");
407
408 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
409 }
410
411 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
412 {
413 struct ir_table *ir_table;
414 struct page *pages;
415 unsigned long *bitmap;
416
417 if (iommu->ir_table)
418 return 0;
419
420 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
421 if (!ir_table)
422 return -ENOMEM;
423
424 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
425 INTR_REMAP_PAGE_ORDER);
426 if (!pages) {
427 pr_err("IR%d: failed to allocate pages of order %d\n",
428 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
429 goto out_free_table;
430 }
431
432 bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
433 sizeof(long), GFP_ATOMIC);
434 if (bitmap == NULL) {
435 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
436 goto out_free_pages;
437 }
438
439 iommu->ir_domain = irq_domain_add_hierarchy(arch_get_ir_parent_domain(),
440 0, INTR_REMAP_TABLE_ENTRIES,
441 NULL, &intel_ir_domain_ops,
442 iommu);
443 if (!iommu->ir_domain) {
444 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
445 goto out_free_bitmap;
446 }
447 iommu->ir_msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
448
449 ir_table->base = page_address(pages);
450 ir_table->bitmap = bitmap;
451 iommu->ir_table = ir_table;
452 return 0;
453
454 out_free_bitmap:
455 kfree(bitmap);
456 out_free_pages:
457 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
458 out_free_table:
459 kfree(ir_table);
460 return -ENOMEM;
461 }
462
463 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
464 {
465 if (iommu && iommu->ir_table) {
466 if (iommu->ir_msi_domain) {
467 irq_domain_remove(iommu->ir_msi_domain);
468 iommu->ir_msi_domain = NULL;
469 }
470 if (iommu->ir_domain) {
471 irq_domain_remove(iommu->ir_domain);
472 iommu->ir_domain = NULL;
473 }
474 free_pages((unsigned long)iommu->ir_table->base,
475 INTR_REMAP_PAGE_ORDER);
476 kfree(iommu->ir_table->bitmap);
477 kfree(iommu->ir_table);
478 iommu->ir_table = NULL;
479 }
480 }
481
482 /*
483 * Disable Interrupt Remapping.
484 */
485 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
486 {
487 unsigned long flags;
488 u32 sts;
489
490 if (!ecap_ir_support(iommu->ecap))
491 return;
492
493 /*
494 * global invalidation of interrupt entry cache before disabling
495 * interrupt-remapping.
496 */
497 qi_global_iec(iommu);
498
499 raw_spin_lock_irqsave(&iommu->register_lock, flags);
500
501 sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
502 if (!(sts & DMA_GSTS_IRES))
503 goto end;
504
505 iommu->gcmd &= ~DMA_GCMD_IRE;
506 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
507
508 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
509 readl, !(sts & DMA_GSTS_IRES), sts);
510
511 end:
512 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
513 }
514
515 static int __init dmar_x2apic_optout(void)
516 {
517 struct acpi_table_dmar *dmar;
518 dmar = (struct acpi_table_dmar *)dmar_tbl;
519 if (!dmar || no_x2apic_optout)
520 return 0;
521 return dmar->flags & DMAR_X2APIC_OPT_OUT;
522 }
523
524 static void __init intel_cleanup_irq_remapping(void)
525 {
526 struct dmar_drhd_unit *drhd;
527 struct intel_iommu *iommu;
528
529 for_each_iommu(iommu, drhd) {
530 if (ecap_ir_support(iommu->ecap)) {
531 iommu_disable_irq_remapping(iommu);
532 intel_teardown_irq_remapping(iommu);
533 }
534 }
535
536 if (x2apic_supported())
537 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
538 }
539
540 static int __init intel_prepare_irq_remapping(void)
541 {
542 struct dmar_drhd_unit *drhd;
543 struct intel_iommu *iommu;
544
545 if (irq_remap_broken) {
546 printk(KERN_WARNING
547 "This system BIOS has enabled interrupt remapping\n"
548 "on a chipset that contains an erratum making that\n"
549 "feature unstable. To maintain system stability\n"
550 "interrupt remapping is being disabled. Please\n"
551 "contact your BIOS vendor for an update\n");
552 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
553 return -ENODEV;
554 }
555
556 if (dmar_table_init() < 0)
557 return -ENODEV;
558
559 if (!dmar_ir_support())
560 return -ENODEV;
561
562 if (parse_ioapics_under_ir() != 1) {
563 printk(KERN_INFO "Not enabling interrupt remapping\n");
564 goto error;
565 }
566
567 /* First make sure all IOMMUs support IRQ remapping */
568 for_each_iommu(iommu, drhd)
569 if (!ecap_ir_support(iommu->ecap))
570 goto error;
571
572 /* Do the allocations early */
573 for_each_iommu(iommu, drhd)
574 if (intel_setup_irq_remapping(iommu))
575 goto error;
576
577 return 0;
578
579 error:
580 intel_cleanup_irq_remapping();
581 return -ENODEV;
582 }
583
584 /*
585 * Set Posted-Interrupts capability.
586 */
587 static inline void set_irq_posting_cap(void)
588 {
589 struct dmar_drhd_unit *drhd;
590 struct intel_iommu *iommu;
591
592 if (!disable_irq_post) {
593 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
594
595 for_each_iommu(iommu, drhd)
596 if (!cap_pi_support(iommu->cap)) {
597 intel_irq_remap_ops.capability &=
598 ~(1 << IRQ_POSTING_CAP);
599 break;
600 }
601 }
602 }
603
604 static int __init intel_enable_irq_remapping(void)
605 {
606 struct dmar_drhd_unit *drhd;
607 struct intel_iommu *iommu;
608 bool setup = false;
609 int eim = 0;
610
611 if (x2apic_supported()) {
612 eim = !dmar_x2apic_optout();
613 if (!eim)
614 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit. You can use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
615 }
616
617 for_each_iommu(iommu, drhd) {
618 /*
619 * If the queued invalidation is already initialized,
620 * shouldn't disable it.
621 */
622 if (iommu->qi)
623 continue;
624
625 /*
626 * Clear previous faults.
627 */
628 dmar_fault(-1, iommu);
629
630 /*
631 * Disable intr remapping and queued invalidation, if already
632 * enabled prior to OS handover.
633 */
634 iommu_disable_irq_remapping(iommu);
635
636 dmar_disable_qi(iommu);
637 }
638
639 /*
640 * check for the Interrupt-remapping support
641 */
642 for_each_iommu(iommu, drhd)
643 if (eim && !ecap_eim_support(iommu->ecap)) {
644 printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
645 " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
646 eim = 0;
647 }
648 eim_mode = eim;
649 if (eim)
650 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
651
652 /*
653 * Enable queued invalidation for all the DRHD's.
654 */
655 for_each_iommu(iommu, drhd) {
656 int ret = dmar_enable_qi(iommu);
657
658 if (ret) {
659 printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
660 " invalidation, ecap %Lx, ret %d\n",
661 drhd->reg_base_addr, iommu->ecap, ret);
662 goto error;
663 }
664 }
665
666 /*
667 * Setup Interrupt-remapping for all the DRHD's now.
668 */
669 for_each_iommu(iommu, drhd) {
670 iommu_set_irq_remapping(iommu, eim);
671 setup = true;
672 }
673
674 if (!setup)
675 goto error;
676
677 irq_remapping_enabled = 1;
678
679 set_irq_posting_cap();
680
681 pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic");
682
683 return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
684
685 error:
686 intel_cleanup_irq_remapping();
687 return -1;
688 }
689
690 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
691 struct intel_iommu *iommu,
692 struct acpi_dmar_hardware_unit *drhd)
693 {
694 struct acpi_dmar_pci_path *path;
695 u8 bus;
696 int count, free = -1;
697
698 bus = scope->bus;
699 path = (struct acpi_dmar_pci_path *)(scope + 1);
700 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
701 / sizeof(struct acpi_dmar_pci_path);
702
703 while (--count > 0) {
704 /*
705 * Access PCI directly due to the PCI
706 * subsystem isn't initialized yet.
707 */
708 bus = read_pci_config_byte(bus, path->device, path->function,
709 PCI_SECONDARY_BUS);
710 path++;
711 }
712
713 for (count = 0; count < MAX_HPET_TBS; count++) {
714 if (ir_hpet[count].iommu == iommu &&
715 ir_hpet[count].id == scope->enumeration_id)
716 return 0;
717 else if (ir_hpet[count].iommu == NULL && free == -1)
718 free = count;
719 }
720 if (free == -1) {
721 pr_warn("Exceeded Max HPET blocks\n");
722 return -ENOSPC;
723 }
724
725 ir_hpet[free].iommu = iommu;
726 ir_hpet[free].id = scope->enumeration_id;
727 ir_hpet[free].bus = bus;
728 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
729 pr_info("HPET id %d under DRHD base 0x%Lx\n",
730 scope->enumeration_id, drhd->address);
731
732 return 0;
733 }
734
735 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
736 struct intel_iommu *iommu,
737 struct acpi_dmar_hardware_unit *drhd)
738 {
739 struct acpi_dmar_pci_path *path;
740 u8 bus;
741 int count, free = -1;
742
743 bus = scope->bus;
744 path = (struct acpi_dmar_pci_path *)(scope + 1);
745 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
746 / sizeof(struct acpi_dmar_pci_path);
747
748 while (--count > 0) {
749 /*
750 * Access PCI directly due to the PCI
751 * subsystem isn't initialized yet.
752 */
753 bus = read_pci_config_byte(bus, path->device, path->function,
754 PCI_SECONDARY_BUS);
755 path++;
756 }
757
758 for (count = 0; count < MAX_IO_APICS; count++) {
759 if (ir_ioapic[count].iommu == iommu &&
760 ir_ioapic[count].id == scope->enumeration_id)
761 return 0;
762 else if (ir_ioapic[count].iommu == NULL && free == -1)
763 free = count;
764 }
765 if (free == -1) {
766 pr_warn("Exceeded Max IO APICS\n");
767 return -ENOSPC;
768 }
769
770 ir_ioapic[free].bus = bus;
771 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
772 ir_ioapic[free].iommu = iommu;
773 ir_ioapic[free].id = scope->enumeration_id;
774 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
775 scope->enumeration_id, drhd->address, iommu->seq_id);
776
777 return 0;
778 }
779
780 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
781 struct intel_iommu *iommu)
782 {
783 int ret = 0;
784 struct acpi_dmar_hardware_unit *drhd;
785 struct acpi_dmar_device_scope *scope;
786 void *start, *end;
787
788 drhd = (struct acpi_dmar_hardware_unit *)header;
789 start = (void *)(drhd + 1);
790 end = ((void *)drhd) + header->length;
791
792 while (start < end && ret == 0) {
793 scope = start;
794 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
795 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
796 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
797 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
798 start += scope->length;
799 }
800
801 return ret;
802 }
803
804 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
805 {
806 int i;
807
808 for (i = 0; i < MAX_HPET_TBS; i++)
809 if (ir_hpet[i].iommu == iommu)
810 ir_hpet[i].iommu = NULL;
811
812 for (i = 0; i < MAX_IO_APICS; i++)
813 if (ir_ioapic[i].iommu == iommu)
814 ir_ioapic[i].iommu = NULL;
815 }
816
817 /*
818 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
819 * hardware unit.
820 */
821 static int __init parse_ioapics_under_ir(void)
822 {
823 struct dmar_drhd_unit *drhd;
824 struct intel_iommu *iommu;
825 bool ir_supported = false;
826 int ioapic_idx;
827
828 for_each_iommu(iommu, drhd)
829 if (ecap_ir_support(iommu->ecap)) {
830 if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
831 return -1;
832
833 ir_supported = true;
834 }
835
836 if (!ir_supported)
837 return 0;
838
839 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
840 int ioapic_id = mpc_ioapic_id(ioapic_idx);
841 if (!map_ioapic_to_ir(ioapic_id)) {
842 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
843 "interrupt remapping will be disabled\n",
844 ioapic_id);
845 return -1;
846 }
847 }
848
849 return 1;
850 }
851
852 static int __init ir_dev_scope_init(void)
853 {
854 int ret;
855
856 if (!irq_remapping_enabled)
857 return 0;
858
859 down_write(&dmar_global_lock);
860 ret = dmar_dev_scope_init();
861 up_write(&dmar_global_lock);
862
863 return ret;
864 }
865 rootfs_initcall(ir_dev_scope_init);
866
867 static void disable_irq_remapping(void)
868 {
869 struct dmar_drhd_unit *drhd;
870 struct intel_iommu *iommu = NULL;
871
872 /*
873 * Disable Interrupt-remapping for all the DRHD's now.
874 */
875 for_each_iommu(iommu, drhd) {
876 if (!ecap_ir_support(iommu->ecap))
877 continue;
878
879 iommu_disable_irq_remapping(iommu);
880 }
881
882 /*
883 * Clear Posted-Interrupts capability.
884 */
885 if (!disable_irq_post)
886 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
887 }
888
889 static int reenable_irq_remapping(int eim)
890 {
891 struct dmar_drhd_unit *drhd;
892 bool setup = false;
893 struct intel_iommu *iommu = NULL;
894
895 for_each_iommu(iommu, drhd)
896 if (iommu->qi)
897 dmar_reenable_qi(iommu);
898
899 /*
900 * Setup Interrupt-remapping for all the DRHD's now.
901 */
902 for_each_iommu(iommu, drhd) {
903 if (!ecap_ir_support(iommu->ecap))
904 continue;
905
906 /* Set up interrupt remapping for iommu.*/
907 iommu_set_irq_remapping(iommu, eim);
908 setup = true;
909 }
910
911 if (!setup)
912 goto error;
913
914 set_irq_posting_cap();
915
916 return 0;
917
918 error:
919 /*
920 * handle error condition gracefully here!
921 */
922 return -1;
923 }
924
925 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
926 {
927 memset(irte, 0, sizeof(*irte));
928
929 irte->present = 1;
930 irte->dst_mode = apic->irq_dest_mode;
931 /*
932 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
933 * actual level or edge trigger will be setup in the IO-APIC
934 * RTE. This will help simplify level triggered irq migration.
935 * For more details, see the comments (in io_apic.c) explainig IO-APIC
936 * irq migration in the presence of interrupt-remapping.
937 */
938 irte->trigger_mode = 0;
939 irte->dlvry_mode = apic->irq_delivery_mode;
940 irte->vector = vector;
941 irte->dest_id = IRTE_DEST(dest);
942 irte->redir_hint = 1;
943 }
944
945 static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
946 {
947 struct intel_iommu *iommu = NULL;
948
949 if (!info)
950 return NULL;
951
952 switch (info->type) {
953 case X86_IRQ_ALLOC_TYPE_IOAPIC:
954 iommu = map_ioapic_to_ir(info->ioapic_id);
955 break;
956 case X86_IRQ_ALLOC_TYPE_HPET:
957 iommu = map_hpet_to_ir(info->hpet_id);
958 break;
959 case X86_IRQ_ALLOC_TYPE_MSI:
960 case X86_IRQ_ALLOC_TYPE_MSIX:
961 iommu = map_dev_to_ir(info->msi_dev);
962 break;
963 default:
964 BUG_ON(1);
965 break;
966 }
967
968 return iommu ? iommu->ir_domain : NULL;
969 }
970
971 static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
972 {
973 struct intel_iommu *iommu;
974
975 if (!info)
976 return NULL;
977
978 switch (info->type) {
979 case X86_IRQ_ALLOC_TYPE_MSI:
980 case X86_IRQ_ALLOC_TYPE_MSIX:
981 iommu = map_dev_to_ir(info->msi_dev);
982 if (iommu)
983 return iommu->ir_msi_domain;
984 break;
985 default:
986 break;
987 }
988
989 return NULL;
990 }
991
992 struct irq_remap_ops intel_irq_remap_ops = {
993 .prepare = intel_prepare_irq_remapping,
994 .enable = intel_enable_irq_remapping,
995 .disable = disable_irq_remapping,
996 .reenable = reenable_irq_remapping,
997 .enable_faulting = enable_drhd_fault_handling,
998 .get_ir_irq_domain = intel_get_ir_irq_domain,
999 .get_irq_domain = intel_get_irq_domain,
1000 };
1001
1002 /*
1003 * Migrate the IO-APIC irq in the presence of intr-remapping.
1004 *
1005 * For both level and edge triggered, irq migration is a simple atomic
1006 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1007 *
1008 * For level triggered, we eliminate the io-apic RTE modification (with the
1009 * updated vector information), by using a virtual vector (io-apic pin number).
1010 * Real vector that is used for interrupting cpu will be coming from
1011 * the interrupt-remapping table entry.
1012 *
1013 * As the migration is a simple atomic update of IRTE, the same mechanism
1014 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1015 */
1016 static int
1017 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1018 bool force)
1019 {
1020 struct intel_ir_data *ir_data = data->chip_data;
1021 struct irte *irte = &ir_data->irte_entry;
1022 struct irq_cfg *cfg = irqd_cfg(data);
1023 struct irq_data *parent = data->parent_data;
1024 int ret;
1025
1026 ret = parent->chip->irq_set_affinity(parent, mask, force);
1027 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1028 return ret;
1029
1030 /*
1031 * Atomically updates the IRTE with the new destination, vector
1032 * and flushes the interrupt entry cache.
1033 */
1034 irte->vector = cfg->vector;
1035 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1036
1037 /* Update the hardware only if the interrupt is in remapped mode. */
1038 if (ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1039 modify_irte(&ir_data->irq_2_iommu, irte);
1040
1041 /*
1042 * After this point, all the interrupts will start arriving
1043 * at the new destination. So, time to cleanup the previous
1044 * vector allocation.
1045 */
1046 send_cleanup_vector(cfg);
1047
1048 return IRQ_SET_MASK_OK_DONE;
1049 }
1050
1051 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1052 struct msi_msg *msg)
1053 {
1054 struct intel_ir_data *ir_data = irq_data->chip_data;
1055
1056 *msg = ir_data->msi_entry;
1057 }
1058
1059 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1060 {
1061 struct intel_ir_data *ir_data = data->chip_data;
1062 struct vcpu_data *vcpu_pi_info = info;
1063
1064 /* stop posting interrupts, back to remapping mode */
1065 if (!vcpu_pi_info) {
1066 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1067 } else {
1068 struct irte irte_pi;
1069
1070 /*
1071 * We are not caching the posted interrupt entry. We
1072 * copy the data from the remapped entry and modify
1073 * the fields which are relevant for posted mode. The
1074 * cached remapped entry is used for switching back to
1075 * remapped mode.
1076 */
1077 memset(&irte_pi, 0, sizeof(irte_pi));
1078 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1079
1080 /* Update the posted mode fields */
1081 irte_pi.p_pst = 1;
1082 irte_pi.p_urgent = 0;
1083 irte_pi.p_vector = vcpu_pi_info->vector;
1084 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1085 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1086 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1087 ~(-1UL << PDA_HIGH_BIT);
1088
1089 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1090 }
1091
1092 return 0;
1093 }
1094
1095 static struct irq_chip intel_ir_chip = {
1096 .irq_ack = ir_ack_apic_edge,
1097 .irq_set_affinity = intel_ir_set_affinity,
1098 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1099 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1100 };
1101
1102 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1103 struct irq_cfg *irq_cfg,
1104 struct irq_alloc_info *info,
1105 int index, int sub_handle)
1106 {
1107 struct IR_IO_APIC_route_entry *entry;
1108 struct irte *irte = &data->irte_entry;
1109 struct msi_msg *msg = &data->msi_entry;
1110
1111 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1112 switch (info->type) {
1113 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1114 /* Set source-id of interrupt request */
1115 set_ioapic_sid(irte, info->ioapic_id);
1116 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1117 info->ioapic_id, irte->present, irte->fpd,
1118 irte->dst_mode, irte->redir_hint,
1119 irte->trigger_mode, irte->dlvry_mode,
1120 irte->avail, irte->vector, irte->dest_id,
1121 irte->sid, irte->sq, irte->svt);
1122
1123 entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
1124 info->ioapic_entry = NULL;
1125 memset(entry, 0, sizeof(*entry));
1126 entry->index2 = (index >> 15) & 0x1;
1127 entry->zero = 0;
1128 entry->format = 1;
1129 entry->index = (index & 0x7fff);
1130 /*
1131 * IO-APIC RTE will be configured with virtual vector.
1132 * irq handler will do the explicit EOI to the io-apic.
1133 */
1134 entry->vector = info->ioapic_pin;
1135 entry->mask = 0; /* enable IRQ */
1136 entry->trigger = info->ioapic_trigger;
1137 entry->polarity = info->ioapic_polarity;
1138 if (info->ioapic_trigger)
1139 entry->mask = 1; /* Mask level triggered irqs. */
1140 break;
1141
1142 case X86_IRQ_ALLOC_TYPE_HPET:
1143 case X86_IRQ_ALLOC_TYPE_MSI:
1144 case X86_IRQ_ALLOC_TYPE_MSIX:
1145 if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
1146 set_hpet_sid(irte, info->hpet_id);
1147 else
1148 set_msi_sid(irte, info->msi_dev);
1149
1150 msg->address_hi = MSI_ADDR_BASE_HI;
1151 msg->data = sub_handle;
1152 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1153 MSI_ADDR_IR_SHV |
1154 MSI_ADDR_IR_INDEX1(index) |
1155 MSI_ADDR_IR_INDEX2(index);
1156 break;
1157
1158 default:
1159 BUG_ON(1);
1160 break;
1161 }
1162 }
1163
1164 static void intel_free_irq_resources(struct irq_domain *domain,
1165 unsigned int virq, unsigned int nr_irqs)
1166 {
1167 struct irq_data *irq_data;
1168 struct intel_ir_data *data;
1169 struct irq_2_iommu *irq_iommu;
1170 unsigned long flags;
1171 int i;
1172
1173 for (i = 0; i < nr_irqs; i++) {
1174 irq_data = irq_domain_get_irq_data(domain, virq + i);
1175 if (irq_data && irq_data->chip_data) {
1176 data = irq_data->chip_data;
1177 irq_iommu = &data->irq_2_iommu;
1178 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1179 clear_entries(irq_iommu);
1180 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1181 irq_domain_reset_irq_data(irq_data);
1182 kfree(data);
1183 }
1184 }
1185 }
1186
1187 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1188 unsigned int virq, unsigned int nr_irqs,
1189 void *arg)
1190 {
1191 struct intel_iommu *iommu = domain->host_data;
1192 struct irq_alloc_info *info = arg;
1193 struct intel_ir_data *data, *ird;
1194 struct irq_data *irq_data;
1195 struct irq_cfg *irq_cfg;
1196 int i, ret, index;
1197
1198 if (!info || !iommu)
1199 return -EINVAL;
1200 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
1201 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
1202 return -EINVAL;
1203
1204 /*
1205 * With IRQ remapping enabled, don't need contiguous CPU vectors
1206 * to support multiple MSI interrupts.
1207 */
1208 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
1209 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1210
1211 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1212 if (ret < 0)
1213 return ret;
1214
1215 ret = -ENOMEM;
1216 data = kzalloc(sizeof(*data), GFP_KERNEL);
1217 if (!data)
1218 goto out_free_parent;
1219
1220 down_read(&dmar_global_lock);
1221 index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs);
1222 up_read(&dmar_global_lock);
1223 if (index < 0) {
1224 pr_warn("Failed to allocate IRTE\n");
1225 kfree(data);
1226 goto out_free_parent;
1227 }
1228
1229 for (i = 0; i < nr_irqs; i++) {
1230 irq_data = irq_domain_get_irq_data(domain, virq + i);
1231 irq_cfg = irqd_cfg(irq_data);
1232 if (!irq_data || !irq_cfg) {
1233 ret = -EINVAL;
1234 goto out_free_data;
1235 }
1236
1237 if (i > 0) {
1238 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1239 if (!ird)
1240 goto out_free_data;
1241 /* Initialize the common data */
1242 ird->irq_2_iommu = data->irq_2_iommu;
1243 ird->irq_2_iommu.sub_handle = i;
1244 } else {
1245 ird = data;
1246 }
1247
1248 irq_data->hwirq = (index << 16) + i;
1249 irq_data->chip_data = ird;
1250 irq_data->chip = &intel_ir_chip;
1251 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1252 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1253 }
1254 return 0;
1255
1256 out_free_data:
1257 intel_free_irq_resources(domain, virq, i);
1258 out_free_parent:
1259 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1260 return ret;
1261 }
1262
1263 static void intel_irq_remapping_free(struct irq_domain *domain,
1264 unsigned int virq, unsigned int nr_irqs)
1265 {
1266 intel_free_irq_resources(domain, virq, nr_irqs);
1267 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1268 }
1269
1270 static void intel_irq_remapping_activate(struct irq_domain *domain,
1271 struct irq_data *irq_data)
1272 {
1273 struct intel_ir_data *data = irq_data->chip_data;
1274
1275 modify_irte(&data->irq_2_iommu, &data->irte_entry);
1276 }
1277
1278 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1279 struct irq_data *irq_data)
1280 {
1281 struct intel_ir_data *data = irq_data->chip_data;
1282 struct irte entry;
1283
1284 memset(&entry, 0, sizeof(entry));
1285 modify_irte(&data->irq_2_iommu, &entry);
1286 }
1287
1288 static struct irq_domain_ops intel_ir_domain_ops = {
1289 .alloc = intel_irq_remapping_alloc,
1290 .free = intel_irq_remapping_free,
1291 .activate = intel_irq_remapping_activate,
1292 .deactivate = intel_irq_remapping_deactivate,
1293 };
1294
1295 /*
1296 * Support of Interrupt Remapping Unit Hotplug
1297 */
1298 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1299 {
1300 int ret;
1301 int eim = x2apic_enabled();
1302
1303 if (eim && !ecap_eim_support(iommu->ecap)) {
1304 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1305 iommu->reg_phys, iommu->ecap);
1306 return -ENODEV;
1307 }
1308
1309 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1310 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1311 iommu->reg_phys);
1312 return -ENODEV;
1313 }
1314
1315 /* TODO: check all IOAPICs are covered by IOMMU */
1316
1317 /* Setup Interrupt-remapping now. */
1318 ret = intel_setup_irq_remapping(iommu);
1319 if (ret) {
1320 pr_err("DRHD %Lx: failed to allocate resource\n",
1321 iommu->reg_phys);
1322 ir_remove_ioapic_hpet_scope(iommu);
1323 return ret;
1324 }
1325
1326 if (!iommu->qi) {
1327 /* Clear previous faults. */
1328 dmar_fault(-1, iommu);
1329 iommu_disable_irq_remapping(iommu);
1330 dmar_disable_qi(iommu);
1331 }
1332
1333 /* Enable queued invalidation */
1334 ret = dmar_enable_qi(iommu);
1335 if (!ret) {
1336 iommu_set_irq_remapping(iommu, eim);
1337 } else {
1338 pr_err("DRHD %Lx: failed to enable queued invalidation, ecap %Lx, ret %d\n",
1339 iommu->reg_phys, iommu->ecap, ret);
1340 intel_teardown_irq_remapping(iommu);
1341 ir_remove_ioapic_hpet_scope(iommu);
1342 }
1343
1344 return ret;
1345 }
1346
1347 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1348 {
1349 int ret = 0;
1350 struct intel_iommu *iommu = dmaru->iommu;
1351
1352 if (!irq_remapping_enabled)
1353 return 0;
1354 if (iommu == NULL)
1355 return -EINVAL;
1356 if (!ecap_ir_support(iommu->ecap))
1357 return 0;
1358 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1359 !cap_pi_support(iommu->cap))
1360 return -EBUSY;
1361
1362 if (insert) {
1363 if (!iommu->ir_table)
1364 ret = dmar_ir_add(dmaru, iommu);
1365 } else {
1366 if (iommu->ir_table) {
1367 if (!bitmap_empty(iommu->ir_table->bitmap,
1368 INTR_REMAP_TABLE_ENTRIES)) {
1369 ret = -EBUSY;
1370 } else {
1371 iommu_disable_irq_remapping(iommu);
1372 intel_teardown_irq_remapping(iommu);
1373 ir_remove_ioapic_hpet_scope(iommu);
1374 }
1375 }
1376 }
1377
1378 return ret;
1379 }
Linux kernel - Deliverables
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