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checkpatch: fix left brace warning
[deliverable/linux.git] / drivers / iommu / intel_irq_remapping.c
1
2 #define pr_fmt(fmt) "DMAR-IR: " fmt
3
4 #include <linux/interrupt.h>
5 #include <linux/dmar.h>
6 #include <linux/spinlock.h>
7 #include <linux/slab.h>
8 #include <linux/jiffies.h>
9 #include <linux/hpet.h>
10 #include <linux/pci.h>
11 #include <linux/irq.h>
12 #include <linux/intel-iommu.h>
13 #include <linux/acpi.h>
14 #include <linux/irqdomain.h>
15 #include <linux/crash_dump.h>
16 #include <asm/io_apic.h>
17 #include <asm/smp.h>
18 #include <asm/cpu.h>
19 #include <asm/irq_remapping.h>
20 #include <asm/pci-direct.h>
21 #include <asm/msidef.h>
22
23 #include "irq_remapping.h"
24
25 enum irq_mode {
26 IRQ_REMAPPING,
27 IRQ_POSTING,
28 };
29
30 struct ioapic_scope {
31 struct intel_iommu *iommu;
32 unsigned int id;
33 unsigned int bus; /* PCI bus number */
34 unsigned int devfn; /* PCI devfn number */
35 };
36
37 struct hpet_scope {
38 struct intel_iommu *iommu;
39 u8 id;
40 unsigned int bus;
41 unsigned int devfn;
42 };
43
44 struct irq_2_iommu {
45 struct intel_iommu *iommu;
46 u16 irte_index;
47 u16 sub_handle;
48 u8 irte_mask;
49 enum irq_mode mode;
50 };
51
52 struct intel_ir_data {
53 struct irq_2_iommu irq_2_iommu;
54 struct irte irte_entry;
55 union {
56 struct msi_msg msi_entry;
57 };
58 };
59
60 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
61 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
62
63 static int __read_mostly eim_mode;
64 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
65 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
66
67 /*
68 * Lock ordering:
69 * ->dmar_global_lock
70 * ->irq_2_ir_lock
71 * ->qi->q_lock
72 * ->iommu->register_lock
73 * Note:
74 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
75 * in single-threaded environment with interrupt disabled, so no need to tabke
76 * the dmar_global_lock.
77 */
78 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
79 static struct irq_domain_ops intel_ir_domain_ops;
80
81 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
82 static int __init parse_ioapics_under_ir(void);
83
84 static bool ir_pre_enabled(struct intel_iommu *iommu)
85 {
86 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
87 }
88
89 static void clear_ir_pre_enabled(struct intel_iommu *iommu)
90 {
91 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
92 }
93
94 static void init_ir_status(struct intel_iommu *iommu)
95 {
96 u32 gsts;
97
98 gsts = readl(iommu->reg + DMAR_GSTS_REG);
99 if (gsts & DMA_GSTS_IRES)
100 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
101 }
102
103 static int alloc_irte(struct intel_iommu *iommu, int irq,
104 struct irq_2_iommu *irq_iommu, u16 count)
105 {
106 struct ir_table *table = iommu->ir_table;
107 unsigned int mask = 0;
108 unsigned long flags;
109 int index;
110
111 if (!count || !irq_iommu)
112 return -1;
113
114 if (count > 1) {
115 count = __roundup_pow_of_two(count);
116 mask = ilog2(count);
117 }
118
119 if (mask > ecap_max_handle_mask(iommu->ecap)) {
120 pr_err("Requested mask %x exceeds the max invalidation handle"
121 " mask value %Lx\n", mask,
122 ecap_max_handle_mask(iommu->ecap));
123 return -1;
124 }
125
126 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
127 index = bitmap_find_free_region(table->bitmap,
128 INTR_REMAP_TABLE_ENTRIES, mask);
129 if (index < 0) {
130 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
131 } else {
132 irq_iommu->iommu = iommu;
133 irq_iommu->irte_index = index;
134 irq_iommu->sub_handle = 0;
135 irq_iommu->irte_mask = mask;
136 irq_iommu->mode = IRQ_REMAPPING;
137 }
138 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
139
140 return index;
141 }
142
143 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
144 {
145 struct qi_desc desc;
146
147 desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
148 | QI_IEC_SELECTIVE;
149 desc.high = 0;
150
151 return qi_submit_sync(&desc, iommu);
152 }
153
154 static int modify_irte(struct irq_2_iommu *irq_iommu,
155 struct irte *irte_modified)
156 {
157 struct intel_iommu *iommu;
158 unsigned long flags;
159 struct irte *irte;
160 int rc, index;
161
162 if (!irq_iommu)
163 return -1;
164
165 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
166
167 iommu = irq_iommu->iommu;
168
169 index = irq_iommu->irte_index + irq_iommu->sub_handle;
170 irte = &iommu->ir_table->base[index];
171
172 set_64bit(&irte->low, irte_modified->low);
173 set_64bit(&irte->high, irte_modified->high);
174 __iommu_flush_cache(iommu, irte, sizeof(*irte));
175
176 rc = qi_flush_iec(iommu, index, 0);
177
178 /* Update iommu mode according to the IRTE mode */
179 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
180 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
181
182 return rc;
183 }
184
185 static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
186 {
187 int i;
188
189 for (i = 0; i < MAX_HPET_TBS; i++)
190 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
191 return ir_hpet[i].iommu;
192 return NULL;
193 }
194
195 static struct intel_iommu *map_ioapic_to_ir(int apic)
196 {
197 int i;
198
199 for (i = 0; i < MAX_IO_APICS; i++)
200 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
201 return ir_ioapic[i].iommu;
202 return NULL;
203 }
204
205 static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
206 {
207 struct dmar_drhd_unit *drhd;
208
209 drhd = dmar_find_matched_drhd_unit(dev);
210 if (!drhd)
211 return NULL;
212
213 return drhd->iommu;
214 }
215
216 static int clear_entries(struct irq_2_iommu *irq_iommu)
217 {
218 struct irte *start, *entry, *end;
219 struct intel_iommu *iommu;
220 int index;
221
222 if (irq_iommu->sub_handle)
223 return 0;
224
225 iommu = irq_iommu->iommu;
226 index = irq_iommu->irte_index;
227
228 start = iommu->ir_table->base + index;
229 end = start + (1 << irq_iommu->irte_mask);
230
231 for (entry = start; entry < end; entry++) {
232 set_64bit(&entry->low, 0);
233 set_64bit(&entry->high, 0);
234 }
235 bitmap_release_region(iommu->ir_table->bitmap, index,
236 irq_iommu->irte_mask);
237
238 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
239 }
240
241 /*
242 * source validation type
243 */
244 #define SVT_NO_VERIFY 0x0 /* no verification is required */
245 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
246 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
247
248 /*
249 * source-id qualifier
250 */
251 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
252 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
253 * the third least significant bit
254 */
255 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
256 * the second and third least significant bits
257 */
258 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
259 * the least three significant bits
260 */
261
262 /*
263 * set SVT, SQ and SID fields of irte to verify
264 * source ids of interrupt requests
265 */
266 static void set_irte_sid(struct irte *irte, unsigned int svt,
267 unsigned int sq, unsigned int sid)
268 {
269 if (disable_sourceid_checking)
270 svt = SVT_NO_VERIFY;
271 irte->svt = svt;
272 irte->sq = sq;
273 irte->sid = sid;
274 }
275
276 static int set_ioapic_sid(struct irte *irte, int apic)
277 {
278 int i;
279 u16 sid = 0;
280
281 if (!irte)
282 return -1;
283
284 down_read(&dmar_global_lock);
285 for (i = 0; i < MAX_IO_APICS; i++) {
286 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
287 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
288 break;
289 }
290 }
291 up_read(&dmar_global_lock);
292
293 if (sid == 0) {
294 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
295 return -1;
296 }
297
298 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
299
300 return 0;
301 }
302
303 static int set_hpet_sid(struct irte *irte, u8 id)
304 {
305 int i;
306 u16 sid = 0;
307
308 if (!irte)
309 return -1;
310
311 down_read(&dmar_global_lock);
312 for (i = 0; i < MAX_HPET_TBS; i++) {
313 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
314 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
315 break;
316 }
317 }
318 up_read(&dmar_global_lock);
319
320 if (sid == 0) {
321 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
322 return -1;
323 }
324
325 /*
326 * Should really use SQ_ALL_16. Some platforms are broken.
327 * While we figure out the right quirks for these broken platforms, use
328 * SQ_13_IGNORE_3 for now.
329 */
330 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
331
332 return 0;
333 }
334
335 struct set_msi_sid_data {
336 struct pci_dev *pdev;
337 u16 alias;
338 };
339
340 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
341 {
342 struct set_msi_sid_data *data = opaque;
343
344 data->pdev = pdev;
345 data->alias = alias;
346
347 return 0;
348 }
349
350 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
351 {
352 struct set_msi_sid_data data;
353
354 if (!irte || !dev)
355 return -1;
356
357 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
358
359 /*
360 * DMA alias provides us with a PCI device and alias. The only case
361 * where the it will return an alias on a different bus than the
362 * device is the case of a PCIe-to-PCI bridge, where the alias is for
363 * the subordinate bus. In this case we can only verify the bus.
364 *
365 * If the alias device is on a different bus than our source device
366 * then we have a topology based alias, use it.
367 *
368 * Otherwise, the alias is for a device DMA quirk and we cannot
369 * assume that MSI uses the same requester ID. Therefore use the
370 * original device.
371 */
372 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
373 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
374 PCI_DEVID(PCI_BUS_NUM(data.alias),
375 dev->bus->number));
376 else if (data.pdev->bus->number != dev->bus->number)
377 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
378 else
379 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
380 PCI_DEVID(dev->bus->number, dev->devfn));
381
382 return 0;
383 }
384
385 static int iommu_load_old_irte(struct intel_iommu *iommu)
386 {
387 struct irte __iomem *old_ir_table;
388 phys_addr_t irt_phys;
389 unsigned int i;
390 size_t size;
391 u64 irta;
392
393 if (!is_kdump_kernel()) {
394 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
395 iommu->name);
396 clear_ir_pre_enabled(iommu);
397 iommu_disable_irq_remapping(iommu);
398 return -EINVAL;
399 }
400
401 /* Check whether the old ir-table has the same size as ours */
402 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
403 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
404 != INTR_REMAP_TABLE_REG_SIZE)
405 return -EINVAL;
406
407 irt_phys = irta & VTD_PAGE_MASK;
408 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
409
410 /* Map the old IR table */
411 old_ir_table = ioremap_cache(irt_phys, size);
412 if (!old_ir_table)
413 return -ENOMEM;
414
415 /* Copy data over */
416 memcpy_fromio(iommu->ir_table->base, old_ir_table, size);
417
418 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
419
420 /*
421 * Now check the table for used entries and mark those as
422 * allocated in the bitmap
423 */
424 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
425 if (iommu->ir_table->base[i].present)
426 bitmap_set(iommu->ir_table->bitmap, i, 1);
427 }
428
429 iounmap(old_ir_table);
430
431 return 0;
432 }
433
434
435 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
436 {
437 unsigned long flags;
438 u64 addr;
439 u32 sts;
440
441 addr = virt_to_phys((void *)iommu->ir_table->base);
442
443 raw_spin_lock_irqsave(&iommu->register_lock, flags);
444
445 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
446 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
447
448 /* Set interrupt-remapping table pointer */
449 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
450
451 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
452 readl, (sts & DMA_GSTS_IRTPS), sts);
453 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
454
455 /*
456 * Global invalidation of interrupt entry cache to make sure the
457 * hardware uses the new irq remapping table.
458 */
459 qi_global_iec(iommu);
460 }
461
462 static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
463 {
464 unsigned long flags;
465 u32 sts;
466
467 raw_spin_lock_irqsave(&iommu->register_lock, flags);
468
469 /* Enable interrupt-remapping */
470 iommu->gcmd |= DMA_GCMD_IRE;
471 iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
472 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
473
474 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
475 readl, (sts & DMA_GSTS_IRES), sts);
476
477 /*
478 * With CFI clear in the Global Command register, we should be
479 * protected from dangerous (i.e. compatibility) interrupts
480 * regardless of x2apic status. Check just to be sure.
481 */
482 if (sts & DMA_GSTS_CFIS)
483 WARN(1, KERN_WARNING
484 "Compatibility-format IRQs enabled despite intr remapping;\n"
485 "you are vulnerable to IRQ injection.\n");
486
487 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
488 }
489
490 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
491 {
492 struct ir_table *ir_table;
493 struct page *pages;
494 unsigned long *bitmap;
495
496 if (iommu->ir_table)
497 return 0;
498
499 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
500 if (!ir_table)
501 return -ENOMEM;
502
503 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
504 INTR_REMAP_PAGE_ORDER);
505 if (!pages) {
506 pr_err("IR%d: failed to allocate pages of order %d\n",
507 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
508 goto out_free_table;
509 }
510
511 bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
512 sizeof(long), GFP_ATOMIC);
513 if (bitmap == NULL) {
514 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
515 goto out_free_pages;
516 }
517
518 iommu->ir_domain = irq_domain_add_hierarchy(arch_get_ir_parent_domain(),
519 0, INTR_REMAP_TABLE_ENTRIES,
520 NULL, &intel_ir_domain_ops,
521 iommu);
522 if (!iommu->ir_domain) {
523 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
524 goto out_free_bitmap;
525 }
526 iommu->ir_msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
527
528 ir_table->base = page_address(pages);
529 ir_table->bitmap = bitmap;
530 iommu->ir_table = ir_table;
531
532 /*
533 * If the queued invalidation is already initialized,
534 * shouldn't disable it.
535 */
536 if (!iommu->qi) {
537 /*
538 * Clear previous faults.
539 */
540 dmar_fault(-1, iommu);
541 dmar_disable_qi(iommu);
542
543 if (dmar_enable_qi(iommu)) {
544 pr_err("Failed to enable queued invalidation\n");
545 goto out_free_bitmap;
546 }
547 }
548
549 init_ir_status(iommu);
550
551 if (ir_pre_enabled(iommu)) {
552 if (iommu_load_old_irte(iommu))
553 pr_err("Failed to copy IR table for %s from previous kernel\n",
554 iommu->name);
555 else
556 pr_info("Copied IR table for %s from previous kernel\n",
557 iommu->name);
558 }
559
560 iommu_set_irq_remapping(iommu, eim_mode);
561
562 return 0;
563
564 out_free_bitmap:
565 kfree(bitmap);
566 out_free_pages:
567 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
568 out_free_table:
569 kfree(ir_table);
570
571 iommu->ir_table = NULL;
572
573 return -ENOMEM;
574 }
575
576 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
577 {
578 if (iommu && iommu->ir_table) {
579 if (iommu->ir_msi_domain) {
580 irq_domain_remove(iommu->ir_msi_domain);
581 iommu->ir_msi_domain = NULL;
582 }
583 if (iommu->ir_domain) {
584 irq_domain_remove(iommu->ir_domain);
585 iommu->ir_domain = NULL;
586 }
587 free_pages((unsigned long)iommu->ir_table->base,
588 INTR_REMAP_PAGE_ORDER);
589 kfree(iommu->ir_table->bitmap);
590 kfree(iommu->ir_table);
591 iommu->ir_table = NULL;
592 }
593 }
594
595 /*
596 * Disable Interrupt Remapping.
597 */
598 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
599 {
600 unsigned long flags;
601 u32 sts;
602
603 if (!ecap_ir_support(iommu->ecap))
604 return;
605
606 /*
607 * global invalidation of interrupt entry cache before disabling
608 * interrupt-remapping.
609 */
610 qi_global_iec(iommu);
611
612 raw_spin_lock_irqsave(&iommu->register_lock, flags);
613
614 sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
615 if (!(sts & DMA_GSTS_IRES))
616 goto end;
617
618 iommu->gcmd &= ~DMA_GCMD_IRE;
619 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
620
621 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
622 readl, !(sts & DMA_GSTS_IRES), sts);
623
624 end:
625 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
626 }
627
628 static int __init dmar_x2apic_optout(void)
629 {
630 struct acpi_table_dmar *dmar;
631 dmar = (struct acpi_table_dmar *)dmar_tbl;
632 if (!dmar || no_x2apic_optout)
633 return 0;
634 return dmar->flags & DMAR_X2APIC_OPT_OUT;
635 }
636
637 static void __init intel_cleanup_irq_remapping(void)
638 {
639 struct dmar_drhd_unit *drhd;
640 struct intel_iommu *iommu;
641
642 for_each_iommu(iommu, drhd) {
643 if (ecap_ir_support(iommu->ecap)) {
644 iommu_disable_irq_remapping(iommu);
645 intel_teardown_irq_remapping(iommu);
646 }
647 }
648
649 if (x2apic_supported())
650 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
651 }
652
653 static int __init intel_prepare_irq_remapping(void)
654 {
655 struct dmar_drhd_unit *drhd;
656 struct intel_iommu *iommu;
657 int eim = 0;
658
659 if (irq_remap_broken) {
660 pr_warn("This system BIOS has enabled interrupt remapping\n"
661 "on a chipset that contains an erratum making that\n"
662 "feature unstable. To maintain system stability\n"
663 "interrupt remapping is being disabled. Please\n"
664 "contact your BIOS vendor for an update\n");
665 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
666 return -ENODEV;
667 }
668
669 if (dmar_table_init() < 0)
670 return -ENODEV;
671
672 if (!dmar_ir_support())
673 return -ENODEV;
674
675 if (parse_ioapics_under_ir() != 1) {
676 pr_info("Not enabling interrupt remapping\n");
677 goto error;
678 }
679
680 /* First make sure all IOMMUs support IRQ remapping */
681 for_each_iommu(iommu, drhd)
682 if (!ecap_ir_support(iommu->ecap))
683 goto error;
684
685 /* Detect remapping mode: lapic or x2apic */
686 if (x2apic_supported()) {
687 eim = !dmar_x2apic_optout();
688 if (!eim) {
689 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
690 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
691 }
692 }
693
694 for_each_iommu(iommu, drhd) {
695 if (eim && !ecap_eim_support(iommu->ecap)) {
696 pr_info("%s does not support EIM\n", iommu->name);
697 eim = 0;
698 }
699 }
700
701 eim_mode = eim;
702 if (eim)
703 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
704
705 /* Do the initializations early */
706 for_each_iommu(iommu, drhd) {
707 if (intel_setup_irq_remapping(iommu)) {
708 pr_err("Failed to setup irq remapping for %s\n",
709 iommu->name);
710 goto error;
711 }
712 }
713
714 return 0;
715
716 error:
717 intel_cleanup_irq_remapping();
718 return -ENODEV;
719 }
720
721 /*
722 * Set Posted-Interrupts capability.
723 */
724 static inline void set_irq_posting_cap(void)
725 {
726 struct dmar_drhd_unit *drhd;
727 struct intel_iommu *iommu;
728
729 if (!disable_irq_post) {
730 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
731
732 for_each_iommu(iommu, drhd)
733 if (!cap_pi_support(iommu->cap)) {
734 intel_irq_remap_ops.capability &=
735 ~(1 << IRQ_POSTING_CAP);
736 break;
737 }
738 }
739 }
740
741 static int __init intel_enable_irq_remapping(void)
742 {
743 struct dmar_drhd_unit *drhd;
744 struct intel_iommu *iommu;
745 bool setup = false;
746
747 /*
748 * Setup Interrupt-remapping for all the DRHD's now.
749 */
750 for_each_iommu(iommu, drhd) {
751 if (!ir_pre_enabled(iommu))
752 iommu_enable_irq_remapping(iommu);
753 setup = true;
754 }
755
756 if (!setup)
757 goto error;
758
759 irq_remapping_enabled = 1;
760
761 set_irq_posting_cap();
762
763 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
764
765 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
766
767 error:
768 intel_cleanup_irq_remapping();
769 return -1;
770 }
771
772 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
773 struct intel_iommu *iommu,
774 struct acpi_dmar_hardware_unit *drhd)
775 {
776 struct acpi_dmar_pci_path *path;
777 u8 bus;
778 int count, free = -1;
779
780 bus = scope->bus;
781 path = (struct acpi_dmar_pci_path *)(scope + 1);
782 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
783 / sizeof(struct acpi_dmar_pci_path);
784
785 while (--count > 0) {
786 /*
787 * Access PCI directly due to the PCI
788 * subsystem isn't initialized yet.
789 */
790 bus = read_pci_config_byte(bus, path->device, path->function,
791 PCI_SECONDARY_BUS);
792 path++;
793 }
794
795 for (count = 0; count < MAX_HPET_TBS; count++) {
796 if (ir_hpet[count].iommu == iommu &&
797 ir_hpet[count].id == scope->enumeration_id)
798 return 0;
799 else if (ir_hpet[count].iommu == NULL && free == -1)
800 free = count;
801 }
802 if (free == -1) {
803 pr_warn("Exceeded Max HPET blocks\n");
804 return -ENOSPC;
805 }
806
807 ir_hpet[free].iommu = iommu;
808 ir_hpet[free].id = scope->enumeration_id;
809 ir_hpet[free].bus = bus;
810 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
811 pr_info("HPET id %d under DRHD base 0x%Lx\n",
812 scope->enumeration_id, drhd->address);
813
814 return 0;
815 }
816
817 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
818 struct intel_iommu *iommu,
819 struct acpi_dmar_hardware_unit *drhd)
820 {
821 struct acpi_dmar_pci_path *path;
822 u8 bus;
823 int count, free = -1;
824
825 bus = scope->bus;
826 path = (struct acpi_dmar_pci_path *)(scope + 1);
827 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
828 / sizeof(struct acpi_dmar_pci_path);
829
830 while (--count > 0) {
831 /*
832 * Access PCI directly due to the PCI
833 * subsystem isn't initialized yet.
834 */
835 bus = read_pci_config_byte(bus, path->device, path->function,
836 PCI_SECONDARY_BUS);
837 path++;
838 }
839
840 for (count = 0; count < MAX_IO_APICS; count++) {
841 if (ir_ioapic[count].iommu == iommu &&
842 ir_ioapic[count].id == scope->enumeration_id)
843 return 0;
844 else if (ir_ioapic[count].iommu == NULL && free == -1)
845 free = count;
846 }
847 if (free == -1) {
848 pr_warn("Exceeded Max IO APICS\n");
849 return -ENOSPC;
850 }
851
852 ir_ioapic[free].bus = bus;
853 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
854 ir_ioapic[free].iommu = iommu;
855 ir_ioapic[free].id = scope->enumeration_id;
856 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
857 scope->enumeration_id, drhd->address, iommu->seq_id);
858
859 return 0;
860 }
861
862 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
863 struct intel_iommu *iommu)
864 {
865 int ret = 0;
866 struct acpi_dmar_hardware_unit *drhd;
867 struct acpi_dmar_device_scope *scope;
868 void *start, *end;
869
870 drhd = (struct acpi_dmar_hardware_unit *)header;
871 start = (void *)(drhd + 1);
872 end = ((void *)drhd) + header->length;
873
874 while (start < end && ret == 0) {
875 scope = start;
876 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
877 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
878 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
879 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
880 start += scope->length;
881 }
882
883 return ret;
884 }
885
886 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
887 {
888 int i;
889
890 for (i = 0; i < MAX_HPET_TBS; i++)
891 if (ir_hpet[i].iommu == iommu)
892 ir_hpet[i].iommu = NULL;
893
894 for (i = 0; i < MAX_IO_APICS; i++)
895 if (ir_ioapic[i].iommu == iommu)
896 ir_ioapic[i].iommu = NULL;
897 }
898
899 /*
900 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
901 * hardware unit.
902 */
903 static int __init parse_ioapics_under_ir(void)
904 {
905 struct dmar_drhd_unit *drhd;
906 struct intel_iommu *iommu;
907 bool ir_supported = false;
908 int ioapic_idx;
909
910 for_each_iommu(iommu, drhd)
911 if (ecap_ir_support(iommu->ecap)) {
912 if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
913 return -1;
914
915 ir_supported = true;
916 }
917
918 if (!ir_supported)
919 return 0;
920
921 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
922 int ioapic_id = mpc_ioapic_id(ioapic_idx);
923 if (!map_ioapic_to_ir(ioapic_id)) {
924 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
925 "interrupt remapping will be disabled\n",
926 ioapic_id);
927 return -1;
928 }
929 }
930
931 return 1;
932 }
933
934 static int __init ir_dev_scope_init(void)
935 {
936 int ret;
937
938 if (!irq_remapping_enabled)
939 return 0;
940
941 down_write(&dmar_global_lock);
942 ret = dmar_dev_scope_init();
943 up_write(&dmar_global_lock);
944
945 return ret;
946 }
947 rootfs_initcall(ir_dev_scope_init);
948
949 static void disable_irq_remapping(void)
950 {
951 struct dmar_drhd_unit *drhd;
952 struct intel_iommu *iommu = NULL;
953
954 /*
955 * Disable Interrupt-remapping for all the DRHD's now.
956 */
957 for_each_iommu(iommu, drhd) {
958 if (!ecap_ir_support(iommu->ecap))
959 continue;
960
961 iommu_disable_irq_remapping(iommu);
962 }
963
964 /*
965 * Clear Posted-Interrupts capability.
966 */
967 if (!disable_irq_post)
968 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
969 }
970
971 static int reenable_irq_remapping(int eim)
972 {
973 struct dmar_drhd_unit *drhd;
974 bool setup = false;
975 struct intel_iommu *iommu = NULL;
976
977 for_each_iommu(iommu, drhd)
978 if (iommu->qi)
979 dmar_reenable_qi(iommu);
980
981 /*
982 * Setup Interrupt-remapping for all the DRHD's now.
983 */
984 for_each_iommu(iommu, drhd) {
985 if (!ecap_ir_support(iommu->ecap))
986 continue;
987
988 /* Set up interrupt remapping for iommu.*/
989 iommu_set_irq_remapping(iommu, eim);
990 iommu_enable_irq_remapping(iommu);
991 setup = true;
992 }
993
994 if (!setup)
995 goto error;
996
997 set_irq_posting_cap();
998
999 return 0;
1000
1001 error:
1002 /*
1003 * handle error condition gracefully here!
1004 */
1005 return -1;
1006 }
1007
1008 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1009 {
1010 memset(irte, 0, sizeof(*irte));
1011
1012 irte->present = 1;
1013 irte->dst_mode = apic->irq_dest_mode;
1014 /*
1015 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1016 * actual level or edge trigger will be setup in the IO-APIC
1017 * RTE. This will help simplify level triggered irq migration.
1018 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1019 * irq migration in the presence of interrupt-remapping.
1020 */
1021 irte->trigger_mode = 0;
1022 irte->dlvry_mode = apic->irq_delivery_mode;
1023 irte->vector = vector;
1024 irte->dest_id = IRTE_DEST(dest);
1025 irte->redir_hint = 1;
1026 }
1027
1028 static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
1029 {
1030 struct intel_iommu *iommu = NULL;
1031
1032 if (!info)
1033 return NULL;
1034
1035 switch (info->type) {
1036 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1037 iommu = map_ioapic_to_ir(info->ioapic_id);
1038 break;
1039 case X86_IRQ_ALLOC_TYPE_HPET:
1040 iommu = map_hpet_to_ir(info->hpet_id);
1041 break;
1042 case X86_IRQ_ALLOC_TYPE_MSI:
1043 case X86_IRQ_ALLOC_TYPE_MSIX:
1044 iommu = map_dev_to_ir(info->msi_dev);
1045 break;
1046 default:
1047 BUG_ON(1);
1048 break;
1049 }
1050
1051 return iommu ? iommu->ir_domain : NULL;
1052 }
1053
1054 static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
1055 {
1056 struct intel_iommu *iommu;
1057
1058 if (!info)
1059 return NULL;
1060
1061 switch (info->type) {
1062 case X86_IRQ_ALLOC_TYPE_MSI:
1063 case X86_IRQ_ALLOC_TYPE_MSIX:
1064 iommu = map_dev_to_ir(info->msi_dev);
1065 if (iommu)
1066 return iommu->ir_msi_domain;
1067 break;
1068 default:
1069 break;
1070 }
1071
1072 return NULL;
1073 }
1074
1075 struct irq_remap_ops intel_irq_remap_ops = {
1076 .prepare = intel_prepare_irq_remapping,
1077 .enable = intel_enable_irq_remapping,
1078 .disable = disable_irq_remapping,
1079 .reenable = reenable_irq_remapping,
1080 .enable_faulting = enable_drhd_fault_handling,
1081 .get_ir_irq_domain = intel_get_ir_irq_domain,
1082 .get_irq_domain = intel_get_irq_domain,
1083 };
1084
1085 /*
1086 * Migrate the IO-APIC irq in the presence of intr-remapping.
1087 *
1088 * For both level and edge triggered, irq migration is a simple atomic
1089 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1090 *
1091 * For level triggered, we eliminate the io-apic RTE modification (with the
1092 * updated vector information), by using a virtual vector (io-apic pin number).
1093 * Real vector that is used for interrupting cpu will be coming from
1094 * the interrupt-remapping table entry.
1095 *
1096 * As the migration is a simple atomic update of IRTE, the same mechanism
1097 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1098 */
1099 static int
1100 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1101 bool force)
1102 {
1103 struct intel_ir_data *ir_data = data->chip_data;
1104 struct irte *irte = &ir_data->irte_entry;
1105 struct irq_cfg *cfg = irqd_cfg(data);
1106 struct irq_data *parent = data->parent_data;
1107 int ret;
1108
1109 ret = parent->chip->irq_set_affinity(parent, mask, force);
1110 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1111 return ret;
1112
1113 /*
1114 * Atomically updates the IRTE with the new destination, vector
1115 * and flushes the interrupt entry cache.
1116 */
1117 irte->vector = cfg->vector;
1118 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1119
1120 /* Update the hardware only if the interrupt is in remapped mode. */
1121 if (ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1122 modify_irte(&ir_data->irq_2_iommu, irte);
1123
1124 /*
1125 * After this point, all the interrupts will start arriving
1126 * at the new destination. So, time to cleanup the previous
1127 * vector allocation.
1128 */
1129 send_cleanup_vector(cfg);
1130
1131 return IRQ_SET_MASK_OK_DONE;
1132 }
1133
1134 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1135 struct msi_msg *msg)
1136 {
1137 struct intel_ir_data *ir_data = irq_data->chip_data;
1138
1139 *msg = ir_data->msi_entry;
1140 }
1141
1142 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1143 {
1144 struct intel_ir_data *ir_data = data->chip_data;
1145 struct vcpu_data *vcpu_pi_info = info;
1146
1147 /* stop posting interrupts, back to remapping mode */
1148 if (!vcpu_pi_info) {
1149 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1150 } else {
1151 struct irte irte_pi;
1152
1153 /*
1154 * We are not caching the posted interrupt entry. We
1155 * copy the data from the remapped entry and modify
1156 * the fields which are relevant for posted mode. The
1157 * cached remapped entry is used for switching back to
1158 * remapped mode.
1159 */
1160 memset(&irte_pi, 0, sizeof(irte_pi));
1161 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1162
1163 /* Update the posted mode fields */
1164 irte_pi.p_pst = 1;
1165 irte_pi.p_urgent = 0;
1166 irte_pi.p_vector = vcpu_pi_info->vector;
1167 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1168 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1169 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1170 ~(-1UL << PDA_HIGH_BIT);
1171
1172 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1173 }
1174
1175 return 0;
1176 }
1177
1178 static struct irq_chip intel_ir_chip = {
1179 .irq_ack = ir_ack_apic_edge,
1180 .irq_set_affinity = intel_ir_set_affinity,
1181 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1182 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1183 };
1184
1185 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1186 struct irq_cfg *irq_cfg,
1187 struct irq_alloc_info *info,
1188 int index, int sub_handle)
1189 {
1190 struct IR_IO_APIC_route_entry *entry;
1191 struct irte *irte = &data->irte_entry;
1192 struct msi_msg *msg = &data->msi_entry;
1193
1194 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1195 switch (info->type) {
1196 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1197 /* Set source-id of interrupt request */
1198 set_ioapic_sid(irte, info->ioapic_id);
1199 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1200 info->ioapic_id, irte->present, irte->fpd,
1201 irte->dst_mode, irte->redir_hint,
1202 irte->trigger_mode, irte->dlvry_mode,
1203 irte->avail, irte->vector, irte->dest_id,
1204 irte->sid, irte->sq, irte->svt);
1205
1206 entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
1207 info->ioapic_entry = NULL;
1208 memset(entry, 0, sizeof(*entry));
1209 entry->index2 = (index >> 15) & 0x1;
1210 entry->zero = 0;
1211 entry->format = 1;
1212 entry->index = (index & 0x7fff);
1213 /*
1214 * IO-APIC RTE will be configured with virtual vector.
1215 * irq handler will do the explicit EOI to the io-apic.
1216 */
1217 entry->vector = info->ioapic_pin;
1218 entry->mask = 0; /* enable IRQ */
1219 entry->trigger = info->ioapic_trigger;
1220 entry->polarity = info->ioapic_polarity;
1221 if (info->ioapic_trigger)
1222 entry->mask = 1; /* Mask level triggered irqs. */
1223 break;
1224
1225 case X86_IRQ_ALLOC_TYPE_HPET:
1226 case X86_IRQ_ALLOC_TYPE_MSI:
1227 case X86_IRQ_ALLOC_TYPE_MSIX:
1228 if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
1229 set_hpet_sid(irte, info->hpet_id);
1230 else
1231 set_msi_sid(irte, info->msi_dev);
1232
1233 msg->address_hi = MSI_ADDR_BASE_HI;
1234 msg->data = sub_handle;
1235 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1236 MSI_ADDR_IR_SHV |
1237 MSI_ADDR_IR_INDEX1(index) |
1238 MSI_ADDR_IR_INDEX2(index);
1239 break;
1240
1241 default:
1242 BUG_ON(1);
1243 break;
1244 }
1245 }
1246
1247 static void intel_free_irq_resources(struct irq_domain *domain,
1248 unsigned int virq, unsigned int nr_irqs)
1249 {
1250 struct irq_data *irq_data;
1251 struct intel_ir_data *data;
1252 struct irq_2_iommu *irq_iommu;
1253 unsigned long flags;
1254 int i;
1255 for (i = 0; i < nr_irqs; i++) {
1256 irq_data = irq_domain_get_irq_data(domain, virq + i);
1257 if (irq_data && irq_data->chip_data) {
1258 data = irq_data->chip_data;
1259 irq_iommu = &data->irq_2_iommu;
1260 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1261 clear_entries(irq_iommu);
1262 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1263 irq_domain_reset_irq_data(irq_data);
1264 kfree(data);
1265 }
1266 }
1267 }
1268
1269 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1270 unsigned int virq, unsigned int nr_irqs,
1271 void *arg)
1272 {
1273 struct intel_iommu *iommu = domain->host_data;
1274 struct irq_alloc_info *info = arg;
1275 struct intel_ir_data *data, *ird;
1276 struct irq_data *irq_data;
1277 struct irq_cfg *irq_cfg;
1278 int i, ret, index;
1279
1280 if (!info || !iommu)
1281 return -EINVAL;
1282 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
1283 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
1284 return -EINVAL;
1285
1286 /*
1287 * With IRQ remapping enabled, don't need contiguous CPU vectors
1288 * to support multiple MSI interrupts.
1289 */
1290 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
1291 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1292
1293 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1294 if (ret < 0)
1295 return ret;
1296
1297 ret = -ENOMEM;
1298 data = kzalloc(sizeof(*data), GFP_KERNEL);
1299 if (!data)
1300 goto out_free_parent;
1301
1302 down_read(&dmar_global_lock);
1303 index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs);
1304 up_read(&dmar_global_lock);
1305 if (index < 0) {
1306 pr_warn("Failed to allocate IRTE\n");
1307 kfree(data);
1308 goto out_free_parent;
1309 }
1310
1311 for (i = 0; i < nr_irqs; i++) {
1312 irq_data = irq_domain_get_irq_data(domain, virq + i);
1313 irq_cfg = irqd_cfg(irq_data);
1314 if (!irq_data || !irq_cfg) {
1315 ret = -EINVAL;
1316 goto out_free_data;
1317 }
1318
1319 if (i > 0) {
1320 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1321 if (!ird)
1322 goto out_free_data;
1323 /* Initialize the common data */
1324 ird->irq_2_iommu = data->irq_2_iommu;
1325 ird->irq_2_iommu.sub_handle = i;
1326 } else {
1327 ird = data;
1328 }
1329
1330 irq_data->hwirq = (index << 16) + i;
1331 irq_data->chip_data = ird;
1332 irq_data->chip = &intel_ir_chip;
1333 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1334 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1335 }
1336 return 0;
1337
1338 out_free_data:
1339 intel_free_irq_resources(domain, virq, i);
1340 out_free_parent:
1341 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1342 return ret;
1343 }
1344
1345 static void intel_irq_remapping_free(struct irq_domain *domain,
1346 unsigned int virq, unsigned int nr_irqs)
1347 {
1348 intel_free_irq_resources(domain, virq, nr_irqs);
1349 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1350 }
1351
1352 static void intel_irq_remapping_activate(struct irq_domain *domain,
1353 struct irq_data *irq_data)
1354 {
1355 struct intel_ir_data *data = irq_data->chip_data;
1356
1357 modify_irte(&data->irq_2_iommu, &data->irte_entry);
1358 }
1359
1360 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1361 struct irq_data *irq_data)
1362 {
1363 struct intel_ir_data *data = irq_data->chip_data;
1364 struct irte entry;
1365
1366 memset(&entry, 0, sizeof(entry));
1367 modify_irte(&data->irq_2_iommu, &entry);
1368 }
1369
1370 static struct irq_domain_ops intel_ir_domain_ops = {
1371 .alloc = intel_irq_remapping_alloc,
1372 .free = intel_irq_remapping_free,
1373 .activate = intel_irq_remapping_activate,
1374 .deactivate = intel_irq_remapping_deactivate,
1375 };
1376
1377 /*
1378 * Support of Interrupt Remapping Unit Hotplug
1379 */
1380 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1381 {
1382 int ret;
1383 int eim = x2apic_enabled();
1384
1385 if (eim && !ecap_eim_support(iommu->ecap)) {
1386 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1387 iommu->reg_phys, iommu->ecap);
1388 return -ENODEV;
1389 }
1390
1391 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1392 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1393 iommu->reg_phys);
1394 return -ENODEV;
1395 }
1396
1397 /* TODO: check all IOAPICs are covered by IOMMU */
1398
1399 /* Setup Interrupt-remapping now. */
1400 ret = intel_setup_irq_remapping(iommu);
1401 if (ret) {
1402 pr_err("Failed to setup irq remapping for %s\n",
1403 iommu->name);
1404 intel_teardown_irq_remapping(iommu);
1405 ir_remove_ioapic_hpet_scope(iommu);
1406 } else {
1407 iommu_enable_irq_remapping(iommu);
1408 }
1409
1410 return ret;
1411 }
1412
1413 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1414 {
1415 int ret = 0;
1416 struct intel_iommu *iommu = dmaru->iommu;
1417
1418 if (!irq_remapping_enabled)
1419 return 0;
1420 if (iommu == NULL)
1421 return -EINVAL;
1422 if (!ecap_ir_support(iommu->ecap))
1423 return 0;
1424 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1425 !cap_pi_support(iommu->cap))
1426 return -EBUSY;
1427
1428 if (insert) {
1429 if (!iommu->ir_table)
1430 ret = dmar_ir_add(dmaru, iommu);
1431 } else {
1432 if (iommu->ir_table) {
1433 if (!bitmap_empty(iommu->ir_table->bitmap,
1434 INTR_REMAP_TABLE_ENTRIES)) {
1435 ret = -EBUSY;
1436 } else {
1437 iommu_disable_irq_remapping(iommu);
1438 intel_teardown_irq_remapping(iommu);
1439 ir_remove_ioapic_hpet_scope(iommu);
1440 }
1441 }
1442 }
1443
1444 return ret;
1445 }
Linux kernel - Deliverables
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