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[deliverable/linux.git] / drivers / iommu / intel_irq_remapping.c
1 #include <linux/interrupt.h>
2 #include <linux/dmar.h>
3 #include <linux/spinlock.h>
4 #include <linux/slab.h>
5 #include <linux/jiffies.h>
6 #include <linux/hpet.h>
7 #include <linux/pci.h>
8 #include <linux/irq.h>
9 #include <asm/io_apic.h>
10 #include <asm/smp.h>
11 #include <asm/cpu.h>
12 #include <linux/intel-iommu.h>
13 #include <acpi/acpi.h>
14 #include <asm/irq_remapping.h>
15 #include <asm/pci-direct.h>
16 #include <asm/msidef.h>
17
18 #include "irq_remapping.h"
19
20 struct ioapic_scope {
21 struct intel_iommu *iommu;
22 unsigned int id;
23 unsigned int bus; /* PCI bus number */
24 unsigned int devfn; /* PCI devfn number */
25 };
26
27 struct hpet_scope {
28 struct intel_iommu *iommu;
29 u8 id;
30 unsigned int bus;
31 unsigned int devfn;
32 };
33
34 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
35 #define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
36
37 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
38 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
39 static int ir_ioapic_num, ir_hpet_num;
40
41 static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
42
43 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
44 {
45 struct irq_cfg *cfg = irq_get_chip_data(irq);
46 return cfg ? &cfg->irq_2_iommu : NULL;
47 }
48
49 static int get_irte(int irq, struct irte *entry)
50 {
51 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
52 unsigned long flags;
53 int index;
54
55 if (!entry || !irq_iommu)
56 return -1;
57
58 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
59
60 index = irq_iommu->irte_index + irq_iommu->sub_handle;
61 *entry = *(irq_iommu->iommu->ir_table->base + index);
62
63 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
64 return 0;
65 }
66
67 static int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
68 {
69 struct ir_table *table = iommu->ir_table;
70 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
71 struct irq_cfg *cfg = irq_get_chip_data(irq);
72 u16 index, start_index;
73 unsigned int mask = 0;
74 unsigned long flags;
75
76 if (!count || !irq_iommu)
77 return -1;
78
79 /*
80 * start the IRTE search from index 0.
81 */
82 index = start_index = 0;
83
84 if (count > 1) {
85 count = __roundup_pow_of_two(count);
86 mask = ilog2(count);
87 }
88
89 if (mask > ecap_max_handle_mask(iommu->ecap)) {
90 printk(KERN_ERR
91 "Requested mask %x exceeds the max invalidation handle"
92 " mask value %Lx\n", mask,
93 ecap_max_handle_mask(iommu->ecap));
94 return -1;
95 }
96
97 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
98 index = bitmap_find_free_region(table->bitmap,
99 INTR_REMAP_TABLE_ENTRIES, mask);
100 if (index < 0) {
101 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
102 } else {
103 cfg->remapped = 1;
104 irq_iommu->iommu = iommu;
105 irq_iommu->irte_index = index;
106 irq_iommu->sub_handle = 0;
107 irq_iommu->irte_mask = mask;
108 }
109 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
110
111 return index;
112 }
113
114 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
115 {
116 struct qi_desc desc;
117
118 desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
119 | QI_IEC_SELECTIVE;
120 desc.high = 0;
121
122 return qi_submit_sync(&desc, iommu);
123 }
124
125 static int map_irq_to_irte_handle(int irq, u16 *sub_handle)
126 {
127 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
128 unsigned long flags;
129 int index;
130
131 if (!irq_iommu)
132 return -1;
133
134 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
135 *sub_handle = irq_iommu->sub_handle;
136 index = irq_iommu->irte_index;
137 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
138 return index;
139 }
140
141 static int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
142 {
143 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
144 struct irq_cfg *cfg = irq_get_chip_data(irq);
145 unsigned long flags;
146
147 if (!irq_iommu)
148 return -1;
149
150 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
151
152 cfg->remapped = 1;
153 irq_iommu->iommu = iommu;
154 irq_iommu->irte_index = index;
155 irq_iommu->sub_handle = subhandle;
156 irq_iommu->irte_mask = 0;
157
158 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
159
160 return 0;
161 }
162
163 static int modify_irte(int irq, struct irte *irte_modified)
164 {
165 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
166 struct intel_iommu *iommu;
167 unsigned long flags;
168 struct irte *irte;
169 int rc, index;
170
171 if (!irq_iommu)
172 return -1;
173
174 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
175
176 iommu = irq_iommu->iommu;
177
178 index = irq_iommu->irte_index + irq_iommu->sub_handle;
179 irte = &iommu->ir_table->base[index];
180
181 set_64bit(&irte->low, irte_modified->low);
182 set_64bit(&irte->high, irte_modified->high);
183 __iommu_flush_cache(iommu, irte, sizeof(*irte));
184
185 rc = qi_flush_iec(iommu, index, 0);
186 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
187
188 return rc;
189 }
190
191 static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
192 {
193 int i;
194
195 for (i = 0; i < MAX_HPET_TBS; i++)
196 if (ir_hpet[i].id == hpet_id)
197 return ir_hpet[i].iommu;
198 return NULL;
199 }
200
201 static struct intel_iommu *map_ioapic_to_ir(int apic)
202 {
203 int i;
204
205 for (i = 0; i < MAX_IO_APICS; i++)
206 if (ir_ioapic[i].id == apic)
207 return ir_ioapic[i].iommu;
208 return NULL;
209 }
210
211 static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
212 {
213 struct dmar_drhd_unit *drhd;
214
215 drhd = dmar_find_matched_drhd_unit(dev);
216 if (!drhd)
217 return NULL;
218
219 return drhd->iommu;
220 }
221
222 static int clear_entries(struct irq_2_iommu *irq_iommu)
223 {
224 struct irte *start, *entry, *end;
225 struct intel_iommu *iommu;
226 int index;
227
228 if (irq_iommu->sub_handle)
229 return 0;
230
231 iommu = irq_iommu->iommu;
232 index = irq_iommu->irte_index + irq_iommu->sub_handle;
233
234 start = iommu->ir_table->base + index;
235 end = start + (1 << irq_iommu->irte_mask);
236
237 for (entry = start; entry < end; entry++) {
238 set_64bit(&entry->low, 0);
239 set_64bit(&entry->high, 0);
240 }
241 bitmap_release_region(iommu->ir_table->bitmap, index,
242 irq_iommu->irte_mask);
243
244 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
245 }
246
247 static int free_irte(int irq)
248 {
249 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
250 unsigned long flags;
251 int rc;
252
253 if (!irq_iommu)
254 return -1;
255
256 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
257
258 rc = clear_entries(irq_iommu);
259
260 irq_iommu->iommu = NULL;
261 irq_iommu->irte_index = 0;
262 irq_iommu->sub_handle = 0;
263 irq_iommu->irte_mask = 0;
264
265 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
266
267 return rc;
268 }
269
270 /*
271 * source validation type
272 */
273 #define SVT_NO_VERIFY 0x0 /* no verification is required */
274 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
275 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
276
277 /*
278 * source-id qualifier
279 */
280 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
281 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
282 * the third least significant bit
283 */
284 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
285 * the second and third least significant bits
286 */
287 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
288 * the least three significant bits
289 */
290
291 /*
292 * set SVT, SQ and SID fields of irte to verify
293 * source ids of interrupt requests
294 */
295 static void set_irte_sid(struct irte *irte, unsigned int svt,
296 unsigned int sq, unsigned int sid)
297 {
298 if (disable_sourceid_checking)
299 svt = SVT_NO_VERIFY;
300 irte->svt = svt;
301 irte->sq = sq;
302 irte->sid = sid;
303 }
304
305 static int set_ioapic_sid(struct irte *irte, int apic)
306 {
307 int i;
308 u16 sid = 0;
309
310 if (!irte)
311 return -1;
312
313 for (i = 0; i < MAX_IO_APICS; i++) {
314 if (ir_ioapic[i].id == apic) {
315 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
316 break;
317 }
318 }
319
320 if (sid == 0) {
321 pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic);
322 return -1;
323 }
324
325 set_irte_sid(irte, 1, 0, sid);
326
327 return 0;
328 }
329
330 static int set_hpet_sid(struct irte *irte, u8 id)
331 {
332 int i;
333 u16 sid = 0;
334
335 if (!irte)
336 return -1;
337
338 for (i = 0; i < MAX_HPET_TBS; i++) {
339 if (ir_hpet[i].id == id) {
340 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
341 break;
342 }
343 }
344
345 if (sid == 0) {
346 pr_warning("Failed to set source-id of HPET block (%d)\n", id);
347 return -1;
348 }
349
350 /*
351 * Should really use SQ_ALL_16. Some platforms are broken.
352 * While we figure out the right quirks for these broken platforms, use
353 * SQ_13_IGNORE_3 for now.
354 */
355 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
356
357 return 0;
358 }
359
360 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
361 {
362 struct pci_dev *bridge;
363
364 if (!irte || !dev)
365 return -1;
366
367 /* PCIe device or Root Complex integrated PCI device */
368 if (pci_is_pcie(dev) || !dev->bus->parent) {
369 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
370 (dev->bus->number << 8) | dev->devfn);
371 return 0;
372 }
373
374 bridge = pci_find_upstream_pcie_bridge(dev);
375 if (bridge) {
376 if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */
377 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
378 (bridge->bus->number << 8) | dev->bus->number);
379 else /* this is a legacy PCI bridge */
380 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
381 (bridge->bus->number << 8) | bridge->devfn);
382 }
383
384 return 0;
385 }
386
387 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
388 {
389 u64 addr;
390 u32 sts;
391 unsigned long flags;
392
393 addr = virt_to_phys((void *)iommu->ir_table->base);
394
395 raw_spin_lock_irqsave(&iommu->register_lock, flags);
396
397 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
398 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
399
400 /* Set interrupt-remapping table pointer */
401 iommu->gcmd |= DMA_GCMD_SIRTP;
402 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
403
404 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
405 readl, (sts & DMA_GSTS_IRTPS), sts);
406 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
407
408 /*
409 * global invalidation of interrupt entry cache before enabling
410 * interrupt-remapping.
411 */
412 qi_global_iec(iommu);
413
414 raw_spin_lock_irqsave(&iommu->register_lock, flags);
415
416 /* Enable interrupt-remapping */
417 iommu->gcmd |= DMA_GCMD_IRE;
418 iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
419 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
420
421 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
422 readl, (sts & DMA_GSTS_IRES), sts);
423
424 /*
425 * With CFI clear in the Global Command register, we should be
426 * protected from dangerous (i.e. compatibility) interrupts
427 * regardless of x2apic status. Check just to be sure.
428 */
429 if (sts & DMA_GSTS_CFIS)
430 WARN(1, KERN_WARNING
431 "Compatibility-format IRQs enabled despite intr remapping;\n"
432 "you are vulnerable to IRQ injection.\n");
433
434 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
435 }
436
437
438 static int intel_setup_irq_remapping(struct intel_iommu *iommu, int mode)
439 {
440 struct ir_table *ir_table;
441 struct page *pages;
442 unsigned long *bitmap;
443
444 ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
445 GFP_ATOMIC);
446
447 if (!iommu->ir_table)
448 return -ENOMEM;
449
450 pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,
451 INTR_REMAP_PAGE_ORDER);
452
453 if (!pages) {
454 pr_err("IR%d: failed to allocate pages of order %d\n",
455 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
456 kfree(iommu->ir_table);
457 return -ENOMEM;
458 }
459
460 bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
461 sizeof(long), GFP_ATOMIC);
462 if (bitmap == NULL) {
463 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
464 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
465 kfree(ir_table);
466 return -ENOMEM;
467 }
468
469 ir_table->base = page_address(pages);
470 ir_table->bitmap = bitmap;
471
472 iommu_set_irq_remapping(iommu, mode);
473 return 0;
474 }
475
476 /*
477 * Disable Interrupt Remapping.
478 */
479 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
480 {
481 unsigned long flags;
482 u32 sts;
483
484 if (!ecap_ir_support(iommu->ecap))
485 return;
486
487 /*
488 * global invalidation of interrupt entry cache before disabling
489 * interrupt-remapping.
490 */
491 qi_global_iec(iommu);
492
493 raw_spin_lock_irqsave(&iommu->register_lock, flags);
494
495 sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
496 if (!(sts & DMA_GSTS_IRES))
497 goto end;
498
499 iommu->gcmd &= ~DMA_GCMD_IRE;
500 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
501
502 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
503 readl, !(sts & DMA_GSTS_IRES), sts);
504
505 end:
506 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
507 }
508
509 static int __init dmar_x2apic_optout(void)
510 {
511 struct acpi_table_dmar *dmar;
512 dmar = (struct acpi_table_dmar *)dmar_tbl;
513 if (!dmar || no_x2apic_optout)
514 return 0;
515 return dmar->flags & DMAR_X2APIC_OPT_OUT;
516 }
517
518 static int __init intel_irq_remapping_supported(void)
519 {
520 struct dmar_drhd_unit *drhd;
521
522 if (disable_irq_remap)
523 return 0;
524 if (irq_remap_broken) {
525 printk(KERN_WARNING
526 "This system BIOS has enabled interrupt remapping\n"
527 "on a chipset that contains an erratum making that\n"
528 "feature unstable. To maintain system stability\n"
529 "interrupt remapping is being disabled. Please\n"
530 "contact your BIOS vendor for an update\n");
531 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
532 disable_irq_remap = 1;
533 return 0;
534 }
535
536 if (!dmar_ir_support())
537 return 0;
538
539 for_each_drhd_unit(drhd) {
540 struct intel_iommu *iommu = drhd->iommu;
541
542 if (!ecap_ir_support(iommu->ecap))
543 return 0;
544 }
545
546 return 1;
547 }
548
549 static int __init intel_enable_irq_remapping(void)
550 {
551 struct dmar_drhd_unit *drhd;
552 bool x2apic_present;
553 int setup = 0;
554 int eim = 0;
555
556 x2apic_present = x2apic_supported();
557
558 if (parse_ioapics_under_ir() != 1) {
559 printk(KERN_INFO "Not enable interrupt remapping\n");
560 goto error;
561 }
562
563 if (x2apic_present) {
564 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
565
566 eim = !dmar_x2apic_optout();
567 if (!eim)
568 printk(KERN_WARNING
569 "Your BIOS is broken and requested that x2apic be disabled.\n"
570 "This will slightly decrease performance.\n"
571 "Use 'intremap=no_x2apic_optout' to override BIOS request.\n");
572 }
573
574 for_each_drhd_unit(drhd) {
575 struct intel_iommu *iommu = drhd->iommu;
576
577 /*
578 * If the queued invalidation is already initialized,
579 * shouldn't disable it.
580 */
581 if (iommu->qi)
582 continue;
583
584 /*
585 * Clear previous faults.
586 */
587 dmar_fault(-1, iommu);
588
589 /*
590 * Disable intr remapping and queued invalidation, if already
591 * enabled prior to OS handover.
592 */
593 iommu_disable_irq_remapping(iommu);
594
595 dmar_disable_qi(iommu);
596 }
597
598 /*
599 * check for the Interrupt-remapping support
600 */
601 for_each_drhd_unit(drhd) {
602 struct intel_iommu *iommu = drhd->iommu;
603
604 if (!ecap_ir_support(iommu->ecap))
605 continue;
606
607 if (eim && !ecap_eim_support(iommu->ecap)) {
608 printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
609 " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
610 goto error;
611 }
612 }
613
614 /*
615 * Enable queued invalidation for all the DRHD's.
616 */
617 for_each_drhd_unit(drhd) {
618 int ret;
619 struct intel_iommu *iommu = drhd->iommu;
620 ret = dmar_enable_qi(iommu);
621
622 if (ret) {
623 printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
624 " invalidation, ecap %Lx, ret %d\n",
625 drhd->reg_base_addr, iommu->ecap, ret);
626 goto error;
627 }
628 }
629
630 /*
631 * Setup Interrupt-remapping for all the DRHD's now.
632 */
633 for_each_drhd_unit(drhd) {
634 struct intel_iommu *iommu = drhd->iommu;
635
636 if (!ecap_ir_support(iommu->ecap))
637 continue;
638
639 if (intel_setup_irq_remapping(iommu, eim))
640 goto error;
641
642 setup = 1;
643 }
644
645 if (!setup)
646 goto error;
647
648 irq_remapping_enabled = 1;
649
650 /*
651 * VT-d has a different layout for IO-APIC entries when
652 * interrupt remapping is enabled. So it needs a special routine
653 * to print IO-APIC entries for debugging purposes too.
654 */
655 x86_io_apic_ops.print_entries = intel_ir_io_apic_print_entries;
656
657 pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic");
658
659 return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
660
661 error:
662 /*
663 * handle error condition gracefully here!
664 */
665
666 if (x2apic_present)
667 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
668
669 return -1;
670 }
671
672 static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
673 struct intel_iommu *iommu)
674 {
675 struct acpi_dmar_pci_path *path;
676 u8 bus;
677 int count;
678
679 bus = scope->bus;
680 path = (struct acpi_dmar_pci_path *)(scope + 1);
681 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
682 / sizeof(struct acpi_dmar_pci_path);
683
684 while (--count > 0) {
685 /*
686 * Access PCI directly due to the PCI
687 * subsystem isn't initialized yet.
688 */
689 bus = read_pci_config_byte(bus, path->device, path->function,
690 PCI_SECONDARY_BUS);
691 path++;
692 }
693 ir_hpet[ir_hpet_num].bus = bus;
694 ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->device, path->function);
695 ir_hpet[ir_hpet_num].iommu = iommu;
696 ir_hpet[ir_hpet_num].id = scope->enumeration_id;
697 ir_hpet_num++;
698 }
699
700 static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
701 struct intel_iommu *iommu)
702 {
703 struct acpi_dmar_pci_path *path;
704 u8 bus;
705 int count;
706
707 bus = scope->bus;
708 path = (struct acpi_dmar_pci_path *)(scope + 1);
709 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
710 / sizeof(struct acpi_dmar_pci_path);
711
712 while (--count > 0) {
713 /*
714 * Access PCI directly due to the PCI
715 * subsystem isn't initialized yet.
716 */
717 bus = read_pci_config_byte(bus, path->device, path->function,
718 PCI_SECONDARY_BUS);
719 path++;
720 }
721
722 ir_ioapic[ir_ioapic_num].bus = bus;
723 ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->device, path->function);
724 ir_ioapic[ir_ioapic_num].iommu = iommu;
725 ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
726 ir_ioapic_num++;
727 }
728
729 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
730 struct intel_iommu *iommu)
731 {
732 struct acpi_dmar_hardware_unit *drhd;
733 struct acpi_dmar_device_scope *scope;
734 void *start, *end;
735
736 drhd = (struct acpi_dmar_hardware_unit *)header;
737
738 start = (void *)(drhd + 1);
739 end = ((void *)drhd) + header->length;
740
741 while (start < end) {
742 scope = start;
743 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
744 if (ir_ioapic_num == MAX_IO_APICS) {
745 printk(KERN_WARNING "Exceeded Max IO APICS\n");
746 return -1;
747 }
748
749 printk(KERN_INFO "IOAPIC id %d under DRHD base "
750 " 0x%Lx IOMMU %d\n", scope->enumeration_id,
751 drhd->address, iommu->seq_id);
752
753 ir_parse_one_ioapic_scope(scope, iommu);
754 } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) {
755 if (ir_hpet_num == MAX_HPET_TBS) {
756 printk(KERN_WARNING "Exceeded Max HPET blocks\n");
757 return -1;
758 }
759
760 printk(KERN_INFO "HPET id %d under DRHD base"
761 " 0x%Lx\n", scope->enumeration_id,
762 drhd->address);
763
764 ir_parse_one_hpet_scope(scope, iommu);
765 }
766 start += scope->length;
767 }
768
769 return 0;
770 }
771
772 /*
773 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
774 * hardware unit.
775 */
776 int __init parse_ioapics_under_ir(void)
777 {
778 struct dmar_drhd_unit *drhd;
779 int ir_supported = 0;
780 int ioapic_idx;
781
782 for_each_drhd_unit(drhd) {
783 struct intel_iommu *iommu = drhd->iommu;
784
785 if (ecap_ir_support(iommu->ecap)) {
786 if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
787 return -1;
788
789 ir_supported = 1;
790 }
791 }
792
793 if (!ir_supported)
794 return 0;
795
796 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
797 int ioapic_id = mpc_ioapic_id(ioapic_idx);
798 if (!map_ioapic_to_ir(ioapic_id)) {
799 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
800 "interrupt remapping will be disabled\n",
801 ioapic_id);
802 return -1;
803 }
804 }
805
806 return 1;
807 }
808
809 static int __init ir_dev_scope_init(void)
810 {
811 if (!irq_remapping_enabled)
812 return 0;
813
814 return dmar_dev_scope_init();
815 }
816 rootfs_initcall(ir_dev_scope_init);
817
818 static void disable_irq_remapping(void)
819 {
820 struct dmar_drhd_unit *drhd;
821 struct intel_iommu *iommu = NULL;
822
823 /*
824 * Disable Interrupt-remapping for all the DRHD's now.
825 */
826 for_each_iommu(iommu, drhd) {
827 if (!ecap_ir_support(iommu->ecap))
828 continue;
829
830 iommu_disable_irq_remapping(iommu);
831 }
832 }
833
834 static int reenable_irq_remapping(int eim)
835 {
836 struct dmar_drhd_unit *drhd;
837 int setup = 0;
838 struct intel_iommu *iommu = NULL;
839
840 for_each_iommu(iommu, drhd)
841 if (iommu->qi)
842 dmar_reenable_qi(iommu);
843
844 /*
845 * Setup Interrupt-remapping for all the DRHD's now.
846 */
847 for_each_iommu(iommu, drhd) {
848 if (!ecap_ir_support(iommu->ecap))
849 continue;
850
851 /* Set up interrupt remapping for iommu.*/
852 iommu_set_irq_remapping(iommu, eim);
853 setup = 1;
854 }
855
856 if (!setup)
857 goto error;
858
859 return 0;
860
861 error:
862 /*
863 * handle error condition gracefully here!
864 */
865 return -1;
866 }
867
868 static void prepare_irte(struct irte *irte, int vector,
869 unsigned int dest)
870 {
871 memset(irte, 0, sizeof(*irte));
872
873 irte->present = 1;
874 irte->dst_mode = apic->irq_dest_mode;
875 /*
876 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
877 * actual level or edge trigger will be setup in the IO-APIC
878 * RTE. This will help simplify level triggered irq migration.
879 * For more details, see the comments (in io_apic.c) explainig IO-APIC
880 * irq migration in the presence of interrupt-remapping.
881 */
882 irte->trigger_mode = 0;
883 irte->dlvry_mode = apic->irq_delivery_mode;
884 irte->vector = vector;
885 irte->dest_id = IRTE_DEST(dest);
886 irte->redir_hint = 1;
887 }
888
889 static int intel_setup_ioapic_entry(int irq,
890 struct IO_APIC_route_entry *route_entry,
891 unsigned int destination, int vector,
892 struct io_apic_irq_attr *attr)
893 {
894 int ioapic_id = mpc_ioapic_id(attr->ioapic);
895 struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id);
896 struct IR_IO_APIC_route_entry *entry;
897 struct irte irte;
898 int index;
899
900 if (!iommu) {
901 pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
902 return -ENODEV;
903 }
904
905 entry = (struct IR_IO_APIC_route_entry *)route_entry;
906
907 index = alloc_irte(iommu, irq, 1);
908 if (index < 0) {
909 pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id);
910 return -ENOMEM;
911 }
912
913 prepare_irte(&irte, vector, destination);
914
915 /* Set source-id of interrupt request */
916 set_ioapic_sid(&irte, ioapic_id);
917
918 modify_irte(irq, &irte);
919
920 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
921 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
922 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
923 "Avail:%X Vector:%02X Dest:%08X "
924 "SID:%04X SQ:%X SVT:%X)\n",
925 attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
926 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
927 irte.avail, irte.vector, irte.dest_id,
928 irte.sid, irte.sq, irte.svt);
929
930 memset(entry, 0, sizeof(*entry));
931
932 entry->index2 = (index >> 15) & 0x1;
933 entry->zero = 0;
934 entry->format = 1;
935 entry->index = (index & 0x7fff);
936 /*
937 * IO-APIC RTE will be configured with virtual vector.
938 * irq handler will do the explicit EOI to the io-apic.
939 */
940 entry->vector = attr->ioapic_pin;
941 entry->mask = 0; /* enable IRQ */
942 entry->trigger = attr->trigger;
943 entry->polarity = attr->polarity;
944
945 /* Mask level triggered irqs.
946 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
947 */
948 if (attr->trigger)
949 entry->mask = 1;
950
951 return 0;
952 }
953
954 /*
955 * Migrate the IO-APIC irq in the presence of intr-remapping.
956 *
957 * For both level and edge triggered, irq migration is a simple atomic
958 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
959 *
960 * For level triggered, we eliminate the io-apic RTE modification (with the
961 * updated vector information), by using a virtual vector (io-apic pin number).
962 * Real vector that is used for interrupting cpu will be coming from
963 * the interrupt-remapping table entry.
964 *
965 * As the migration is a simple atomic update of IRTE, the same mechanism
966 * is used to migrate MSI irq's in the presence of interrupt-remapping.
967 */
968 static int
969 intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
970 bool force)
971 {
972 struct irq_cfg *cfg = data->chip_data;
973 unsigned int dest, irq = data->irq;
974 struct irte irte;
975 int err;
976
977 if (!config_enabled(CONFIG_SMP))
978 return -EINVAL;
979
980 if (!cpumask_intersects(mask, cpu_online_mask))
981 return -EINVAL;
982
983 if (get_irte(irq, &irte))
984 return -EBUSY;
985
986 err = assign_irq_vector(irq, cfg, mask);
987 if (err)
988 return err;
989
990 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
991 if (err) {
992 if (assign_irq_vector(irq, cfg, data->affinity))
993 pr_err("Failed to recover vector for irq %d\n", irq);
994 return err;
995 }
996
997 irte.vector = cfg->vector;
998 irte.dest_id = IRTE_DEST(dest);
999
1000 /*
1001 * Atomically updates the IRTE with the new destination, vector
1002 * and flushes the interrupt entry cache.
1003 */
1004 modify_irte(irq, &irte);
1005
1006 /*
1007 * After this point, all the interrupts will start arriving
1008 * at the new destination. So, time to cleanup the previous
1009 * vector allocation.
1010 */
1011 if (cfg->move_in_progress)
1012 send_cleanup_vector(cfg);
1013
1014 cpumask_copy(data->affinity, mask);
1015 return 0;
1016 }
1017
1018 static void intel_compose_msi_msg(struct pci_dev *pdev,
1019 unsigned int irq, unsigned int dest,
1020 struct msi_msg *msg, u8 hpet_id)
1021 {
1022 struct irq_cfg *cfg;
1023 struct irte irte;
1024 u16 sub_handle = 0;
1025 int ir_index;
1026
1027 cfg = irq_get_chip_data(irq);
1028
1029 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
1030 BUG_ON(ir_index == -1);
1031
1032 prepare_irte(&irte, cfg->vector, dest);
1033
1034 /* Set source-id of interrupt request */
1035 if (pdev)
1036 set_msi_sid(&irte, pdev);
1037 else
1038 set_hpet_sid(&irte, hpet_id);
1039
1040 modify_irte(irq, &irte);
1041
1042 msg->address_hi = MSI_ADDR_BASE_HI;
1043 msg->data = sub_handle;
1044 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1045 MSI_ADDR_IR_SHV |
1046 MSI_ADDR_IR_INDEX1(ir_index) |
1047 MSI_ADDR_IR_INDEX2(ir_index);
1048 }
1049
1050 /*
1051 * Map the PCI dev to the corresponding remapping hardware unit
1052 * and allocate 'nvec' consecutive interrupt-remapping table entries
1053 * in it.
1054 */
1055 static int intel_msi_alloc_irq(struct pci_dev *dev, int irq, int nvec)
1056 {
1057 struct intel_iommu *iommu;
1058 int index;
1059
1060 iommu = map_dev_to_ir(dev);
1061 if (!iommu) {
1062 printk(KERN_ERR
1063 "Unable to map PCI %s to iommu\n", pci_name(dev));
1064 return -ENOENT;
1065 }
1066
1067 index = alloc_irte(iommu, irq, nvec);
1068 if (index < 0) {
1069 printk(KERN_ERR
1070 "Unable to allocate %d IRTE for PCI %s\n", nvec,
1071 pci_name(dev));
1072 return -ENOSPC;
1073 }
1074 return index;
1075 }
1076
1077 static int intel_msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
1078 int index, int sub_handle)
1079 {
1080 struct intel_iommu *iommu;
1081
1082 iommu = map_dev_to_ir(pdev);
1083 if (!iommu)
1084 return -ENOENT;
1085 /*
1086 * setup the mapping between the irq and the IRTE
1087 * base index, the sub_handle pointing to the
1088 * appropriate interrupt remap table entry.
1089 */
1090 set_irte_irq(irq, iommu, index, sub_handle);
1091
1092 return 0;
1093 }
1094
1095 static int intel_setup_hpet_msi(unsigned int irq, unsigned int id)
1096 {
1097 struct intel_iommu *iommu = map_hpet_to_ir(id);
1098 int index;
1099
1100 if (!iommu)
1101 return -1;
1102
1103 index = alloc_irte(iommu, irq, 1);
1104 if (index < 0)
1105 return -1;
1106
1107 return 0;
1108 }
1109
1110 struct irq_remap_ops intel_irq_remap_ops = {
1111 .supported = intel_irq_remapping_supported,
1112 .prepare = dmar_table_init,
1113 .enable = intel_enable_irq_remapping,
1114 .disable = disable_irq_remapping,
1115 .reenable = reenable_irq_remapping,
1116 .enable_faulting = enable_drhd_fault_handling,
1117 .setup_ioapic_entry = intel_setup_ioapic_entry,
1118 .set_affinity = intel_ioapic_set_affinity,
1119 .free_irq = free_irte,
1120 .compose_msi_msg = intel_compose_msi_msg,
1121 .msi_alloc_irq = intel_msi_alloc_irq,
1122 .msi_setup_irq = intel_msi_setup_irq,
1123 .setup_hpet_msi = intel_setup_hpet_msi,
1124 };
Linux kernel - Deliverables
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