drivers/iommu/ipmmu-vmsa.c

   1 /*
   2  * IPMMU VMSA
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/export.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/iommu.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_data/ipmmu-vmsa.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/sizes.h>
  23 #include <linux/slab.h>
  24
  25 #include <asm/dma-iommu.h>
  26 #include <asm/pgalloc.h>
  27
  28 struct ipmmu_vmsa_device {
  29         struct device *dev;
  30         void __iomem *base;
  31         struct list_head list;
  32
  33         const struct ipmmu_vmsa_platform_data *pdata;
  34         unsigned int num_utlbs;
  35
  36         struct dma_iommu_mapping *mapping;
  37 };
  38
  39 struct ipmmu_vmsa_domain {
  40         struct ipmmu_vmsa_device *mmu;
  41         struct iommu_domain *io_domain;
  42
  43         unsigned int context_id;
  44         spinlock_t lock;                        /* Protects mappings */
  45         pgd_t *pgd;
  46 };
  47
  48 struct ipmmu_vmsa_archdata {
  49         struct ipmmu_vmsa_device *mmu;
  50         unsigned int *utlbs;
  51         unsigned int num_utlbs;
  52 };
  53
  54 static DEFINE_SPINLOCK(ipmmu_devices_lock);
  55 static LIST_HEAD(ipmmu_devices);
  56
  57 #define TLB_LOOP_TIMEOUT                100     /* 100us */
  58
  59 /* -----------------------------------------------------------------------------
  60  * Registers Definition
  61  */
  62
  63 #define IM_NS_ALIAS_OFFSET              0x800
  64
  65 #define IM_CTX_SIZE                     0x40
  66
  67 #define IMCTR                           0x0000
  68 #define IMCTR_TRE                       (1 << 17)
  69 #define IMCTR_AFE                       (1 << 16)
  70 #define IMCTR_RTSEL_MASK                (3 << 4)
  71 #define IMCTR_RTSEL_SHIFT               4
  72 #define IMCTR_TREN                      (1 << 3)
  73 #define IMCTR_INTEN                     (1 << 2)
  74 #define IMCTR_FLUSH                     (1 << 1)
  75 #define IMCTR_MMUEN                     (1 << 0)
  76
  77 #define IMCAAR                          0x0004
  78
  79 #define IMTTBCR                         0x0008
  80 #define IMTTBCR_EAE                     (1 << 31)
  81 #define IMTTBCR_PMB                     (1 << 30)
  82 #define IMTTBCR_SH1_NON_SHAREABLE       (0 << 28)
  83 #define IMTTBCR_SH1_OUTER_SHAREABLE     (2 << 28)
  84 #define IMTTBCR_SH1_INNER_SHAREABLE     (3 << 28)
  85 #define IMTTBCR_SH1_MASK                (3 << 28)
  86 #define IMTTBCR_ORGN1_NC                (0 << 26)
  87 #define IMTTBCR_ORGN1_WB_WA             (1 << 26)
  88 #define IMTTBCR_ORGN1_WT                (2 << 26)
  89 #define IMTTBCR_ORGN1_WB                (3 << 26)
  90 #define IMTTBCR_ORGN1_MASK              (3 << 26)
  91 #define IMTTBCR_IRGN1_NC                (0 << 24)
  92 #define IMTTBCR_IRGN1_WB_WA             (1 << 24)
  93 #define IMTTBCR_IRGN1_WT                (2 << 24)
  94 #define IMTTBCR_IRGN1_WB                (3 << 24)
  95 #define IMTTBCR_IRGN1_MASK              (3 << 24)
  96 #define IMTTBCR_TSZ1_MASK               (7 << 16)
  97 #define IMTTBCR_TSZ1_SHIFT              16
  98 #define IMTTBCR_SH0_NON_SHAREABLE       (0 << 12)
  99 #define IMTTBCR_SH0_OUTER_SHAREABLE     (2 << 12)
 100 #define IMTTBCR_SH0_INNER_SHAREABLE     (3 << 12)
 101 #define IMTTBCR_SH0_MASK                (3 << 12)
 102 #define IMTTBCR_ORGN0_NC                (0 << 10)
 103 #define IMTTBCR_ORGN0_WB_WA             (1 << 10)
 104 #define IMTTBCR_ORGN0_WT                (2 << 10)
 105 #define IMTTBCR_ORGN0_WB                (3 << 10)
 106 #define IMTTBCR_ORGN0_MASK              (3 << 10)
 107 #define IMTTBCR_IRGN0_NC                (0 << 8)
 108 #define IMTTBCR_IRGN0_WB_WA             (1 << 8)
 109 #define IMTTBCR_IRGN0_WT                (2 << 8)
 110 #define IMTTBCR_IRGN0_WB                (3 << 8)
 111 #define IMTTBCR_IRGN0_MASK              (3 << 8)
 112 #define IMTTBCR_SL0_LVL_2               (0 << 4)
 113 #define IMTTBCR_SL0_LVL_1               (1 << 4)
 114 #define IMTTBCR_TSZ0_MASK               (7 << 0)
 115 #define IMTTBCR_TSZ0_SHIFT              O
 116
 117 #define IMBUSCR                         0x000c
 118 #define IMBUSCR_DVM                     (1 << 2)
 119 #define IMBUSCR_BUSSEL_SYS              (0 << 0)
 120 #define IMBUSCR_BUSSEL_CCI              (1 << 0)
 121 #define IMBUSCR_BUSSEL_IMCAAR           (2 << 0)
 122 #define IMBUSCR_BUSSEL_CCI_IMCAAR       (3 << 0)
 123 #define IMBUSCR_BUSSEL_MASK             (3 << 0)
 124
 125 #define IMTTLBR0                        0x0010
 126 #define IMTTUBR0                        0x0014
 127 #define IMTTLBR1                        0x0018
 128 #define IMTTUBR1                        0x001c
 129
 130 #define IMSTR                           0x0020
 131 #define IMSTR_ERRLVL_MASK               (3 << 12)
 132 #define IMSTR_ERRLVL_SHIFT              12
 133 #define IMSTR_ERRCODE_TLB_FORMAT        (1 << 8)
 134 #define IMSTR_ERRCODE_ACCESS_PERM       (4 << 8)
 135 #define IMSTR_ERRCODE_SECURE_ACCESS     (5 << 8)
 136 #define IMSTR_ERRCODE_MASK              (7 << 8)
 137 #define IMSTR_MHIT                      (1 << 4)
 138 #define IMSTR_ABORT                     (1 << 2)
 139 #define IMSTR_PF                        (1 << 1)
 140 #define IMSTR_TF                        (1 << 0)
 141
 142 #define IMMAIR0                         0x0028
 143 #define IMMAIR1                         0x002c
 144 #define IMMAIR_ATTR_MASK                0xff
 145 #define IMMAIR_ATTR_DEVICE              0x04
 146 #define IMMAIR_ATTR_NC                  0x44
 147 #define IMMAIR_ATTR_WBRWA               0xff
 148 #define IMMAIR_ATTR_SHIFT(n)            ((n) << 3)
 149 #define IMMAIR_ATTR_IDX_NC              0
 150 #define IMMAIR_ATTR_IDX_WBRWA           1
 151 #define IMMAIR_ATTR_IDX_DEV             2
 152
 153 #define IMEAR                           0x0030
 154
 155 #define IMPCTR                          0x0200
 156 #define IMPSTR                          0x0208
 157 #define IMPEAR                          0x020c
 158 #define IMPMBA(n)                       (0x0280 + ((n) * 4))
 159 #define IMPMBD(n)                       (0x02c0 + ((n) * 4))
 160
 161 #define IMUCTR(n)                       (0x0300 + ((n) * 16))
 162 #define IMUCTR_FIXADDEN                 (1 << 31)
 163 #define IMUCTR_FIXADD_MASK              (0xff << 16)
 164 #define IMUCTR_FIXADD_SHIFT             16
 165 #define IMUCTR_TTSEL_MMU(n)             ((n) << 4)
 166 #define IMUCTR_TTSEL_PMB                (8 << 4)
 167 #define IMUCTR_TTSEL_MASK               (15 << 4)
 168 #define IMUCTR_FLUSH                    (1 << 1)
 169 #define IMUCTR_MMUEN                    (1 << 0)
 170
 171 #define IMUASID(n)                      (0x0308 + ((n) * 16))
 172 #define IMUASID_ASID8_MASK              (0xff << 8)
 173 #define IMUASID_ASID8_SHIFT             8
 174 #define IMUASID_ASID0_MASK              (0xff << 0)
 175 #define IMUASID_ASID0_SHIFT             0
 176
 177 /* -----------------------------------------------------------------------------
 178  * Page Table Bits
 179  */
 180
 181 /*
 182  * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory access,
 183  * Long-descriptor format" that the NStable bit being set in a table descriptor
 184  * will result in the NStable and NS bits of all child entries being ignored and
 185  * considered as being set. The IPMMU seems not to comply with this, as it
 186  * generates a secure access page fault if any of the NStable and NS bits isn't
 187  * set when running in non-secure mode.
 188  */
 189 #ifndef PMD_NSTABLE
 190 #define PMD_NSTABLE                     (_AT(pmdval_t, 1) << 63)
 191 #endif
 192
 193 #define ARM_VMSA_PTE_XN                 (((pteval_t)3) << 53)
 194 #define ARM_VMSA_PTE_CONT               (((pteval_t)1) << 52)
 195 #define ARM_VMSA_PTE_AF                 (((pteval_t)1) << 10)
 196 #define ARM_VMSA_PTE_SH_NS              (((pteval_t)0) << 8)
 197 #define ARM_VMSA_PTE_SH_OS              (((pteval_t)2) << 8)
 198 #define ARM_VMSA_PTE_SH_IS              (((pteval_t)3) << 8)
 199 #define ARM_VMSA_PTE_SH_MASK            (((pteval_t)3) << 8)
 200 #define ARM_VMSA_PTE_NS                 (((pteval_t)1) << 5)
 201 #define ARM_VMSA_PTE_PAGE               (((pteval_t)3) << 0)
 202
 203 /* Stage-1 PTE */
 204 #define ARM_VMSA_PTE_nG                 (((pteval_t)1) << 11)
 205 #define ARM_VMSA_PTE_AP_UNPRIV          (((pteval_t)1) << 6)
 206 #define ARM_VMSA_PTE_AP_RDONLY          (((pteval_t)2) << 6)
 207 #define ARM_VMSA_PTE_AP_MASK            (((pteval_t)3) << 6)
 208 #define ARM_VMSA_PTE_ATTRINDX_MASK      (((pteval_t)3) << 2)
 209 #define ARM_VMSA_PTE_ATTRINDX_SHIFT     2
 210
 211 #define ARM_VMSA_PTE_ATTRS_MASK \
 212         (ARM_VMSA_PTE_XN | ARM_VMSA_PTE_CONT | ARM_VMSA_PTE_nG | \
 213          ARM_VMSA_PTE_AF | ARM_VMSA_PTE_SH_MASK | ARM_VMSA_PTE_AP_MASK | \
 214          ARM_VMSA_PTE_NS | ARM_VMSA_PTE_ATTRINDX_MASK)
 215
 216 #define ARM_VMSA_PTE_CONT_ENTRIES       16
 217 #define ARM_VMSA_PTE_CONT_SIZE          (PAGE_SIZE * ARM_VMSA_PTE_CONT_ENTRIES)
 218
 219 #define IPMMU_PTRS_PER_PTE              512
 220 #define IPMMU_PTRS_PER_PMD              512
 221 #define IPMMU_PTRS_PER_PGD              4
 222
 223 /* -----------------------------------------------------------------------------
 224  * Read/Write Access
 225  */
 226
 227 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset)
 228 {
 229         return ioread32(mmu->base + offset);
 230 }
 231
 232 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset,
 233                         u32 data)
 234 {
 235         iowrite32(data, mmu->base + offset);
 236 }
 237
 238 static u32 ipmmu_ctx_read(struct ipmmu_vmsa_domain *domain, unsigned int reg)
 239 {
 240         return ipmmu_read(domain->mmu, domain->context_id * IM_CTX_SIZE + reg);
 241 }
 242
 243 static void ipmmu_ctx_write(struct ipmmu_vmsa_domain *domain, unsigned int reg,
 244                             u32 data)
 245 {
 246         ipmmu_write(domain->mmu, domain->context_id * IM_CTX_SIZE + reg, data);
 247 }
 248
 249 /* -----------------------------------------------------------------------------
 250  * TLB and microTLB Management
 251  */
 252
 253 /* Wait for any pending TLB invalidations to complete */
 254 static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain)
 255 {
 256         unsigned int count = 0;
 257
 258         while (ipmmu_ctx_read(domain, IMCTR) & IMCTR_FLUSH) {
 259                 cpu_relax();
 260                 if (++count == TLB_LOOP_TIMEOUT) {
 261                         dev_err_ratelimited(domain->mmu->dev,
 262                         "TLB sync timed out -- MMU may be deadlocked\n");
 263                         return;
 264                 }
 265                 udelay(1);
 266         }
 267 }
 268
 269 static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain)
 270 {
 271         u32 reg;
 272
 273         reg = ipmmu_ctx_read(domain, IMCTR);
 274         reg |= IMCTR_FLUSH;
 275         ipmmu_ctx_write(domain, IMCTR, reg);
 276
 277         ipmmu_tlb_sync(domain);
 278 }
 279
 280 /*
 281  * Enable MMU translation for the microTLB.
 282  */
 283 static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain,
 284                               unsigned int utlb)
 285 {
 286         struct ipmmu_vmsa_device *mmu = domain->mmu;
 287
 288         /*
 289          * TODO: Reference-count the microTLB as several bus masters can be
 290          * connected to the same microTLB.
 291          */
 292
 293         /* TODO: What should we set the ASID to ? */
 294         ipmmu_write(mmu, IMUASID(utlb), 0);
 295         /* TODO: Do we need to flush the microTLB ? */
 296         ipmmu_write(mmu, IMUCTR(utlb),
 297                     IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_FLUSH |
 298                     IMUCTR_MMUEN);
 299 }
 300
 301 /*
 302  * Disable MMU translation for the microTLB.
 303  */
 304 static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain,
 305                                unsigned int utlb)
 306 {
 307         struct ipmmu_vmsa_device *mmu = domain->mmu;
 308
 309         ipmmu_write(mmu, IMUCTR(utlb), 0);
 310 }
 311
 312 static void ipmmu_flush_pgtable(struct ipmmu_vmsa_device *mmu, void *addr,
 313                                 size_t size)
 314 {
 315         unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
 316
 317         /*
 318          * TODO: Add support for coherent walk through CCI with DVM and remove
 319          * cache handling.
 320          */
 321         dma_map_page(mmu->dev, virt_to_page(addr), offset, size, DMA_TO_DEVICE);
 322 }
 323
 324 /* -----------------------------------------------------------------------------
 325  * Domain/Context Management
 326  */
 327
 328 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
 329 {
 330         phys_addr_t ttbr;
 331         u32 reg;
 332
 333         /*
 334          * TODO: When adding support for multiple contexts, find an unused
 335          * context.
 336          */
 337         domain->context_id = 0;
 338
 339         /* TTBR0 */
 340         ipmmu_flush_pgtable(domain->mmu, domain->pgd,
 341                             IPMMU_PTRS_PER_PGD * sizeof(*domain->pgd));
 342         ttbr = __pa(domain->pgd);
 343         ipmmu_ctx_write(domain, IMTTLBR0, ttbr);
 344         ipmmu_ctx_write(domain, IMTTUBR0, ttbr >> 32);
 345
 346         /*
 347          * TTBCR
 348          * We use long descriptors with inner-shareable WBWA tables and allocate
 349          * the whole 32-bit VA space to TTBR0.
 350          */
 351         ipmmu_ctx_write(domain, IMTTBCR, IMTTBCR_EAE |
 352                         IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
 353                         IMTTBCR_IRGN0_WB_WA | IMTTBCR_SL0_LVL_1);
 354
 355         /*
 356          * MAIR0
 357          * We need three attributes only, non-cacheable, write-back read/write
 358          * allocate and device memory.
 359          */
 360         reg = (IMMAIR_ATTR_NC << IMMAIR_ATTR_SHIFT(IMMAIR_ATTR_IDX_NC))
 361             | (IMMAIR_ATTR_WBRWA << IMMAIR_ATTR_SHIFT(IMMAIR_ATTR_IDX_WBRWA))
 362             | (IMMAIR_ATTR_DEVICE << IMMAIR_ATTR_SHIFT(IMMAIR_ATTR_IDX_DEV));
 363         ipmmu_ctx_write(domain, IMMAIR0, reg);
 364
 365         /* IMBUSCR */
 366         ipmmu_ctx_write(domain, IMBUSCR,
 367                         ipmmu_ctx_read(domain, IMBUSCR) &
 368                         ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
 369
 370         /*
 371          * IMSTR
 372          * Clear all interrupt flags.
 373          */
 374         ipmmu_ctx_write(domain, IMSTR, ipmmu_ctx_read(domain, IMSTR));
 375
 376         /*
 377          * IMCTR
 378          * Enable the MMU and interrupt generation. The long-descriptor
 379          * translation table format doesn't use TEX remapping. Don't enable AF
 380          * software management as we have no use for it. Flush the TLB as
 381          * required when modifying the context registers.
 382          */
 383         ipmmu_ctx_write(domain, IMCTR, IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
 384
 385         return 0;
 386 }
 387
 388 static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
 389 {
 390         /*
 391          * Disable the context. Flush the TLB as required when modifying the
 392          * context registers.
 393          *
 394          * TODO: Is TLB flush really needed ?
 395          */
 396         ipmmu_ctx_write(domain, IMCTR, IMCTR_FLUSH);
 397         ipmmu_tlb_sync(domain);
 398 }
 399
 400 /* -----------------------------------------------------------------------------
 401  * Fault Handling
 402  */
 403
 404 static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
 405 {
 406         const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF;
 407         struct ipmmu_vmsa_device *mmu = domain->mmu;
 408         u32 status;
 409         u32 iova;
 410
 411         status = ipmmu_ctx_read(domain, IMSTR);
 412         if (!(status & err_mask))
 413                 return IRQ_NONE;
 414
 415         iova = ipmmu_ctx_read(domain, IMEAR);
 416
 417         /*
 418          * Clear the error status flags. Unlike traditional interrupt flag
 419          * registers that must be cleared by writing 1, this status register
 420          * seems to require 0. The error address register must be read before,
 421          * otherwise its value will be 0.
 422          */
 423         ipmmu_ctx_write(domain, IMSTR, 0);
 424
 425         /* Log fatal errors. */
 426         if (status & IMSTR_MHIT)
 427                 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%08x\n",
 428                                     iova);
 429         if (status & IMSTR_ABORT)
 430                 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%08x\n",
 431                                     iova);
 432
 433         if (!(status & (IMSTR_PF | IMSTR_TF)))
 434                 return IRQ_NONE;
 435
 436         /*
 437          * Try to handle page faults and translation faults.
 438          *
 439          * TODO: We need to look up the faulty device based on the I/O VA. Use
 440          * the IOMMU device for now.
 441          */
 442         if (!report_iommu_fault(domain->io_domain, mmu->dev, iova, 0))
 443                 return IRQ_HANDLED;
 444
 445         dev_err_ratelimited(mmu->dev,
 446                             "Unhandled fault: status 0x%08x iova 0x%08x\n",
 447                             status, iova);
 448
 449         return IRQ_HANDLED;
 450 }
 451
 452 static irqreturn_t ipmmu_irq(int irq, void *dev)
 453 {
 454         struct ipmmu_vmsa_device *mmu = dev;
 455         struct iommu_domain *io_domain;
 456         struct ipmmu_vmsa_domain *domain;
 457
 458         if (!mmu->mapping)
 459                 return IRQ_NONE;
 460
 461         io_domain = mmu->mapping->domain;
 462         domain = io_domain->priv;
 463
 464         return ipmmu_domain_irq(domain);
 465 }
 466
 467 /* -----------------------------------------------------------------------------
 468  * Page Table Management
 469  */
 470
 471 #define pud_pgtable(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK))
 472
 473 static void ipmmu_free_ptes(pmd_t *pmd)
 474 {
 475         pgtable_t table = pmd_pgtable(*pmd);
 476         __free_page(table);
 477 }
 478
 479 static void ipmmu_free_pmds(pud_t *pud)
 480 {
 481         pmd_t *pmd = pmd_offset(pud, 0);
 482         pgtable_t table;
 483         unsigned int i;
 484
 485         for (i = 0; i < IPMMU_PTRS_PER_PMD; ++i) {
 486                 if (!pmd_table(*pmd))
 487                         continue;
 488
 489                 ipmmu_free_ptes(pmd);
 490                 pmd++;
 491         }
 492
 493         table = pud_pgtable(*pud);
 494         __free_page(table);
 495 }
 496
 497 static void ipmmu_free_pgtables(struct ipmmu_vmsa_domain *domain)
 498 {
 499         pgd_t *pgd, *pgd_base = domain->pgd;
 500         unsigned int i;
 501
 502         /*
 503          * Recursively free the page tables for this domain. We don't care about
 504          * speculative TLB filling, because the TLB will be nuked next time this
 505          * context bank is re-allocated and no devices currently map to these
 506          * tables.
 507          */
 508         pgd = pgd_base;
 509         for (i = 0; i < IPMMU_PTRS_PER_PGD; ++i) {
 510                 if (pgd_none(*pgd))
 511                         continue;
 512                 ipmmu_free_pmds((pud_t *)pgd);
 513                 pgd++;
 514         }
 515
 516         kfree(pgd_base);
 517 }
 518
 519 /*
 520  * We can't use the (pgd|pud|pmd|pte)_populate or the set_(pgd|pud|pmd|pte)
 521  * functions as they would flush the CPU TLB.
 522  */
 523
 524 static pte_t *ipmmu_alloc_pte(struct ipmmu_vmsa_device *mmu, pmd_t *pmd,
 525                               unsigned long iova)
 526 {
 527         pte_t *pte;
 528
 529         if (!pmd_none(*pmd))
 530                 return pte_offset_kernel(pmd, iova);
 531
 532         pte = (pte_t *)get_zeroed_page(GFP_ATOMIC);
 533         if (!pte)
 534                 return NULL;
 535
 536         ipmmu_flush_pgtable(mmu, pte, PAGE_SIZE);
 537         *pmd = __pmd(__pa(pte) | PMD_NSTABLE | PMD_TYPE_TABLE);
 538         ipmmu_flush_pgtable(mmu, pmd, sizeof(*pmd));
 539
 540         return pte + pte_index(iova);
 541 }
 542
 543 static pmd_t *ipmmu_alloc_pmd(struct ipmmu_vmsa_device *mmu, pgd_t *pgd,
 544                               unsigned long iova)
 545 {
 546         pud_t *pud = (pud_t *)pgd;
 547         pmd_t *pmd;
 548
 549         if (!pud_none(*pud))
 550                 return pmd_offset(pud, iova);
 551
 552         pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC);
 553         if (!pmd)
 554                 return NULL;
 555
 556         ipmmu_flush_pgtable(mmu, pmd, PAGE_SIZE);
 557         *pud = __pud(__pa(pmd) | PMD_NSTABLE | PMD_TYPE_TABLE);
 558         ipmmu_flush_pgtable(mmu, pud, sizeof(*pud));
 559
 560         return pmd + pmd_index(iova);
 561 }
 562
 563 static u64 ipmmu_page_prot(unsigned int prot, u64 type)
 564 {
 565         u64 pgprot = ARM_VMSA_PTE_nG | ARM_VMSA_PTE_AF
 566                    | ARM_VMSA_PTE_SH_IS | ARM_VMSA_PTE_AP_UNPRIV
 567                    | ARM_VMSA_PTE_NS | type;
 568
 569         if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
 570                 pgprot |= ARM_VMSA_PTE_AP_RDONLY;
 571
 572         if (prot & IOMMU_CACHE)
 573                 pgprot |= IMMAIR_ATTR_IDX_WBRWA << ARM_VMSA_PTE_ATTRINDX_SHIFT;
 574
 575         if (prot & IOMMU_NOEXEC)
 576                 pgprot |= ARM_VMSA_PTE_XN;
 577         else if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
 578                 /* If no access create a faulting entry to avoid TLB fills. */
 579                 pgprot &= ~ARM_VMSA_PTE_PAGE;
 580
 581         return pgprot;
 582 }
 583
 584 static int ipmmu_alloc_init_pte(struct ipmmu_vmsa_device *mmu, pmd_t *pmd,
 585                                 unsigned long iova, unsigned long pfn,
 586                                 size_t size, int prot)
 587 {
 588         pteval_t pteval = ipmmu_page_prot(prot, ARM_VMSA_PTE_PAGE);
 589         unsigned int num_ptes = 1;
 590         pte_t *pte, *start;
 591         unsigned int i;
 592
 593         pte = ipmmu_alloc_pte(mmu, pmd, iova);
 594         if (!pte)
 595                 return -ENOMEM;
 596
 597         start = pte;
 598
 599         /*
 600          * Install the page table entries. We can be called both for a single
 601          * page or for a block of 16 physically contiguous pages. In the latter
 602          * case set the PTE contiguous hint.
 603          */
 604         if (size == SZ_64K) {
 605                 pteval |= ARM_VMSA_PTE_CONT;
 606                 num_ptes = ARM_VMSA_PTE_CONT_ENTRIES;
 607         }
 608
 609         for (i = num_ptes; i; --i)
 610                 *pte++ = pfn_pte(pfn++, __pgprot(pteval));
 611
 612         ipmmu_flush_pgtable(mmu, start, sizeof(*pte) * num_ptes);
 613
 614         return 0;
 615 }
 616
 617 static int ipmmu_alloc_init_pmd(struct ipmmu_vmsa_device *mmu, pmd_t *pmd,
 618                                 unsigned long iova, unsigned long pfn,
 619                                 int prot)
 620 {
 621         pmdval_t pmdval = ipmmu_page_prot(prot, PMD_TYPE_SECT);
 622
 623         *pmd = pfn_pmd(pfn, __pgprot(pmdval));
 624         ipmmu_flush_pgtable(mmu, pmd, sizeof(*pmd));
 625
 626         return 0;
 627 }
 628
 629 static int ipmmu_create_mapping(struct ipmmu_vmsa_domain *domain,
 630                                 unsigned long iova, phys_addr_t paddr,
 631                                 size_t size, int prot)
 632 {
 633         struct ipmmu_vmsa_device *mmu = domain->mmu;
 634         pgd_t *pgd = domain->pgd;
 635         unsigned long flags;
 636         unsigned long pfn;
 637         pmd_t *pmd;
 638         int ret;
 639
 640         if (!pgd)
 641                 return -EINVAL;
 642
 643         if (size & ~PAGE_MASK)
 644                 return -EINVAL;
 645
 646         if (paddr & ~((1ULL << 40) - 1))
 647                 return -ERANGE;
 648
 649         pfn = __phys_to_pfn(paddr);
 650         pgd += pgd_index(iova);
 651
 652         /* Update the page tables. */
 653         spin_lock_irqsave(&domain->lock, flags);
 654
 655         pmd = ipmmu_alloc_pmd(mmu, pgd, iova);
 656         if (!pmd) {
 657                 ret = -ENOMEM;
 658                 goto done;
 659         }
 660
 661         switch (size) {
 662         case SZ_2M:
 663                 ret = ipmmu_alloc_init_pmd(mmu, pmd, iova, pfn, prot);
 664                 break;
 665         case SZ_64K:
 666         case SZ_4K:
 667                 ret = ipmmu_alloc_init_pte(mmu, pmd, iova, pfn, size, prot);
 668                 break;
 669         default:
 670                 ret = -EINVAL;
 671                 break;
 672         }
 673
 674 done:
 675         spin_unlock_irqrestore(&domain->lock, flags);
 676
 677         if (!ret)
 678                 ipmmu_tlb_invalidate(domain);
 679
 680         return ret;
 681 }
 682
 683 static void ipmmu_clear_pud(struct ipmmu_vmsa_device *mmu, pud_t *pud)
 684 {
 685         pgtable_t table = pud_pgtable(*pud);
 686
 687         /* Clear the PUD. */
 688         *pud = __pud(0);
 689         ipmmu_flush_pgtable(mmu, pud, sizeof(*pud));
 690
 691         /* Free the page table. */
 692         __free_page(table);
 693 }
 694
 695 static void ipmmu_clear_pmd(struct ipmmu_vmsa_device *mmu, pud_t *pud,
 696                             pmd_t *pmd)
 697 {
 698         pmd_t pmdval = *pmd;
 699         unsigned int i;
 700
 701         /* Clear the PMD. */
 702         *pmd = __pmd(0);
 703         ipmmu_flush_pgtable(mmu, pmd, sizeof(*pmd));
 704
 705         /* Free the page table. */
 706         if (pmd_table(pmdval)) {
 707                 pgtable_t table = pmd_pgtable(pmdval);
 708
 709                 __free_page(table);
 710         }
 711
 712         /* Check whether the PUD is still needed. */
 713         pmd = pmd_offset(pud, 0);
 714         for (i = 0; i < IPMMU_PTRS_PER_PMD; ++i) {
 715                 if (!pmd_none(pmd[i]))
 716                         return;
 717         }
 718
 719         /* Clear the parent PUD. */
 720         ipmmu_clear_pud(mmu, pud);
 721 }
 722
 723 static void ipmmu_clear_pte(struct ipmmu_vmsa_device *mmu, pud_t *pud,
 724                             pmd_t *pmd, pte_t *pte, unsigned int num_ptes)
 725 {
 726         unsigned int i;
 727
 728         /* Clear the PTE. */
 729         for (i = num_ptes; i; --i)
 730                 pte[i-1] = __pte(0);
 731
 732         ipmmu_flush_pgtable(mmu, pte, sizeof(*pte) * num_ptes);
 733
 734         /* Check whether the PMD is still needed. */
 735         pte = pte_offset_kernel(pmd, 0);
 736         for (i = 0; i < IPMMU_PTRS_PER_PTE; ++i) {
 737                 if (!pte_none(pte[i]))
 738                         return;
 739         }
 740
 741         /* Clear the parent PMD. */
 742         ipmmu_clear_pmd(mmu, pud, pmd);
 743 }
 744
 745 static int ipmmu_split_pmd(struct ipmmu_vmsa_device *mmu, pmd_t *pmd)
 746 {
 747         pte_t *pte, *start;
 748         pteval_t pteval;
 749         unsigned long pfn;
 750         unsigned int i;
 751
 752         pte = (pte_t *)get_zeroed_page(GFP_ATOMIC);
 753         if (!pte)
 754                 return -ENOMEM;
 755
 756         /* Copy the PMD attributes. */
 757         pteval = (pmd_val(*pmd) & ARM_VMSA_PTE_ATTRS_MASK)
 758                | ARM_VMSA_PTE_CONT | ARM_VMSA_PTE_PAGE;
 759
 760         pfn = pmd_pfn(*pmd);
 761         start = pte;
 762
 763         for (i = IPMMU_PTRS_PER_PTE; i; --i)
 764                 *pte++ = pfn_pte(pfn++, __pgprot(pteval));
 765
 766         ipmmu_flush_pgtable(mmu, start, PAGE_SIZE);
 767         *pmd = __pmd(__pa(start) | PMD_NSTABLE | PMD_TYPE_TABLE);
 768         ipmmu_flush_pgtable(mmu, pmd, sizeof(*pmd));
 769
 770         return 0;
 771 }
 772
 773 static void ipmmu_split_pte(struct ipmmu_vmsa_device *mmu, pte_t *pte)
 774 {
 775         unsigned int i;
 776
 777         for (i = ARM_VMSA_PTE_CONT_ENTRIES; i; --i)
 778                 pte[i-1] = __pte(pte_val(*pte) & ~ARM_VMSA_PTE_CONT);
 779
 780         ipmmu_flush_pgtable(mmu, pte, sizeof(*pte) * ARM_VMSA_PTE_CONT_ENTRIES);
 781 }
 782
 783 static int ipmmu_clear_mapping(struct ipmmu_vmsa_domain *domain,
 784                                unsigned long iova, size_t size)
 785 {
 786         struct ipmmu_vmsa_device *mmu = domain->mmu;
 787         unsigned long flags;
 788         pgd_t *pgd = domain->pgd;
 789         pud_t *pud;
 790         pmd_t *pmd;
 791         pte_t *pte;
 792
 793         if (!pgd)
 794                 return -EINVAL;
 795
 796         if (size & ~PAGE_MASK)
 797                 return -EINVAL;
 798
 799         pgd += pgd_index(iova);
 800         pud = (pud_t *)pgd;
 801
 802         spin_lock_irqsave(&domain->lock, flags);
 803
 804         /* If there's no PUD or PMD we're done. */
 805         if (pud_none(*pud))
 806                 goto done;
 807
 808         pmd = pmd_offset(pud, iova);
 809         if (pmd_none(*pmd))
 810                 goto done;
 811
 812         /*
 813          * When freeing a 2MB block just clear the PMD. In the unlikely case the
 814          * block is mapped as individual pages this will free the corresponding
 815          * PTE page table.
 816          */
 817         if (size == SZ_2M) {
 818                 ipmmu_clear_pmd(mmu, pud, pmd);
 819                 goto done;
 820         }
 821
 822         /*
 823          * If the PMD has been mapped as a section remap it as pages to allow
 824          * freeing individual pages.
 825          */
 826         if (pmd_sect(*pmd))
 827                 ipmmu_split_pmd(mmu, pmd);
 828
 829         pte = pte_offset_kernel(pmd, iova);
 830
 831         /*
 832          * When freeing a 64kB block just clear the PTE entries. We don't have
 833          * to care about the contiguous hint of the surrounding entries.
 834          */
 835         if (size == SZ_64K) {
 836                 ipmmu_clear_pte(mmu, pud, pmd, pte, ARM_VMSA_PTE_CONT_ENTRIES);
 837                 goto done;
 838         }
 839
 840         /*
 841          * If the PTE has been mapped with the contiguous hint set remap it and
 842          * its surrounding PTEs to allow unmapping a single page.
 843          */
 844         if (pte_val(*pte) & ARM_VMSA_PTE_CONT)
 845                 ipmmu_split_pte(mmu, pte);
 846
 847         /* Clear the PTE. */
 848         ipmmu_clear_pte(mmu, pud, pmd, pte, 1);
 849
 850 done:
 851         spin_unlock_irqrestore(&domain->lock, flags);
 852
 853         ipmmu_tlb_invalidate(domain);
 854
 855         return 0;
 856 }
 857
 858 /* -----------------------------------------------------------------------------
 859  * IOMMU Operations
 860  */
 861
 862 static int ipmmu_domain_init(struct iommu_domain *io_domain)
 863 {
 864         struct ipmmu_vmsa_domain *domain;
 865
 866         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 867         if (!domain)
 868                 return -ENOMEM;
 869
 870         spin_lock_init(&domain->lock);
 871
 872         domain->pgd = kzalloc(IPMMU_PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
 873         if (!domain->pgd) {
 874                 kfree(domain);
 875                 return -ENOMEM;
 876         }
 877
 878         io_domain->priv = domain;
 879         domain->io_domain = io_domain;
 880
 881         return 0;
 882 }
 883
 884 static void ipmmu_domain_destroy(struct iommu_domain *io_domain)
 885 {
 886         struct ipmmu_vmsa_domain *domain = io_domain->priv;
 887
 888         /*
 889          * Free the domain resources. We assume that all devices have already
 890          * been detached.
 891          */
 892         ipmmu_domain_destroy_context(domain);
 893         ipmmu_free_pgtables(domain);
 894         kfree(domain);
 895 }
 896
 897 static int ipmmu_attach_device(struct iommu_domain *io_domain,
 898                                struct device *dev)
 899 {
 900         struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
 901         struct ipmmu_vmsa_device *mmu = archdata->mmu;
 902         struct ipmmu_vmsa_domain *domain = io_domain->priv;
 903         unsigned long flags;
 904         unsigned int i;
 905         int ret = 0;
 906
 907         if (!mmu) {
 908                 dev_err(dev, "Cannot attach to IPMMU\n");
 909                 return -ENXIO;
 910         }
 911
 912         spin_lock_irqsave(&domain->lock, flags);
 913
 914         if (!domain->mmu) {
 915                 /* The domain hasn't been used yet, initialize it. */
 916                 domain->mmu = mmu;
 917                 ret = ipmmu_domain_init_context(domain);
 918         } else if (domain->mmu != mmu) {
 919                 /*
 920                  * Something is wrong, we can't attach two devices using
 921                  * different IOMMUs to the same domain.
 922                  */
 923                 dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n",
 924                         dev_name(mmu->dev), dev_name(domain->mmu->dev));
 925                 ret = -EINVAL;
 926         }
 927
 928         spin_unlock_irqrestore(&domain->lock, flags);
 929
 930         if (ret < 0)
 931                 return ret;
 932
 933         for (i = 0; i < archdata->num_utlbs; ++i)
 934                 ipmmu_utlb_enable(domain, archdata->utlbs[i]);
 935
 936         return 0;
 937 }
 938
 939 static void ipmmu_detach_device(struct iommu_domain *io_domain,
 940                                 struct device *dev)
 941 {
 942         struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
 943         struct ipmmu_vmsa_domain *domain = io_domain->priv;
 944         unsigned int i;
 945
 946         for (i = 0; i < archdata->num_utlbs; ++i)
 947                 ipmmu_utlb_disable(domain, archdata->utlbs[i]);
 948
 949         /*
 950          * TODO: Optimize by disabling the context when no device is attached.
 951          */
 952 }
 953
 954 static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova,
 955                      phys_addr_t paddr, size_t size, int prot)
 956 {
 957         struct ipmmu_vmsa_domain *domain = io_domain->priv;
 958
 959         if (!domain)
 960                 return -ENODEV;
 961
 962         return ipmmu_create_mapping(domain, iova, paddr, size, prot);
 963 }
 964
 965 static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
 966                           size_t size)
 967 {
 968         struct ipmmu_vmsa_domain *domain = io_domain->priv;
 969         int ret;
 970
 971         ret = ipmmu_clear_mapping(domain, iova, size);
 972         return ret ? 0 : size;
 973 }
 974
 975 static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain,
 976                                       dma_addr_t iova)
 977 {
 978         struct ipmmu_vmsa_domain *domain = io_domain->priv;
 979         pgd_t pgd;
 980         pud_t pud;
 981         pmd_t pmd;
 982         pte_t pte;
 983
 984         /* TODO: Is locking needed ? */
 985
 986         if (!domain->pgd)
 987                 return 0;
 988
 989         pgd = *(domain->pgd + pgd_index(iova));
 990         if (pgd_none(pgd))
 991                 return 0;
 992
 993         pud = *pud_offset(&pgd, iova);
 994         if (pud_none(pud))
 995                 return 0;
 996
 997         pmd = *pmd_offset(&pud, iova);
 998         if (pmd_none(pmd))
 999                 return 0;
1000
1001         if (pmd_sect(pmd))
1002                 return __pfn_to_phys(pmd_pfn(pmd)) | (iova & ~PMD_MASK);
1003
1004         pte = *(pmd_page_vaddr(pmd) + pte_index(iova));
1005         if (pte_none(pte))
1006                 return 0;
1007
1008         return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK);
1009 }
1010
1011 static int ipmmu_find_utlbs(struct ipmmu_vmsa_device *mmu, struct device *dev,
1012                             unsigned int **_utlbs)
1013 {
1014         unsigned int *utlbs;
1015         unsigned int i;
1016         int count;
1017
1018         if (mmu->pdata) {
1019                 const struct ipmmu_vmsa_master *master = mmu->pdata->masters;
1020                 const char *devname = dev_name(dev);
1021                 unsigned int i;
1022
1023                 for (i = 0; i < mmu->pdata->num_masters; ++i, ++master) {
1024                         if (strcmp(master->name, devname) == 0) {
1025                                 utlbs = kmalloc(sizeof(*utlbs), GFP_KERNEL);
1026                                 if (!utlbs)
1027                                         return -ENOMEM;
1028
1029                                 utlbs[0] = master->utlb;
1030
1031                                 *_utlbs = utlbs;
1032                                 return 1;
1033                         }
1034                 }
1035
1036                 return -EINVAL;
1037         }
1038
1039         count = of_count_phandle_with_args(dev->of_node, "iommus",
1040                                            "#iommu-cells");
1041         if (count < 0)
1042                 return -EINVAL;
1043
1044         utlbs = kcalloc(count, sizeof(*utlbs), GFP_KERNEL);
1045         if (!utlbs)
1046                 return -ENOMEM;
1047
1048         for (i = 0; i < count; ++i) {
1049                 struct of_phandle_args args;
1050                 int ret;
1051
1052                 ret = of_parse_phandle_with_args(dev->of_node, "iommus",
1053                                                  "#iommu-cells", i, &args);
1054                 if (ret < 0)
1055                         goto error;
1056
1057                 of_node_put(args.np);
1058
1059                 if (args.np != mmu->dev->of_node || args.args_count != 1)
1060                         goto error;
1061
1062                 utlbs[i] = args.args[0];
1063         }
1064
1065         *_utlbs = utlbs;
1066
1067         return count;
1068
1069 error:
1070         kfree(utlbs);
1071         return -EINVAL;
1072 }
1073
1074 static int ipmmu_add_device(struct device *dev)
1075 {
1076         struct ipmmu_vmsa_archdata *archdata;
1077         struct ipmmu_vmsa_device *mmu;
1078         struct iommu_group *group = NULL;
1079         unsigned int *utlbs = NULL;
1080         unsigned int i;
1081         int num_utlbs = 0;
1082         int ret;
1083
1084         if (dev->archdata.iommu) {
1085                 dev_warn(dev, "IOMMU driver already assigned to device %s\n",
1086                          dev_name(dev));
1087                 return -EINVAL;
1088         }
1089
1090         /* Find the master corresponding to the device. */
1091         spin_lock(&ipmmu_devices_lock);
1092
1093         list_for_each_entry(mmu, &ipmmu_devices, list) {
1094                 num_utlbs = ipmmu_find_utlbs(mmu, dev, &utlbs);
1095                 if (num_utlbs) {
1096                         /*
1097                          * TODO Take a reference to the MMU to protect
1098                          * against device removal.
1099                          */
1100                         break;
1101                 }
1102         }
1103
1104         spin_unlock(&ipmmu_devices_lock);
1105
1106         if (num_utlbs <= 0)
1107                 return -ENODEV;
1108
1109         for (i = 0; i < num_utlbs; ++i) {
1110                 if (utlbs[i] >= mmu->num_utlbs) {
1111                         ret = -EINVAL;
1112                         goto error;
1113                 }
1114         }
1115
1116         /* Create a device group and add the device to it. */
1117         group = iommu_group_alloc();
1118         if (IS_ERR(group)) {
1119                 dev_err(dev, "Failed to allocate IOMMU group\n");
1120                 ret = PTR_ERR(group);
1121                 goto error;
1122         }
1123
1124         ret = iommu_group_add_device(group, dev);
1125         iommu_group_put(group);
1126
1127         if (ret < 0) {
1128                 dev_err(dev, "Failed to add device to IPMMU group\n");
1129                 group = NULL;
1130                 goto error;
1131         }
1132
1133         archdata = kzalloc(sizeof(*archdata), GFP_KERNEL);
1134         if (!archdata) {
1135                 ret = -ENOMEM;
1136                 goto error;
1137         }
1138
1139         archdata->mmu = mmu;
1140         archdata->utlbs = utlbs;
1141         archdata->num_utlbs = num_utlbs;
1142         dev->archdata.iommu = archdata;
1143
1144         /*
1145          * Create the ARM mapping, used by the ARM DMA mapping core to allocate
1146          * VAs. This will allocate a corresponding IOMMU domain.
1147          *
1148          * TODO:
1149          * - Create one mapping per context (TLB).
1150          * - Make the mapping size configurable ? We currently use a 2GB mapping
1151          *   at a 1GB offset to ensure that NULL VAs will fault.
1152          */
1153         if (!mmu->mapping) {
1154                 struct dma_iommu_mapping *mapping;
1155
1156                 mapping = arm_iommu_create_mapping(&platform_bus_type,
1157                                                    SZ_1G, SZ_2G);
1158                 if (IS_ERR(mapping)) {
1159                         dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n");
1160                         ret = PTR_ERR(mapping);
1161                         goto error;
1162                 }
1163
1164                 mmu->mapping = mapping;
1165         }
1166
1167         /* Attach the ARM VA mapping to the device. */
1168         ret = arm_iommu_attach_device(dev, mmu->mapping);
1169         if (ret < 0) {
1170                 dev_err(dev, "Failed to attach device to VA mapping\n");
1171                 goto error;
1172         }
1173
1174         return 0;
1175
1176 error:
1177         arm_iommu_release_mapping(mmu->mapping);
1178
1179         kfree(dev->archdata.iommu);
1180         kfree(utlbs);
1181
1182         dev->archdata.iommu = NULL;
1183
1184         if (!IS_ERR_OR_NULL(group))
1185                 iommu_group_remove_device(dev);
1186
1187         return ret;
1188 }
1189
1190 static void ipmmu_remove_device(struct device *dev)
1191 {
1192         struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
1193
1194         arm_iommu_detach_device(dev);
1195         iommu_group_remove_device(dev);
1196
1197         kfree(archdata->utlbs);
1198         kfree(archdata);
1199
1200         dev->archdata.iommu = NULL;
1201 }
1202
1203 static const struct iommu_ops ipmmu_ops = {
1204         .domain_init = ipmmu_domain_init,
1205         .domain_destroy = ipmmu_domain_destroy,
1206         .attach_dev = ipmmu_attach_device,
1207         .detach_dev = ipmmu_detach_device,
1208         .map = ipmmu_map,
1209         .unmap = ipmmu_unmap,
1210         .map_sg = default_iommu_map_sg,
1211         .iova_to_phys = ipmmu_iova_to_phys,
1212         .add_device = ipmmu_add_device,
1213         .remove_device = ipmmu_remove_device,
1214         .pgsize_bitmap = SZ_2M | SZ_64K | SZ_4K,
1215 };
1216
1217 /* -----------------------------------------------------------------------------
1218  * Probe/remove and init
1219  */
1220
1221 static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
1222 {
1223         unsigned int i;
1224
1225         /* Disable all contexts. */
1226         for (i = 0; i < 4; ++i)
1227                 ipmmu_write(mmu, i * IM_CTX_SIZE + IMCTR, 0);
1228 }
1229
1230 static int ipmmu_probe(struct platform_device *pdev)
1231 {
1232         struct ipmmu_vmsa_device *mmu;
1233         struct resource *res;
1234         int irq;
1235         int ret;
1236
1237         if (!IS_ENABLED(CONFIG_OF) && !pdev->dev.platform_data) {
1238                 dev_err(&pdev->dev, "missing platform data\n");
1239                 return -EINVAL;
1240         }
1241
1242         mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL);
1243         if (!mmu) {
1244                 dev_err(&pdev->dev, "cannot allocate device data\n");
1245                 return -ENOMEM;
1246         }
1247
1248         mmu->dev = &pdev->dev;
1249         mmu->pdata = pdev->dev.platform_data;
1250         mmu->num_utlbs = 32;
1251
1252         /* Map I/O memory and request IRQ. */
1253         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1254         mmu->base = devm_ioremap_resource(&pdev->dev, res);
1255         if (IS_ERR(mmu->base))
1256                 return PTR_ERR(mmu->base);
1257
1258         /*
1259          * The IPMMU has two register banks, for secure and non-secure modes.
1260          * The bank mapped at the beginning of the IPMMU address space
1261          * corresponds to the running mode of the CPU. When running in secure
1262          * mode the non-secure register bank is also available at an offset.
1263          *
1264          * Secure mode operation isn't clearly documented and is thus currently
1265          * not implemented in the driver. Furthermore, preliminary tests of
1266          * non-secure operation with the main register bank were not successful.
1267          * Offset the registers base unconditionally to point to the non-secure
1268          * alias space for now.
1269          */
1270         mmu->base += IM_NS_ALIAS_OFFSET;
1271
1272         irq = platform_get_irq(pdev, 0);
1273         if (irq < 0) {
1274                 dev_err(&pdev->dev, "no IRQ found\n");
1275                 return irq;
1276         }
1277
1278         ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0,
1279                                dev_name(&pdev->dev), mmu);
1280         if (ret < 0) {
1281                 dev_err(&pdev->dev, "failed to request IRQ %d\n", irq);
1282                 return ret;
1283         }
1284
1285         ipmmu_device_reset(mmu);
1286
1287         /*
1288          * We can't create the ARM mapping here as it requires the bus to have
1289          * an IOMMU, which only happens when bus_set_iommu() is called in
1290          * ipmmu_init() after the probe function returns.
1291          */
1292
1293         spin_lock(&ipmmu_devices_lock);
1294         list_add(&mmu->list, &ipmmu_devices);
1295         spin_unlock(&ipmmu_devices_lock);
1296
1297         platform_set_drvdata(pdev, mmu);
1298
1299         return 0;
1300 }
1301
1302 static int ipmmu_remove(struct platform_device *pdev)
1303 {
1304         struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev);
1305
1306         spin_lock(&ipmmu_devices_lock);
1307         list_del(&mmu->list);
1308         spin_unlock(&ipmmu_devices_lock);
1309
1310         arm_iommu_release_mapping(mmu->mapping);
1311
1312         ipmmu_device_reset(mmu);
1313
1314         return 0;
1315 }
1316
1317 static const struct of_device_id ipmmu_of_ids[] = {
1318         { .compatible = "renesas,ipmmu-vmsa", },
1319 };
1320
1321 static struct platform_driver ipmmu_driver = {
1322         .driver = {
1323                 .name = "ipmmu-vmsa",
1324                 .of_match_table = of_match_ptr(ipmmu_of_ids),
1325         },
1326         .probe = ipmmu_probe,
1327         .remove = ipmmu_remove,
1328 };
1329
1330 static int __init ipmmu_init(void)
1331 {
1332         int ret;
1333
1334         ret = platform_driver_register(&ipmmu_driver);
1335         if (ret < 0)
1336                 return ret;
1337
1338         if (!iommu_present(&platform_bus_type))
1339                 bus_set_iommu(&platform_bus_type, &ipmmu_ops);
1340
1341         return 0;
1342 }
1343
1344 static void __exit ipmmu_exit(void)
1345 {
1346         return platform_driver_unregister(&ipmmu_driver);
1347 }
1348
1349 subsys_initcall(ipmmu_init);
1350 module_exit(ipmmu_exit);
1351
1352 MODULE_DESCRIPTION("IOMMU API for Renesas VMSA-compatible IPMMU");
1353 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1354 MODULE_LICENSE("GPL v2");