2 * IOMMU API for SMMU in Tegra30
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #define pr_fmt(fmt) "%s(): " fmt, __func__
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
28 #include <linux/pagemap.h>
29 #include <linux/device.h>
30 #include <linux/sched.h>
31 #include <linux/iommu.h>
34 #include <linux/of_iommu.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
39 #include <asm/cacheflush.h>
41 #include <mach/iomap.h>
42 #include <mach/tegra-ahb.h>
67 #define HWG_AFI (1 << HWGRP_AFI)
68 #define HWG_AVPC (1 << HWGRP_AVPC)
69 #define HWG_DC (1 << HWGRP_DC)
70 #define HWG_DCB (1 << HWGRP_DCB)
71 #define HWG_EPP (1 << HWGRP_EPP)
72 #define HWG_G2 (1 << HWGRP_G2)
73 #define HWG_HC (1 << HWGRP_HC)
74 #define HWG_HDA (1 << HWGRP_HDA)
75 #define HWG_ISP (1 << HWGRP_ISP)
76 #define HWG_MPE (1 << HWGRP_MPE)
77 #define HWG_NV (1 << HWGRP_NV)
78 #define HWG_NV2 (1 << HWGRP_NV2)
79 #define HWG_PPCS (1 << HWGRP_PPCS)
80 #define HWG_SATA (1 << HWGRP_SATA)
81 #define HWG_VDE (1 << HWGRP_VDE)
82 #define HWG_VI (1 << HWGRP_VI)
84 /* bitmap of the page sizes currently supported */
85 #define SMMU_IOMMU_PGSIZES (SZ_4K)
87 #define SMMU_CONFIG 0x10
88 #define SMMU_CONFIG_DISABLE 0
89 #define SMMU_CONFIG_ENABLE 1
91 /* REVISIT: To support multiple MCs */
101 #define SMMU_CACHE_CONFIG_BASE 0x14
102 #define __SMMU_CACHE_CONFIG(mc, cache) (SMMU_CACHE_CONFIG_BASE + 4 * cache)
103 #define SMMU_CACHE_CONFIG(cache) __SMMU_CACHE_CONFIG(_MC, cache)
105 #define SMMU_CACHE_CONFIG_STATS_SHIFT 31
106 #define SMMU_CACHE_CONFIG_STATS_ENABLE (1 << SMMU_CACHE_CONFIG_STATS_SHIFT)
107 #define SMMU_CACHE_CONFIG_STATS_TEST_SHIFT 30
108 #define SMMU_CACHE_CONFIG_STATS_TEST (1 << SMMU_CACHE_CONFIG_STATS_TEST_SHIFT)
110 #define SMMU_TLB_CONFIG_HIT_UNDER_MISS__ENABLE (1 << 29)
111 #define SMMU_TLB_CONFIG_ACTIVE_LINES__VALUE 0x10
112 #define SMMU_TLB_CONFIG_RESET_VAL 0x20000010
114 #define SMMU_PTC_CONFIG_CACHE__ENABLE (1 << 29)
115 #define SMMU_PTC_CONFIG_INDEX_MAP__PATTERN 0x3f
116 #define SMMU_PTC_CONFIG_RESET_VAL 0x2000003f
118 #define SMMU_PTB_ASID 0x1c
119 #define SMMU_PTB_ASID_CURRENT_SHIFT 0
121 #define SMMU_PTB_DATA 0x20
122 #define SMMU_PTB_DATA_RESET_VAL 0
123 #define SMMU_PTB_DATA_ASID_NONSECURE_SHIFT 29
124 #define SMMU_PTB_DATA_ASID_WRITABLE_SHIFT 30
125 #define SMMU_PTB_DATA_ASID_READABLE_SHIFT 31
127 #define SMMU_TLB_FLUSH 0x30
128 #define SMMU_TLB_FLUSH_VA_MATCH_ALL 0
129 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2
130 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3
131 #define SMMU_TLB_FLUSH_ASID_SHIFT 29
132 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0
133 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1
134 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31
136 #define SMMU_PTC_FLUSH 0x34
137 #define SMMU_PTC_FLUSH_TYPE_ALL 0
138 #define SMMU_PTC_FLUSH_TYPE_ADR 1
139 #define SMMU_PTC_FLUSH_ADR_SHIFT 4
141 #define SMMU_ASID_SECURITY 0x38
143 #define SMMU_STATS_CACHE_COUNT_BASE 0x1f0
145 #define SMMU_STATS_CACHE_COUNT(mc, cache, hitmiss) \
146 (SMMU_STATS_CACHE_COUNT_BASE + 8 * cache + 4 * hitmiss)
148 #define SMMU_TRANSLATION_ENABLE_0 0x228
149 #define SMMU_TRANSLATION_ENABLE_1 0x22c
150 #define SMMU_TRANSLATION_ENABLE_2 0x230
152 #define SMMU_AFI_ASID 0x238 /* PCIE */
153 #define SMMU_AVPC_ASID 0x23c /* AVP */
154 #define SMMU_DC_ASID 0x240 /* Display controller */
155 #define SMMU_DCB_ASID 0x244 /* Display controller B */
156 #define SMMU_EPP_ASID 0x248 /* Encoder pre-processor */
157 #define SMMU_G2_ASID 0x24c /* 2D engine */
158 #define SMMU_HC_ASID 0x250 /* Host1x */
159 #define SMMU_HDA_ASID 0x254 /* High-def audio */
160 #define SMMU_ISP_ASID 0x258 /* Image signal processor */
161 #define SMMU_MPE_ASID 0x264 /* MPEG encoder */
162 #define SMMU_NV_ASID 0x268 /* (3D) */
163 #define SMMU_NV2_ASID 0x26c /* (3D) */
164 #define SMMU_PPCS_ASID 0x270 /* AHB */
165 #define SMMU_SATA_ASID 0x278 /* SATA */
166 #define SMMU_VDE_ASID 0x27c /* Video decoder */
167 #define SMMU_VI_ASID 0x280 /* Video input */
169 #define SMMU_PDE_NEXT_SHIFT 28
171 #define SMMU_TLB_FLUSH_VA_SECTION__MASK 0xffc00000
172 #define SMMU_TLB_FLUSH_VA_SECTION__SHIFT 12 /* right shift */
173 #define SMMU_TLB_FLUSH_VA_GROUP__MASK 0xffffc000
174 #define SMMU_TLB_FLUSH_VA_GROUP__SHIFT 12 /* right shift */
175 #define SMMU_TLB_FLUSH_VA(iova, which) \
176 ((((iova) & SMMU_TLB_FLUSH_VA_##which##__MASK) >> \
177 SMMU_TLB_FLUSH_VA_##which##__SHIFT) | \
178 SMMU_TLB_FLUSH_VA_MATCH_##which)
179 #define SMMU_PTB_ASID_CUR(n) \
180 ((n) << SMMU_PTB_ASID_CURRENT_SHIFT)
181 #define SMMU_TLB_FLUSH_ASID_MATCH_disable \
182 (SMMU_TLB_FLUSH_ASID_MATCH_DISABLE << \
183 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
184 #define SMMU_TLB_FLUSH_ASID_MATCH__ENABLE \
185 (SMMU_TLB_FLUSH_ASID_MATCH_ENABLE << \
186 SMMU_TLB_FLUSH_ASID_MATCH_SHIFT)
188 #define SMMU_PAGE_SHIFT 12
189 #define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
190 #define SMMU_PAGE_MASK ((1 << SMMU_PAGE_SHIFT) - 1)
192 #define SMMU_PDIR_COUNT 1024
193 #define SMMU_PDIR_SIZE (sizeof(unsigned long) * SMMU_PDIR_COUNT)
194 #define SMMU_PTBL_COUNT 1024
195 #define SMMU_PTBL_SIZE (sizeof(unsigned long) * SMMU_PTBL_COUNT)
196 #define SMMU_PDIR_SHIFT 12
197 #define SMMU_PDE_SHIFT 12
198 #define SMMU_PTE_SHIFT 12
199 #define SMMU_PFN_MASK 0x000fffff
201 #define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
202 #define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
203 #define SMMU_PDN_TO_ADDR(pdn) ((pdn) << 22)
205 #define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
206 #define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
207 #define _NONSECURE (1 << SMMU_PTB_DATA_ASID_NONSECURE_SHIFT)
208 #define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT)
209 #define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
211 #define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
213 #define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
214 #define _PDE_ATTR_N (_PDE_ATTR | _PDE_NEXT)
215 #define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
217 #define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
218 #define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
220 #define SMMU_MK_PDIR(page, attr) \
221 ((page_to_phys(page) >> SMMU_PDIR_SHIFT) | (attr))
222 #define SMMU_MK_PDE(page, attr) \
223 (unsigned long)((page_to_phys(page) >> SMMU_PDE_SHIFT) | (attr))
224 #define SMMU_EX_PTBL_PAGE(pde) \
225 pfn_to_page((unsigned long)(pde) & SMMU_PFN_MASK)
226 #define SMMU_PFN_TO_PTE(pfn, attr) (unsigned long)((pfn) | (attr))
228 #define SMMU_ASID_ENABLE(asid) ((asid) | (1 << 31))
229 #define SMMU_ASID_DISABLE 0
230 #define SMMU_ASID_ASID(n) ((n) & ~SMMU_ASID_ENABLE(0))
232 #define NUM_SMMU_REG_BANKS 3
234 #define smmu_client_enable_hwgrp(c, m) smmu_client_set_hwgrp(c, m, 1)
235 #define smmu_client_disable_hwgrp(c) smmu_client_set_hwgrp(c, 0, 0)
236 #define __smmu_client_enable_hwgrp(c, m) __smmu_client_set_hwgrp(c, m, 1)
237 #define __smmu_client_disable_hwgrp(c) __smmu_client_set_hwgrp(c, 0, 0)
239 #define HWGRP_INIT(client) [HWGRP_##client] = SMMU_##client##_ASID
241 static const u32 smmu_hwgrp_asid_reg
[] = {
259 #define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x])
262 * Per client for address space
266 struct list_head list
;
275 struct smmu_device
*smmu
; /* back pointer to container */
277 spinlock_t lock
; /* for pagetable */
278 struct page
*pdir_page
;
279 unsigned long pdir_attr
;
280 unsigned long pde_attr
;
281 unsigned long pte_attr
;
282 unsigned int *pte_count
;
284 struct list_head client
;
285 spinlock_t client_lock
; /* for client list */
288 struct smmu_debugfs_info
{
289 struct smmu_device
*smmu
;
295 * Per SMMU device - IOMMU device
298 void __iomem
*regs
[NUM_SMMU_REG_BANKS
];
299 unsigned long iovmm_base
; /* remappable base address */
300 unsigned long page_count
; /* total remappable size */
304 struct page
*avp_vector_page
; /* dummy page shared by all AS's */
307 * Register image savers for suspend/resume
309 unsigned long translation_enable_0
;
310 unsigned long translation_enable_1
;
311 unsigned long translation_enable_2
;
312 unsigned long asid_security
;
314 struct dentry
*debugfs_root
;
315 struct smmu_debugfs_info
*debugfs_info
;
317 struct device_node
*ahb
;
320 struct smmu_as as
[0]; /* Run-time allocated array */
323 static struct smmu_device
*smmu_handle
; /* unique for a system */
326 * SMMU register accessors
328 static inline u32
smmu_read(struct smmu_device
*smmu
, size_t offs
)
332 return readl(smmu
->regs
[0] + offs
- 0x10);
333 BUG_ON(offs
< 0x1f0);
335 return readl(smmu
->regs
[1] + offs
- 0x1f0);
336 BUG_ON(offs
< 0x228);
338 return readl(smmu
->regs
[2] + offs
- 0x228);
342 static inline void smmu_write(struct smmu_device
*smmu
, u32 val
, size_t offs
)
346 writel(val
, smmu
->regs
[0] + offs
- 0x10);
349 BUG_ON(offs
< 0x1f0);
351 writel(val
, smmu
->regs
[1] + offs
- 0x1f0);
354 BUG_ON(offs
< 0x228);
356 writel(val
, smmu
->regs
[2] + offs
- 0x228);
362 #define VA_PAGE_TO_PA(va, page) \
363 (page_to_phys(page) + ((unsigned long)(va) & ~PAGE_MASK))
365 #define FLUSH_CPU_DCACHE(va, page, size) \
367 unsigned long _pa_ = VA_PAGE_TO_PA(va, page); \
368 __cpuc_flush_dcache_area((void *)(va), (size_t)(size)); \
369 outer_flush_range(_pa_, _pa_+(size_t)(size)); \
373 * Any interaction between any block on PPSB and a block on APB or AHB
374 * must have these read-back barriers to ensure the APB/AHB bus
375 * transaction is complete before initiating activity on the PPSB
378 #define FLUSH_SMMU_REGS(smmu) smmu_read(smmu, SMMU_CONFIG)
380 #define smmu_client_hwgrp(c) (u32)((c)->dev->platform_data)
382 static int __smmu_client_set_hwgrp(struct smmu_client
*c
,
383 unsigned long map
, int on
)
386 struct smmu_as
*as
= c
->as
;
387 u32 val
, offs
, mask
= SMMU_ASID_ENABLE(as
->asid
);
388 struct smmu_device
*smmu
= as
->smmu
;
394 map
= smmu_client_hwgrp(c
);
396 for_each_set_bit(i
, &map
, HWGRP_COUNT
) {
397 offs
= HWGRP_ASID_REG(i
);
398 val
= smmu_read(smmu
, offs
);
400 if (WARN_ON(val
& mask
))
404 WARN_ON((val
& mask
) == mask
);
407 smmu_write(smmu
, val
, offs
);
409 FLUSH_SMMU_REGS(smmu
);
414 for_each_set_bit(i
, &map
, HWGRP_COUNT
) {
415 offs
= HWGRP_ASID_REG(i
);
416 val
= smmu_read(smmu
, offs
);
418 smmu_write(smmu
, val
, offs
);
423 static int smmu_client_set_hwgrp(struct smmu_client
*c
, u32 map
, int on
)
427 struct smmu_as
*as
= c
->as
;
428 struct smmu_device
*smmu
= as
->smmu
;
430 spin_lock_irqsave(&smmu
->lock
, flags
);
431 val
= __smmu_client_set_hwgrp(c
, map
, on
);
432 spin_unlock_irqrestore(&smmu
->lock
, flags
);
437 * Flush all TLB entries and all PTC entries
438 * Caller must lock smmu
440 static void smmu_flush_regs(struct smmu_device
*smmu
, int enable
)
444 smmu_write(smmu
, SMMU_PTC_FLUSH_TYPE_ALL
, SMMU_PTC_FLUSH
);
445 FLUSH_SMMU_REGS(smmu
);
446 val
= SMMU_TLB_FLUSH_VA_MATCH_ALL
|
447 SMMU_TLB_FLUSH_ASID_MATCH_disable
;
448 smmu_write(smmu
, val
, SMMU_TLB_FLUSH
);
451 smmu_write(smmu
, SMMU_CONFIG_ENABLE
, SMMU_CONFIG
);
452 FLUSH_SMMU_REGS(smmu
);
455 static int smmu_setup_regs(struct smmu_device
*smmu
)
460 for (i
= 0; i
< smmu
->num_as
; i
++) {
461 struct smmu_as
*as
= &smmu
->as
[i
];
462 struct smmu_client
*c
;
464 smmu_write(smmu
, SMMU_PTB_ASID_CUR(as
->asid
), SMMU_PTB_ASID
);
465 val
= as
->pdir_page
?
466 SMMU_MK_PDIR(as
->pdir_page
, as
->pdir_attr
) :
467 SMMU_PTB_DATA_RESET_VAL
;
468 smmu_write(smmu
, val
, SMMU_PTB_DATA
);
470 list_for_each_entry(c
, &as
->client
, list
)
471 __smmu_client_set_hwgrp(c
, c
->hwgrp
, 1);
474 smmu_write(smmu
, smmu
->translation_enable_0
, SMMU_TRANSLATION_ENABLE_0
);
475 smmu_write(smmu
, smmu
->translation_enable_1
, SMMU_TRANSLATION_ENABLE_1
);
476 smmu_write(smmu
, smmu
->translation_enable_2
, SMMU_TRANSLATION_ENABLE_2
);
477 smmu_write(smmu
, smmu
->asid_security
, SMMU_ASID_SECURITY
);
478 smmu_write(smmu
, SMMU_TLB_CONFIG_RESET_VAL
, SMMU_CACHE_CONFIG(_TLB
));
479 smmu_write(smmu
, SMMU_PTC_CONFIG_RESET_VAL
, SMMU_CACHE_CONFIG(_PTC
));
481 smmu_flush_regs(smmu
, 1);
483 return tegra_ahb_enable_smmu(smmu
->ahb
);
486 static void flush_ptc_and_tlb(struct smmu_device
*smmu
,
487 struct smmu_as
*as
, dma_addr_t iova
,
488 unsigned long *pte
, struct page
*page
, int is_pde
)
491 unsigned long tlb_flush_va
= is_pde
492 ? SMMU_TLB_FLUSH_VA(iova
, SECTION
)
493 : SMMU_TLB_FLUSH_VA(iova
, GROUP
);
495 val
= SMMU_PTC_FLUSH_TYPE_ADR
| VA_PAGE_TO_PA(pte
, page
);
496 smmu_write(smmu
, val
, SMMU_PTC_FLUSH
);
497 FLUSH_SMMU_REGS(smmu
);
499 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE
|
500 (as
->asid
<< SMMU_TLB_FLUSH_ASID_SHIFT
);
501 smmu_write(smmu
, val
, SMMU_TLB_FLUSH
);
502 FLUSH_SMMU_REGS(smmu
);
505 static void free_ptbl(struct smmu_as
*as
, dma_addr_t iova
)
507 unsigned long pdn
= SMMU_ADDR_TO_PDN(iova
);
508 unsigned long *pdir
= (unsigned long *)page_address(as
->pdir_page
);
510 if (pdir
[pdn
] != _PDE_VACANT(pdn
)) {
511 dev_dbg(as
->smmu
->dev
, "pdn: %lx\n", pdn
);
513 ClearPageReserved(SMMU_EX_PTBL_PAGE(pdir
[pdn
]));
514 __free_page(SMMU_EX_PTBL_PAGE(pdir
[pdn
]));
515 pdir
[pdn
] = _PDE_VACANT(pdn
);
516 FLUSH_CPU_DCACHE(&pdir
[pdn
], as
->pdir_page
, sizeof pdir
[pdn
]);
517 flush_ptc_and_tlb(as
->smmu
, as
, iova
, &pdir
[pdn
],
522 static void free_pdir(struct smmu_as
*as
)
526 struct device
*dev
= as
->smmu
->dev
;
531 addr
= as
->smmu
->iovmm_base
;
532 count
= as
->smmu
->page_count
;
533 while (count
-- > 0) {
535 addr
+= SMMU_PAGE_SIZE
* SMMU_PTBL_COUNT
;
537 ClearPageReserved(as
->pdir_page
);
538 __free_page(as
->pdir_page
);
539 as
->pdir_page
= NULL
;
540 devm_kfree(dev
, as
->pte_count
);
541 as
->pte_count
= NULL
;
545 * Maps PTBL for given iova and returns the PTE address
546 * Caller must unmap the mapped PTBL returned in *ptbl_page_p
548 static unsigned long *locate_pte(struct smmu_as
*as
,
549 dma_addr_t iova
, bool allocate
,
550 struct page
**ptbl_page_p
,
551 unsigned int **count
)
553 unsigned long ptn
= SMMU_ADDR_TO_PFN(iova
);
554 unsigned long pdn
= SMMU_ADDR_TO_PDN(iova
);
555 unsigned long *pdir
= page_address(as
->pdir_page
);
558 if (pdir
[pdn
] != _PDE_VACANT(pdn
)) {
559 /* Mapped entry table already exists */
560 *ptbl_page_p
= SMMU_EX_PTBL_PAGE(pdir
[pdn
]);
561 ptbl
= page_address(*ptbl_page_p
);
562 } else if (!allocate
) {
566 unsigned long addr
= SMMU_PDN_TO_ADDR(pdn
);
568 /* Vacant - allocate a new page table */
569 dev_dbg(as
->smmu
->dev
, "New PTBL pdn: %lx\n", pdn
);
571 *ptbl_page_p
= alloc_page(GFP_ATOMIC
);
573 dev_err(as
->smmu
->dev
,
574 "failed to allocate smmu_device page table\n");
577 SetPageReserved(*ptbl_page_p
);
578 ptbl
= (unsigned long *)page_address(*ptbl_page_p
);
579 for (pn
= 0; pn
< SMMU_PTBL_COUNT
;
580 pn
++, addr
+= SMMU_PAGE_SIZE
) {
581 ptbl
[pn
] = _PTE_VACANT(addr
);
583 FLUSH_CPU_DCACHE(ptbl
, *ptbl_page_p
, SMMU_PTBL_SIZE
);
584 pdir
[pdn
] = SMMU_MK_PDE(*ptbl_page_p
,
585 as
->pde_attr
| _PDE_NEXT
);
586 FLUSH_CPU_DCACHE(&pdir
[pdn
], as
->pdir_page
, sizeof pdir
[pdn
]);
587 flush_ptc_and_tlb(as
->smmu
, as
, iova
, &pdir
[pdn
],
590 *count
= &as
->pte_count
[pdn
];
592 return &ptbl
[ptn
% SMMU_PTBL_COUNT
];
595 #ifdef CONFIG_SMMU_SIG_DEBUG
596 static void put_signature(struct smmu_as
*as
,
597 dma_addr_t iova
, unsigned long pfn
)
600 unsigned long *vaddr
;
602 page
= pfn_to_page(pfn
);
603 vaddr
= page_address(page
);
608 vaddr
[1] = pfn
<< PAGE_SHIFT
;
609 FLUSH_CPU_DCACHE(vaddr
, page
, sizeof(vaddr
[0]) * 2);
612 static inline void put_signature(struct smmu_as
*as
,
613 unsigned long addr
, unsigned long pfn
)
619 * Caller must not hold as->lock
621 static int alloc_pdir(struct smmu_as
*as
)
623 unsigned long *pdir
, flags
;
626 struct smmu_device
*smmu
= as
->smmu
;
631 * do the allocation, then grab as->lock
633 cnt
= devm_kzalloc(smmu
->dev
,
634 sizeof(cnt
[0]) * SMMU_PDIR_COUNT
,
636 page
= alloc_page(GFP_KERNEL
| __GFP_DMA
);
638 spin_lock_irqsave(&as
->lock
, flags
);
641 /* We raced, free the redundant */
647 dev_err(smmu
->dev
, "failed to allocate at %s\n", __func__
);
652 as
->pdir_page
= page
;
655 SetPageReserved(as
->pdir_page
);
656 pdir
= page_address(as
->pdir_page
);
658 for (pdn
= 0; pdn
< SMMU_PDIR_COUNT
; pdn
++)
659 pdir
[pdn
] = _PDE_VACANT(pdn
);
660 FLUSH_CPU_DCACHE(pdir
, as
->pdir_page
, SMMU_PDIR_SIZE
);
661 val
= SMMU_PTC_FLUSH_TYPE_ADR
| VA_PAGE_TO_PA(pdir
, as
->pdir_page
);
662 smmu_write(smmu
, val
, SMMU_PTC_FLUSH
);
663 FLUSH_SMMU_REGS(as
->smmu
);
664 val
= SMMU_TLB_FLUSH_VA_MATCH_ALL
|
665 SMMU_TLB_FLUSH_ASID_MATCH__ENABLE
|
666 (as
->asid
<< SMMU_TLB_FLUSH_ASID_SHIFT
);
667 smmu_write(smmu
, val
, SMMU_TLB_FLUSH
);
668 FLUSH_SMMU_REGS(as
->smmu
);
670 spin_unlock_irqrestore(&as
->lock
, flags
);
675 spin_unlock_irqrestore(&as
->lock
, flags
);
677 devm_kfree(smmu
->dev
, cnt
);
683 static void __smmu_iommu_unmap(struct smmu_as
*as
, dma_addr_t iova
)
689 pte
= locate_pte(as
, iova
, false, &page
, &count
);
693 if (WARN_ON(*pte
== _PTE_VACANT(iova
)))
696 *pte
= _PTE_VACANT(iova
);
697 FLUSH_CPU_DCACHE(pte
, page
, sizeof(*pte
));
698 flush_ptc_and_tlb(as
->smmu
, as
, iova
, pte
, page
, 0);
701 smmu_flush_regs(as
->smmu
, 0);
705 static void __smmu_iommu_map_pfn(struct smmu_as
*as
, dma_addr_t iova
,
708 struct smmu_device
*smmu
= as
->smmu
;
713 pte
= locate_pte(as
, iova
, true, &page
, &count
);
717 if (*pte
== _PTE_VACANT(iova
))
719 *pte
= SMMU_PFN_TO_PTE(pfn
, as
->pte_attr
);
720 if (unlikely((*pte
== _PTE_VACANT(iova
))))
722 FLUSH_CPU_DCACHE(pte
, page
, sizeof(*pte
));
723 flush_ptc_and_tlb(smmu
, as
, iova
, pte
, page
, 0);
724 put_signature(as
, iova
, pfn
);
727 static int smmu_iommu_map(struct iommu_domain
*domain
, unsigned long iova
,
728 phys_addr_t pa
, size_t bytes
, int prot
)
730 struct smmu_as
*as
= domain
->priv
;
731 unsigned long pfn
= __phys_to_pfn(pa
);
734 dev_dbg(as
->smmu
->dev
, "[%d] %08lx:%08x\n", as
->asid
, iova
, pa
);
739 spin_lock_irqsave(&as
->lock
, flags
);
740 __smmu_iommu_map_pfn(as
, iova
, pfn
);
741 spin_unlock_irqrestore(&as
->lock
, flags
);
745 static size_t smmu_iommu_unmap(struct iommu_domain
*domain
, unsigned long iova
,
748 struct smmu_as
*as
= domain
->priv
;
751 dev_dbg(as
->smmu
->dev
, "[%d] %08lx\n", as
->asid
, iova
);
753 spin_lock_irqsave(&as
->lock
, flags
);
754 __smmu_iommu_unmap(as
, iova
);
755 spin_unlock_irqrestore(&as
->lock
, flags
);
756 return SMMU_PAGE_SIZE
;
759 static phys_addr_t
smmu_iommu_iova_to_phys(struct iommu_domain
*domain
,
762 struct smmu_as
*as
= domain
->priv
;
769 spin_lock_irqsave(&as
->lock
, flags
);
771 pte
= locate_pte(as
, iova
, true, &page
, &count
);
772 pfn
= *pte
& SMMU_PFN_MASK
;
773 WARN_ON(!pfn_valid(pfn
));
774 dev_dbg(as
->smmu
->dev
,
775 "iova:%08lx pfn:%08lx asid:%d\n", iova
, pfn
, as
->asid
);
777 spin_unlock_irqrestore(&as
->lock
, flags
);
778 return PFN_PHYS(pfn
);
781 static int smmu_iommu_domain_has_cap(struct iommu_domain
*domain
,
787 static int smmu_iommu_attach_dev(struct iommu_domain
*domain
,
790 struct smmu_as
*as
= domain
->priv
;
791 struct smmu_device
*smmu
= as
->smmu
;
792 struct smmu_client
*client
, *c
;
796 client
= devm_kzalloc(smmu
->dev
, sizeof(*c
), GFP_KERNEL
);
801 map
= (unsigned long)dev
->platform_data
;
805 err
= smmu_client_enable_hwgrp(client
, map
);
809 spin_lock(&as
->client_lock
);
810 list_for_each_entry(c
, &as
->client
, list
) {
813 "%s is already attached\n", dev_name(c
->dev
));
818 list_add(&client
->list
, &as
->client
);
819 spin_unlock(&as
->client_lock
);
822 * Reserve "page zero" for AVP vectors using a common dummy
825 if (map
& HWG_AVPC
) {
828 page
= as
->smmu
->avp_vector_page
;
829 __smmu_iommu_map_pfn(as
, 0, page_to_pfn(page
));
831 pr_info("Reserve \"page zero\" for AVP vectors using a common dummy\n");
834 dev_dbg(smmu
->dev
, "%s is attached\n", dev_name(dev
));
838 smmu_client_disable_hwgrp(client
);
839 spin_unlock(&as
->client_lock
);
841 devm_kfree(smmu
->dev
, client
);
845 static void smmu_iommu_detach_dev(struct iommu_domain
*domain
,
848 struct smmu_as
*as
= domain
->priv
;
849 struct smmu_device
*smmu
= as
->smmu
;
850 struct smmu_client
*c
;
852 spin_lock(&as
->client_lock
);
854 list_for_each_entry(c
, &as
->client
, list
) {
856 smmu_client_disable_hwgrp(c
);
858 devm_kfree(smmu
->dev
, c
);
861 "%s is detached\n", dev_name(c
->dev
));
865 dev_err(smmu
->dev
, "Couldn't find %s\n", dev_name(dev
));
867 spin_unlock(&as
->client_lock
);
870 static int smmu_iommu_domain_init(struct iommu_domain
*domain
)
872 int i
, err
= -EAGAIN
;
875 struct smmu_device
*smmu
= smmu_handle
;
877 /* Look for a free AS with lock held */
878 for (i
= 0; i
< smmu
->num_as
; i
++) {
884 err
= alloc_pdir(as
);
891 if (i
== smmu
->num_as
)
892 dev_err(smmu
->dev
, "no free AS\n");
896 spin_lock_irqsave(&smmu
->lock
, flags
);
898 /* Update PDIR register */
899 smmu_write(smmu
, SMMU_PTB_ASID_CUR(as
->asid
), SMMU_PTB_ASID
);
901 SMMU_MK_PDIR(as
->pdir_page
, as
->pdir_attr
), SMMU_PTB_DATA
);
902 FLUSH_SMMU_REGS(smmu
);
904 spin_unlock_irqrestore(&smmu
->lock
, flags
);
908 domain
->geometry
.aperture_start
= smmu
->iovmm_base
;
909 domain
->geometry
.aperture_end
= smmu
->iovmm_base
+
910 smmu
->page_count
* SMMU_PAGE_SIZE
- 1;
911 domain
->geometry
.force_aperture
= true;
913 dev_dbg(smmu
->dev
, "smmu_as@%p\n", as
);
918 static void smmu_iommu_domain_destroy(struct iommu_domain
*domain
)
920 struct smmu_as
*as
= domain
->priv
;
921 struct smmu_device
*smmu
= as
->smmu
;
924 spin_lock_irqsave(&as
->lock
, flags
);
927 spin_lock(&smmu
->lock
);
928 smmu_write(smmu
, SMMU_PTB_ASID_CUR(as
->asid
), SMMU_PTB_ASID
);
929 smmu_write(smmu
, SMMU_PTB_DATA_RESET_VAL
, SMMU_PTB_DATA
);
930 FLUSH_SMMU_REGS(smmu
);
931 spin_unlock(&smmu
->lock
);
936 if (!list_empty(&as
->client
)) {
937 struct smmu_client
*c
;
939 list_for_each_entry(c
, &as
->client
, list
)
940 smmu_iommu_detach_dev(domain
, c
->dev
);
943 spin_unlock_irqrestore(&as
->lock
, flags
);
946 dev_dbg(smmu
->dev
, "smmu_as@%p\n", as
);
949 static struct iommu_ops smmu_iommu_ops
= {
950 .domain_init
= smmu_iommu_domain_init
,
951 .domain_destroy
= smmu_iommu_domain_destroy
,
952 .attach_dev
= smmu_iommu_attach_dev
,
953 .detach_dev
= smmu_iommu_detach_dev
,
954 .map
= smmu_iommu_map
,
955 .unmap
= smmu_iommu_unmap
,
956 .iova_to_phys
= smmu_iommu_iova_to_phys
,
957 .domain_has_cap
= smmu_iommu_domain_has_cap
,
958 .pgsize_bitmap
= SMMU_IOMMU_PGSIZES
,
961 /* Should be in the order of enum */
962 static const char * const smmu_debugfs_mc
[] = { "mc", };
963 static const char * const smmu_debugfs_cache
[] = { "tlb", "ptc", };
965 static ssize_t
smmu_debugfs_stats_write(struct file
*file
,
966 const char __user
*buffer
,
967 size_t count
, loff_t
*pos
)
969 struct smmu_debugfs_info
*info
;
970 struct smmu_device
*smmu
;
978 const char * const command
[] = {
983 char str
[] = "reset";
987 count
= min_t(size_t, count
, sizeof(str
));
988 if (copy_from_user(str
, buffer
, count
))
991 for (i
= 0; i
< ARRAY_SIZE(command
); i
++)
992 if (strncmp(str
, command
[i
],
993 strlen(command
[i
])) == 0)
996 if (i
== ARRAY_SIZE(command
))
999 dent
= file
->f_dentry
;
1000 info
= dent
->d_inode
->i_private
;
1003 offs
= SMMU_CACHE_CONFIG(info
->cache
);
1004 val
= smmu_read(smmu
, offs
);
1007 val
&= ~SMMU_CACHE_CONFIG_STATS_ENABLE
;
1008 val
&= ~SMMU_CACHE_CONFIG_STATS_TEST
;
1009 smmu_write(smmu
, val
, offs
);
1012 val
|= SMMU_CACHE_CONFIG_STATS_ENABLE
;
1013 val
&= ~SMMU_CACHE_CONFIG_STATS_TEST
;
1014 smmu_write(smmu
, val
, offs
);
1017 val
|= SMMU_CACHE_CONFIG_STATS_TEST
;
1018 smmu_write(smmu
, val
, offs
);
1019 val
&= ~SMMU_CACHE_CONFIG_STATS_TEST
;
1020 smmu_write(smmu
, val
, offs
);
1027 dev_dbg(smmu
->dev
, "%s() %08x, %08x @%08x\n", __func__
,
1028 val
, smmu_read(smmu
, offs
), offs
);
1033 static int smmu_debugfs_stats_show(struct seq_file
*s
, void *v
)
1035 struct smmu_debugfs_info
*info
;
1036 struct smmu_device
*smmu
;
1037 struct dentry
*dent
;
1039 const char * const stats
[] = { "hit", "miss", };
1041 dent
= d_find_alias(s
->private);
1042 info
= dent
->d_inode
->i_private
;
1045 for (i
= 0; i
< ARRAY_SIZE(stats
); i
++) {
1049 offs
= SMMU_STATS_CACHE_COUNT(info
->mc
, info
->cache
, i
);
1050 val
= smmu_read(smmu
, offs
);
1051 seq_printf(s
, "%s:%08x ", stats
[i
], val
);
1053 dev_dbg(smmu
->dev
, "%s() %s %08x @%08x\n", __func__
,
1054 stats
[i
], val
, offs
);
1056 seq_printf(s
, "\n");
1061 static int smmu_debugfs_stats_open(struct inode
*inode
, struct file
*file
)
1063 return single_open(file
, smmu_debugfs_stats_show
, inode
);
1066 static const struct file_operations smmu_debugfs_stats_fops
= {
1067 .open
= smmu_debugfs_stats_open
,
1069 .llseek
= seq_lseek
,
1070 .release
= single_release
,
1071 .write
= smmu_debugfs_stats_write
,
1074 static void smmu_debugfs_delete(struct smmu_device
*smmu
)
1076 debugfs_remove_recursive(smmu
->debugfs_root
);
1077 kfree(smmu
->debugfs_info
);
1080 static void smmu_debugfs_create(struct smmu_device
*smmu
)
1084 struct dentry
*root
;
1086 bytes
= ARRAY_SIZE(smmu_debugfs_mc
) * ARRAY_SIZE(smmu_debugfs_cache
) *
1087 sizeof(*smmu
->debugfs_info
);
1088 smmu
->debugfs_info
= kmalloc(bytes
, GFP_KERNEL
);
1089 if (!smmu
->debugfs_info
)
1092 root
= debugfs_create_dir(dev_name(smmu
->dev
), NULL
);
1095 smmu
->debugfs_root
= root
;
1097 for (i
= 0; i
< ARRAY_SIZE(smmu_debugfs_mc
); i
++) {
1101 mc
= debugfs_create_dir(smmu_debugfs_mc
[i
], root
);
1105 for (j
= 0; j
< ARRAY_SIZE(smmu_debugfs_cache
); j
++) {
1106 struct dentry
*cache
;
1107 struct smmu_debugfs_info
*info
;
1109 info
= smmu
->debugfs_info
;
1110 info
+= i
* ARRAY_SIZE(smmu_debugfs_mc
) + j
;
1115 cache
= debugfs_create_file(smmu_debugfs_cache
[j
],
1116 S_IWUGO
| S_IRUGO
, mc
,
1118 &smmu_debugfs_stats_fops
);
1127 smmu_debugfs_delete(smmu
);
1130 static int tegra_smmu_suspend(struct device
*dev
)
1132 struct smmu_device
*smmu
= dev_get_drvdata(dev
);
1134 smmu
->translation_enable_0
= smmu_read(smmu
, SMMU_TRANSLATION_ENABLE_0
);
1135 smmu
->translation_enable_1
= smmu_read(smmu
, SMMU_TRANSLATION_ENABLE_1
);
1136 smmu
->translation_enable_2
= smmu_read(smmu
, SMMU_TRANSLATION_ENABLE_2
);
1137 smmu
->asid_security
= smmu_read(smmu
, SMMU_ASID_SECURITY
);
1141 static int tegra_smmu_resume(struct device
*dev
)
1143 struct smmu_device
*smmu
= dev_get_drvdata(dev
);
1144 unsigned long flags
;
1147 spin_lock_irqsave(&smmu
->lock
, flags
);
1148 err
= smmu_setup_regs(smmu
);
1149 spin_unlock_irqrestore(&smmu
->lock
, flags
);
1153 static int tegra_smmu_probe(struct platform_device
*pdev
)
1155 struct smmu_device
*smmu
;
1156 struct device
*dev
= &pdev
->dev
;
1157 int i
, asids
, err
= 0;
1158 dma_addr_t
uninitialized_var(base
);
1159 size_t bytes
, uninitialized_var(size
);
1164 BUILD_BUG_ON(PAGE_SHIFT
!= SMMU_PAGE_SHIFT
);
1166 if (of_property_read_u32(dev
->of_node
, "nvidia,#asids", &asids
))
1169 bytes
= sizeof(*smmu
) + asids
* sizeof(*smmu
->as
);
1170 smmu
= devm_kzalloc(dev
, bytes
, GFP_KERNEL
);
1172 dev_err(dev
, "failed to allocate smmu_device\n");
1176 for (i
= 0; i
< ARRAY_SIZE(smmu
->regs
); i
++) {
1177 struct resource
*res
;
1179 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, i
);
1182 smmu
->regs
[i
] = devm_request_and_ioremap(&pdev
->dev
, res
);
1187 err
= of_get_dma_window(dev
->of_node
, NULL
, 0, NULL
, &base
, &size
);
1191 if (size
& SMMU_PAGE_MASK
)
1194 size
>>= SMMU_PAGE_SHIFT
;
1198 smmu
->ahb
= of_parse_phandle(dev
->of_node
, "nvidia,ahb", 0);
1203 smmu
->num_as
= asids
;
1204 smmu
->iovmm_base
= base
;
1205 smmu
->page_count
= size
;
1207 smmu
->translation_enable_0
= ~0;
1208 smmu
->translation_enable_1
= ~0;
1209 smmu
->translation_enable_2
= ~0;
1210 smmu
->asid_security
= 0;
1212 for (i
= 0; i
< smmu
->num_as
; i
++) {
1213 struct smmu_as
*as
= &smmu
->as
[i
];
1217 as
->pdir_attr
= _PDIR_ATTR
;
1218 as
->pde_attr
= _PDE_ATTR
;
1219 as
->pte_attr
= _PTE_ATTR
;
1221 spin_lock_init(&as
->lock
);
1222 INIT_LIST_HEAD(&as
->client
);
1224 spin_lock_init(&smmu
->lock
);
1225 err
= smmu_setup_regs(smmu
);
1228 platform_set_drvdata(pdev
, smmu
);
1230 smmu
->avp_vector_page
= alloc_page(GFP_KERNEL
);
1231 if (!smmu
->avp_vector_page
)
1234 smmu_debugfs_create(smmu
);
1239 static int tegra_smmu_remove(struct platform_device
*pdev
)
1241 struct smmu_device
*smmu
= platform_get_drvdata(pdev
);
1244 smmu_debugfs_delete(smmu
);
1246 smmu_write(smmu
, SMMU_CONFIG_DISABLE
, SMMU_CONFIG
);
1247 for (i
= 0; i
< smmu
->num_as
; i
++)
1248 free_pdir(&smmu
->as
[i
]);
1249 __free_page(smmu
->avp_vector_page
);
1254 const struct dev_pm_ops tegra_smmu_pm_ops
= {
1255 .suspend
= tegra_smmu_suspend
,
1256 .resume
= tegra_smmu_resume
,
1260 static struct of_device_id tegra_smmu_of_match
[] __devinitdata
= {
1261 { .compatible
= "nvidia,tegra30-smmu", },
1264 MODULE_DEVICE_TABLE(of
, tegra_smmu_of_match
);
1267 static struct platform_driver tegra_smmu_driver
= {
1268 .probe
= tegra_smmu_probe
,
1269 .remove
= tegra_smmu_remove
,
1271 .owner
= THIS_MODULE
,
1272 .name
= "tegra-smmu",
1273 .pm
= &tegra_smmu_pm_ops
,
1274 .of_match_table
= of_match_ptr(tegra_smmu_of_match
),
1278 static int __devinit
tegra_smmu_init(void)
1280 bus_set_iommu(&platform_bus_type
, &smmu_iommu_ops
);
1281 return platform_driver_register(&tegra_smmu_driver
);
1284 static void __exit
tegra_smmu_exit(void)
1286 platform_driver_unregister(&tegra_smmu_driver
);
1289 subsys_initcall(tegra_smmu_init
);
1290 module_exit(tegra_smmu_exit
);
1292 MODULE_DESCRIPTION("IOMMU API for SMMU in Tegra30");
1293 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
1294 MODULE_ALIAS("platform:tegra-smmu");
1295 MODULE_LICENSE("GPL v2");