Merge branch 'mailbox-for-next' of git://git.linaro.org/landing-teams/working/fujitsu...
[deliverable/linux.git] / drivers / irqchip / Kconfig
1 config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
5 config ARM_GIC
6 bool
7 select IRQ_DOMAIN
8 select IRQ_DOMAIN_HIERARCHY
9 select MULTI_IRQ_HANDLER
10
11 config ARM_GIC_MAX_NR
12 int
13 default 2 if ARCH_REALVIEW
14 default 1
15
16 config ARM_GIC_V2M
17 bool
18 depends on ARM_GIC
19 depends on PCI && PCI_MSI
20 select PCI_MSI_IRQ_DOMAIN
21
22 config GIC_NON_BANKED
23 bool
24
25 config ARM_GIC_V3
26 bool
27 select IRQ_DOMAIN
28 select MULTI_IRQ_HANDLER
29 select IRQ_DOMAIN_HIERARCHY
30
31 config ARM_GIC_V3_ITS
32 bool
33 select PCI_MSI_IRQ_DOMAIN
34
35 config HISILICON_IRQ_MBIGEN
36 bool "Support mbigen interrupt controller"
37 default n
38 depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
39 help
40 Enable the mbigen interrupt controller used on
41 Hisilicon platform.
42
43 config ARM_NVIC
44 bool
45 select IRQ_DOMAIN
46 select IRQ_DOMAIN_HIERARCHY
47 select GENERIC_IRQ_CHIP
48
49 config ARM_VIC
50 bool
51 select IRQ_DOMAIN
52 select MULTI_IRQ_HANDLER
53
54 config ARM_VIC_NR
55 int
56 default 4 if ARCH_S5PV210
57 default 2
58 depends on ARM_VIC
59 help
60 The maximum number of VICs available in the system, for
61 power management.
62
63 config ARMADA_370_XP_IRQ
64 bool
65 select GENERIC_IRQ_CHIP
66 select PCI_MSI_IRQ_DOMAIN if PCI_MSI
67
68 config ALPINE_MSI
69 bool
70 depends on PCI && PCI_MSI
71 select GENERIC_IRQ_CHIP
72 select PCI_MSI_IRQ_DOMAIN
73
74 config ATMEL_AIC_IRQ
75 bool
76 select GENERIC_IRQ_CHIP
77 select IRQ_DOMAIN
78 select MULTI_IRQ_HANDLER
79 select SPARSE_IRQ
80
81 config ATMEL_AIC5_IRQ
82 bool
83 select GENERIC_IRQ_CHIP
84 select IRQ_DOMAIN
85 select MULTI_IRQ_HANDLER
86 select SPARSE_IRQ
87
88 config I8259
89 bool
90 select IRQ_DOMAIN
91
92 config BCM6345_L1_IRQ
93 bool
94 select GENERIC_IRQ_CHIP
95 select IRQ_DOMAIN
96
97 config BCM7038_L1_IRQ
98 bool
99 select GENERIC_IRQ_CHIP
100 select IRQ_DOMAIN
101
102 config BCM7120_L2_IRQ
103 bool
104 select GENERIC_IRQ_CHIP
105 select IRQ_DOMAIN
106
107 config BRCMSTB_L2_IRQ
108 bool
109 select GENERIC_IRQ_CHIP
110 select IRQ_DOMAIN
111
112 config DW_APB_ICTL
113 bool
114 select GENERIC_IRQ_CHIP
115 select IRQ_DOMAIN
116
117 config IMGPDC_IRQ
118 bool
119 select GENERIC_IRQ_CHIP
120 select IRQ_DOMAIN
121
122 config IRQ_MIPS_CPU
123 bool
124 select GENERIC_IRQ_CHIP
125 select IRQ_DOMAIN
126
127 config CLPS711X_IRQCHIP
128 bool
129 depends on ARCH_CLPS711X
130 select IRQ_DOMAIN
131 select MULTI_IRQ_HANDLER
132 select SPARSE_IRQ
133 default y
134
135 config OR1K_PIC
136 bool
137 select IRQ_DOMAIN
138
139 config OMAP_IRQCHIP
140 bool
141 select GENERIC_IRQ_CHIP
142 select IRQ_DOMAIN
143
144 config ORION_IRQCHIP
145 bool
146 select IRQ_DOMAIN
147 select MULTI_IRQ_HANDLER
148
149 config PIC32_EVIC
150 bool
151 select GENERIC_IRQ_CHIP
152 select IRQ_DOMAIN
153
154 config RENESAS_INTC_IRQPIN
155 bool
156 select IRQ_DOMAIN
157
158 config RENESAS_IRQC
159 bool
160 select GENERIC_IRQ_CHIP
161 select IRQ_DOMAIN
162
163 config ST_IRQCHIP
164 bool
165 select REGMAP
166 select MFD_SYSCON
167 help
168 Enables SysCfg Controlled IRQs on STi based platforms.
169
170 config TANGO_IRQ
171 bool
172 select IRQ_DOMAIN
173 select GENERIC_IRQ_CHIP
174
175 config TB10X_IRQC
176 bool
177 select IRQ_DOMAIN
178 select GENERIC_IRQ_CHIP
179
180 config TS4800_IRQ
181 tristate "TS-4800 IRQ controller"
182 select IRQ_DOMAIN
183 depends on HAS_IOMEM
184 depends on SOC_IMX51 || COMPILE_TEST
185 help
186 Support for the TS-4800 FPGA IRQ controller
187
188 config VERSATILE_FPGA_IRQ
189 bool
190 select IRQ_DOMAIN
191
192 config VERSATILE_FPGA_IRQ_NR
193 int
194 default 4
195 depends on VERSATILE_FPGA_IRQ
196
197 config XTENSA_MX
198 bool
199 select IRQ_DOMAIN
200
201 config IRQ_CROSSBAR
202 bool
203 help
204 Support for a CROSSBAR ip that precedes the main interrupt controller.
205 The primary irqchip invokes the crossbar's callback which inturn allocates
206 a free irq and configures the IP. Thus the peripheral interrupts are
207 routed to one of the free irqchip interrupt lines.
208
209 config KEYSTONE_IRQ
210 tristate "Keystone 2 IRQ controller IP"
211 depends on ARCH_KEYSTONE
212 help
213 Support for Texas Instruments Keystone 2 IRQ controller IP which
214 is part of the Keystone 2 IPC mechanism
215
216 config MIPS_GIC
217 bool
218 select GENERIC_IRQ_IPI
219 select IRQ_DOMAIN_HIERARCHY
220 select MIPS_CM
221
222 config INGENIC_IRQ
223 bool
224 depends on MACH_INGENIC
225 default y
226
227 config RENESAS_H8300H_INTC
228 bool
229 select IRQ_DOMAIN
230
231 config RENESAS_H8S_INTC
232 bool
233 select IRQ_DOMAIN
234
235 config IMX_GPCV2
236 bool
237 select IRQ_DOMAIN
238 help
239 Enables the wakeup IRQs for IMX platforms with GPCv2 block
240
241 config IRQ_MXS
242 def_bool y if MACH_ASM9260 || ARCH_MXS
243 select IRQ_DOMAIN
244 select STMP_DEVICE
245
246 config MVEBU_ODMI
247 bool
248 select GENERIC_MSI_IRQ_DOMAIN
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