2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Combiner irqchip for EXYNOS
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/err.h>
12 #include <linux/export.h>
13 #include <linux/init.h>
15 #include <linux/irqdomain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <asm/mach/irq.h>
24 #define COMBINER_ENABLE_SET 0x0
25 #define COMBINER_ENABLE_CLEAR 0x4
26 #define COMBINER_INT_STATUS 0xC
28 static DEFINE_SPINLOCK(irq_controller_lock
);
30 struct combiner_chip_data
{
31 unsigned int irq_offset
;
32 unsigned int irq_mask
;
36 static struct irq_domain
*combiner_irq_domain
;
37 static struct combiner_chip_data combiner_data
[MAX_COMBINER_NR
];
39 static inline void __iomem
*combiner_base(struct irq_data
*data
)
41 struct combiner_chip_data
*combiner_data
=
42 irq_data_get_irq_chip_data(data
);
44 return combiner_data
->base
;
47 static void combiner_mask_irq(struct irq_data
*data
)
49 u32 mask
= 1 << (data
->hwirq
% 32);
51 __raw_writel(mask
, combiner_base(data
) + COMBINER_ENABLE_CLEAR
);
54 static void combiner_unmask_irq(struct irq_data
*data
)
56 u32 mask
= 1 << (data
->hwirq
% 32);
58 __raw_writel(mask
, combiner_base(data
) + COMBINER_ENABLE_SET
);
61 static void combiner_handle_cascade_irq(unsigned int irq
, struct irq_desc
*desc
)
63 struct combiner_chip_data
*chip_data
= irq_get_handler_data(irq
);
64 struct irq_chip
*chip
= irq_get_chip(irq
);
65 unsigned int cascade_irq
, combiner_irq
;
68 chained_irq_enter(chip
, desc
);
70 spin_lock(&irq_controller_lock
);
71 status
= __raw_readl(chip_data
->base
+ COMBINER_INT_STATUS
);
72 spin_unlock(&irq_controller_lock
);
73 status
&= chip_data
->irq_mask
;
78 combiner_irq
= __ffs(status
);
80 cascade_irq
= combiner_irq
+ (chip_data
->irq_offset
& ~31);
81 if (unlikely(cascade_irq
>= NR_IRQS
))
82 do_bad_IRQ(cascade_irq
, desc
);
84 generic_handle_irq(cascade_irq
);
87 chained_irq_exit(chip
, desc
);
90 static struct irq_chip combiner_chip
= {
92 .irq_mask
= combiner_mask_irq
,
93 .irq_unmask
= combiner_unmask_irq
,
96 static void __init
combiner_cascade_irq(unsigned int combiner_nr
, unsigned int irq
)
100 if (soc_is_exynos5250())
101 max_nr
= EXYNOS5_MAX_COMBINER_NR
;
103 max_nr
= EXYNOS4_MAX_COMBINER_NR
;
105 if (combiner_nr
>= max_nr
)
107 if (irq_set_handler_data(irq
, &combiner_data
[combiner_nr
]) != 0)
109 irq_set_chained_handler(irq
, combiner_handle_cascade_irq
);
112 static void __init
combiner_init_one(unsigned int combiner_nr
,
115 combiner_data
[combiner_nr
].base
= base
;
116 combiner_data
[combiner_nr
].irq_offset
= irq_find_mapping(
117 combiner_irq_domain
, combiner_nr
* MAX_IRQ_IN_COMBINER
);
118 combiner_data
[combiner_nr
].irq_mask
= 0xff << ((combiner_nr
% 4) << 3);
120 /* Disable all interrupts */
121 __raw_writel(combiner_data
[combiner_nr
].irq_mask
,
122 base
+ COMBINER_ENABLE_CLEAR
);
126 static int combiner_irq_domain_xlate(struct irq_domain
*d
,
127 struct device_node
*controller
,
128 const u32
*intspec
, unsigned int intsize
,
129 unsigned long *out_hwirq
,
130 unsigned int *out_type
)
132 if (d
->of_node
!= controller
)
138 *out_hwirq
= intspec
[0] * MAX_IRQ_IN_COMBINER
+ intspec
[1];
144 static int combiner_irq_domain_xlate(struct irq_domain
*d
,
145 struct device_node
*controller
,
146 const u32
*intspec
, unsigned int intsize
,
147 unsigned long *out_hwirq
,
148 unsigned int *out_type
)
154 static int combiner_irq_domain_map(struct irq_domain
*d
, unsigned int irq
,
157 irq_set_chip_and_handler(irq
, &combiner_chip
, handle_level_irq
);
158 irq_set_chip_data(irq
, &combiner_data
[hw
>> 3]);
159 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
164 static struct irq_domain_ops combiner_irq_domain_ops
= {
165 .xlate
= combiner_irq_domain_xlate
,
166 .map
= combiner_irq_domain_map
,
169 void __init
combiner_init(void __iomem
*combiner_base
,
170 struct device_node
*np
)
172 int i
, irq
, irq_base
;
173 unsigned int max_nr
, nr_irq
;
176 if (of_property_read_u32(np
, "samsung,combiner-nr", &max_nr
)) {
177 pr_warning("%s: number of combiners not specified, "
178 "setting default as %d.\n",
179 __func__
, EXYNOS4_MAX_COMBINER_NR
);
180 max_nr
= EXYNOS4_MAX_COMBINER_NR
;
183 max_nr
= soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR
:
184 EXYNOS4_MAX_COMBINER_NR
;
186 nr_irq
= max_nr
* MAX_IRQ_IN_COMBINER
;
188 irq_base
= irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq
, 0);
189 if (IS_ERR_VALUE(irq_base
)) {
190 irq_base
= COMBINER_IRQ(0, 0);
191 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__
, irq_base
);
194 combiner_irq_domain
= irq_domain_add_legacy(np
, nr_irq
, irq_base
, 0,
195 &combiner_irq_domain_ops
, &combiner_data
);
196 if (WARN_ON(!combiner_irq_domain
)) {
197 pr_warning("%s: irq domain init failed\n", __func__
);
201 for (i
= 0; i
< max_nr
; i
++) {
202 combiner_init_one(i
, combiner_base
+ (i
>> 2) * 0x10);
206 irq
= irq_of_parse_and_map(np
, i
);
208 combiner_cascade_irq(i
, irq
);
213 static int __init
combiner_of_init(struct device_node
*np
,
214 struct device_node
*parent
)
216 void __iomem
*combiner_base
;
218 combiner_base
= of_iomap(np
, 0);
219 if (!combiner_base
) {
220 pr_err("%s: failed to map combiner registers\n", __func__
);
224 combiner_init(combiner_base
, np
);
228 IRQCHIP_DECLARE(exynos4210_combiner
, "samsung,exynos4210-combiner",