2 * Broadcom BCM7038 style Level 1 interrupt controller driver
4 * Copyright (C) 2014 Broadcom Corporation
5 * Author: Kevin Cernekee
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 #include <linux/bitops.h>
15 #include <linux/kconfig.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/irq.h>
22 #include <linux/irqdomain.h>
23 #include <linux/module.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_address.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30 #include <linux/smp.h>
31 #include <linux/types.h>
32 #include <linux/irqchip/chained_irq.h>
36 #define IRQS_PER_WORD 32
37 #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
40 struct bcm7038_l1_cpu
;
42 struct bcm7038_l1_chip
{
45 struct irq_domain
*domain
;
46 struct bcm7038_l1_cpu
*cpus
[NR_CPUS
];
47 u8 affinity
[MAX_WORDS
* IRQS_PER_WORD
];
50 struct bcm7038_l1_cpu
{
51 void __iomem
*map_base
;
56 * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
59 * 0x1000_1400: W0_STATUS
60 * 0x1000_1404: W1_STATUS
61 * 0x1000_1408: W0_MASK_STATUS
62 * 0x1000_140c: W1_MASK_STATUS
63 * 0x1000_1410: W0_MASK_SET
64 * 0x1000_1414: W1_MASK_SET
65 * 0x1000_1418: W0_MASK_CLEAR
66 * 0x1000_141c: W1_MASK_CLEAR
69 * 0xf03e_1500: W0_STATUS
70 * 0xf03e_1504: W1_STATUS
71 * 0xf03e_1508: W2_STATUS
72 * 0xf03e_150c: W3_STATUS
73 * 0xf03e_1510: W4_STATUS
74 * 0xf03e_1514: W0_MASK_STATUS
75 * 0xf03e_1518: W1_MASK_STATUS
79 static inline unsigned int reg_status(struct bcm7038_l1_chip
*intc
,
82 return (0 * intc
->n_words
+ word
) * sizeof(u32
);
85 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip
*intc
,
88 return (1 * intc
->n_words
+ word
) * sizeof(u32
);
91 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip
*intc
,
94 return (2 * intc
->n_words
+ word
) * sizeof(u32
);
97 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip
*intc
,
100 return (3 * intc
->n_words
+ word
) * sizeof(u32
);
103 static inline u32
l1_readl(void __iomem
*reg
)
105 if (IS_ENABLED(CONFIG_MIPS
) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN
))
106 return ioread32be(reg
);
111 static inline void l1_writel(u32 val
, void __iomem
*reg
)
113 if (IS_ENABLED(CONFIG_MIPS
) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN
))
114 iowrite32be(val
, reg
);
119 static void bcm7038_l1_irq_handle(unsigned int irq
, struct irq_desc
*desc
)
121 struct bcm7038_l1_chip
*intc
= irq_desc_get_handler_data(desc
);
122 struct bcm7038_l1_cpu
*cpu
;
123 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
127 cpu
= intc
->cpus
[cpu_logical_map(smp_processor_id())];
132 chained_irq_enter(chip
, desc
);
134 for (idx
= 0; idx
< intc
->n_words
; idx
++) {
135 int base
= idx
* IRQS_PER_WORD
;
136 unsigned long pending
, flags
;
139 raw_spin_lock_irqsave(&intc
->lock
, flags
);
140 pending
= l1_readl(cpu
->map_base
+ reg_status(intc
, idx
)) &
141 ~cpu
->mask_cache
[idx
];
142 raw_spin_unlock_irqrestore(&intc
->lock
, flags
);
144 for_each_set_bit(hwirq
, &pending
, IRQS_PER_WORD
) {
145 generic_handle_irq(irq_find_mapping(intc
->domain
,
150 chained_irq_exit(chip
, desc
);
153 static void __bcm7038_l1_unmask(struct irq_data
*d
, unsigned int cpu_idx
)
155 struct bcm7038_l1_chip
*intc
= irq_data_get_irq_chip_data(d
);
156 u32 word
= d
->hwirq
/ IRQS_PER_WORD
;
157 u32 mask
= BIT(d
->hwirq
% IRQS_PER_WORD
);
159 intc
->cpus
[cpu_idx
]->mask_cache
[word
] &= ~mask
;
160 l1_writel(mask
, intc
->cpus
[cpu_idx
]->map_base
+
161 reg_mask_clr(intc
, word
));
164 static void __bcm7038_l1_mask(struct irq_data
*d
, unsigned int cpu_idx
)
166 struct bcm7038_l1_chip
*intc
= irq_data_get_irq_chip_data(d
);
167 u32 word
= d
->hwirq
/ IRQS_PER_WORD
;
168 u32 mask
= BIT(d
->hwirq
% IRQS_PER_WORD
);
170 intc
->cpus
[cpu_idx
]->mask_cache
[word
] |= mask
;
171 l1_writel(mask
, intc
->cpus
[cpu_idx
]->map_base
+
172 reg_mask_set(intc
, word
));
175 static void bcm7038_l1_unmask(struct irq_data
*d
)
177 struct bcm7038_l1_chip
*intc
= irq_data_get_irq_chip_data(d
);
180 raw_spin_lock_irqsave(&intc
->lock
, flags
);
181 __bcm7038_l1_unmask(d
, intc
->affinity
[d
->hwirq
]);
182 raw_spin_unlock_irqrestore(&intc
->lock
, flags
);
185 static void bcm7038_l1_mask(struct irq_data
*d
)
187 struct bcm7038_l1_chip
*intc
= irq_data_get_irq_chip_data(d
);
190 raw_spin_lock_irqsave(&intc
->lock
, flags
);
191 __bcm7038_l1_mask(d
, intc
->affinity
[d
->hwirq
]);
192 raw_spin_unlock_irqrestore(&intc
->lock
, flags
);
195 static int bcm7038_l1_set_affinity(struct irq_data
*d
,
196 const struct cpumask
*dest
,
199 struct bcm7038_l1_chip
*intc
= irq_data_get_irq_chip_data(d
);
201 irq_hw_number_t hw
= d
->hwirq
;
202 u32 word
= hw
/ IRQS_PER_WORD
;
203 u32 mask
= BIT(hw
% IRQS_PER_WORD
);
204 unsigned int first_cpu
= cpumask_any_and(dest
, cpu_online_mask
);
207 raw_spin_lock_irqsave(&intc
->lock
, flags
);
209 was_disabled
= !!(intc
->cpus
[intc
->affinity
[hw
]]->mask_cache
[word
] &
211 __bcm7038_l1_mask(d
, intc
->affinity
[hw
]);
212 intc
->affinity
[hw
] = first_cpu
;
214 __bcm7038_l1_unmask(d
, first_cpu
);
216 raw_spin_unlock_irqrestore(&intc
->lock
, flags
);
220 static int __init
bcm7038_l1_init_one(struct device_node
*dn
,
222 struct bcm7038_l1_chip
*intc
)
226 struct bcm7038_l1_cpu
*cpu
;
227 unsigned int i
, n_words
, parent_irq
;
229 if (of_address_to_resource(dn
, idx
, &res
))
231 sz
= resource_size(&res
);
232 n_words
= sz
/ REG_BYTES_PER_IRQ_WORD
;
234 if (n_words
> MAX_WORDS
)
236 else if (!intc
->n_words
)
237 intc
->n_words
= n_words
;
238 else if (intc
->n_words
!= n_words
)
241 cpu
= intc
->cpus
[idx
] = kzalloc(sizeof(*cpu
) + n_words
* sizeof(u32
),
246 cpu
->map_base
= ioremap(res
.start
, sz
);
250 for (i
= 0; i
< n_words
; i
++) {
251 l1_writel(0xffffffff, cpu
->map_base
+ reg_mask_set(intc
, i
));
252 cpu
->mask_cache
[i
] = 0xffffffff;
255 parent_irq
= irq_of_parse_and_map(dn
, idx
);
257 pr_err("failed to map parent interrupt %d\n", parent_irq
);
260 irq_set_handler_data(parent_irq
, intc
);
261 irq_set_chained_handler(parent_irq
, bcm7038_l1_irq_handle
);
266 static struct irq_chip bcm7038_l1_irq_chip
= {
267 .name
= "bcm7038-l1",
268 .irq_mask
= bcm7038_l1_mask
,
269 .irq_unmask
= bcm7038_l1_unmask
,
270 .irq_set_affinity
= bcm7038_l1_set_affinity
,
273 static int bcm7038_l1_map(struct irq_domain
*d
, unsigned int virq
,
274 irq_hw_number_t hw_irq
)
276 irq_set_chip_and_handler(virq
, &bcm7038_l1_irq_chip
, handle_level_irq
);
277 irq_set_chip_data(virq
, d
->host_data
);
281 static const struct irq_domain_ops bcm7038_l1_domain_ops
= {
282 .xlate
= irq_domain_xlate_onecell
,
283 .map
= bcm7038_l1_map
,
286 int __init
bcm7038_l1_of_init(struct device_node
*dn
,
287 struct device_node
*parent
)
289 struct bcm7038_l1_chip
*intc
;
292 intc
= kzalloc(sizeof(*intc
), GFP_KERNEL
);
296 raw_spin_lock_init(&intc
->lock
);
297 for_each_possible_cpu(idx
) {
298 ret
= bcm7038_l1_init_one(dn
, idx
, intc
);
302 pr_err("failed to remap intc L1 registers\n");
307 intc
->domain
= irq_domain_add_linear(dn
, IRQS_PER_WORD
* intc
->n_words
,
308 &bcm7038_l1_domain_ops
,
315 pr_info("registered BCM7038 L1 intc (mem: 0x%p, IRQs: %d)\n",
316 intc
->cpus
[0]->map_base
, IRQS_PER_WORD
* intc
->n_words
);
321 for_each_possible_cpu(idx
) {
322 struct bcm7038_l1_cpu
*cpu
= intc
->cpus
[idx
];
326 iounmap(cpu
->map_base
);
335 IRQCHIP_DECLARE(bcm7038_l1
, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init
);