drivers/irqchip/irq-crossbar.c

   1 /*
   2  *  drivers/irqchip/irq-crossbar.c
   3  *
   4  *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *  Author: Sricharan R <r.sricharan@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  */
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/slab.h>
  18
  19 #include "irqchip.h"
  20
  21 #define IRQ_FREE        -1
  22 #define IRQ_RESERVED    -2
  23 #define IRQ_SKIP        -3
  24 #define GIC_IRQ_START   32
  25
  26 /**
  27  * struct crossbar_device - crossbar device description
  28  * @lock: spinlock serializing access to @irq_map
  29  * @int_max: maximum number of supported interrupts
  30  * @safe_map: safe default value to initialize the crossbar
  31  * @max_crossbar_sources: Maximum number of crossbar sources
  32  * @irq_map: array of interrupts to crossbar number mapping
  33  * @crossbar_base: crossbar base address
  34  * @register_offsets: offsets for each irq number
  35  * @write: register write function pointer
  36  */
  37 struct crossbar_device {
  38         raw_spinlock_t lock;
  39         uint int_max;
  40         uint safe_map;
  41         uint max_crossbar_sources;
  42         uint *irq_map;
  43         void __iomem *crossbar_base;
  44         int *register_offsets;
  45         void (*write)(int, int);
  46 };
  47
  48 static struct crossbar_device *cb;
  49
  50 static void crossbar_writel(int irq_no, int cb_no)
  51 {
  52         writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
  53 }
  54
  55 static void crossbar_writew(int irq_no, int cb_no)
  56 {
  57         writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
  58 }
  59
  60 static void crossbar_writeb(int irq_no, int cb_no)
  61 {
  62         writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
  63 }
  64
  65 static struct irq_chip crossbar_chip = {
  66         .name                   = "CBAR",
  67         .irq_eoi                = irq_chip_eoi_parent,
  68         .irq_mask               = irq_chip_mask_parent,
  69         .irq_unmask             = irq_chip_unmask_parent,
  70         .irq_retrigger          = irq_chip_retrigger_hierarchy,
  71         .irq_set_wake           = irq_chip_set_wake_parent,
  72 #ifdef CONFIG_SMP
  73         .irq_set_affinity       = irq_chip_set_affinity_parent,
  74 #endif
  75 };
  76
  77 static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
  78                             irq_hw_number_t hwirq)
  79 {
  80         struct of_phandle_args args;
  81         int i;
  82         int err;
  83
  84         raw_spin_lock(&cb->lock);
  85         for (i = cb->int_max - 1; i >= 0; i--) {
  86                 if (cb->irq_map[i] == IRQ_FREE) {
  87                         cb->irq_map[i] = hwirq;
  88                         break;
  89                 }
  90         }
  91         raw_spin_unlock(&cb->lock);
  92
  93         if (i < 0)
  94                 return -ENODEV;
  95
  96         args.np = domain->parent->of_node;
  97         args.args_count = 3;
  98         args.args[0] = 0;       /* SPI */
  99         args.args[1] = i;
 100         args.args[2] = IRQ_TYPE_LEVEL_HIGH;
 101
 102         err = irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
 103         if (err)
 104                 cb->irq_map[i] = IRQ_FREE;
 105         else
 106                 cb->write(i, hwirq);
 107
 108         return err;
 109 }
 110
 111 static int crossbar_domain_alloc(struct irq_domain *d, unsigned int virq,
 112                                  unsigned int nr_irqs, void *data)
 113 {
 114         struct of_phandle_args *args = data;
 115         irq_hw_number_t hwirq;
 116         int i;
 117
 118         if (args->args_count != 3)
 119                 return -EINVAL; /* Not GIC compliant */
 120         if (args->args[0] != 0)
 121                 return -EINVAL; /* No PPI should point to this domain */
 122
 123         hwirq = args->args[1];
 124         if ((hwirq + nr_irqs) > cb->max_crossbar_sources)
 125                 return -EINVAL; /* Can't deal with this */
 126
 127         for (i = 0; i < nr_irqs; i++) {
 128                 int err = allocate_gic_irq(d, virq + i, hwirq + i);
 129
 130                 if (err)
 131                         return err;
 132
 133                 irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
 134                                               &crossbar_chip, NULL);
 135         }
 136
 137         return 0;
 138 }
 139
 140 /**
 141  * crossbar_domain_free - unmap/free a crossbar<->irq connection
 142  * @domain: domain of irq to unmap
 143  * @virq: virq number
 144  * @nr_irqs: number of irqs to free
 145  *
 146  * We do not maintain a use count of total number of map/unmap
 147  * calls for a particular irq to find out if a irq can be really
 148  * unmapped. This is because unmap is called during irq_dispose_mapping(irq),
 149  * after which irq is anyways unusable. So an explicit map has to be called
 150  * after that.
 151  */
 152 static void crossbar_domain_free(struct irq_domain *domain, unsigned int virq,
 153                                  unsigned int nr_irqs)
 154 {
 155         int i;
 156
 157         raw_spin_lock(&cb->lock);
 158         for (i = 0; i < nr_irqs; i++) {
 159                 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
 160
 161                 irq_domain_reset_irq_data(d);
 162                 cb->irq_map[d->hwirq] = IRQ_FREE;
 163                 cb->write(d->hwirq, cb->safe_map);
 164         }
 165         raw_spin_unlock(&cb->lock);
 166 }
 167
 168 static int crossbar_domain_xlate(struct irq_domain *d,
 169                                  struct device_node *controller,
 170                                  const u32 *intspec, unsigned int intsize,
 171                                  unsigned long *out_hwirq,
 172                                  unsigned int *out_type)
 173 {
 174         if (d->of_node != controller)
 175                 return -EINVAL; /* Shouldn't happen, really... */
 176         if (intsize != 3)
 177                 return -EINVAL; /* Not GIC compliant */
 178         if (intspec[0] != 0)
 179                 return -EINVAL; /* No PPI should point to this domain */
 180
 181         *out_hwirq = intspec[1];
 182         *out_type = intspec[2];
 183         return 0;
 184 }
 185
 186 static const struct irq_domain_ops crossbar_domain_ops = {
 187         .alloc  = crossbar_domain_alloc,
 188         .free   = crossbar_domain_free,
 189         .xlate  = crossbar_domain_xlate,
 190 };
 191
 192 static int __init crossbar_of_init(struct device_node *node)
 193 {
 194         int i, size, max = 0, reserved = 0, entry;
 195         const __be32 *irqsr;
 196         int ret = -ENOMEM;
 197
 198         cb = kzalloc(sizeof(*cb), GFP_KERNEL);
 199
 200         if (!cb)
 201                 return ret;
 202
 203         cb->crossbar_base = of_iomap(node, 0);
 204         if (!cb->crossbar_base)
 205                 goto err_cb;
 206
 207         of_property_read_u32(node, "ti,max-crossbar-sources",
 208                              &cb->max_crossbar_sources);
 209         if (!cb->max_crossbar_sources) {
 210                 pr_err("missing 'ti,max-crossbar-sources' property\n");
 211                 ret = -EINVAL;
 212                 goto err_base;
 213         }
 214
 215         of_property_read_u32(node, "ti,max-irqs", &max);
 216         if (!max) {
 217                 pr_err("missing 'ti,max-irqs' property\n");
 218                 ret = -EINVAL;
 219                 goto err_base;
 220         }
 221         cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
 222         if (!cb->irq_map)
 223                 goto err_base;
 224
 225         cb->int_max = max;
 226
 227         for (i = 0; i < max; i++)
 228                 cb->irq_map[i] = IRQ_FREE;
 229
 230         /* Get and mark reserved irqs */
 231         irqsr = of_get_property(node, "ti,irqs-reserved", &size);
 232         if (irqsr) {
 233                 size /= sizeof(__be32);
 234
 235                 for (i = 0; i < size; i++) {
 236                         of_property_read_u32_index(node,
 237                                                    "ti,irqs-reserved",
 238                                                    i, &entry);
 239                         if (entry >= max) {
 240                                 pr_err("Invalid reserved entry\n");
 241                                 ret = -EINVAL;
 242                                 goto err_irq_map;
 243                         }
 244                         cb->irq_map[entry] = IRQ_RESERVED;
 245                 }
 246         }
 247
 248         /* Skip irqs hardwired to bypass the crossbar */
 249         irqsr = of_get_property(node, "ti,irqs-skip", &size);
 250         if (irqsr) {
 251                 size /= sizeof(__be32);
 252
 253                 for (i = 0; i < size; i++) {
 254                         of_property_read_u32_index(node,
 255                                                    "ti,irqs-skip",
 256                                                    i, &entry);
 257                         if (entry >= max) {
 258                                 pr_err("Invalid skip entry\n");
 259                                 ret = -EINVAL;
 260                                 goto err_irq_map;
 261                         }
 262                         cb->irq_map[entry] = IRQ_SKIP;
 263                 }
 264         }
 265
 266
 267         cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
 268         if (!cb->register_offsets)
 269                 goto err_irq_map;
 270
 271         of_property_read_u32(node, "ti,reg-size", &size);
 272
 273         switch (size) {
 274         case 1:
 275                 cb->write = crossbar_writeb;
 276                 break;
 277         case 2:
 278                 cb->write = crossbar_writew;
 279                 break;
 280         case 4:
 281                 cb->write = crossbar_writel;
 282                 break;
 283         default:
 284                 pr_err("Invalid reg-size property\n");
 285                 ret = -EINVAL;
 286                 goto err_reg_offset;
 287                 break;
 288         }
 289
 290         /*
 291          * Register offsets are not linear because of the
 292          * reserved irqs. so find and store the offsets once.
 293          */
 294         for (i = 0; i < max; i++) {
 295                 if (cb->irq_map[i] == IRQ_RESERVED)
 296                         continue;
 297
 298                 cb->register_offsets[i] = reserved;
 299                 reserved += size;
 300         }
 301
 302         of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
 303         /* Initialize the crossbar with safe map to start with */
 304         for (i = 0; i < max; i++) {
 305                 if (cb->irq_map[i] == IRQ_RESERVED ||
 306                     cb->irq_map[i] == IRQ_SKIP)
 307                         continue;
 308
 309                 cb->write(i, cb->safe_map);
 310         }
 311
 312         raw_spin_lock_init(&cb->lock);
 313
 314         return 0;
 315
 316 err_reg_offset:
 317         kfree(cb->register_offsets);
 318 err_irq_map:
 319         kfree(cb->irq_map);
 320 err_base:
 321         iounmap(cb->crossbar_base);
 322 err_cb:
 323         kfree(cb);
 324
 325         cb = NULL;
 326         return ret;
 327 }
 328
 329 static int __init irqcrossbar_init(struct device_node *node,
 330                                    struct device_node *parent)
 331 {
 332         struct irq_domain *parent_domain, *domain;
 333         int err;
 334
 335         if (!parent) {
 336                 pr_err("%s: no parent, giving up\n", node->full_name);
 337                 return -ENODEV;
 338         }
 339
 340         parent_domain = irq_find_host(parent);
 341         if (!parent_domain) {
 342                 pr_err("%s: unable to obtain parent domain\n", node->full_name);
 343                 return -ENXIO;
 344         }
 345
 346         err = crossbar_of_init(node);
 347         if (err)
 348                 return err;
 349
 350         domain = irq_domain_add_hierarchy(parent_domain, 0,
 351                                           cb->max_crossbar_sources,
 352                                           node, &crossbar_domain_ops,
 353                                           NULL);
 354         if (!domain) {
 355                 pr_err("%s: failed to allocated domain\n", node->full_name);
 356                 return -ENOMEM;
 357         }
 358
 359         return 0;
 360 }
 361
 362 IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irq-crossbar", irqcrossbar_init);