drivers/irqchip/irq-crossbar.c

   1 /*
   2  *  drivers/irqchip/irq-crossbar.c
   3  *
   4  *  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *  Author: Sricharan R <r.sricharan@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  */
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/slab.h>
  18
  19 #include "irqchip.h"
  20
  21 #define IRQ_FREE        -1
  22 #define IRQ_RESERVED    -2
  23 #define IRQ_SKIP        -3
  24 #define GIC_IRQ_START   32
  25
  26 /**
  27  * struct crossbar_device - crossbar device description
  28  * @lock: spinlock serializing access to @irq_map
  29  * @int_max: maximum number of supported interrupts
  30  * @safe_map: safe default value to initialize the crossbar
  31  * @max_crossbar_sources: Maximum number of crossbar sources
  32  * @irq_map: array of interrupts to crossbar number mapping
  33  * @crossbar_base: crossbar base address
  34  * @register_offsets: offsets for each irq number
  35  * @write: register write function pointer
  36  */
  37 struct crossbar_device {
  38         raw_spinlock_t lock;
  39         uint int_max;
  40         uint safe_map;
  41         uint max_crossbar_sources;
  42         uint *irq_map;
  43         void __iomem *crossbar_base;
  44         int *register_offsets;
  45         void (*write)(int, int);
  46 };
  47
  48 static struct crossbar_device *cb;
  49
  50 static void crossbar_writel(int irq_no, int cb_no)
  51 {
  52         writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
  53 }
  54
  55 static void crossbar_writew(int irq_no, int cb_no)
  56 {
  57         writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
  58 }
  59
  60 static void crossbar_writeb(int irq_no, int cb_no)
  61 {
  62         writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
  63 }
  64
  65 static struct irq_chip crossbar_chip = {
  66         .name                   = "CBAR",
  67         .irq_eoi                = irq_chip_eoi_parent,
  68         .irq_mask               = irq_chip_mask_parent,
  69         .irq_unmask             = irq_chip_unmask_parent,
  70         .irq_retrigger          = irq_chip_retrigger_hierarchy,
  71         .irq_set_type           = irq_chip_set_type_parent,
  72         .flags                  = IRQCHIP_MASK_ON_SUSPEND |
  73                                   IRQCHIP_SKIP_SET_WAKE,
  74 #ifdef CONFIG_SMP
  75         .irq_set_affinity       = irq_chip_set_affinity_parent,
  76 #endif
  77 };
  78
  79 static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
  80                             irq_hw_number_t hwirq)
  81 {
  82         struct of_phandle_args args;
  83         int i;
  84         int err;
  85
  86         raw_spin_lock(&cb->lock);
  87         for (i = cb->int_max - 1; i >= 0; i--) {
  88                 if (cb->irq_map[i] == IRQ_FREE) {
  89                         cb->irq_map[i] = hwirq;
  90                         break;
  91                 }
  92         }
  93         raw_spin_unlock(&cb->lock);
  94
  95         if (i < 0)
  96                 return -ENODEV;
  97
  98         args.np = domain->parent->of_node;
  99         args.args_count = 3;
 100         args.args[0] = 0;       /* SPI */
 101         args.args[1] = i;
 102         args.args[2] = IRQ_TYPE_LEVEL_HIGH;
 103
 104         err = irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
 105         if (err)
 106                 cb->irq_map[i] = IRQ_FREE;
 107         else
 108                 cb->write(i, hwirq);
 109
 110         return err;
 111 }
 112
 113 static int crossbar_domain_alloc(struct irq_domain *d, unsigned int virq,
 114                                  unsigned int nr_irqs, void *data)
 115 {
 116         struct of_phandle_args *args = data;
 117         irq_hw_number_t hwirq;
 118         int i;
 119
 120         if (args->args_count != 3)
 121                 return -EINVAL; /* Not GIC compliant */
 122         if (args->args[0] != 0)
 123                 return -EINVAL; /* No PPI should point to this domain */
 124
 125         hwirq = args->args[1];
 126         if ((hwirq + nr_irqs) > cb->max_crossbar_sources)
 127                 return -EINVAL; /* Can't deal with this */
 128
 129         for (i = 0; i < nr_irqs; i++) {
 130                 int err = allocate_gic_irq(d, virq + i, hwirq + i);
 131
 132                 if (err)
 133                         return err;
 134
 135                 irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
 136                                               &crossbar_chip, NULL);
 137         }
 138
 139         return 0;
 140 }
 141
 142 /**
 143  * crossbar_domain_free - unmap/free a crossbar<->irq connection
 144  * @domain: domain of irq to unmap
 145  * @virq: virq number
 146  * @nr_irqs: number of irqs to free
 147  *
 148  * We do not maintain a use count of total number of map/unmap
 149  * calls for a particular irq to find out if a irq can be really
 150  * unmapped. This is because unmap is called during irq_dispose_mapping(irq),
 151  * after which irq is anyways unusable. So an explicit map has to be called
 152  * after that.
 153  */
 154 static void crossbar_domain_free(struct irq_domain *domain, unsigned int virq,
 155                                  unsigned int nr_irqs)
 156 {
 157         int i;
 158
 159         raw_spin_lock(&cb->lock);
 160         for (i = 0; i < nr_irqs; i++) {
 161                 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
 162
 163                 irq_domain_reset_irq_data(d);
 164                 cb->irq_map[d->hwirq] = IRQ_FREE;
 165                 cb->write(d->hwirq, cb->safe_map);
 166         }
 167         raw_spin_unlock(&cb->lock);
 168 }
 169
 170 static int crossbar_domain_xlate(struct irq_domain *d,
 171                                  struct device_node *controller,
 172                                  const u32 *intspec, unsigned int intsize,
 173                                  unsigned long *out_hwirq,
 174                                  unsigned int *out_type)
 175 {
 176         if (d->of_node != controller)
 177                 return -EINVAL; /* Shouldn't happen, really... */
 178         if (intsize != 3)
 179                 return -EINVAL; /* Not GIC compliant */
 180         if (intspec[0] != 0)
 181                 return -EINVAL; /* No PPI should point to this domain */
 182
 183         *out_hwirq = intspec[1];
 184         *out_type = intspec[2];
 185         return 0;
 186 }
 187
 188 static const struct irq_domain_ops crossbar_domain_ops = {
 189         .alloc  = crossbar_domain_alloc,
 190         .free   = crossbar_domain_free,
 191         .xlate  = crossbar_domain_xlate,
 192 };
 193
 194 static int __init crossbar_of_init(struct device_node *node)
 195 {
 196         int i, size, max = 0, reserved = 0, entry;
 197         const __be32 *irqsr;
 198         int ret = -ENOMEM;
 199
 200         cb = kzalloc(sizeof(*cb), GFP_KERNEL);
 201
 202         if (!cb)
 203                 return ret;
 204
 205         cb->crossbar_base = of_iomap(node, 0);
 206         if (!cb->crossbar_base)
 207                 goto err_cb;
 208
 209         of_property_read_u32(node, "ti,max-crossbar-sources",
 210                              &cb->max_crossbar_sources);
 211         if (!cb->max_crossbar_sources) {
 212                 pr_err("missing 'ti,max-crossbar-sources' property\n");
 213                 ret = -EINVAL;
 214                 goto err_base;
 215         }
 216
 217         of_property_read_u32(node, "ti,max-irqs", &max);
 218         if (!max) {
 219                 pr_err("missing 'ti,max-irqs' property\n");
 220                 ret = -EINVAL;
 221                 goto err_base;
 222         }
 223         cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
 224         if (!cb->irq_map)
 225                 goto err_base;
 226
 227         cb->int_max = max;
 228
 229         for (i = 0; i < max; i++)
 230                 cb->irq_map[i] = IRQ_FREE;
 231
 232         /* Get and mark reserved irqs */
 233         irqsr = of_get_property(node, "ti,irqs-reserved", &size);
 234         if (irqsr) {
 235                 size /= sizeof(__be32);
 236
 237                 for (i = 0; i < size; i++) {
 238                         of_property_read_u32_index(node,
 239                                                    "ti,irqs-reserved",
 240                                                    i, &entry);
 241                         if (entry >= max) {
 242                                 pr_err("Invalid reserved entry\n");
 243                                 ret = -EINVAL;
 244                                 goto err_irq_map;
 245                         }
 246                         cb->irq_map[entry] = IRQ_RESERVED;
 247                 }
 248         }
 249
 250         /* Skip irqs hardwired to bypass the crossbar */
 251         irqsr = of_get_property(node, "ti,irqs-skip", &size);
 252         if (irqsr) {
 253                 size /= sizeof(__be32);
 254
 255                 for (i = 0; i < size; i++) {
 256                         of_property_read_u32_index(node,
 257                                                    "ti,irqs-skip",
 258                                                    i, &entry);
 259                         if (entry >= max) {
 260                                 pr_err("Invalid skip entry\n");
 261                                 ret = -EINVAL;
 262                                 goto err_irq_map;
 263                         }
 264                         cb->irq_map[entry] = IRQ_SKIP;
 265                 }
 266         }
 267
 268
 269         cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
 270         if (!cb->register_offsets)
 271                 goto err_irq_map;
 272
 273         of_property_read_u32(node, "ti,reg-size", &size);
 274
 275         switch (size) {
 276         case 1:
 277                 cb->write = crossbar_writeb;
 278                 break;
 279         case 2:
 280                 cb->write = crossbar_writew;
 281                 break;
 282         case 4:
 283                 cb->write = crossbar_writel;
 284                 break;
 285         default:
 286                 pr_err("Invalid reg-size property\n");
 287                 ret = -EINVAL;
 288                 goto err_reg_offset;
 289                 break;
 290         }
 291
 292         /*
 293          * Register offsets are not linear because of the
 294          * reserved irqs. so find and store the offsets once.
 295          */
 296         for (i = 0; i < max; i++) {
 297                 if (cb->irq_map[i] == IRQ_RESERVED)
 298                         continue;
 299
 300                 cb->register_offsets[i] = reserved;
 301                 reserved += size;
 302         }
 303
 304         of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
 305         /* Initialize the crossbar with safe map to start with */
 306         for (i = 0; i < max; i++) {
 307                 if (cb->irq_map[i] == IRQ_RESERVED ||
 308                     cb->irq_map[i] == IRQ_SKIP)
 309                         continue;
 310
 311                 cb->write(i, cb->safe_map);
 312         }
 313
 314         raw_spin_lock_init(&cb->lock);
 315
 316         return 0;
 317
 318 err_reg_offset:
 319         kfree(cb->register_offsets);
 320 err_irq_map:
 321         kfree(cb->irq_map);
 322 err_base:
 323         iounmap(cb->crossbar_base);
 324 err_cb:
 325         kfree(cb);
 326
 327         cb = NULL;
 328         return ret;
 329 }
 330
 331 static int __init irqcrossbar_init(struct device_node *node,
 332                                    struct device_node *parent)
 333 {
 334         struct irq_domain *parent_domain, *domain;
 335         int err;
 336
 337         if (!parent) {
 338                 pr_err("%s: no parent, giving up\n", node->full_name);
 339                 return -ENODEV;
 340         }
 341
 342         parent_domain = irq_find_host(parent);
 343         if (!parent_domain) {
 344                 pr_err("%s: unable to obtain parent domain\n", node->full_name);
 345                 return -ENXIO;
 346         }
 347
 348         err = crossbar_of_init(node);
 349         if (err)
 350                 return err;
 351
 352         domain = irq_domain_add_hierarchy(parent_domain, 0,
 353                                           cb->max_crossbar_sources,
 354                                           node, &crossbar_domain_ops,
 355                                           NULL);
 356         if (!domain) {
 357                 pr_err("%s: failed to allocated domain\n", node->full_name);
 358                 return -ENOMEM;
 359         }
 360
 361         return 0;
 362 }
 363
 364 IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irq-crossbar", irqcrossbar_init);