2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/bitmap.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/log2.h>
24 #include <linux/msi.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_pci.h>
29 #include <linux/of_platform.h>
30 #include <linux/percpu.h>
31 #include <linux/slab.h>
33 #include <linux/irqchip.h>
34 #include <linux/irqchip/arm-gic-v3.h>
36 #include <asm/cacheflush.h>
37 #include <asm/cputype.h>
38 #include <asm/exception.h>
40 #include "irq-gic-common.h"
42 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
43 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
45 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
48 * Collection structure - just an ID, and a redistributor address to
49 * ping. We use one per CPU as a bag of interrupts assigned to this
52 struct its_collection
{
58 * The ITS structure - contains most of the infrastructure, with the
59 * top-level MSI domain, the command queue, the collections, and the
60 * list of devices writing to it.
64 struct list_head entry
;
66 unsigned long phys_base
;
67 struct its_cmd_block
*cmd_base
;
68 struct its_cmd_block
*cmd_write
;
72 } tables
[GITS_BASER_NR_REGS
];
73 struct its_collection
*collections
;
74 struct list_head its_device_list
;
79 #define ITS_ITT_ALIGN SZ_256
81 /* Convert page order to size in bytes */
82 #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
84 struct event_lpi_map
{
85 unsigned long *lpi_map
;
87 irq_hw_number_t lpi_base
;
92 * The ITS view of a device - belongs to an ITS, a collection, owns an
93 * interrupt translation table, and a list of interrupts.
96 struct list_head entry
;
98 struct event_lpi_map event_map
;
104 static LIST_HEAD(its_nodes
);
105 static DEFINE_SPINLOCK(its_lock
);
106 static struct device_node
*gic_root_node
;
107 static struct rdists
*gic_rdists
;
109 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
110 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
112 static struct its_collection
*dev_event_to_col(struct its_device
*its_dev
,
115 struct its_node
*its
= its_dev
->its
;
117 return its
->collections
+ its_dev
->event_map
.col_map
[event
];
121 * ITS command descriptors - parameters to be encoded in a command
124 struct its_cmd_desc
{
127 struct its_device
*dev
;
132 struct its_device
*dev
;
137 struct its_device
*dev
;
142 struct its_collection
*col
;
147 struct its_device
*dev
;
153 struct its_device
*dev
;
154 struct its_collection
*col
;
159 struct its_device
*dev
;
164 struct its_collection
*col
;
170 * The ITS command block, which is what the ITS actually parses.
172 struct its_cmd_block
{
176 #define ITS_CMD_QUEUE_SZ SZ_64K
177 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
179 typedef struct its_collection
*(*its_cmd_builder_t
)(struct its_cmd_block
*,
180 struct its_cmd_desc
*);
182 static void its_encode_cmd(struct its_cmd_block
*cmd
, u8 cmd_nr
)
184 cmd
->raw_cmd
[0] &= ~0xffUL
;
185 cmd
->raw_cmd
[0] |= cmd_nr
;
188 static void its_encode_devid(struct its_cmd_block
*cmd
, u32 devid
)
190 cmd
->raw_cmd
[0] &= BIT_ULL(32) - 1;
191 cmd
->raw_cmd
[0] |= ((u64
)devid
) << 32;
194 static void its_encode_event_id(struct its_cmd_block
*cmd
, u32 id
)
196 cmd
->raw_cmd
[1] &= ~0xffffffffUL
;
197 cmd
->raw_cmd
[1] |= id
;
200 static void its_encode_phys_id(struct its_cmd_block
*cmd
, u32 phys_id
)
202 cmd
->raw_cmd
[1] &= 0xffffffffUL
;
203 cmd
->raw_cmd
[1] |= ((u64
)phys_id
) << 32;
206 static void its_encode_size(struct its_cmd_block
*cmd
, u8 size
)
208 cmd
->raw_cmd
[1] &= ~0x1fUL
;
209 cmd
->raw_cmd
[1] |= size
& 0x1f;
212 static void its_encode_itt(struct its_cmd_block
*cmd
, u64 itt_addr
)
214 cmd
->raw_cmd
[2] &= ~0xffffffffffffUL
;
215 cmd
->raw_cmd
[2] |= itt_addr
& 0xffffffffff00UL
;
218 static void its_encode_valid(struct its_cmd_block
*cmd
, int valid
)
220 cmd
->raw_cmd
[2] &= ~(1UL << 63);
221 cmd
->raw_cmd
[2] |= ((u64
)!!valid
) << 63;
224 static void its_encode_target(struct its_cmd_block
*cmd
, u64 target_addr
)
226 cmd
->raw_cmd
[2] &= ~(0xffffffffUL
<< 16);
227 cmd
->raw_cmd
[2] |= (target_addr
& (0xffffffffUL
<< 16));
230 static void its_encode_collection(struct its_cmd_block
*cmd
, u16 col
)
232 cmd
->raw_cmd
[2] &= ~0xffffUL
;
233 cmd
->raw_cmd
[2] |= col
;
236 static inline void its_fixup_cmd(struct its_cmd_block
*cmd
)
238 /* Let's fixup BE commands */
239 cmd
->raw_cmd
[0] = cpu_to_le64(cmd
->raw_cmd
[0]);
240 cmd
->raw_cmd
[1] = cpu_to_le64(cmd
->raw_cmd
[1]);
241 cmd
->raw_cmd
[2] = cpu_to_le64(cmd
->raw_cmd
[2]);
242 cmd
->raw_cmd
[3] = cpu_to_le64(cmd
->raw_cmd
[3]);
245 static struct its_collection
*its_build_mapd_cmd(struct its_cmd_block
*cmd
,
246 struct its_cmd_desc
*desc
)
248 unsigned long itt_addr
;
249 u8 size
= ilog2(desc
->its_mapd_cmd
.dev
->nr_ites
);
251 itt_addr
= virt_to_phys(desc
->its_mapd_cmd
.dev
->itt
);
252 itt_addr
= ALIGN(itt_addr
, ITS_ITT_ALIGN
);
254 its_encode_cmd(cmd
, GITS_CMD_MAPD
);
255 its_encode_devid(cmd
, desc
->its_mapd_cmd
.dev
->device_id
);
256 its_encode_size(cmd
, size
- 1);
257 its_encode_itt(cmd
, itt_addr
);
258 its_encode_valid(cmd
, desc
->its_mapd_cmd
.valid
);
265 static struct its_collection
*its_build_mapc_cmd(struct its_cmd_block
*cmd
,
266 struct its_cmd_desc
*desc
)
268 its_encode_cmd(cmd
, GITS_CMD_MAPC
);
269 its_encode_collection(cmd
, desc
->its_mapc_cmd
.col
->col_id
);
270 its_encode_target(cmd
, desc
->its_mapc_cmd
.col
->target_address
);
271 its_encode_valid(cmd
, desc
->its_mapc_cmd
.valid
);
275 return desc
->its_mapc_cmd
.col
;
278 static struct its_collection
*its_build_mapvi_cmd(struct its_cmd_block
*cmd
,
279 struct its_cmd_desc
*desc
)
281 struct its_collection
*col
;
283 col
= dev_event_to_col(desc
->its_mapvi_cmd
.dev
,
284 desc
->its_mapvi_cmd
.event_id
);
286 its_encode_cmd(cmd
, GITS_CMD_MAPVI
);
287 its_encode_devid(cmd
, desc
->its_mapvi_cmd
.dev
->device_id
);
288 its_encode_event_id(cmd
, desc
->its_mapvi_cmd
.event_id
);
289 its_encode_phys_id(cmd
, desc
->its_mapvi_cmd
.phys_id
);
290 its_encode_collection(cmd
, col
->col_id
);
297 static struct its_collection
*its_build_movi_cmd(struct its_cmd_block
*cmd
,
298 struct its_cmd_desc
*desc
)
300 struct its_collection
*col
;
302 col
= dev_event_to_col(desc
->its_movi_cmd
.dev
,
303 desc
->its_movi_cmd
.event_id
);
305 its_encode_cmd(cmd
, GITS_CMD_MOVI
);
306 its_encode_devid(cmd
, desc
->its_movi_cmd
.dev
->device_id
);
307 its_encode_event_id(cmd
, desc
->its_movi_cmd
.event_id
);
308 its_encode_collection(cmd
, desc
->its_movi_cmd
.col
->col_id
);
315 static struct its_collection
*its_build_discard_cmd(struct its_cmd_block
*cmd
,
316 struct its_cmd_desc
*desc
)
318 struct its_collection
*col
;
320 col
= dev_event_to_col(desc
->its_discard_cmd
.dev
,
321 desc
->its_discard_cmd
.event_id
);
323 its_encode_cmd(cmd
, GITS_CMD_DISCARD
);
324 its_encode_devid(cmd
, desc
->its_discard_cmd
.dev
->device_id
);
325 its_encode_event_id(cmd
, desc
->its_discard_cmd
.event_id
);
332 static struct its_collection
*its_build_inv_cmd(struct its_cmd_block
*cmd
,
333 struct its_cmd_desc
*desc
)
335 struct its_collection
*col
;
337 col
= dev_event_to_col(desc
->its_inv_cmd
.dev
,
338 desc
->its_inv_cmd
.event_id
);
340 its_encode_cmd(cmd
, GITS_CMD_INV
);
341 its_encode_devid(cmd
, desc
->its_inv_cmd
.dev
->device_id
);
342 its_encode_event_id(cmd
, desc
->its_inv_cmd
.event_id
);
349 static struct its_collection
*its_build_invall_cmd(struct its_cmd_block
*cmd
,
350 struct its_cmd_desc
*desc
)
352 its_encode_cmd(cmd
, GITS_CMD_INVALL
);
353 its_encode_collection(cmd
, desc
->its_mapc_cmd
.col
->col_id
);
360 static u64
its_cmd_ptr_to_offset(struct its_node
*its
,
361 struct its_cmd_block
*ptr
)
363 return (ptr
- its
->cmd_base
) * sizeof(*ptr
);
366 static int its_queue_full(struct its_node
*its
)
371 widx
= its
->cmd_write
- its
->cmd_base
;
372 ridx
= readl_relaxed(its
->base
+ GITS_CREADR
) / sizeof(struct its_cmd_block
);
374 /* This is incredibly unlikely to happen, unless the ITS locks up. */
375 if (((widx
+ 1) % ITS_CMD_QUEUE_NR_ENTRIES
) == ridx
)
381 static struct its_cmd_block
*its_allocate_entry(struct its_node
*its
)
383 struct its_cmd_block
*cmd
;
384 u32 count
= 1000000; /* 1s! */
386 while (its_queue_full(its
)) {
389 pr_err_ratelimited("ITS queue not draining\n");
396 cmd
= its
->cmd_write
++;
398 /* Handle queue wrapping */
399 if (its
->cmd_write
== (its
->cmd_base
+ ITS_CMD_QUEUE_NR_ENTRIES
))
400 its
->cmd_write
= its
->cmd_base
;
405 static struct its_cmd_block
*its_post_commands(struct its_node
*its
)
407 u64 wr
= its_cmd_ptr_to_offset(its
, its
->cmd_write
);
409 writel_relaxed(wr
, its
->base
+ GITS_CWRITER
);
411 return its
->cmd_write
;
414 static void its_flush_cmd(struct its_node
*its
, struct its_cmd_block
*cmd
)
417 * Make sure the commands written to memory are observable by
420 if (its
->flags
& ITS_FLAGS_CMDQ_NEEDS_FLUSHING
)
421 __flush_dcache_area(cmd
, sizeof(*cmd
));
426 static void its_wait_for_range_completion(struct its_node
*its
,
427 struct its_cmd_block
*from
,
428 struct its_cmd_block
*to
)
430 u64 rd_idx
, from_idx
, to_idx
;
431 u32 count
= 1000000; /* 1s! */
433 from_idx
= its_cmd_ptr_to_offset(its
, from
);
434 to_idx
= its_cmd_ptr_to_offset(its
, to
);
437 rd_idx
= readl_relaxed(its
->base
+ GITS_CREADR
);
438 if (rd_idx
>= to_idx
|| rd_idx
< from_idx
)
443 pr_err_ratelimited("ITS queue timeout\n");
451 static void its_send_single_command(struct its_node
*its
,
452 its_cmd_builder_t builder
,
453 struct its_cmd_desc
*desc
)
455 struct its_cmd_block
*cmd
, *sync_cmd
, *next_cmd
;
456 struct its_collection
*sync_col
;
459 raw_spin_lock_irqsave(&its
->lock
, flags
);
461 cmd
= its_allocate_entry(its
);
462 if (!cmd
) { /* We're soooooo screewed... */
463 pr_err_ratelimited("ITS can't allocate, dropping command\n");
464 raw_spin_unlock_irqrestore(&its
->lock
, flags
);
467 sync_col
= builder(cmd
, desc
);
468 its_flush_cmd(its
, cmd
);
471 sync_cmd
= its_allocate_entry(its
);
473 pr_err_ratelimited("ITS can't SYNC, skipping\n");
476 its_encode_cmd(sync_cmd
, GITS_CMD_SYNC
);
477 its_encode_target(sync_cmd
, sync_col
->target_address
);
478 its_fixup_cmd(sync_cmd
);
479 its_flush_cmd(its
, sync_cmd
);
483 next_cmd
= its_post_commands(its
);
484 raw_spin_unlock_irqrestore(&its
->lock
, flags
);
486 its_wait_for_range_completion(its
, cmd
, next_cmd
);
489 static void its_send_inv(struct its_device
*dev
, u32 event_id
)
491 struct its_cmd_desc desc
;
493 desc
.its_inv_cmd
.dev
= dev
;
494 desc
.its_inv_cmd
.event_id
= event_id
;
496 its_send_single_command(dev
->its
, its_build_inv_cmd
, &desc
);
499 static void its_send_mapd(struct its_device
*dev
, int valid
)
501 struct its_cmd_desc desc
;
503 desc
.its_mapd_cmd
.dev
= dev
;
504 desc
.its_mapd_cmd
.valid
= !!valid
;
506 its_send_single_command(dev
->its
, its_build_mapd_cmd
, &desc
);
509 static void its_send_mapc(struct its_node
*its
, struct its_collection
*col
,
512 struct its_cmd_desc desc
;
514 desc
.its_mapc_cmd
.col
= col
;
515 desc
.its_mapc_cmd
.valid
= !!valid
;
517 its_send_single_command(its
, its_build_mapc_cmd
, &desc
);
520 static void its_send_mapvi(struct its_device
*dev
, u32 irq_id
, u32 id
)
522 struct its_cmd_desc desc
;
524 desc
.its_mapvi_cmd
.dev
= dev
;
525 desc
.its_mapvi_cmd
.phys_id
= irq_id
;
526 desc
.its_mapvi_cmd
.event_id
= id
;
528 its_send_single_command(dev
->its
, its_build_mapvi_cmd
, &desc
);
531 static void its_send_movi(struct its_device
*dev
,
532 struct its_collection
*col
, u32 id
)
534 struct its_cmd_desc desc
;
536 desc
.its_movi_cmd
.dev
= dev
;
537 desc
.its_movi_cmd
.col
= col
;
538 desc
.its_movi_cmd
.event_id
= id
;
540 its_send_single_command(dev
->its
, its_build_movi_cmd
, &desc
);
543 static void its_send_discard(struct its_device
*dev
, u32 id
)
545 struct its_cmd_desc desc
;
547 desc
.its_discard_cmd
.dev
= dev
;
548 desc
.its_discard_cmd
.event_id
= id
;
550 its_send_single_command(dev
->its
, its_build_discard_cmd
, &desc
);
553 static void its_send_invall(struct its_node
*its
, struct its_collection
*col
)
555 struct its_cmd_desc desc
;
557 desc
.its_invall_cmd
.col
= col
;
559 its_send_single_command(its
, its_build_invall_cmd
, &desc
);
563 * irqchip functions - assumes MSI, mostly.
566 static inline u32
its_get_event_id(struct irq_data
*d
)
568 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
569 return d
->hwirq
- its_dev
->event_map
.lpi_base
;
572 static void lpi_set_config(struct irq_data
*d
, bool enable
)
574 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
575 irq_hw_number_t hwirq
= d
->hwirq
;
576 u32 id
= its_get_event_id(d
);
577 u8
*cfg
= page_address(gic_rdists
->prop_page
) + hwirq
- 8192;
580 *cfg
|= LPI_PROP_ENABLED
;
582 *cfg
&= ~LPI_PROP_ENABLED
;
585 * Make the above write visible to the redistributors.
586 * And yes, we're flushing exactly: One. Single. Byte.
589 if (gic_rdists
->flags
& RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING
)
590 __flush_dcache_area(cfg
, sizeof(*cfg
));
593 its_send_inv(its_dev
, id
);
596 static void its_mask_irq(struct irq_data
*d
)
598 lpi_set_config(d
, false);
601 static void its_unmask_irq(struct irq_data
*d
)
603 lpi_set_config(d
, true);
606 static int its_set_affinity(struct irq_data
*d
, const struct cpumask
*mask_val
,
609 unsigned int cpu
= cpumask_any_and(mask_val
, cpu_online_mask
);
610 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
611 struct its_collection
*target_col
;
612 u32 id
= its_get_event_id(d
);
614 if (cpu
>= nr_cpu_ids
)
617 target_col
= &its_dev
->its
->collections
[cpu
];
618 its_send_movi(its_dev
, target_col
, id
);
619 its_dev
->event_map
.col_map
[id
] = cpu
;
621 return IRQ_SET_MASK_OK_DONE
;
624 static void its_irq_compose_msi_msg(struct irq_data
*d
, struct msi_msg
*msg
)
626 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
627 struct its_node
*its
;
631 addr
= its
->phys_base
+ GITS_TRANSLATER
;
633 msg
->address_lo
= addr
& ((1UL << 32) - 1);
634 msg
->address_hi
= addr
>> 32;
635 msg
->data
= its_get_event_id(d
);
638 static struct irq_chip its_irq_chip
= {
640 .irq_mask
= its_mask_irq
,
641 .irq_unmask
= its_unmask_irq
,
642 .irq_eoi
= irq_chip_eoi_parent
,
643 .irq_set_affinity
= its_set_affinity
,
644 .irq_compose_msi_msg
= its_irq_compose_msi_msg
,
648 * How we allocate LPIs:
650 * The GIC has id_bits bits for interrupt identifiers. From there, we
651 * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
652 * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
655 * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
657 #define IRQS_PER_CHUNK_SHIFT 5
658 #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT)
660 static unsigned long *lpi_bitmap
;
661 static u32 lpi_chunks
;
662 static DEFINE_SPINLOCK(lpi_lock
);
664 static int its_lpi_to_chunk(int lpi
)
666 return (lpi
- 8192) >> IRQS_PER_CHUNK_SHIFT
;
669 static int its_chunk_to_lpi(int chunk
)
671 return (chunk
<< IRQS_PER_CHUNK_SHIFT
) + 8192;
674 static int its_lpi_init(u32 id_bits
)
676 lpi_chunks
= its_lpi_to_chunk(1UL << id_bits
);
678 lpi_bitmap
= kzalloc(BITS_TO_LONGS(lpi_chunks
) * sizeof(long),
685 pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks
);
689 static unsigned long *its_lpi_alloc_chunks(int nr_irqs
, int *base
, int *nr_ids
)
691 unsigned long *bitmap
= NULL
;
696 nr_chunks
= DIV_ROUND_UP(nr_irqs
, IRQS_PER_CHUNK
);
698 spin_lock(&lpi_lock
);
701 chunk_id
= bitmap_find_next_zero_area(lpi_bitmap
, lpi_chunks
,
703 if (chunk_id
< lpi_chunks
)
707 } while (nr_chunks
> 0);
712 bitmap
= kzalloc(BITS_TO_LONGS(nr_chunks
* IRQS_PER_CHUNK
) * sizeof (long),
717 for (i
= 0; i
< nr_chunks
; i
++)
718 set_bit(chunk_id
+ i
, lpi_bitmap
);
720 *base
= its_chunk_to_lpi(chunk_id
);
721 *nr_ids
= nr_chunks
* IRQS_PER_CHUNK
;
724 spin_unlock(&lpi_lock
);
732 static void its_lpi_free(struct event_lpi_map
*map
)
734 int base
= map
->lpi_base
;
735 int nr_ids
= map
->nr_lpis
;
738 spin_lock(&lpi_lock
);
740 for (lpi
= base
; lpi
< (base
+ nr_ids
); lpi
+= IRQS_PER_CHUNK
) {
741 int chunk
= its_lpi_to_chunk(lpi
);
742 BUG_ON(chunk
> lpi_chunks
);
743 if (test_bit(chunk
, lpi_bitmap
)) {
744 clear_bit(chunk
, lpi_bitmap
);
746 pr_err("Bad LPI chunk %d\n", chunk
);
750 spin_unlock(&lpi_lock
);
757 * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
758 * deal with (one configuration byte per interrupt). PENDBASE has to
759 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
761 #define LPI_PROPBASE_SZ SZ_64K
762 #define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K)
765 * This is how many bits of ID we need, including the useless ones.
767 #define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K)
769 #define LPI_PROP_DEFAULT_PRIO 0xa0
771 static int __init
its_alloc_lpi_tables(void)
775 gic_rdists
->prop_page
= alloc_pages(GFP_NOWAIT
,
776 get_order(LPI_PROPBASE_SZ
));
777 if (!gic_rdists
->prop_page
) {
778 pr_err("Failed to allocate PROPBASE\n");
782 paddr
= page_to_phys(gic_rdists
->prop_page
);
783 pr_info("GIC: using LPI property table @%pa\n", &paddr
);
785 /* Priority 0xa0, Group-1, disabled */
786 memset(page_address(gic_rdists
->prop_page
),
787 LPI_PROP_DEFAULT_PRIO
| LPI_PROP_GROUP1
,
790 /* Make sure the GIC will observe the written configuration */
791 __flush_dcache_area(page_address(gic_rdists
->prop_page
), LPI_PROPBASE_SZ
);
796 static const char *its_base_type_string
[] = {
797 [GITS_BASER_TYPE_DEVICE
] = "Devices",
798 [GITS_BASER_TYPE_VCPU
] = "Virtual CPUs",
799 [GITS_BASER_TYPE_CPU
] = "Physical CPUs",
800 [GITS_BASER_TYPE_COLLECTION
] = "Interrupt Collections",
801 [GITS_BASER_TYPE_RESERVED5
] = "Reserved (5)",
802 [GITS_BASER_TYPE_RESERVED6
] = "Reserved (6)",
803 [GITS_BASER_TYPE_RESERVED7
] = "Reserved (7)",
806 static void its_free_tables(struct its_node
*its
)
810 for (i
= 0; i
< GITS_BASER_NR_REGS
; i
++) {
811 if (its
->tables
[i
].base
) {
812 free_pages((unsigned long)its
->tables
[i
].base
,
813 its
->tables
[i
].order
);
814 its
->tables
[i
].base
= NULL
;
819 static int its_alloc_tables(const char *node_name
, struct its_node
*its
)
824 u64 shr
= GITS_BASER_InnerShareable
;
829 if (its
->flags
& ITS_FLAGS_WORKAROUND_CAVIUM_22375
) {
831 * erratum 22375: only alloc 8MB table size
832 * erratum 24313: ignore memory access type
835 ids
= 0x14; /* 20 bits, 8MB */
837 cache
= GITS_BASER_WaWb
;
838 typer
= readq_relaxed(its
->base
+ GITS_TYPER
);
839 ids
= GITS_TYPER_DEVBITS(typer
);
842 for (i
= 0; i
< GITS_BASER_NR_REGS
; i
++) {
843 u64 val
= readq_relaxed(its
->base
+ GITS_BASER
+ i
* 8);
844 u64 type
= GITS_BASER_TYPE(val
);
845 u64 entry_size
= GITS_BASER_ENTRY_SIZE(val
);
846 int order
= get_order(psz
);
851 if (type
== GITS_BASER_TYPE_NONE
)
855 * Allocate as many entries as required to fit the
856 * range of device IDs that the ITS can grok... The ID
857 * space being incredibly sparse, this results in a
858 * massive waste of memory.
860 * For other tables, only allocate a single page.
862 if (type
== GITS_BASER_TYPE_DEVICE
) {
864 * 'order' was initialized earlier to the default page
865 * granule of the the ITS. We can't have an allocation
866 * smaller than that. If the requested allocation
867 * is smaller, round up to the default page granule.
869 order
= max(get_order((1UL << ids
) * entry_size
),
871 if (order
>= MAX_ORDER
) {
872 order
= MAX_ORDER
- 1;
873 pr_warn("%s: Device Table too large, reduce its page order to %u\n",
879 alloc_pages
= (PAGE_ORDER_TO_SIZE(order
) / psz
);
880 if (alloc_pages
> GITS_BASER_PAGES_MAX
) {
881 alloc_pages
= GITS_BASER_PAGES_MAX
;
882 order
= get_order(GITS_BASER_PAGES_MAX
* psz
);
883 pr_warn("%s: Device Table too large, reduce its page order to %u (%u pages)\n",
884 node_name
, order
, alloc_pages
);
887 base
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
, order
);
893 its
->tables
[i
].base
= base
;
894 its
->tables
[i
].order
= order
;
897 val
= (virt_to_phys(base
) |
898 (type
<< GITS_BASER_TYPE_SHIFT
) |
899 ((entry_size
- 1) << GITS_BASER_ENTRY_SIZE_SHIFT
) |
906 val
|= GITS_BASER_PAGE_SIZE_4K
;
909 val
|= GITS_BASER_PAGE_SIZE_16K
;
912 val
|= GITS_BASER_PAGE_SIZE_64K
;
916 val
|= alloc_pages
- 1;
918 writeq_relaxed(val
, its
->base
+ GITS_BASER
+ i
* 8);
919 tmp
= readq_relaxed(its
->base
+ GITS_BASER
+ i
* 8);
921 if ((val
^ tmp
) & GITS_BASER_SHAREABILITY_MASK
) {
923 * Shareability didn't stick. Just use
924 * whatever the read reported, which is likely
925 * to be the only thing this redistributor
926 * supports. If that's zero, make it
927 * non-cacheable as well.
929 shr
= tmp
& GITS_BASER_SHAREABILITY_MASK
;
931 cache
= GITS_BASER_nC
;
932 __flush_dcache_area(base
, PAGE_ORDER_TO_SIZE(order
));
937 if ((val
^ tmp
) & GITS_BASER_PAGE_SIZE_MASK
) {
939 * Page size didn't stick. Let's try a smaller
940 * size and retry. If we reach 4K, then
941 * something is horribly wrong...
943 free_pages((unsigned long)base
, order
);
944 its
->tables
[i
].base
= NULL
;
949 goto retry_alloc_baser
;
952 goto retry_alloc_baser
;
957 pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
959 (unsigned long) val
, (unsigned long) tmp
);
964 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
965 (int)(PAGE_ORDER_TO_SIZE(order
) / entry_size
),
966 its_base_type_string
[type
],
967 (unsigned long)virt_to_phys(base
),
968 psz
/ SZ_1K
, (int)shr
>> GITS_BASER_SHAREABILITY_SHIFT
);
974 its_free_tables(its
);
979 static int its_alloc_collections(struct its_node
*its
)
981 its
->collections
= kzalloc(nr_cpu_ids
* sizeof(*its
->collections
),
983 if (!its
->collections
)
989 static void its_cpu_init_lpis(void)
991 void __iomem
*rbase
= gic_data_rdist_rd_base();
992 struct page
*pend_page
;
995 /* If we didn't allocate the pending table yet, do it now */
996 pend_page
= gic_data_rdist()->pend_page
;
1000 * The pending pages have to be at least 64kB aligned,
1001 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
1003 pend_page
= alloc_pages(GFP_NOWAIT
| __GFP_ZERO
,
1004 get_order(max(LPI_PENDBASE_SZ
, SZ_64K
)));
1006 pr_err("Failed to allocate PENDBASE for CPU%d\n",
1007 smp_processor_id());
1011 /* Make sure the GIC will observe the zero-ed page */
1012 __flush_dcache_area(page_address(pend_page
), LPI_PENDBASE_SZ
);
1014 paddr
= page_to_phys(pend_page
);
1015 pr_info("CPU%d: using LPI pending table @%pa\n",
1016 smp_processor_id(), &paddr
);
1017 gic_data_rdist()->pend_page
= pend_page
;
1021 val
= readl_relaxed(rbase
+ GICR_CTLR
);
1022 val
&= ~GICR_CTLR_ENABLE_LPIS
;
1023 writel_relaxed(val
, rbase
+ GICR_CTLR
);
1026 * Make sure any change to the table is observable by the GIC.
1031 val
= (page_to_phys(gic_rdists
->prop_page
) |
1032 GICR_PROPBASER_InnerShareable
|
1033 GICR_PROPBASER_WaWb
|
1034 ((LPI_NRBITS
- 1) & GICR_PROPBASER_IDBITS_MASK
));
1036 writeq_relaxed(val
, rbase
+ GICR_PROPBASER
);
1037 tmp
= readq_relaxed(rbase
+ GICR_PROPBASER
);
1039 if ((tmp
^ val
) & GICR_PROPBASER_SHAREABILITY_MASK
) {
1040 if (!(tmp
& GICR_PROPBASER_SHAREABILITY_MASK
)) {
1042 * The HW reports non-shareable, we must
1043 * remove the cacheability attributes as
1046 val
&= ~(GICR_PROPBASER_SHAREABILITY_MASK
|
1047 GICR_PROPBASER_CACHEABILITY_MASK
);
1048 val
|= GICR_PROPBASER_nC
;
1049 writeq_relaxed(val
, rbase
+ GICR_PROPBASER
);
1051 pr_info_once("GIC: using cache flushing for LPI property table\n");
1052 gic_rdists
->flags
|= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING
;
1056 val
= (page_to_phys(pend_page
) |
1057 GICR_PENDBASER_InnerShareable
|
1058 GICR_PENDBASER_WaWb
);
1060 writeq_relaxed(val
, rbase
+ GICR_PENDBASER
);
1061 tmp
= readq_relaxed(rbase
+ GICR_PENDBASER
);
1063 if (!(tmp
& GICR_PENDBASER_SHAREABILITY_MASK
)) {
1065 * The HW reports non-shareable, we must remove the
1066 * cacheability attributes as well.
1068 val
&= ~(GICR_PENDBASER_SHAREABILITY_MASK
|
1069 GICR_PENDBASER_CACHEABILITY_MASK
);
1070 val
|= GICR_PENDBASER_nC
;
1071 writeq_relaxed(val
, rbase
+ GICR_PENDBASER
);
1075 val
= readl_relaxed(rbase
+ GICR_CTLR
);
1076 val
|= GICR_CTLR_ENABLE_LPIS
;
1077 writel_relaxed(val
, rbase
+ GICR_CTLR
);
1079 /* Make sure the GIC has seen the above */
1083 static void its_cpu_init_collection(void)
1085 struct its_node
*its
;
1088 spin_lock(&its_lock
);
1089 cpu
= smp_processor_id();
1091 list_for_each_entry(its
, &its_nodes
, entry
) {
1095 * We now have to bind each collection to its target
1098 if (readq_relaxed(its
->base
+ GITS_TYPER
) & GITS_TYPER_PTA
) {
1100 * This ITS wants the physical address of the
1103 target
= gic_data_rdist()->phys_base
;
1106 * This ITS wants a linear CPU number.
1108 target
= readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER
);
1109 target
= GICR_TYPER_CPU_NUMBER(target
) << 16;
1112 /* Perform collection mapping */
1113 its
->collections
[cpu
].target_address
= target
;
1114 its
->collections
[cpu
].col_id
= cpu
;
1116 its_send_mapc(its
, &its
->collections
[cpu
], 1);
1117 its_send_invall(its
, &its
->collections
[cpu
]);
1120 spin_unlock(&its_lock
);
1123 static struct its_device
*its_find_device(struct its_node
*its
, u32 dev_id
)
1125 struct its_device
*its_dev
= NULL
, *tmp
;
1126 unsigned long flags
;
1128 raw_spin_lock_irqsave(&its
->lock
, flags
);
1130 list_for_each_entry(tmp
, &its
->its_device_list
, entry
) {
1131 if (tmp
->device_id
== dev_id
) {
1137 raw_spin_unlock_irqrestore(&its
->lock
, flags
);
1142 static struct its_device
*its_create_device(struct its_node
*its
, u32 dev_id
,
1145 struct its_device
*dev
;
1146 unsigned long *lpi_map
;
1147 unsigned long flags
;
1148 u16
*col_map
= NULL
;
1155 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1157 * At least one bit of EventID is being used, hence a minimum
1158 * of two entries. No, the architecture doesn't let you
1159 * express an ITT with a single entry.
1161 nr_ites
= max(2UL, roundup_pow_of_two(nvecs
));
1162 sz
= nr_ites
* its
->ite_size
;
1163 sz
= max(sz
, ITS_ITT_ALIGN
) + ITS_ITT_ALIGN
- 1;
1164 itt
= kzalloc(sz
, GFP_KERNEL
);
1165 lpi_map
= its_lpi_alloc_chunks(nvecs
, &lpi_base
, &nr_lpis
);
1167 col_map
= kzalloc(sizeof(*col_map
) * nr_lpis
, GFP_KERNEL
);
1169 if (!dev
|| !itt
|| !lpi_map
|| !col_map
) {
1177 __flush_dcache_area(itt
, sz
);
1181 dev
->nr_ites
= nr_ites
;
1182 dev
->event_map
.lpi_map
= lpi_map
;
1183 dev
->event_map
.col_map
= col_map
;
1184 dev
->event_map
.lpi_base
= lpi_base
;
1185 dev
->event_map
.nr_lpis
= nr_lpis
;
1186 dev
->device_id
= dev_id
;
1187 INIT_LIST_HEAD(&dev
->entry
);
1189 raw_spin_lock_irqsave(&its
->lock
, flags
);
1190 list_add(&dev
->entry
, &its
->its_device_list
);
1191 raw_spin_unlock_irqrestore(&its
->lock
, flags
);
1193 /* Map device to its ITT */
1194 its_send_mapd(dev
, 1);
1199 static void its_free_device(struct its_device
*its_dev
)
1201 unsigned long flags
;
1203 raw_spin_lock_irqsave(&its_dev
->its
->lock
, flags
);
1204 list_del(&its_dev
->entry
);
1205 raw_spin_unlock_irqrestore(&its_dev
->its
->lock
, flags
);
1206 kfree(its_dev
->itt
);
1210 static int its_alloc_device_irq(struct its_device
*dev
, irq_hw_number_t
*hwirq
)
1214 idx
= find_first_zero_bit(dev
->event_map
.lpi_map
,
1215 dev
->event_map
.nr_lpis
);
1216 if (idx
== dev
->event_map
.nr_lpis
)
1219 *hwirq
= dev
->event_map
.lpi_base
+ idx
;
1220 set_bit(idx
, dev
->event_map
.lpi_map
);
1225 static int its_msi_prepare(struct irq_domain
*domain
, struct device
*dev
,
1226 int nvec
, msi_alloc_info_t
*info
)
1228 struct its_node
*its
;
1229 struct its_device
*its_dev
;
1230 struct msi_domain_info
*msi_info
;
1234 * We ignore "dev" entierely, and rely on the dev_id that has
1235 * been passed via the scratchpad. This limits this domain's
1236 * usefulness to upper layers that definitely know that they
1237 * are built on top of the ITS.
1239 dev_id
= info
->scratchpad
[0].ul
;
1241 msi_info
= msi_get_domain_info(domain
);
1242 its
= msi_info
->data
;
1244 its_dev
= its_find_device(its
, dev_id
);
1247 * We already have seen this ID, probably through
1248 * another alias (PCI bridge of some sort). No need to
1249 * create the device.
1251 pr_debug("Reusing ITT for devID %x\n", dev_id
);
1255 its_dev
= its_create_device(its
, dev_id
, nvec
);
1259 pr_debug("ITT %d entries, %d bits\n", nvec
, ilog2(nvec
));
1261 info
->scratchpad
[0].ptr
= its_dev
;
1265 static struct msi_domain_ops its_msi_domain_ops
= {
1266 .msi_prepare
= its_msi_prepare
,
1269 static int its_irq_gic_domain_alloc(struct irq_domain
*domain
,
1271 irq_hw_number_t hwirq
)
1273 struct irq_fwspec fwspec
;
1275 if (irq_domain_get_of_node(domain
->parent
)) {
1276 fwspec
.fwnode
= domain
->parent
->fwnode
;
1277 fwspec
.param_count
= 3;
1278 fwspec
.param
[0] = GIC_IRQ_TYPE_LPI
;
1279 fwspec
.param
[1] = hwirq
;
1280 fwspec
.param
[2] = IRQ_TYPE_EDGE_RISING
;
1285 return irq_domain_alloc_irqs_parent(domain
, virq
, 1, &fwspec
);
1288 static int its_irq_domain_alloc(struct irq_domain
*domain
, unsigned int virq
,
1289 unsigned int nr_irqs
, void *args
)
1291 msi_alloc_info_t
*info
= args
;
1292 struct its_device
*its_dev
= info
->scratchpad
[0].ptr
;
1293 irq_hw_number_t hwirq
;
1297 for (i
= 0; i
< nr_irqs
; i
++) {
1298 err
= its_alloc_device_irq(its_dev
, &hwirq
);
1302 err
= its_irq_gic_domain_alloc(domain
, virq
+ i
, hwirq
);
1306 irq_domain_set_hwirq_and_chip(domain
, virq
+ i
,
1307 hwirq
, &its_irq_chip
, its_dev
);
1308 pr_debug("ID:%d pID:%d vID:%d\n",
1309 (int)(hwirq
- its_dev
->event_map
.lpi_base
),
1310 (int) hwirq
, virq
+ i
);
1316 static void its_irq_domain_activate(struct irq_domain
*domain
,
1319 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
1320 u32 event
= its_get_event_id(d
);
1322 /* Bind the LPI to the first possible CPU */
1323 its_dev
->event_map
.col_map
[event
] = cpumask_first(cpu_online_mask
);
1325 /* Map the GIC IRQ and event to the device */
1326 its_send_mapvi(its_dev
, d
->hwirq
, event
);
1329 static void its_irq_domain_deactivate(struct irq_domain
*domain
,
1332 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
1333 u32 event
= its_get_event_id(d
);
1335 /* Stop the delivery of interrupts */
1336 its_send_discard(its_dev
, event
);
1339 static void its_irq_domain_free(struct irq_domain
*domain
, unsigned int virq
,
1340 unsigned int nr_irqs
)
1342 struct irq_data
*d
= irq_domain_get_irq_data(domain
, virq
);
1343 struct its_device
*its_dev
= irq_data_get_irq_chip_data(d
);
1346 for (i
= 0; i
< nr_irqs
; i
++) {
1347 struct irq_data
*data
= irq_domain_get_irq_data(domain
,
1349 u32 event
= its_get_event_id(data
);
1351 /* Mark interrupt index as unused */
1352 clear_bit(event
, its_dev
->event_map
.lpi_map
);
1354 /* Nuke the entry in the domain */
1355 irq_domain_reset_irq_data(data
);
1358 /* If all interrupts have been freed, start mopping the floor */
1359 if (bitmap_empty(its_dev
->event_map
.lpi_map
,
1360 its_dev
->event_map
.nr_lpis
)) {
1361 its_lpi_free(&its_dev
->event_map
);
1363 /* Unmap device/itt */
1364 its_send_mapd(its_dev
, 0);
1365 its_free_device(its_dev
);
1368 irq_domain_free_irqs_parent(domain
, virq
, nr_irqs
);
1371 static const struct irq_domain_ops its_domain_ops
= {
1372 .alloc
= its_irq_domain_alloc
,
1373 .free
= its_irq_domain_free
,
1374 .activate
= its_irq_domain_activate
,
1375 .deactivate
= its_irq_domain_deactivate
,
1378 static int its_force_quiescent(void __iomem
*base
)
1380 u32 count
= 1000000; /* 1s */
1383 val
= readl_relaxed(base
+ GITS_CTLR
);
1384 if (val
& GITS_CTLR_QUIESCENT
)
1387 /* Disable the generation of all interrupts to this ITS */
1388 val
&= ~GITS_CTLR_ENABLE
;
1389 writel_relaxed(val
, base
+ GITS_CTLR
);
1391 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
1393 val
= readl_relaxed(base
+ GITS_CTLR
);
1394 if (val
& GITS_CTLR_QUIESCENT
)
1406 static void __maybe_unused
its_enable_quirk_cavium_22375(void *data
)
1408 struct its_node
*its
= data
;
1410 its
->flags
|= ITS_FLAGS_WORKAROUND_CAVIUM_22375
;
1413 static const struct gic_quirk its_quirks
[] = {
1414 #ifdef CONFIG_CAVIUM_ERRATUM_22375
1416 .desc
= "ITS: Cavium errata 22375, 24313",
1417 .iidr
= 0xa100034c, /* ThunderX pass 1.x */
1419 .init
= its_enable_quirk_cavium_22375
,
1426 static void its_enable_quirks(struct its_node
*its
)
1428 u32 iidr
= readl_relaxed(its
->base
+ GITS_IIDR
);
1430 gic_enable_quirks(iidr
, its_quirks
, its
);
1433 static int its_probe(struct device_node
*node
, struct irq_domain
*parent
)
1435 struct resource res
;
1436 struct its_node
*its
;
1437 void __iomem
*its_base
;
1438 struct irq_domain
*inner_domain
;
1443 err
= of_address_to_resource(node
, 0, &res
);
1445 pr_warn("%s: no regs?\n", node
->full_name
);
1449 its_base
= ioremap(res
.start
, resource_size(&res
));
1451 pr_warn("%s: unable to map registers\n", node
->full_name
);
1455 val
= readl_relaxed(its_base
+ GITS_PIDR2
) & GIC_PIDR2_ARCH_MASK
;
1456 if (val
!= 0x30 && val
!= 0x40) {
1457 pr_warn("%s: no ITS detected, giving up\n", node
->full_name
);
1462 err
= its_force_quiescent(its_base
);
1464 pr_warn("%s: failed to quiesce, giving up\n",
1469 pr_info("ITS: %s\n", node
->full_name
);
1471 its
= kzalloc(sizeof(*its
), GFP_KERNEL
);
1477 raw_spin_lock_init(&its
->lock
);
1478 INIT_LIST_HEAD(&its
->entry
);
1479 INIT_LIST_HEAD(&its
->its_device_list
);
1480 its
->base
= its_base
;
1481 its
->phys_base
= res
.start
;
1482 its
->ite_size
= ((readl_relaxed(its_base
+ GITS_TYPER
) >> 4) & 0xf) + 1;
1484 its
->cmd_base
= kzalloc(ITS_CMD_QUEUE_SZ
, GFP_KERNEL
);
1485 if (!its
->cmd_base
) {
1489 its
->cmd_write
= its
->cmd_base
;
1491 its_enable_quirks(its
);
1493 err
= its_alloc_tables(node
->full_name
, its
);
1497 err
= its_alloc_collections(its
);
1499 goto out_free_tables
;
1501 baser
= (virt_to_phys(its
->cmd_base
) |
1503 GITS_CBASER_InnerShareable
|
1504 (ITS_CMD_QUEUE_SZ
/ SZ_4K
- 1) |
1507 writeq_relaxed(baser
, its
->base
+ GITS_CBASER
);
1508 tmp
= readq_relaxed(its
->base
+ GITS_CBASER
);
1510 if ((tmp
^ baser
) & GITS_CBASER_SHAREABILITY_MASK
) {
1511 if (!(tmp
& GITS_CBASER_SHAREABILITY_MASK
)) {
1513 * The HW reports non-shareable, we must
1514 * remove the cacheability attributes as
1517 baser
&= ~(GITS_CBASER_SHAREABILITY_MASK
|
1518 GITS_CBASER_CACHEABILITY_MASK
);
1519 baser
|= GITS_CBASER_nC
;
1520 writeq_relaxed(baser
, its
->base
+ GITS_CBASER
);
1522 pr_info("ITS: using cache flushing for cmd queue\n");
1523 its
->flags
|= ITS_FLAGS_CMDQ_NEEDS_FLUSHING
;
1526 writeq_relaxed(0, its
->base
+ GITS_CWRITER
);
1527 writel_relaxed(GITS_CTLR_ENABLE
, its
->base
+ GITS_CTLR
);
1529 if (of_property_read_bool(node
, "msi-controller")) {
1530 struct msi_domain_info
*info
;
1532 info
= kzalloc(sizeof(*info
), GFP_KERNEL
);
1535 goto out_free_tables
;
1538 inner_domain
= irq_domain_add_tree(node
, &its_domain_ops
, its
);
1539 if (!inner_domain
) {
1542 goto out_free_tables
;
1545 inner_domain
->parent
= parent
;
1546 inner_domain
->bus_token
= DOMAIN_BUS_NEXUS
;
1547 info
->ops
= &its_msi_domain_ops
;
1549 inner_domain
->host_data
= info
;
1552 spin_lock(&its_lock
);
1553 list_add(&its
->entry
, &its_nodes
);
1554 spin_unlock(&its_lock
);
1559 its_free_tables(its
);
1561 kfree(its
->cmd_base
);
1566 pr_err("ITS: failed probing %s (%d)\n", node
->full_name
, err
);
1570 static bool gic_rdists_supports_plpis(void)
1572 return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER
) & GICR_TYPER_PLPIS
);
1575 int its_cpu_init(void)
1577 if (!list_empty(&its_nodes
)) {
1578 if (!gic_rdists_supports_plpis()) {
1579 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
1582 its_cpu_init_lpis();
1583 its_cpu_init_collection();
1589 static struct of_device_id its_device_id
[] = {
1590 { .compatible
= "arm,gic-v3-its", },
1594 int its_init(struct device_node
*node
, struct rdists
*rdists
,
1595 struct irq_domain
*parent_domain
)
1597 struct device_node
*np
;
1599 for (np
= of_find_matching_node(node
, its_device_id
); np
;
1600 np
= of_find_matching_node(np
, its_device_id
)) {
1601 its_probe(np
, parent_domain
);
1604 if (list_empty(&its_nodes
)) {
1605 pr_warn("ITS: No ITS available, not enabling LPIs\n");
1609 gic_rdists
= rdists
;
1610 gic_root_node
= node
;
1612 its_alloc_lpi_tables();
1613 its_lpi_init(rdists
->id_bits
);