2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/cpu.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/percpu.h>
25 #include <linux/slab.h>
27 #include <linux/irqchip/arm-gic-v3.h>
29 #include <asm/cputype.h>
30 #include <asm/exception.h>
31 #include <asm/smp_plat.h>
33 #include "irq-gic-common.h"
36 struct gic_chip_data
{
37 void __iomem
*dist_base
;
38 void __iomem
**redist_base
;
39 void __percpu __iomem
**rdist
;
40 struct irq_domain
*domain
;
46 static struct gic_chip_data gic_data __read_mostly
;
48 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdist))
49 #define gic_data_rdist_rd_base() (*gic_data_rdist())
50 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
52 /* Our default, arbitrary priority value. Linux only uses one anyway. */
53 #define DEFAULT_PMR_VALUE 0xf0
55 static inline unsigned int gic_irq(struct irq_data
*d
)
60 static inline int gic_irq_in_rdist(struct irq_data
*d
)
62 return gic_irq(d
) < 32;
65 static inline void __iomem
*gic_dist_base(struct irq_data
*d
)
67 if (gic_irq_in_rdist(d
)) /* SGI+PPI -> SGI_base for this CPU */
68 return gic_data_rdist_sgi_base();
70 if (d
->hwirq
<= 1023) /* SPI -> dist_base */
71 return gic_data
.dist_base
;
74 BUG(); /* LPI Detected!!! */
79 static void gic_do_wait_for_rwp(void __iomem
*base
)
81 u32 count
= 1000000; /* 1s! */
83 while (readl_relaxed(base
+ GICD_CTLR
) & GICD_CTLR_RWP
) {
86 pr_err_ratelimited("RWP timeout, gone fishing\n");
94 /* Wait for completion of a distributor change */
95 static void gic_dist_wait_for_rwp(void)
97 gic_do_wait_for_rwp(gic_data
.dist_base
);
100 /* Wait for completion of a redistributor change */
101 static void gic_redist_wait_for_rwp(void)
103 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
106 /* Low level accessors */
107 static u64
gic_read_iar(void)
111 asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1
) : "=r" (irqstat
));
115 static void gic_write_pmr(u64 val
)
117 asm volatile("msr_s " __stringify(ICC_PMR_EL1
) ", %0" : : "r" (val
));
120 static void gic_write_ctlr(u64 val
)
122 asm volatile("msr_s " __stringify(ICC_CTLR_EL1
) ", %0" : : "r" (val
));
126 static void gic_write_grpen1(u64 val
)
128 asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1
) ", %0" : : "r" (val
));
132 static void gic_write_sgi1r(u64 val
)
134 asm volatile("msr_s " __stringify(ICC_SGI1R_EL1
) ", %0" : : "r" (val
));
137 static void gic_enable_sre(void)
141 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1
) : "=r" (val
));
142 val
|= ICC_SRE_EL1_SRE
;
143 asm volatile("msr_s " __stringify(ICC_SRE_EL1
) ", %0" : : "r" (val
));
147 * Need to check that the SRE bit has actually been set. If
148 * not, it means that SRE is disabled at EL2. We're going to
149 * die painfully, and there is nothing we can do about it.
151 * Kindly inform the luser.
153 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1
) : "=r" (val
));
154 if (!(val
& ICC_SRE_EL1_SRE
))
155 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
158 static void gic_enable_redist(void)
161 u32 count
= 1000000; /* 1s! */
164 rbase
= gic_data_rdist_rd_base();
166 /* Wake up this CPU redistributor */
167 val
= readl_relaxed(rbase
+ GICR_WAKER
);
168 val
&= ~GICR_WAKER_ProcessorSleep
;
169 writel_relaxed(val
, rbase
+ GICR_WAKER
);
171 while (readl_relaxed(rbase
+ GICR_WAKER
) & GICR_WAKER_ChildrenAsleep
) {
174 pr_err_ratelimited("redist didn't wake up...\n");
183 * Routines to disable, enable, EOI and route interrupts
185 static void gic_poke_irq(struct irq_data
*d
, u32 offset
)
187 u32 mask
= 1 << (gic_irq(d
) % 32);
188 void (*rwp_wait
)(void);
191 if (gic_irq_in_rdist(d
)) {
192 base
= gic_data_rdist_sgi_base();
193 rwp_wait
= gic_redist_wait_for_rwp
;
195 base
= gic_data
.dist_base
;
196 rwp_wait
= gic_dist_wait_for_rwp
;
199 writel_relaxed(mask
, base
+ offset
+ (gic_irq(d
) / 32) * 4);
203 static int gic_peek_irq(struct irq_data
*d
, u32 offset
)
205 u32 mask
= 1 << (gic_irq(d
) % 32);
208 if (gic_irq_in_rdist(d
))
209 base
= gic_data_rdist_sgi_base();
211 base
= gic_data
.dist_base
;
213 return !!(readl_relaxed(base
+ offset
+ (gic_irq(d
) / 32) * 4) & mask
);
216 static void gic_mask_irq(struct irq_data
*d
)
218 gic_poke_irq(d
, GICD_ICENABLER
);
221 static void gic_unmask_irq(struct irq_data
*d
)
223 gic_poke_irq(d
, GICD_ISENABLER
);
226 static void gic_eoi_irq(struct irq_data
*d
)
228 gic_write_eoir(gic_irq(d
));
231 static int gic_set_type(struct irq_data
*d
, unsigned int type
)
233 unsigned int irq
= gic_irq(d
);
234 void (*rwp_wait
)(void);
237 /* Interrupt configuration for SGIs can't be changed */
241 if (type
!= IRQ_TYPE_LEVEL_HIGH
&& type
!= IRQ_TYPE_EDGE_RISING
)
244 if (gic_irq_in_rdist(d
)) {
245 base
= gic_data_rdist_sgi_base();
246 rwp_wait
= gic_redist_wait_for_rwp
;
248 base
= gic_data
.dist_base
;
249 rwp_wait
= gic_dist_wait_for_rwp
;
252 gic_configure_irq(irq
, type
, base
, rwp_wait
);
257 static u64
gic_mpidr_to_affinity(u64 mpidr
)
261 aff
= (MPIDR_AFFINITY_LEVEL(mpidr
, 3) << 32 |
262 MPIDR_AFFINITY_LEVEL(mpidr
, 2) << 16 |
263 MPIDR_AFFINITY_LEVEL(mpidr
, 1) << 8 |
264 MPIDR_AFFINITY_LEVEL(mpidr
, 0));
269 static asmlinkage
void __exception_irq_entry
gic_handle_irq(struct pt_regs
*regs
)
274 irqnr
= gic_read_iar();
276 if (likely(irqnr
> 15 && irqnr
< 1020)) {
277 u64 irq
= irq_find_mapping(gic_data
.domain
, irqnr
);
279 handle_IRQ(irq
, regs
);
283 WARN_ONCE(true, "Unexpected SPI received!\n");
284 gic_write_eoir(irqnr
);
287 gic_write_eoir(irqnr
);
289 handle_IPI(irqnr
, regs
);
291 WARN_ONCE(true, "Unexpected SGI received!\n");
295 } while (irqnr
!= ICC_IAR1_EL1_SPURIOUS
);
298 static void __init
gic_dist_init(void)
302 void __iomem
*base
= gic_data
.dist_base
;
304 /* Disable the distributor */
305 writel_relaxed(0, base
+ GICD_CTLR
);
306 gic_dist_wait_for_rwp();
308 gic_dist_config(base
, gic_data
.irq_nr
, gic_dist_wait_for_rwp
);
310 /* Enable distributor with ARE, Group1 */
311 writel_relaxed(GICD_CTLR_ARE_NS
| GICD_CTLR_ENABLE_G1A
| GICD_CTLR_ENABLE_G1
,
315 * Set all global interrupts to the boot CPU only. ARE must be
318 affinity
= gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
319 for (i
= 32; i
< gic_data
.irq_nr
; i
++)
320 writeq_relaxed(affinity
, base
+ GICD_IROUTER
+ i
* 8);
323 static int gic_populate_rdist(void)
325 u64 mpidr
= cpu_logical_map(smp_processor_id());
331 * Convert affinity to a 32bit value that can be matched to
332 * GICR_TYPER bits [63:32].
334 aff
= (MPIDR_AFFINITY_LEVEL(mpidr
, 3) << 24 |
335 MPIDR_AFFINITY_LEVEL(mpidr
, 2) << 16 |
336 MPIDR_AFFINITY_LEVEL(mpidr
, 1) << 8 |
337 MPIDR_AFFINITY_LEVEL(mpidr
, 0));
339 for (i
= 0; i
< gic_data
.redist_regions
; i
++) {
340 void __iomem
*ptr
= gic_data
.redist_base
[i
];
343 reg
= readl_relaxed(ptr
+ GICR_PIDR2
) & GIC_PIDR2_ARCH_MASK
;
344 if (reg
!= GIC_PIDR2_ARCH_GICv3
&&
345 reg
!= GIC_PIDR2_ARCH_GICv4
) { /* We're in trouble... */
346 pr_warn("No redistributor present @%p\n", ptr
);
351 typer
= readq_relaxed(ptr
+ GICR_TYPER
);
352 if ((typer
>> 32) == aff
) {
353 gic_data_rdist_rd_base() = ptr
;
354 pr_info("CPU%d: found redistributor %llx @%p\n",
356 (unsigned long long)mpidr
, ptr
);
360 if (gic_data
.redist_stride
) {
361 ptr
+= gic_data
.redist_stride
;
363 ptr
+= SZ_64K
* 2; /* Skip RD_base + SGI_base */
364 if (typer
& GICR_TYPER_VLPIS
)
365 ptr
+= SZ_64K
* 2; /* Skip VLPI_base + reserved page */
367 } while (!(typer
& GICR_TYPER_LAST
));
370 /* We couldn't even deal with ourselves... */
371 WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
372 smp_processor_id(), (unsigned long long)mpidr
);
376 static void gic_cpu_init(void)
380 /* Register ourselves with the rest of the world */
381 if (gic_populate_rdist())
386 rbase
= gic_data_rdist_sgi_base();
388 gic_cpu_config(rbase
, gic_redist_wait_for_rwp
);
390 /* Enable system registers */
393 /* Set priority mask register */
394 gic_write_pmr(DEFAULT_PMR_VALUE
);
396 /* EOI deactivates interrupt too (mode 0) */
397 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir
);
399 /* ... and let's hit the road... */
404 static int gic_secondary_init(struct notifier_block
*nfb
,
405 unsigned long action
, void *hcpu
)
407 if (action
== CPU_STARTING
|| action
== CPU_STARTING_FROZEN
)
413 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
414 * priority because the GIC needs to be up before the ARM generic timers.
416 static struct notifier_block gic_cpu_notifier
= {
417 .notifier_call
= gic_secondary_init
,
421 static u16
gic_compute_target_list(int *base_cpu
, const struct cpumask
*mask
,
425 u64 mpidr
= cpu_logical_map(cpu
);
428 while (cpu
< nr_cpu_ids
) {
430 * If we ever get a cluster of more than 16 CPUs, just
431 * scream and skip that CPU.
433 if (WARN_ON((mpidr
& 0xff) >= 16))
436 tlist
|= 1 << (mpidr
& 0xf);
438 cpu
= cpumask_next(cpu
, mask
);
439 if (cpu
== nr_cpu_ids
)
442 mpidr
= cpu_logical_map(cpu
);
444 if (cluster_id
!= (mpidr
& ~0xffUL
)) {
454 static void gic_send_sgi(u64 cluster_id
, u16 tlist
, unsigned int irq
)
458 val
= (MPIDR_AFFINITY_LEVEL(cluster_id
, 3) << 48 |
459 MPIDR_AFFINITY_LEVEL(cluster_id
, 2) << 32 |
461 MPIDR_AFFINITY_LEVEL(cluster_id
, 1) << 16 |
464 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val
);
465 gic_write_sgi1r(val
);
468 static void gic_raise_softirq(const struct cpumask
*mask
, unsigned int irq
)
472 if (WARN_ON(irq
>= 16))
476 * Ensure that stores to Normal memory are visible to the
477 * other CPUs before issuing the IPI.
481 for_each_cpu_mask(cpu
, *mask
) {
482 u64 cluster_id
= cpu_logical_map(cpu
) & ~0xffUL
;
485 tlist
= gic_compute_target_list(&cpu
, mask
, cluster_id
);
486 gic_send_sgi(cluster_id
, tlist
, irq
);
489 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
493 static void gic_smp_init(void)
495 set_smp_cross_call(gic_raise_softirq
);
496 register_cpu_notifier(&gic_cpu_notifier
);
499 static int gic_set_affinity(struct irq_data
*d
, const struct cpumask
*mask_val
,
502 unsigned int cpu
= cpumask_any_and(mask_val
, cpu_online_mask
);
507 if (gic_irq_in_rdist(d
))
510 /* If interrupt was enabled, disable it first */
511 enabled
= gic_peek_irq(d
, GICD_ISENABLER
);
515 reg
= gic_dist_base(d
) + GICD_IROUTER
+ (gic_irq(d
) * 8);
516 val
= gic_mpidr_to_affinity(cpu_logical_map(cpu
));
518 writeq_relaxed(val
, reg
);
521 * If the interrupt was enabled, enabled it again. Otherwise,
522 * just wait for the distributor to have digested our changes.
527 gic_dist_wait_for_rwp();
529 return IRQ_SET_MASK_OK
;
532 #define gic_set_affinity NULL
533 #define gic_smp_init() do { } while(0)
536 static struct irq_chip gic_chip
= {
538 .irq_mask
= gic_mask_irq
,
539 .irq_unmask
= gic_unmask_irq
,
540 .irq_eoi
= gic_eoi_irq
,
541 .irq_set_type
= gic_set_type
,
542 .irq_set_affinity
= gic_set_affinity
,
545 static int gic_irq_domain_map(struct irq_domain
*d
, unsigned int irq
,
548 /* SGIs are private to the core kernel */
553 irq_set_percpu_devid(irq
);
554 irq_set_chip_and_handler(irq
, &gic_chip
,
555 handle_percpu_devid_irq
);
556 set_irq_flags(irq
, IRQF_VALID
| IRQF_NOAUTOEN
);
559 if (hw
>= 32 && hw
< gic_data
.irq_nr
) {
560 irq_set_chip_and_handler(irq
, &gic_chip
,
562 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
564 irq_set_chip_data(irq
, d
->host_data
);
568 static int gic_irq_domain_xlate(struct irq_domain
*d
,
569 struct device_node
*controller
,
570 const u32
*intspec
, unsigned int intsize
,
571 unsigned long *out_hwirq
, unsigned int *out_type
)
573 if (d
->of_node
!= controller
)
580 *out_hwirq
= intspec
[1] + 32;
583 *out_hwirq
= intspec
[1] + 16;
589 *out_type
= intspec
[2] & IRQ_TYPE_SENSE_MASK
;
593 static const struct irq_domain_ops gic_irq_domain_ops
= {
594 .map
= gic_irq_domain_map
,
595 .xlate
= gic_irq_domain_xlate
,
598 static int __init
gic_of_init(struct device_node
*node
, struct device_node
*parent
)
600 void __iomem
*dist_base
;
601 void __iomem
**redist_base
;
609 dist_base
= of_iomap(node
, 0);
611 pr_err("%s: unable to map gic dist registers\n",
616 reg
= readl_relaxed(dist_base
+ GICD_PIDR2
) & GIC_PIDR2_ARCH_MASK
;
617 if (reg
!= GIC_PIDR2_ARCH_GICv3
&& reg
!= GIC_PIDR2_ARCH_GICv4
) {
618 pr_err("%s: no distributor detected, giving up\n",
624 if (of_property_read_u32(node
, "#redistributor-regions", &redist_regions
))
627 redist_base
= kzalloc(sizeof(*redist_base
) * redist_regions
, GFP_KERNEL
);
633 for (i
= 0; i
< redist_regions
; i
++) {
634 redist_base
[i
] = of_iomap(node
, 1 + i
);
635 if (!redist_base
[i
]) {
636 pr_err("%s: couldn't map region %d\n",
639 goto out_unmap_rdist
;
643 if (of_property_read_u64(node
, "redistributor-stride", &redist_stride
))
646 gic_data
.dist_base
= dist_base
;
647 gic_data
.redist_base
= redist_base
;
648 gic_data
.redist_regions
= redist_regions
;
649 gic_data
.redist_stride
= redist_stride
;
652 * Find out how many interrupts are supported.
653 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
655 gic_irqs
= readl_relaxed(gic_data
.dist_base
+ GICD_TYPER
) & 0x1f;
656 gic_irqs
= (gic_irqs
+ 1) * 32;
659 gic_data
.irq_nr
= gic_irqs
;
661 gic_data
.domain
= irq_domain_add_tree(node
, &gic_irq_domain_ops
,
663 gic_data
.rdist
= alloc_percpu(typeof(*gic_data
.rdist
));
665 if (WARN_ON(!gic_data
.domain
) || WARN_ON(!gic_data
.rdist
)) {
670 set_handle_irq(gic_handle_irq
);
680 irq_domain_remove(gic_data
.domain
);
681 free_percpu(gic_data
.rdist
);
683 for (i
= 0; i
< redist_regions
; i
++)
685 iounmap(redist_base
[i
]);
692 IRQCHIP_DECLARE(gic_v3
, "arm,gic-v3", gic_of_init
);