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irqchip/gic-v3: Make gic_enable_sre an inline function
[deliverable/linux.git] / drivers / irqchip / irq-gic-v3.c
1 /*
2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include <linux/cpu.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/percpu.h>
26 #include <linux/slab.h>
27
28 #include <linux/irqchip.h>
29 #include <linux/irqchip/arm-gic-v3.h>
30
31 #include <asm/cputype.h>
32 #include <asm/exception.h>
33 #include <asm/smp_plat.h>
34 #include <asm/virt.h>
35
36 #include "irq-gic-common.h"
37
38 struct redist_region {
39 void __iomem *redist_base;
40 phys_addr_t phys_base;
41 };
42
43 struct gic_chip_data {
44 void __iomem *dist_base;
45 struct redist_region *redist_regions;
46 struct rdists rdists;
47 struct irq_domain *domain;
48 u64 redist_stride;
49 u32 nr_redist_regions;
50 unsigned int irq_nr;
51 };
52
53 static struct gic_chip_data gic_data __read_mostly;
54 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
55
56 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
57 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
58 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
59
60 /* Our default, arbitrary priority value. Linux only uses one anyway. */
61 #define DEFAULT_PMR_VALUE 0xf0
62
63 static inline unsigned int gic_irq(struct irq_data *d)
64 {
65 return d->hwirq;
66 }
67
68 static inline int gic_irq_in_rdist(struct irq_data *d)
69 {
70 return gic_irq(d) < 32;
71 }
72
73 static inline void __iomem *gic_dist_base(struct irq_data *d)
74 {
75 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
76 return gic_data_rdist_sgi_base();
77
78 if (d->hwirq <= 1023) /* SPI -> dist_base */
79 return gic_data.dist_base;
80
81 return NULL;
82 }
83
84 static void gic_do_wait_for_rwp(void __iomem *base)
85 {
86 u32 count = 1000000; /* 1s! */
87
88 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
89 count--;
90 if (!count) {
91 pr_err_ratelimited("RWP timeout, gone fishing\n");
92 return;
93 }
94 cpu_relax();
95 udelay(1);
96 };
97 }
98
99 /* Wait for completion of a distributor change */
100 static void gic_dist_wait_for_rwp(void)
101 {
102 gic_do_wait_for_rwp(gic_data.dist_base);
103 }
104
105 /* Wait for completion of a redistributor change */
106 static void gic_redist_wait_for_rwp(void)
107 {
108 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
109 }
110
111 /* Low level accessors */
112 static u64 gic_read_iar_common(void)
113 {
114 u64 irqstat;
115
116 asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
117 return irqstat;
118 }
119
120 /*
121 * Cavium ThunderX erratum 23154
122 *
123 * The gicv3 of ThunderX requires a modified version for reading the
124 * IAR status to ensure data synchronization (access to icc_iar1_el1
125 * is not sync'ed before and after).
126 */
127 static u64 gic_read_iar_cavium_thunderx(void)
128 {
129 u64 irqstat;
130
131 asm volatile(
132 "nop;nop;nop;nop\n\t"
133 "nop;nop;nop;nop\n\t"
134 "mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"
135 "nop;nop;nop;nop"
136 : "=r" (irqstat));
137 mb();
138
139 return irqstat;
140 }
141
142 static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx);
143
144 static u64 __maybe_unused gic_read_iar(void)
145 {
146 if (static_branch_unlikely(&is_cavium_thunderx))
147 return gic_read_iar_cavium_thunderx();
148 else
149 return gic_read_iar_common();
150 }
151
152 static void __maybe_unused gic_write_pmr(u64 val)
153 {
154 asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
155 }
156
157 static void __maybe_unused gic_write_ctlr(u64 val)
158 {
159 asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
160 isb();
161 }
162
163 static void __maybe_unused gic_write_grpen1(u64 val)
164 {
165 asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
166 isb();
167 }
168
169 static void __maybe_unused gic_write_sgi1r(u64 val)
170 {
171 asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
172 }
173
174 static void gic_enable_redist(bool enable)
175 {
176 void __iomem *rbase;
177 u32 count = 1000000; /* 1s! */
178 u32 val;
179
180 rbase = gic_data_rdist_rd_base();
181
182 val = readl_relaxed(rbase + GICR_WAKER);
183 if (enable)
184 /* Wake up this CPU redistributor */
185 val &= ~GICR_WAKER_ProcessorSleep;
186 else
187 val |= GICR_WAKER_ProcessorSleep;
188 writel_relaxed(val, rbase + GICR_WAKER);
189
190 if (!enable) { /* Check that GICR_WAKER is writeable */
191 val = readl_relaxed(rbase + GICR_WAKER);
192 if (!(val & GICR_WAKER_ProcessorSleep))
193 return; /* No PM support in this redistributor */
194 }
195
196 while (count--) {
197 val = readl_relaxed(rbase + GICR_WAKER);
198 if (enable ^ (val & GICR_WAKER_ChildrenAsleep))
199 break;
200 cpu_relax();
201 udelay(1);
202 };
203 if (!count)
204 pr_err_ratelimited("redistributor failed to %s...\n",
205 enable ? "wakeup" : "sleep");
206 }
207
208 /*
209 * Routines to disable, enable, EOI and route interrupts
210 */
211 static int gic_peek_irq(struct irq_data *d, u32 offset)
212 {
213 u32 mask = 1 << (gic_irq(d) % 32);
214 void __iomem *base;
215
216 if (gic_irq_in_rdist(d))
217 base = gic_data_rdist_sgi_base();
218 else
219 base = gic_data.dist_base;
220
221 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
222 }
223
224 static void gic_poke_irq(struct irq_data *d, u32 offset)
225 {
226 u32 mask = 1 << (gic_irq(d) % 32);
227 void (*rwp_wait)(void);
228 void __iomem *base;
229
230 if (gic_irq_in_rdist(d)) {
231 base = gic_data_rdist_sgi_base();
232 rwp_wait = gic_redist_wait_for_rwp;
233 } else {
234 base = gic_data.dist_base;
235 rwp_wait = gic_dist_wait_for_rwp;
236 }
237
238 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
239 rwp_wait();
240 }
241
242 static void gic_mask_irq(struct irq_data *d)
243 {
244 gic_poke_irq(d, GICD_ICENABLER);
245 }
246
247 static void gic_eoimode1_mask_irq(struct irq_data *d)
248 {
249 gic_mask_irq(d);
250 /*
251 * When masking a forwarded interrupt, make sure it is
252 * deactivated as well.
253 *
254 * This ensures that an interrupt that is getting
255 * disabled/masked will not get "stuck", because there is
256 * noone to deactivate it (guest is being terminated).
257 */
258 if (irqd_is_forwarded_to_vcpu(d))
259 gic_poke_irq(d, GICD_ICACTIVER);
260 }
261
262 static void gic_unmask_irq(struct irq_data *d)
263 {
264 gic_poke_irq(d, GICD_ISENABLER);
265 }
266
267 static int gic_irq_set_irqchip_state(struct irq_data *d,
268 enum irqchip_irq_state which, bool val)
269 {
270 u32 reg;
271
272 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
273 return -EINVAL;
274
275 switch (which) {
276 case IRQCHIP_STATE_PENDING:
277 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
278 break;
279
280 case IRQCHIP_STATE_ACTIVE:
281 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
282 break;
283
284 case IRQCHIP_STATE_MASKED:
285 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
286 break;
287
288 default:
289 return -EINVAL;
290 }
291
292 gic_poke_irq(d, reg);
293 return 0;
294 }
295
296 static int gic_irq_get_irqchip_state(struct irq_data *d,
297 enum irqchip_irq_state which, bool *val)
298 {
299 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
300 return -EINVAL;
301
302 switch (which) {
303 case IRQCHIP_STATE_PENDING:
304 *val = gic_peek_irq(d, GICD_ISPENDR);
305 break;
306
307 case IRQCHIP_STATE_ACTIVE:
308 *val = gic_peek_irq(d, GICD_ISACTIVER);
309 break;
310
311 case IRQCHIP_STATE_MASKED:
312 *val = !gic_peek_irq(d, GICD_ISENABLER);
313 break;
314
315 default:
316 return -EINVAL;
317 }
318
319 return 0;
320 }
321
322 static void gic_eoi_irq(struct irq_data *d)
323 {
324 gic_write_eoir(gic_irq(d));
325 }
326
327 static void gic_eoimode1_eoi_irq(struct irq_data *d)
328 {
329 /*
330 * No need to deactivate an LPI, or an interrupt that
331 * is is getting forwarded to a vcpu.
332 */
333 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
334 return;
335 gic_write_dir(gic_irq(d));
336 }
337
338 static int gic_set_type(struct irq_data *d, unsigned int type)
339 {
340 unsigned int irq = gic_irq(d);
341 void (*rwp_wait)(void);
342 void __iomem *base;
343
344 /* Interrupt configuration for SGIs can't be changed */
345 if (irq < 16)
346 return -EINVAL;
347
348 /* SPIs have restrictions on the supported types */
349 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
350 type != IRQ_TYPE_EDGE_RISING)
351 return -EINVAL;
352
353 if (gic_irq_in_rdist(d)) {
354 base = gic_data_rdist_sgi_base();
355 rwp_wait = gic_redist_wait_for_rwp;
356 } else {
357 base = gic_data.dist_base;
358 rwp_wait = gic_dist_wait_for_rwp;
359 }
360
361 return gic_configure_irq(irq, type, base, rwp_wait);
362 }
363
364 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
365 {
366 if (vcpu)
367 irqd_set_forwarded_to_vcpu(d);
368 else
369 irqd_clr_forwarded_to_vcpu(d);
370 return 0;
371 }
372
373 static u64 gic_mpidr_to_affinity(u64 mpidr)
374 {
375 u64 aff;
376
377 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
378 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
379 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
380 MPIDR_AFFINITY_LEVEL(mpidr, 0));
381
382 return aff;
383 }
384
385 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
386 {
387 u64 irqnr;
388
389 do {
390 irqnr = gic_read_iar();
391
392 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
393 int err;
394
395 if (static_key_true(&supports_deactivate))
396 gic_write_eoir(irqnr);
397
398 err = handle_domain_irq(gic_data.domain, irqnr, regs);
399 if (err) {
400 WARN_ONCE(true, "Unexpected interrupt received!\n");
401 if (static_key_true(&supports_deactivate)) {
402 if (irqnr < 8192)
403 gic_write_dir(irqnr);
404 } else {
405 gic_write_eoir(irqnr);
406 }
407 }
408 continue;
409 }
410 if (irqnr < 16) {
411 gic_write_eoir(irqnr);
412 if (static_key_true(&supports_deactivate))
413 gic_write_dir(irqnr);
414 #ifdef CONFIG_SMP
415 handle_IPI(irqnr, regs);
416 #else
417 WARN_ONCE(true, "Unexpected SGI received!\n");
418 #endif
419 continue;
420 }
421 } while (irqnr != ICC_IAR1_EL1_SPURIOUS);
422 }
423
424 static void __init gic_dist_init(void)
425 {
426 unsigned int i;
427 u64 affinity;
428 void __iomem *base = gic_data.dist_base;
429
430 /* Disable the distributor */
431 writel_relaxed(0, base + GICD_CTLR);
432 gic_dist_wait_for_rwp();
433
434 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
435
436 /* Enable distributor with ARE, Group1 */
437 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
438 base + GICD_CTLR);
439
440 /*
441 * Set all global interrupts to the boot CPU only. ARE must be
442 * enabled.
443 */
444 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
445 for (i = 32; i < gic_data.irq_nr; i++)
446 writeq_relaxed(affinity, base + GICD_IROUTER + i * 8);
447 }
448
449 static int gic_populate_rdist(void)
450 {
451 u64 mpidr = cpu_logical_map(smp_processor_id());
452 u64 typer;
453 u32 aff;
454 int i;
455
456 /*
457 * Convert affinity to a 32bit value that can be matched to
458 * GICR_TYPER bits [63:32].
459 */
460 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
461 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
462 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
463 MPIDR_AFFINITY_LEVEL(mpidr, 0));
464
465 for (i = 0; i < gic_data.nr_redist_regions; i++) {
466 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
467 u32 reg;
468
469 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
470 if (reg != GIC_PIDR2_ARCH_GICv3 &&
471 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
472 pr_warn("No redistributor present @%p\n", ptr);
473 break;
474 }
475
476 do {
477 typer = readq_relaxed(ptr + GICR_TYPER);
478 if ((typer >> 32) == aff) {
479 u64 offset = ptr - gic_data.redist_regions[i].redist_base;
480 gic_data_rdist_rd_base() = ptr;
481 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset;
482 pr_info("CPU%d: found redistributor %llx region %d:%pa\n",
483 smp_processor_id(),
484 (unsigned long long)mpidr,
485 i, &gic_data_rdist()->phys_base);
486 return 0;
487 }
488
489 if (gic_data.redist_stride) {
490 ptr += gic_data.redist_stride;
491 } else {
492 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
493 if (typer & GICR_TYPER_VLPIS)
494 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
495 }
496 } while (!(typer & GICR_TYPER_LAST));
497 }
498
499 /* We couldn't even deal with ourselves... */
500 WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n",
501 smp_processor_id(), (unsigned long long)mpidr);
502 return -ENODEV;
503 }
504
505 static void gic_cpu_sys_reg_init(void)
506 {
507 /*
508 * Need to check that the SRE bit has actually been set. If
509 * not, it means that SRE is disabled at EL2. We're going to
510 * die painfully, and there is nothing we can do about it.
511 *
512 * Kindly inform the luser.
513 */
514 if (!gic_enable_sre())
515 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
516
517 /* Set priority mask register */
518 gic_write_pmr(DEFAULT_PMR_VALUE);
519
520 if (static_key_true(&supports_deactivate)) {
521 /* EOI drops priority only (mode 1) */
522 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
523 } else {
524 /* EOI deactivates interrupt too (mode 0) */
525 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
526 }
527
528 /* ... and let's hit the road... */
529 gic_write_grpen1(1);
530 }
531
532 static int gic_dist_supports_lpis(void)
533 {
534 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS);
535 }
536
537 static void gic_cpu_init(void)
538 {
539 void __iomem *rbase;
540
541 /* Register ourselves with the rest of the world */
542 if (gic_populate_rdist())
543 return;
544
545 gic_enable_redist(true);
546
547 rbase = gic_data_rdist_sgi_base();
548
549 gic_cpu_config(rbase, gic_redist_wait_for_rwp);
550
551 /* Give LPIs a spin */
552 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
553 its_cpu_init();
554
555 /* initialise system registers */
556 gic_cpu_sys_reg_init();
557 }
558
559 #ifdef CONFIG_SMP
560 static int gic_secondary_init(struct notifier_block *nfb,
561 unsigned long action, void *hcpu)
562 {
563 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
564 gic_cpu_init();
565 return NOTIFY_OK;
566 }
567
568 /*
569 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
570 * priority because the GIC needs to be up before the ARM generic timers.
571 */
572 static struct notifier_block gic_cpu_notifier = {
573 .notifier_call = gic_secondary_init,
574 .priority = 100,
575 };
576
577 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
578 u64 cluster_id)
579 {
580 int cpu = *base_cpu;
581 u64 mpidr = cpu_logical_map(cpu);
582 u16 tlist = 0;
583
584 while (cpu < nr_cpu_ids) {
585 /*
586 * If we ever get a cluster of more than 16 CPUs, just
587 * scream and skip that CPU.
588 */
589 if (WARN_ON((mpidr & 0xff) >= 16))
590 goto out;
591
592 tlist |= 1 << (mpidr & 0xf);
593
594 cpu = cpumask_next(cpu, mask);
595 if (cpu >= nr_cpu_ids)
596 goto out;
597
598 mpidr = cpu_logical_map(cpu);
599
600 if (cluster_id != (mpidr & ~0xffUL)) {
601 cpu--;
602 goto out;
603 }
604 }
605 out:
606 *base_cpu = cpu;
607 return tlist;
608 }
609
610 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
611 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
612 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
613
614 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
615 {
616 u64 val;
617
618 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
619 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
620 irq << ICC_SGI1R_SGI_ID_SHIFT |
621 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
622 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
623
624 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
625 gic_write_sgi1r(val);
626 }
627
628 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
629 {
630 int cpu;
631
632 if (WARN_ON(irq >= 16))
633 return;
634
635 /*
636 * Ensure that stores to Normal memory are visible to the
637 * other CPUs before issuing the IPI.
638 */
639 smp_wmb();
640
641 for_each_cpu(cpu, mask) {
642 u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL;
643 u16 tlist;
644
645 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
646 gic_send_sgi(cluster_id, tlist, irq);
647 }
648
649 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
650 isb();
651 }
652
653 static void gic_smp_init(void)
654 {
655 set_smp_cross_call(gic_raise_softirq);
656 register_cpu_notifier(&gic_cpu_notifier);
657 }
658
659 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
660 bool force)
661 {
662 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
663 void __iomem *reg;
664 int enabled;
665 u64 val;
666
667 if (gic_irq_in_rdist(d))
668 return -EINVAL;
669
670 /* If interrupt was enabled, disable it first */
671 enabled = gic_peek_irq(d, GICD_ISENABLER);
672 if (enabled)
673 gic_mask_irq(d);
674
675 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
676 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
677
678 writeq_relaxed(val, reg);
679
680 /*
681 * If the interrupt was enabled, enabled it again. Otherwise,
682 * just wait for the distributor to have digested our changes.
683 */
684 if (enabled)
685 gic_unmask_irq(d);
686 else
687 gic_dist_wait_for_rwp();
688
689 return IRQ_SET_MASK_OK;
690 }
691 #else
692 #define gic_set_affinity NULL
693 #define gic_smp_init() do { } while(0)
694 #endif
695
696 #ifdef CONFIG_CPU_PM
697 static int gic_cpu_pm_notifier(struct notifier_block *self,
698 unsigned long cmd, void *v)
699 {
700 if (cmd == CPU_PM_EXIT) {
701 gic_enable_redist(true);
702 gic_cpu_sys_reg_init();
703 } else if (cmd == CPU_PM_ENTER) {
704 gic_write_grpen1(0);
705 gic_enable_redist(false);
706 }
707 return NOTIFY_OK;
708 }
709
710 static struct notifier_block gic_cpu_pm_notifier_block = {
711 .notifier_call = gic_cpu_pm_notifier,
712 };
713
714 static void gic_cpu_pm_init(void)
715 {
716 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
717 }
718
719 #else
720 static inline void gic_cpu_pm_init(void) { }
721 #endif /* CONFIG_CPU_PM */
722
723 static struct irq_chip gic_chip = {
724 .name = "GICv3",
725 .irq_mask = gic_mask_irq,
726 .irq_unmask = gic_unmask_irq,
727 .irq_eoi = gic_eoi_irq,
728 .irq_set_type = gic_set_type,
729 .irq_set_affinity = gic_set_affinity,
730 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
731 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
732 .flags = IRQCHIP_SET_TYPE_MASKED,
733 };
734
735 static struct irq_chip gic_eoimode1_chip = {
736 .name = "GICv3",
737 .irq_mask = gic_eoimode1_mask_irq,
738 .irq_unmask = gic_unmask_irq,
739 .irq_eoi = gic_eoimode1_eoi_irq,
740 .irq_set_type = gic_set_type,
741 .irq_set_affinity = gic_set_affinity,
742 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
743 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
744 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
745 .flags = IRQCHIP_SET_TYPE_MASKED,
746 };
747
748 #define GIC_ID_NR (1U << gic_data.rdists.id_bits)
749
750 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
751 irq_hw_number_t hw)
752 {
753 struct irq_chip *chip = &gic_chip;
754
755 if (static_key_true(&supports_deactivate))
756 chip = &gic_eoimode1_chip;
757
758 /* SGIs are private to the core kernel */
759 if (hw < 16)
760 return -EPERM;
761 /* Nothing here */
762 if (hw >= gic_data.irq_nr && hw < 8192)
763 return -EPERM;
764 /* Off limits */
765 if (hw >= GIC_ID_NR)
766 return -EPERM;
767
768 /* PPIs */
769 if (hw < 32) {
770 irq_set_percpu_devid(irq);
771 irq_domain_set_info(d, irq, hw, chip, d->host_data,
772 handle_percpu_devid_irq, NULL, NULL);
773 irq_set_status_flags(irq, IRQ_NOAUTOEN);
774 }
775 /* SPIs */
776 if (hw >= 32 && hw < gic_data.irq_nr) {
777 irq_domain_set_info(d, irq, hw, chip, d->host_data,
778 handle_fasteoi_irq, NULL, NULL);
779 irq_set_probe(irq);
780 }
781 /* LPIs */
782 if (hw >= 8192 && hw < GIC_ID_NR) {
783 if (!gic_dist_supports_lpis())
784 return -EPERM;
785 irq_domain_set_info(d, irq, hw, chip, d->host_data,
786 handle_fasteoi_irq, NULL, NULL);
787 }
788
789 return 0;
790 }
791
792 static int gic_irq_domain_xlate(struct irq_domain *d,
793 struct device_node *controller,
794 const u32 *intspec, unsigned int intsize,
795 unsigned long *out_hwirq, unsigned int *out_type)
796 {
797 if (d->of_node != controller)
798 return -EINVAL;
799 if (intsize < 3)
800 return -EINVAL;
801
802 switch(intspec[0]) {
803 case 0: /* SPI */
804 *out_hwirq = intspec[1] + 32;
805 break;
806 case 1: /* PPI */
807 *out_hwirq = intspec[1] + 16;
808 break;
809 case GIC_IRQ_TYPE_LPI: /* LPI */
810 *out_hwirq = intspec[1];
811 break;
812 default:
813 return -EINVAL;
814 }
815
816 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
817 return 0;
818 }
819
820 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
821 unsigned int nr_irqs, void *arg)
822 {
823 int i, ret;
824 irq_hw_number_t hwirq;
825 unsigned int type = IRQ_TYPE_NONE;
826 struct of_phandle_args *irq_data = arg;
827
828 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args,
829 irq_data->args_count, &hwirq, &type);
830 if (ret)
831 return ret;
832
833 for (i = 0; i < nr_irqs; i++)
834 gic_irq_domain_map(domain, virq + i, hwirq + i);
835
836 return 0;
837 }
838
839 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
840 unsigned int nr_irqs)
841 {
842 int i;
843
844 for (i = 0; i < nr_irqs; i++) {
845 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
846 irq_set_handler(virq + i, NULL);
847 irq_domain_reset_irq_data(d);
848 }
849 }
850
851 static const struct irq_domain_ops gic_irq_domain_ops = {
852 .xlate = gic_irq_domain_xlate,
853 .alloc = gic_irq_domain_alloc,
854 .free = gic_irq_domain_free,
855 };
856
857 static void gicv3_enable_quirks(void)
858 {
859 if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154))
860 static_branch_enable(&is_cavium_thunderx);
861 }
862
863 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
864 {
865 void __iomem *dist_base;
866 struct redist_region *rdist_regs;
867 u64 redist_stride;
868 u32 nr_redist_regions;
869 u32 typer;
870 u32 reg;
871 int gic_irqs;
872 int err;
873 int i;
874
875 dist_base = of_iomap(node, 0);
876 if (!dist_base) {
877 pr_err("%s: unable to map gic dist registers\n",
878 node->full_name);
879 return -ENXIO;
880 }
881
882 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
883 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
884 pr_err("%s: no distributor detected, giving up\n",
885 node->full_name);
886 err = -ENODEV;
887 goto out_unmap_dist;
888 }
889
890 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
891 nr_redist_regions = 1;
892
893 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL);
894 if (!rdist_regs) {
895 err = -ENOMEM;
896 goto out_unmap_dist;
897 }
898
899 for (i = 0; i < nr_redist_regions; i++) {
900 struct resource res;
901 int ret;
902
903 ret = of_address_to_resource(node, 1 + i, &res);
904 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
905 if (ret || !rdist_regs[i].redist_base) {
906 pr_err("%s: couldn't map region %d\n",
907 node->full_name, i);
908 err = -ENODEV;
909 goto out_unmap_rdist;
910 }
911 rdist_regs[i].phys_base = res.start;
912 }
913
914 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
915 redist_stride = 0;
916
917 if (!is_hyp_mode_available())
918 static_key_slow_dec(&supports_deactivate);
919
920 if (static_key_true(&supports_deactivate))
921 pr_info("GIC: Using split EOI/Deactivate mode\n");
922
923 gic_data.dist_base = dist_base;
924 gic_data.redist_regions = rdist_regs;
925 gic_data.nr_redist_regions = nr_redist_regions;
926 gic_data.redist_stride = redist_stride;
927
928 gicv3_enable_quirks();
929
930 /*
931 * Find out how many interrupts are supported.
932 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
933 */
934 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
935 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer);
936 gic_irqs = GICD_TYPER_IRQS(typer);
937 if (gic_irqs > 1020)
938 gic_irqs = 1020;
939 gic_data.irq_nr = gic_irqs;
940
941 gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops,
942 &gic_data);
943 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
944
945 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
946 err = -ENOMEM;
947 goto out_free;
948 }
949
950 set_handle_irq(gic_handle_irq);
951
952 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
953 its_init(node, &gic_data.rdists, gic_data.domain);
954
955 gic_smp_init();
956 gic_dist_init();
957 gic_cpu_init();
958 gic_cpu_pm_init();
959
960 return 0;
961
962 out_free:
963 if (gic_data.domain)
964 irq_domain_remove(gic_data.domain);
965 free_percpu(gic_data.rdists.rdist);
966 out_unmap_rdist:
967 for (i = 0; i < nr_redist_regions; i++)
968 if (rdist_regs[i].redist_base)
969 iounmap(rdist_regs[i].redist_base);
970 kfree(rdist_regs);
971 out_unmap_dist:
972 iounmap(dist_base);
973 return err;
974 }
975
976 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
Linux kernel - Deliverables
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