2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #define pr_fmt(fmt) "GICv3: " fmt
20 #include <linux/acpi.h>
21 #include <linux/cpu.h>
22 #include <linux/cpu_pm.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/irqdomain.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/percpu.h>
30 #include <linux/slab.h>
32 #include <linux/irqchip.h>
33 #include <linux/irqchip/arm-gic-common.h>
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/irq-partition-percpu.h>
37 #include <asm/cputype.h>
38 #include <asm/exception.h>
39 #include <asm/smp_plat.h>
42 #include "irq-gic-common.h"
44 struct redist_region
{
45 void __iomem
*redist_base
;
46 phys_addr_t phys_base
;
50 struct gic_chip_data
{
51 struct fwnode_handle
*fwnode
;
52 void __iomem
*dist_base
;
53 struct redist_region
*redist_regions
;
55 struct irq_domain
*domain
;
57 u32 nr_redist_regions
;
59 struct partition_desc
*ppi_descs
[16];
62 static struct gic_chip_data gic_data __read_mostly
;
63 static struct static_key supports_deactivate
= STATIC_KEY_INIT_TRUE
;
65 static struct gic_kvm_info gic_v3_kvm_info
;
67 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
68 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
69 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
71 /* Our default, arbitrary priority value. Linux only uses one anyway. */
72 #define DEFAULT_PMR_VALUE 0xf0
74 static inline unsigned int gic_irq(struct irq_data
*d
)
79 static inline int gic_irq_in_rdist(struct irq_data
*d
)
81 return gic_irq(d
) < 32;
84 static inline void __iomem
*gic_dist_base(struct irq_data
*d
)
86 if (gic_irq_in_rdist(d
)) /* SGI+PPI -> SGI_base for this CPU */
87 return gic_data_rdist_sgi_base();
89 if (d
->hwirq
<= 1023) /* SPI -> dist_base */
90 return gic_data
.dist_base
;
95 static void gic_do_wait_for_rwp(void __iomem
*base
)
97 u32 count
= 1000000; /* 1s! */
99 while (readl_relaxed(base
+ GICD_CTLR
) & GICD_CTLR_RWP
) {
102 pr_err_ratelimited("RWP timeout, gone fishing\n");
110 /* Wait for completion of a distributor change */
111 static void gic_dist_wait_for_rwp(void)
113 gic_do_wait_for_rwp(gic_data
.dist_base
);
116 /* Wait for completion of a redistributor change */
117 static void gic_redist_wait_for_rwp(void)
119 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
123 static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx
);
125 static u64 __maybe_unused
gic_read_iar(void)
127 if (static_branch_unlikely(&is_cavium_thunderx
))
128 return gic_read_iar_cavium_thunderx();
130 return gic_read_iar_common();
134 static void gic_enable_redist(bool enable
)
137 u32 count
= 1000000; /* 1s! */
140 rbase
= gic_data_rdist_rd_base();
142 val
= readl_relaxed(rbase
+ GICR_WAKER
);
144 /* Wake up this CPU redistributor */
145 val
&= ~GICR_WAKER_ProcessorSleep
;
147 val
|= GICR_WAKER_ProcessorSleep
;
148 writel_relaxed(val
, rbase
+ GICR_WAKER
);
150 if (!enable
) { /* Check that GICR_WAKER is writeable */
151 val
= readl_relaxed(rbase
+ GICR_WAKER
);
152 if (!(val
& GICR_WAKER_ProcessorSleep
))
153 return; /* No PM support in this redistributor */
157 val
= readl_relaxed(rbase
+ GICR_WAKER
);
158 if (enable
^ (bool)(val
& GICR_WAKER_ChildrenAsleep
))
164 pr_err_ratelimited("redistributor failed to %s...\n",
165 enable
? "wakeup" : "sleep");
169 * Routines to disable, enable, EOI and route interrupts
171 static int gic_peek_irq(struct irq_data
*d
, u32 offset
)
173 u32 mask
= 1 << (gic_irq(d
) % 32);
176 if (gic_irq_in_rdist(d
))
177 base
= gic_data_rdist_sgi_base();
179 base
= gic_data
.dist_base
;
181 return !!(readl_relaxed(base
+ offset
+ (gic_irq(d
) / 32) * 4) & mask
);
184 static void gic_poke_irq(struct irq_data
*d
, u32 offset
)
186 u32 mask
= 1 << (gic_irq(d
) % 32);
187 void (*rwp_wait
)(void);
190 if (gic_irq_in_rdist(d
)) {
191 base
= gic_data_rdist_sgi_base();
192 rwp_wait
= gic_redist_wait_for_rwp
;
194 base
= gic_data
.dist_base
;
195 rwp_wait
= gic_dist_wait_for_rwp
;
198 writel_relaxed(mask
, base
+ offset
+ (gic_irq(d
) / 32) * 4);
202 static void gic_mask_irq(struct irq_data
*d
)
204 gic_poke_irq(d
, GICD_ICENABLER
);
207 static void gic_eoimode1_mask_irq(struct irq_data
*d
)
211 * When masking a forwarded interrupt, make sure it is
212 * deactivated as well.
214 * This ensures that an interrupt that is getting
215 * disabled/masked will not get "stuck", because there is
216 * noone to deactivate it (guest is being terminated).
218 if (irqd_is_forwarded_to_vcpu(d
))
219 gic_poke_irq(d
, GICD_ICACTIVER
);
222 static void gic_unmask_irq(struct irq_data
*d
)
224 gic_poke_irq(d
, GICD_ISENABLER
);
227 static int gic_irq_set_irqchip_state(struct irq_data
*d
,
228 enum irqchip_irq_state which
, bool val
)
232 if (d
->hwirq
>= gic_data
.irq_nr
) /* PPI/SPI only */
236 case IRQCHIP_STATE_PENDING
:
237 reg
= val
? GICD_ISPENDR
: GICD_ICPENDR
;
240 case IRQCHIP_STATE_ACTIVE
:
241 reg
= val
? GICD_ISACTIVER
: GICD_ICACTIVER
;
244 case IRQCHIP_STATE_MASKED
:
245 reg
= val
? GICD_ICENABLER
: GICD_ISENABLER
;
252 gic_poke_irq(d
, reg
);
256 static int gic_irq_get_irqchip_state(struct irq_data
*d
,
257 enum irqchip_irq_state which
, bool *val
)
259 if (d
->hwirq
>= gic_data
.irq_nr
) /* PPI/SPI only */
263 case IRQCHIP_STATE_PENDING
:
264 *val
= gic_peek_irq(d
, GICD_ISPENDR
);
267 case IRQCHIP_STATE_ACTIVE
:
268 *val
= gic_peek_irq(d
, GICD_ISACTIVER
);
271 case IRQCHIP_STATE_MASKED
:
272 *val
= !gic_peek_irq(d
, GICD_ISENABLER
);
282 static void gic_eoi_irq(struct irq_data
*d
)
284 gic_write_eoir(gic_irq(d
));
287 static void gic_eoimode1_eoi_irq(struct irq_data
*d
)
290 * No need to deactivate an LPI, or an interrupt that
291 * is is getting forwarded to a vcpu.
293 if (gic_irq(d
) >= 8192 || irqd_is_forwarded_to_vcpu(d
))
295 gic_write_dir(gic_irq(d
));
298 static int gic_set_type(struct irq_data
*d
, unsigned int type
)
300 unsigned int irq
= gic_irq(d
);
301 void (*rwp_wait
)(void);
304 /* Interrupt configuration for SGIs can't be changed */
308 /* SPIs have restrictions on the supported types */
309 if (irq
>= 32 && type
!= IRQ_TYPE_LEVEL_HIGH
&&
310 type
!= IRQ_TYPE_EDGE_RISING
)
313 if (gic_irq_in_rdist(d
)) {
314 base
= gic_data_rdist_sgi_base();
315 rwp_wait
= gic_redist_wait_for_rwp
;
317 base
= gic_data
.dist_base
;
318 rwp_wait
= gic_dist_wait_for_rwp
;
321 return gic_configure_irq(irq
, type
, base
, rwp_wait
);
324 static int gic_irq_set_vcpu_affinity(struct irq_data
*d
, void *vcpu
)
327 irqd_set_forwarded_to_vcpu(d
);
329 irqd_clr_forwarded_to_vcpu(d
);
333 static u64
gic_mpidr_to_affinity(unsigned long mpidr
)
337 aff
= ((u64
)MPIDR_AFFINITY_LEVEL(mpidr
, 3) << 32 |
338 MPIDR_AFFINITY_LEVEL(mpidr
, 2) << 16 |
339 MPIDR_AFFINITY_LEVEL(mpidr
, 1) << 8 |
340 MPIDR_AFFINITY_LEVEL(mpidr
, 0));
345 static asmlinkage
void __exception_irq_entry
gic_handle_irq(struct pt_regs
*regs
)
350 irqnr
= gic_read_iar();
352 if (likely(irqnr
> 15 && irqnr
< 1020) || irqnr
>= 8192) {
355 if (static_key_true(&supports_deactivate
))
356 gic_write_eoir(irqnr
);
358 err
= handle_domain_irq(gic_data
.domain
, irqnr
, regs
);
360 WARN_ONCE(true, "Unexpected interrupt received!\n");
361 if (static_key_true(&supports_deactivate
)) {
363 gic_write_dir(irqnr
);
365 gic_write_eoir(irqnr
);
371 gic_write_eoir(irqnr
);
372 if (static_key_true(&supports_deactivate
))
373 gic_write_dir(irqnr
);
376 * Unlike GICv2, we don't need an smp_rmb() here.
377 * The control dependency from gic_read_iar to
378 * the ISB in gic_write_eoir is enough to ensure
379 * that any shared data read by handle_IPI will
380 * be read after the ACK.
382 handle_IPI(irqnr
, regs
);
384 WARN_ONCE(true, "Unexpected SGI received!\n");
388 } while (irqnr
!= ICC_IAR1_EL1_SPURIOUS
);
391 static void __init
gic_dist_init(void)
395 void __iomem
*base
= gic_data
.dist_base
;
397 /* Disable the distributor */
398 writel_relaxed(0, base
+ GICD_CTLR
);
399 gic_dist_wait_for_rwp();
402 * Configure SPIs as non-secure Group-1. This will only matter
403 * if the GIC only has a single security state. This will not
404 * do the right thing if the kernel is running in secure mode,
405 * but that's not the intended use case anyway.
407 for (i
= 32; i
< gic_data
.irq_nr
; i
+= 32)
408 writel_relaxed(~0, base
+ GICD_IGROUPR
+ i
/ 8);
410 gic_dist_config(base
, gic_data
.irq_nr
, gic_dist_wait_for_rwp
);
412 /* Enable distributor with ARE, Group1 */
413 writel_relaxed(GICD_CTLR_ARE_NS
| GICD_CTLR_ENABLE_G1A
| GICD_CTLR_ENABLE_G1
,
417 * Set all global interrupts to the boot CPU only. ARE must be
420 affinity
= gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
421 for (i
= 32; i
< gic_data
.irq_nr
; i
++)
422 gic_write_irouter(affinity
, base
+ GICD_IROUTER
+ i
* 8);
425 static int gic_populate_rdist(void)
427 unsigned long mpidr
= cpu_logical_map(smp_processor_id());
433 * Convert affinity to a 32bit value that can be matched to
434 * GICR_TYPER bits [63:32].
436 aff
= (MPIDR_AFFINITY_LEVEL(mpidr
, 3) << 24 |
437 MPIDR_AFFINITY_LEVEL(mpidr
, 2) << 16 |
438 MPIDR_AFFINITY_LEVEL(mpidr
, 1) << 8 |
439 MPIDR_AFFINITY_LEVEL(mpidr
, 0));
441 for (i
= 0; i
< gic_data
.nr_redist_regions
; i
++) {
442 void __iomem
*ptr
= gic_data
.redist_regions
[i
].redist_base
;
445 reg
= readl_relaxed(ptr
+ GICR_PIDR2
) & GIC_PIDR2_ARCH_MASK
;
446 if (reg
!= GIC_PIDR2_ARCH_GICv3
&&
447 reg
!= GIC_PIDR2_ARCH_GICv4
) { /* We're in trouble... */
448 pr_warn("No redistributor present @%p\n", ptr
);
453 typer
= gic_read_typer(ptr
+ GICR_TYPER
);
454 if ((typer
>> 32) == aff
) {
455 u64 offset
= ptr
- gic_data
.redist_regions
[i
].redist_base
;
456 gic_data_rdist_rd_base() = ptr
;
457 gic_data_rdist()->phys_base
= gic_data
.redist_regions
[i
].phys_base
+ offset
;
458 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
459 smp_processor_id(), mpidr
, i
,
460 &gic_data_rdist()->phys_base
);
464 if (gic_data
.redist_regions
[i
].single_redist
)
467 if (gic_data
.redist_stride
) {
468 ptr
+= gic_data
.redist_stride
;
470 ptr
+= SZ_64K
* 2; /* Skip RD_base + SGI_base */
471 if (typer
& GICR_TYPER_VLPIS
)
472 ptr
+= SZ_64K
* 2; /* Skip VLPI_base + reserved page */
474 } while (!(typer
& GICR_TYPER_LAST
));
477 /* We couldn't even deal with ourselves... */
478 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
479 smp_processor_id(), mpidr
);
483 static void gic_cpu_sys_reg_init(void)
486 * Need to check that the SRE bit has actually been set. If
487 * not, it means that SRE is disabled at EL2. We're going to
488 * die painfully, and there is nothing we can do about it.
490 * Kindly inform the luser.
492 if (!gic_enable_sre())
493 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
495 /* Set priority mask register */
496 gic_write_pmr(DEFAULT_PMR_VALUE
);
498 if (static_key_true(&supports_deactivate
)) {
499 /* EOI drops priority only (mode 1) */
500 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop
);
502 /* EOI deactivates interrupt too (mode 0) */
503 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir
);
506 /* ... and let's hit the road... */
510 static int gic_dist_supports_lpis(void)
512 return !!(readl_relaxed(gic_data
.dist_base
+ GICD_TYPER
) & GICD_TYPER_LPIS
);
515 static void gic_cpu_init(void)
519 /* Register ourselves with the rest of the world */
520 if (gic_populate_rdist())
523 gic_enable_redist(true);
525 rbase
= gic_data_rdist_sgi_base();
527 /* Configure SGIs/PPIs as non-secure Group-1 */
528 writel_relaxed(~0, rbase
+ GICR_IGROUPR0
);
530 gic_cpu_config(rbase
, gic_redist_wait_for_rwp
);
532 /* Give LPIs a spin */
533 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS
) && gic_dist_supports_lpis())
536 /* initialise system registers */
537 gic_cpu_sys_reg_init();
541 static int gic_secondary_init(struct notifier_block
*nfb
,
542 unsigned long action
, void *hcpu
)
544 if (action
== CPU_STARTING
|| action
== CPU_STARTING_FROZEN
)
550 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
551 * priority because the GIC needs to be up before the ARM generic timers.
553 static struct notifier_block gic_cpu_notifier
= {
554 .notifier_call
= gic_secondary_init
,
558 static u16
gic_compute_target_list(int *base_cpu
, const struct cpumask
*mask
,
559 unsigned long cluster_id
)
562 unsigned long mpidr
= cpu_logical_map(cpu
);
565 while (cpu
< nr_cpu_ids
) {
567 * If we ever get a cluster of more than 16 CPUs, just
568 * scream and skip that CPU.
570 if (WARN_ON((mpidr
& 0xff) >= 16))
573 tlist
|= 1 << (mpidr
& 0xf);
575 cpu
= cpumask_next(cpu
, mask
);
576 if (cpu
>= nr_cpu_ids
)
579 mpidr
= cpu_logical_map(cpu
);
581 if (cluster_id
!= (mpidr
& ~0xffUL
)) {
591 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
592 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
593 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
595 static void gic_send_sgi(u64 cluster_id
, u16 tlist
, unsigned int irq
)
599 val
= (MPIDR_TO_SGI_AFFINITY(cluster_id
, 3) |
600 MPIDR_TO_SGI_AFFINITY(cluster_id
, 2) |
601 irq
<< ICC_SGI1R_SGI_ID_SHIFT
|
602 MPIDR_TO_SGI_AFFINITY(cluster_id
, 1) |
603 tlist
<< ICC_SGI1R_TARGET_LIST_SHIFT
);
605 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val
);
606 gic_write_sgi1r(val
);
609 static void gic_raise_softirq(const struct cpumask
*mask
, unsigned int irq
)
613 if (WARN_ON(irq
>= 16))
617 * Ensure that stores to Normal memory are visible to the
618 * other CPUs before issuing the IPI.
622 for_each_cpu(cpu
, mask
) {
623 unsigned long cluster_id
= cpu_logical_map(cpu
) & ~0xffUL
;
626 tlist
= gic_compute_target_list(&cpu
, mask
, cluster_id
);
627 gic_send_sgi(cluster_id
, tlist
, irq
);
630 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
634 static void gic_smp_init(void)
636 set_smp_cross_call(gic_raise_softirq
);
637 register_cpu_notifier(&gic_cpu_notifier
);
640 static int gic_set_affinity(struct irq_data
*d
, const struct cpumask
*mask_val
,
643 unsigned int cpu
= cpumask_any_and(mask_val
, cpu_online_mask
);
648 if (gic_irq_in_rdist(d
))
651 /* If interrupt was enabled, disable it first */
652 enabled
= gic_peek_irq(d
, GICD_ISENABLER
);
656 reg
= gic_dist_base(d
) + GICD_IROUTER
+ (gic_irq(d
) * 8);
657 val
= gic_mpidr_to_affinity(cpu_logical_map(cpu
));
659 gic_write_irouter(val
, reg
);
662 * If the interrupt was enabled, enabled it again. Otherwise,
663 * just wait for the distributor to have digested our changes.
668 gic_dist_wait_for_rwp();
670 return IRQ_SET_MASK_OK_DONE
;
673 #define gic_set_affinity NULL
674 #define gic_smp_init() do { } while(0)
678 static int gic_cpu_pm_notifier(struct notifier_block
*self
,
679 unsigned long cmd
, void *v
)
681 if (cmd
== CPU_PM_EXIT
) {
682 gic_enable_redist(true);
683 gic_cpu_sys_reg_init();
684 } else if (cmd
== CPU_PM_ENTER
) {
686 gic_enable_redist(false);
691 static struct notifier_block gic_cpu_pm_notifier_block
= {
692 .notifier_call
= gic_cpu_pm_notifier
,
695 static void gic_cpu_pm_init(void)
697 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block
);
701 static inline void gic_cpu_pm_init(void) { }
702 #endif /* CONFIG_CPU_PM */
704 static struct irq_chip gic_chip
= {
706 .irq_mask
= gic_mask_irq
,
707 .irq_unmask
= gic_unmask_irq
,
708 .irq_eoi
= gic_eoi_irq
,
709 .irq_set_type
= gic_set_type
,
710 .irq_set_affinity
= gic_set_affinity
,
711 .irq_get_irqchip_state
= gic_irq_get_irqchip_state
,
712 .irq_set_irqchip_state
= gic_irq_set_irqchip_state
,
713 .flags
= IRQCHIP_SET_TYPE_MASKED
,
716 static struct irq_chip gic_eoimode1_chip
= {
718 .irq_mask
= gic_eoimode1_mask_irq
,
719 .irq_unmask
= gic_unmask_irq
,
720 .irq_eoi
= gic_eoimode1_eoi_irq
,
721 .irq_set_type
= gic_set_type
,
722 .irq_set_affinity
= gic_set_affinity
,
723 .irq_get_irqchip_state
= gic_irq_get_irqchip_state
,
724 .irq_set_irqchip_state
= gic_irq_set_irqchip_state
,
725 .irq_set_vcpu_affinity
= gic_irq_set_vcpu_affinity
,
726 .flags
= IRQCHIP_SET_TYPE_MASKED
,
729 #define GIC_ID_NR (1U << gic_data.rdists.id_bits)
731 static int gic_irq_domain_map(struct irq_domain
*d
, unsigned int irq
,
734 struct irq_chip
*chip
= &gic_chip
;
736 if (static_key_true(&supports_deactivate
))
737 chip
= &gic_eoimode1_chip
;
739 /* SGIs are private to the core kernel */
743 if (hw
>= gic_data
.irq_nr
&& hw
< 8192)
751 irq_set_percpu_devid(irq
);
752 irq_domain_set_info(d
, irq
, hw
, chip
, d
->host_data
,
753 handle_percpu_devid_irq
, NULL
, NULL
);
754 irq_set_status_flags(irq
, IRQ_NOAUTOEN
);
757 if (hw
>= 32 && hw
< gic_data
.irq_nr
) {
758 irq_domain_set_info(d
, irq
, hw
, chip
, d
->host_data
,
759 handle_fasteoi_irq
, NULL
, NULL
);
763 if (hw
>= 8192 && hw
< GIC_ID_NR
) {
764 if (!gic_dist_supports_lpis())
766 irq_domain_set_info(d
, irq
, hw
, chip
, d
->host_data
,
767 handle_fasteoi_irq
, NULL
, NULL
);
773 static int gic_irq_domain_translate(struct irq_domain
*d
,
774 struct irq_fwspec
*fwspec
,
775 unsigned long *hwirq
,
778 if (is_of_node(fwspec
->fwnode
)) {
779 if (fwspec
->param_count
< 3)
782 switch (fwspec
->param
[0]) {
784 *hwirq
= fwspec
->param
[1] + 32;
787 *hwirq
= fwspec
->param
[1] + 16;
789 case GIC_IRQ_TYPE_LPI
: /* LPI */
790 *hwirq
= fwspec
->param
[1];
796 *type
= fwspec
->param
[2] & IRQ_TYPE_SENSE_MASK
;
800 if (is_fwnode_irqchip(fwspec
->fwnode
)) {
801 if(fwspec
->param_count
!= 2)
804 *hwirq
= fwspec
->param
[0];
805 *type
= fwspec
->param
[1];
812 static int gic_irq_domain_alloc(struct irq_domain
*domain
, unsigned int virq
,
813 unsigned int nr_irqs
, void *arg
)
816 irq_hw_number_t hwirq
;
817 unsigned int type
= IRQ_TYPE_NONE
;
818 struct irq_fwspec
*fwspec
= arg
;
820 ret
= gic_irq_domain_translate(domain
, fwspec
, &hwirq
, &type
);
824 for (i
= 0; i
< nr_irqs
; i
++)
825 gic_irq_domain_map(domain
, virq
+ i
, hwirq
+ i
);
830 static void gic_irq_domain_free(struct irq_domain
*domain
, unsigned int virq
,
831 unsigned int nr_irqs
)
835 for (i
= 0; i
< nr_irqs
; i
++) {
836 struct irq_data
*d
= irq_domain_get_irq_data(domain
, virq
+ i
);
837 irq_set_handler(virq
+ i
, NULL
);
838 irq_domain_reset_irq_data(d
);
842 static int gic_irq_domain_select(struct irq_domain
*d
,
843 struct irq_fwspec
*fwspec
,
844 enum irq_domain_bus_token bus_token
)
847 if (fwspec
->fwnode
!= d
->fwnode
)
850 /* If this is not DT, then we have a single domain */
851 if (!is_of_node(fwspec
->fwnode
))
855 * If this is a PPI and we have a 4th (non-null) parameter,
856 * then we need to match the partition domain.
858 if (fwspec
->param_count
>= 4 &&
859 fwspec
->param
[0] == 1 && fwspec
->param
[3] != 0)
860 return d
== partition_get_domain(gic_data
.ppi_descs
[fwspec
->param
[1]]);
862 return d
== gic_data
.domain
;
865 static const struct irq_domain_ops gic_irq_domain_ops
= {
866 .translate
= gic_irq_domain_translate
,
867 .alloc
= gic_irq_domain_alloc
,
868 .free
= gic_irq_domain_free
,
869 .select
= gic_irq_domain_select
,
872 static int partition_domain_translate(struct irq_domain
*d
,
873 struct irq_fwspec
*fwspec
,
874 unsigned long *hwirq
,
877 struct device_node
*np
;
880 np
= of_find_node_by_phandle(fwspec
->param
[3]);
884 ret
= partition_translate_id(gic_data
.ppi_descs
[fwspec
->param
[1]],
885 of_node_to_fwnode(np
));
890 *type
= fwspec
->param
[2] & IRQ_TYPE_SENSE_MASK
;
895 static const struct irq_domain_ops partition_domain_ops
= {
896 .translate
= partition_domain_translate
,
897 .select
= gic_irq_domain_select
,
900 static void gicv3_enable_quirks(void)
903 if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154
))
904 static_branch_enable(&is_cavium_thunderx
);
908 static int __init
gic_init_bases(void __iomem
*dist_base
,
909 struct redist_region
*rdist_regs
,
910 u32 nr_redist_regions
,
912 struct fwnode_handle
*handle
)
914 struct device_node
*node
;
919 if (!is_hyp_mode_available())
920 static_key_slow_dec(&supports_deactivate
);
922 if (static_key_true(&supports_deactivate
))
923 pr_info("GIC: Using split EOI/Deactivate mode\n");
925 gic_data
.fwnode
= handle
;
926 gic_data
.dist_base
= dist_base
;
927 gic_data
.redist_regions
= rdist_regs
;
928 gic_data
.nr_redist_regions
= nr_redist_regions
;
929 gic_data
.redist_stride
= redist_stride
;
931 gicv3_enable_quirks();
934 * Find out how many interrupts are supported.
935 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
937 typer
= readl_relaxed(gic_data
.dist_base
+ GICD_TYPER
);
938 gic_data
.rdists
.id_bits
= GICD_TYPER_ID_BITS(typer
);
939 gic_irqs
= GICD_TYPER_IRQS(typer
);
942 gic_data
.irq_nr
= gic_irqs
;
944 gic_data
.domain
= irq_domain_create_tree(handle
, &gic_irq_domain_ops
,
946 gic_data
.rdists
.rdist
= alloc_percpu(typeof(*gic_data
.rdists
.rdist
));
948 if (WARN_ON(!gic_data
.domain
) || WARN_ON(!gic_data
.rdists
.rdist
)) {
953 set_handle_irq(gic_handle_irq
);
955 node
= to_of_node(handle
);
956 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS
) && gic_dist_supports_lpis() &&
957 node
) /* Temp hack to prevent ITS init for ACPI */
958 its_init(node
, &gic_data
.rdists
, gic_data
.domain
);
969 irq_domain_remove(gic_data
.domain
);
970 free_percpu(gic_data
.rdists
.rdist
);
974 static int __init
gic_validate_dist_version(void __iomem
*dist_base
)
976 u32 reg
= readl_relaxed(dist_base
+ GICD_PIDR2
) & GIC_PIDR2_ARCH_MASK
;
978 if (reg
!= GIC_PIDR2_ARCH_GICv3
&& reg
!= GIC_PIDR2_ARCH_GICv4
)
984 static int get_cpu_number(struct device_node
*dn
)
990 cell
= of_get_property(dn
, "reg", NULL
);
994 hwid
= of_read_number(cell
, of_n_addr_cells(dn
));
997 * Non affinity bits must be set to 0 in the DT
999 if (hwid
& ~MPIDR_HWID_BITMASK
)
1002 for (i
= 0; i
< num_possible_cpus(); i
++)
1003 if (cpu_logical_map(i
) == hwid
)
1009 /* Create all possible partitions at boot time */
1010 static void __init
gic_populate_ppi_partitions(struct device_node
*gic_node
)
1012 struct device_node
*parts_node
, *child_part
;
1013 int part_idx
= 0, i
;
1015 struct partition_affinity
*parts
;
1017 parts_node
= of_find_node_by_name(gic_node
, "ppi-partitions");
1021 nr_parts
= of_get_child_count(parts_node
);
1026 parts
= kzalloc(sizeof(*parts
) * nr_parts
, GFP_KERNEL
);
1027 if (WARN_ON(!parts
))
1030 for_each_child_of_node(parts_node
, child_part
) {
1031 struct partition_affinity
*part
;
1034 part
= &parts
[part_idx
];
1036 part
->partition_id
= of_node_to_fwnode(child_part
);
1038 pr_info("GIC: PPI partition %s[%d] { ",
1039 child_part
->name
, part_idx
);
1041 n
= of_property_count_elems_of_size(child_part
, "affinity",
1045 for (i
= 0; i
< n
; i
++) {
1048 struct device_node
*cpu_node
;
1050 err
= of_property_read_u32_index(child_part
, "affinity",
1055 cpu_node
= of_find_node_by_phandle(cpu_phandle
);
1056 if (WARN_ON(!cpu_node
))
1059 cpu
= get_cpu_number(cpu_node
);
1060 if (WARN_ON(cpu
== -1))
1063 pr_cont("%s[%d] ", cpu_node
->full_name
, cpu
);
1065 cpumask_set_cpu(cpu
, &part
->mask
);
1072 for (i
= 0; i
< 16; i
++) {
1074 struct partition_desc
*desc
;
1075 struct irq_fwspec ppi_fwspec
= {
1076 .fwnode
= gic_data
.fwnode
,
1081 [2] = IRQ_TYPE_NONE
,
1085 irq
= irq_create_fwspec_mapping(&ppi_fwspec
);
1088 desc
= partition_create_desc(gic_data
.fwnode
, parts
, nr_parts
,
1089 irq
, &partition_domain_ops
);
1093 gic_data
.ppi_descs
[i
] = desc
;
1097 static void __init
gic_of_setup_kvm_info(struct device_node
*node
)
1103 gic_v3_kvm_info
.type
= GIC_V3
;
1105 gic_v3_kvm_info
.maint_irq
= irq_of_parse_and_map(node
, 0);
1106 if (!gic_v3_kvm_info
.maint_irq
)
1109 if (of_property_read_u32(node
, "#redistributor-regions",
1113 gicv_idx
+= 3; /* Also skip GICD, GICC, GICH */
1114 ret
= of_address_to_resource(node
, gicv_idx
, &r
);
1116 gic_v3_kvm_info
.vcpu
= r
;
1118 gic_set_kvm_info(&gic_v3_kvm_info
);
1121 static int __init
gic_of_init(struct device_node
*node
, struct device_node
*parent
)
1123 void __iomem
*dist_base
;
1124 struct redist_region
*rdist_regs
;
1126 u32 nr_redist_regions
;
1129 dist_base
= of_iomap(node
, 0);
1131 pr_err("%s: unable to map gic dist registers\n",
1136 err
= gic_validate_dist_version(dist_base
);
1138 pr_err("%s: no distributor detected, giving up\n",
1140 goto out_unmap_dist
;
1143 if (of_property_read_u32(node
, "#redistributor-regions", &nr_redist_regions
))
1144 nr_redist_regions
= 1;
1146 rdist_regs
= kzalloc(sizeof(*rdist_regs
) * nr_redist_regions
, GFP_KERNEL
);
1149 goto out_unmap_dist
;
1152 for (i
= 0; i
< nr_redist_regions
; i
++) {
1153 struct resource res
;
1156 ret
= of_address_to_resource(node
, 1 + i
, &res
);
1157 rdist_regs
[i
].redist_base
= of_iomap(node
, 1 + i
);
1158 if (ret
|| !rdist_regs
[i
].redist_base
) {
1159 pr_err("%s: couldn't map region %d\n",
1160 node
->full_name
, i
);
1162 goto out_unmap_rdist
;
1164 rdist_regs
[i
].phys_base
= res
.start
;
1167 if (of_property_read_u64(node
, "redistributor-stride", &redist_stride
))
1170 err
= gic_init_bases(dist_base
, rdist_regs
, nr_redist_regions
,
1171 redist_stride
, &node
->fwnode
);
1173 goto out_unmap_rdist
;
1175 gic_populate_ppi_partitions(node
);
1176 gic_of_setup_kvm_info(node
);
1180 for (i
= 0; i
< nr_redist_regions
; i
++)
1181 if (rdist_regs
[i
].redist_base
)
1182 iounmap(rdist_regs
[i
].redist_base
);
1189 IRQCHIP_DECLARE(gic_v3
, "arm,gic-v3", gic_of_init
);
1194 void __iomem
*dist_base
;
1195 struct redist_region
*redist_regs
;
1196 u32 nr_redist_regions
;
1200 phys_addr_t vcpu_base
;
1201 } acpi_data __initdata
;
1204 gic_acpi_register_redist(phys_addr_t phys_base
, void __iomem
*redist_base
)
1206 static int count
= 0;
1208 acpi_data
.redist_regs
[count
].phys_base
= phys_base
;
1209 acpi_data
.redist_regs
[count
].redist_base
= redist_base
;
1210 acpi_data
.redist_regs
[count
].single_redist
= acpi_data
.single_redist
;
1215 gic_acpi_parse_madt_redist(struct acpi_subtable_header
*header
,
1216 const unsigned long end
)
1218 struct acpi_madt_generic_redistributor
*redist
=
1219 (struct acpi_madt_generic_redistributor
*)header
;
1220 void __iomem
*redist_base
;
1222 redist_base
= ioremap(redist
->base_address
, redist
->length
);
1224 pr_err("Couldn't map GICR region @%llx\n", redist
->base_address
);
1228 gic_acpi_register_redist(redist
->base_address
, redist_base
);
1233 gic_acpi_parse_madt_gicc(struct acpi_subtable_header
*header
,
1234 const unsigned long end
)
1236 struct acpi_madt_generic_interrupt
*gicc
=
1237 (struct acpi_madt_generic_interrupt
*)header
;
1238 u32 reg
= readl_relaxed(acpi_data
.dist_base
+ GICD_PIDR2
) & GIC_PIDR2_ARCH_MASK
;
1239 u32 size
= reg
== GIC_PIDR2_ARCH_GICv4
? SZ_64K
* 4 : SZ_64K
* 2;
1240 void __iomem
*redist_base
;
1242 redist_base
= ioremap(gicc
->gicr_base_address
, size
);
1246 gic_acpi_register_redist(gicc
->gicr_base_address
, redist_base
);
1250 static int __init
gic_acpi_collect_gicr_base(void)
1252 acpi_tbl_entry_handler redist_parser
;
1253 enum acpi_madt_type type
;
1255 if (acpi_data
.single_redist
) {
1256 type
= ACPI_MADT_TYPE_GENERIC_INTERRUPT
;
1257 redist_parser
= gic_acpi_parse_madt_gicc
;
1259 type
= ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR
;
1260 redist_parser
= gic_acpi_parse_madt_redist
;
1263 /* Collect redistributor base addresses in GICR entries */
1264 if (acpi_table_parse_madt(type
, redist_parser
, 0) > 0)
1267 pr_info("No valid GICR entries exist\n");
1271 static int __init
gic_acpi_match_gicr(struct acpi_subtable_header
*header
,
1272 const unsigned long end
)
1274 /* Subtable presence means that redist exists, that's it */
1278 static int __init
gic_acpi_match_gicc(struct acpi_subtable_header
*header
,
1279 const unsigned long end
)
1281 struct acpi_madt_generic_interrupt
*gicc
=
1282 (struct acpi_madt_generic_interrupt
*)header
;
1285 * If GICC is enabled and has valid gicr base address, then it means
1286 * GICR base is presented via GICC
1288 if ((gicc
->flags
& ACPI_MADT_ENABLED
) && gicc
->gicr_base_address
)
1294 static int __init
gic_acpi_count_gicr_regions(void)
1299 * Count how many redistributor regions we have. It is not allowed
1300 * to mix redistributor description, GICR and GICC subtables have to be
1301 * mutually exclusive.
1303 count
= acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR
,
1304 gic_acpi_match_gicr
, 0);
1306 acpi_data
.single_redist
= false;
1310 count
= acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT
,
1311 gic_acpi_match_gicc
, 0);
1313 acpi_data
.single_redist
= true;
1318 static bool __init
acpi_validate_gic_table(struct acpi_subtable_header
*header
,
1319 struct acpi_probe_entry
*ape
)
1321 struct acpi_madt_generic_distributor
*dist
;
1324 dist
= (struct acpi_madt_generic_distributor
*)header
;
1325 if (dist
->version
!= ape
->driver_data
)
1328 /* We need to do that exercise anyway, the sooner the better */
1329 count
= gic_acpi_count_gicr_regions();
1333 acpi_data
.nr_redist_regions
= count
;
1337 static int __init
gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header
*header
,
1338 const unsigned long end
)
1340 struct acpi_madt_generic_interrupt
*gicc
=
1341 (struct acpi_madt_generic_interrupt
*)header
;
1343 static int first_madt
= true;
1345 /* Skip unusable CPUs */
1346 if (!(gicc
->flags
& ACPI_MADT_ENABLED
))
1349 maint_irq_mode
= (gicc
->flags
& ACPI_MADT_VGIC_IRQ_MODE
) ?
1350 ACPI_EDGE_SENSITIVE
: ACPI_LEVEL_SENSITIVE
;
1355 acpi_data
.maint_irq
= gicc
->vgic_interrupt
;
1356 acpi_data
.maint_irq_mode
= maint_irq_mode
;
1357 acpi_data
.vcpu_base
= gicc
->gicv_base_address
;
1363 * The maintenance interrupt and GICV should be the same for every CPU
1365 if ((acpi_data
.maint_irq
!= gicc
->vgic_interrupt
) ||
1366 (acpi_data
.maint_irq_mode
!= maint_irq_mode
) ||
1367 (acpi_data
.vcpu_base
!= gicc
->gicv_base_address
))
1373 static bool __init
gic_acpi_collect_virt_info(void)
1377 count
= acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT
,
1378 gic_acpi_parse_virt_madt_gicc
, 0);
1383 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
1384 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1385 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1387 static void __init
gic_acpi_setup_kvm_info(void)
1391 if (!gic_acpi_collect_virt_info()) {
1392 pr_warn("Unable to get hardware information used for virtualization\n");
1396 gic_v3_kvm_info
.type
= GIC_V3
;
1398 irq
= acpi_register_gsi(NULL
, acpi_data
.maint_irq
,
1399 acpi_data
.maint_irq_mode
,
1404 gic_v3_kvm_info
.maint_irq
= irq
;
1406 if (acpi_data
.vcpu_base
) {
1407 struct resource
*vcpu
= &gic_v3_kvm_info
.vcpu
;
1409 vcpu
->flags
= IORESOURCE_MEM
;
1410 vcpu
->start
= acpi_data
.vcpu_base
;
1411 vcpu
->end
= vcpu
->start
+ ACPI_GICV2_VCPU_MEM_SIZE
- 1;
1414 gic_set_kvm_info(&gic_v3_kvm_info
);
1418 gic_acpi_init(struct acpi_subtable_header
*header
, const unsigned long end
)
1420 struct acpi_madt_generic_distributor
*dist
;
1421 struct fwnode_handle
*domain_handle
;
1425 /* Get distributor base address */
1426 dist
= (struct acpi_madt_generic_distributor
*)header
;
1427 acpi_data
.dist_base
= ioremap(dist
->base_address
,
1428 ACPI_GICV3_DIST_MEM_SIZE
);
1429 if (!acpi_data
.dist_base
) {
1430 pr_err("Unable to map GICD registers\n");
1434 err
= gic_validate_dist_version(acpi_data
.dist_base
);
1436 pr_err("No distributor detected at @%p, giving up",
1437 acpi_data
.dist_base
);
1438 goto out_dist_unmap
;
1441 size
= sizeof(*acpi_data
.redist_regs
) * acpi_data
.nr_redist_regions
;
1442 acpi_data
.redist_regs
= kzalloc(size
, GFP_KERNEL
);
1443 if (!acpi_data
.redist_regs
) {
1445 goto out_dist_unmap
;
1448 err
= gic_acpi_collect_gicr_base();
1450 goto out_redist_unmap
;
1452 domain_handle
= irq_domain_alloc_fwnode(acpi_data
.dist_base
);
1453 if (!domain_handle
) {
1455 goto out_redist_unmap
;
1458 err
= gic_init_bases(acpi_data
.dist_base
, acpi_data
.redist_regs
,
1459 acpi_data
.nr_redist_regions
, 0, domain_handle
);
1461 goto out_fwhandle_free
;
1463 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC
, domain_handle
);
1464 gic_acpi_setup_kvm_info();
1469 irq_domain_free_fwnode(domain_handle
);
1471 for (i
= 0; i
< acpi_data
.nr_redist_regions
; i
++)
1472 if (acpi_data
.redist_regs
[i
].redist_base
)
1473 iounmap(acpi_data
.redist_regs
[i
].redist_base
);
1474 kfree(acpi_data
.redist_regs
);
1476 iounmap(acpi_data
.dist_base
);
1479 IRQCHIP_ACPI_DECLARE(gic_v3
, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR
,
1480 acpi_validate_gic_table
, ACPI_MADT_GIC_VERSION_V3
,
1482 IRQCHIP_ACPI_DECLARE(gic_v4
, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR
,
1483 acpi_validate_gic_table
, ACPI_MADT_GIC_VERSION_V4
,
1485 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4
, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR
,
1486 acpi_validate_gic_table
, ACPI_MADT_GIC_VERSION_NONE
,