2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Interrupt architecture for the GIC:
10 * o There is one Interrupt Distributor, which receives interrupts
11 * from system devices and sends them to the Interrupt Controllers.
13 * o There is one CPU Interface per CPU, which sends interrupts sent
14 * by the Distributor, and interrupts generated locally, to the
15 * associated CPU. The base address of the CPU interface is usually
16 * aliased so that the same address points to different chips depending
17 * on the CPU it is accessed from.
19 * Note that IRQs 0-31 are special - they are local to each CPU.
20 * As such, the enable set/clear, pending set/clear and active bit
21 * registers are banked per-cpu for these sources.
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/err.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/smp.h>
29 #include <linux/cpu.h>
30 #include <linux/cpu_pm.h>
31 #include <linux/cpumask.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36 #include <linux/acpi.h>
37 #include <linux/irqdomain.h>
38 #include <linux/interrupt.h>
39 #include <linux/percpu.h>
40 #include <linux/slab.h>
41 #include <linux/irqchip.h>
42 #include <linux/irqchip/chained_irq.h>
43 #include <linux/irqchip/arm-gic.h>
44 #include <linux/irqchip/arm-gic-acpi.h>
46 #include <asm/cputype.h>
48 #include <asm/exception.h>
49 #include <asm/smp_plat.h>
51 #include "irq-gic-common.h"
54 void __iomem
*common_base
;
55 void __percpu
* __iomem
*percpu_base
;
58 struct gic_chip_data
{
59 union gic_base dist_base
;
60 union gic_base cpu_base
;
62 u32 saved_spi_enable
[DIV_ROUND_UP(1020, 32)];
63 u32 saved_spi_conf
[DIV_ROUND_UP(1020, 16)];
64 u32 saved_spi_target
[DIV_ROUND_UP(1020, 4)];
65 u32 __percpu
*saved_ppi_enable
;
66 u32 __percpu
*saved_ppi_conf
;
68 struct irq_domain
*domain
;
69 unsigned int gic_irqs
;
70 #ifdef CONFIG_GIC_NON_BANKED
71 void __iomem
*(*get_base
)(union gic_base
*);
75 static DEFINE_RAW_SPINLOCK(irq_controller_lock
);
78 * The GIC mapping of CPU interfaces does not necessarily match
79 * the logical CPU numbering. Let's use a mapping as returned
82 #define NR_GIC_CPU_IF 8
83 static u8 gic_cpu_map
[NR_GIC_CPU_IF
] __read_mostly
;
89 static struct gic_chip_data gic_data
[MAX_GIC_NR
] __read_mostly
;
91 #ifdef CONFIG_GIC_NON_BANKED
92 static void __iomem
*gic_get_percpu_base(union gic_base
*base
)
94 return raw_cpu_read(*base
->percpu_base
);
97 static void __iomem
*gic_get_common_base(union gic_base
*base
)
99 return base
->common_base
;
102 static inline void __iomem
*gic_data_dist_base(struct gic_chip_data
*data
)
104 return data
->get_base(&data
->dist_base
);
107 static inline void __iomem
*gic_data_cpu_base(struct gic_chip_data
*data
)
109 return data
->get_base(&data
->cpu_base
);
112 static inline void gic_set_base_accessor(struct gic_chip_data
*data
,
113 void __iomem
*(*f
)(union gic_base
*))
118 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
119 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
120 #define gic_set_base_accessor(d, f)
123 static inline void __iomem
*gic_dist_base(struct irq_data
*d
)
125 struct gic_chip_data
*gic_data
= irq_data_get_irq_chip_data(d
);
126 return gic_data_dist_base(gic_data
);
129 static inline void __iomem
*gic_cpu_base(struct irq_data
*d
)
131 struct gic_chip_data
*gic_data
= irq_data_get_irq_chip_data(d
);
132 return gic_data_cpu_base(gic_data
);
135 static inline unsigned int gic_irq(struct irq_data
*d
)
141 * Routines to acknowledge, disable and enable interrupts
143 static void gic_poke_irq(struct irq_data
*d
, u32 offset
)
145 u32 mask
= 1 << (gic_irq(d
) % 32);
146 writel_relaxed(mask
, gic_dist_base(d
) + offset
+ (gic_irq(d
) / 32) * 4);
149 static int gic_peek_irq(struct irq_data
*d
, u32 offset
)
151 u32 mask
= 1 << (gic_irq(d
) % 32);
152 return !!(readl_relaxed(gic_dist_base(d
) + offset
+ (gic_irq(d
) / 32) * 4) & mask
);
155 static void gic_mask_irq(struct irq_data
*d
)
157 gic_poke_irq(d
, GIC_DIST_ENABLE_CLEAR
);
160 static void gic_unmask_irq(struct irq_data
*d
)
162 gic_poke_irq(d
, GIC_DIST_ENABLE_SET
);
165 static void gic_eoi_irq(struct irq_data
*d
)
167 writel_relaxed(gic_irq(d
), gic_cpu_base(d
) + GIC_CPU_EOI
);
170 static int gic_irq_set_irqchip_state(struct irq_data
*d
,
171 enum irqchip_irq_state which
, bool val
)
176 case IRQCHIP_STATE_PENDING
:
177 reg
= val
? GIC_DIST_PENDING_SET
: GIC_DIST_PENDING_CLEAR
;
180 case IRQCHIP_STATE_ACTIVE
:
181 reg
= val
? GIC_DIST_ACTIVE_SET
: GIC_DIST_ACTIVE_CLEAR
;
184 case IRQCHIP_STATE_MASKED
:
185 reg
= val
? GIC_DIST_ENABLE_CLEAR
: GIC_DIST_ENABLE_SET
;
192 gic_poke_irq(d
, reg
);
196 static int gic_irq_get_irqchip_state(struct irq_data
*d
,
197 enum irqchip_irq_state which
, bool *val
)
200 case IRQCHIP_STATE_PENDING
:
201 *val
= gic_peek_irq(d
, GIC_DIST_PENDING_SET
);
204 case IRQCHIP_STATE_ACTIVE
:
205 *val
= gic_peek_irq(d
, GIC_DIST_ACTIVE_SET
);
208 case IRQCHIP_STATE_MASKED
:
209 *val
= !gic_peek_irq(d
, GIC_DIST_ENABLE_SET
);
219 static int gic_set_type(struct irq_data
*d
, unsigned int type
)
221 void __iomem
*base
= gic_dist_base(d
);
222 unsigned int gicirq
= gic_irq(d
);
224 /* Interrupt configuration for SGIs can't be changed */
228 /* SPIs have restrictions on the supported types */
229 if (gicirq
>= 32 && type
!= IRQ_TYPE_LEVEL_HIGH
&&
230 type
!= IRQ_TYPE_EDGE_RISING
)
233 return gic_configure_irq(gicirq
, type
, base
, NULL
);
237 static int gic_set_affinity(struct irq_data
*d
, const struct cpumask
*mask_val
,
240 void __iomem
*reg
= gic_dist_base(d
) + GIC_DIST_TARGET
+ (gic_irq(d
) & ~3);
241 unsigned int cpu
, shift
= (gic_irq(d
) % 4) * 8;
246 cpu
= cpumask_any_and(mask_val
, cpu_online_mask
);
248 cpu
= cpumask_first(mask_val
);
250 if (cpu
>= NR_GIC_CPU_IF
|| cpu
>= nr_cpu_ids
)
253 raw_spin_lock_irqsave(&irq_controller_lock
, flags
);
254 mask
= 0xff << shift
;
255 bit
= gic_cpu_map
[cpu
] << shift
;
256 val
= readl_relaxed(reg
) & ~mask
;
257 writel_relaxed(val
| bit
, reg
);
258 raw_spin_unlock_irqrestore(&irq_controller_lock
, flags
);
260 return IRQ_SET_MASK_OK
;
264 static void __exception_irq_entry
gic_handle_irq(struct pt_regs
*regs
)
267 struct gic_chip_data
*gic
= &gic_data
[0];
268 void __iomem
*cpu_base
= gic_data_cpu_base(gic
);
271 irqstat
= readl_relaxed(cpu_base
+ GIC_CPU_INTACK
);
272 irqnr
= irqstat
& GICC_IAR_INT_ID_MASK
;
274 if (likely(irqnr
> 15 && irqnr
< 1021)) {
275 handle_domain_irq(gic
->domain
, irqnr
, regs
);
279 writel_relaxed(irqstat
, cpu_base
+ GIC_CPU_EOI
);
281 handle_IPI(irqnr
, regs
);
289 static void gic_handle_cascade_irq(unsigned int irq
, struct irq_desc
*desc
)
291 struct gic_chip_data
*chip_data
= irq_desc_get_handler_data(desc
);
292 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
293 unsigned int cascade_irq
, gic_irq
;
294 unsigned long status
;
296 chained_irq_enter(chip
, desc
);
298 raw_spin_lock(&irq_controller_lock
);
299 status
= readl_relaxed(gic_data_cpu_base(chip_data
) + GIC_CPU_INTACK
);
300 raw_spin_unlock(&irq_controller_lock
);
302 gic_irq
= (status
& GICC_IAR_INT_ID_MASK
);
303 if (gic_irq
== GICC_INT_SPURIOUS
)
306 cascade_irq
= irq_find_mapping(chip_data
->domain
, gic_irq
);
307 if (unlikely(gic_irq
< 32 || gic_irq
> 1020))
308 handle_bad_irq(cascade_irq
, desc
);
310 generic_handle_irq(cascade_irq
);
313 chained_irq_exit(chip
, desc
);
316 static struct irq_chip gic_chip
= {
318 .irq_mask
= gic_mask_irq
,
319 .irq_unmask
= gic_unmask_irq
,
320 .irq_eoi
= gic_eoi_irq
,
321 .irq_set_type
= gic_set_type
,
323 .irq_set_affinity
= gic_set_affinity
,
325 .irq_get_irqchip_state
= gic_irq_get_irqchip_state
,
326 .irq_set_irqchip_state
= gic_irq_set_irqchip_state
,
327 .flags
= IRQCHIP_SET_TYPE_MASKED
|
328 IRQCHIP_SKIP_SET_WAKE
|
329 IRQCHIP_MASK_ON_SUSPEND
,
332 void __init
gic_cascade_irq(unsigned int gic_nr
, unsigned int irq
)
334 if (gic_nr
>= MAX_GIC_NR
)
336 irq_set_chained_handler_and_data(irq
, gic_handle_cascade_irq
,
340 static u8
gic_get_cpumask(struct gic_chip_data
*gic
)
342 void __iomem
*base
= gic_data_dist_base(gic
);
345 for (i
= mask
= 0; i
< 32; i
+= 4) {
346 mask
= readl_relaxed(base
+ GIC_DIST_TARGET
+ i
);
353 if (!mask
&& num_possible_cpus() > 1)
354 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
359 static void gic_cpu_if_up(void)
361 void __iomem
*cpu_base
= gic_data_cpu_base(&gic_data
[0]);
365 * Preserve bypass disable bits to be written back later
367 bypass
= readl(cpu_base
+ GIC_CPU_CTRL
);
368 bypass
&= GICC_DIS_BYPASS_MASK
;
370 writel_relaxed(bypass
| GICC_ENABLE
, cpu_base
+ GIC_CPU_CTRL
);
374 static void __init
gic_dist_init(struct gic_chip_data
*gic
)
378 unsigned int gic_irqs
= gic
->gic_irqs
;
379 void __iomem
*base
= gic_data_dist_base(gic
);
381 writel_relaxed(GICD_DISABLE
, base
+ GIC_DIST_CTRL
);
384 * Set all global interrupts to this CPU only.
386 cpumask
= gic_get_cpumask(gic
);
387 cpumask
|= cpumask
<< 8;
388 cpumask
|= cpumask
<< 16;
389 for (i
= 32; i
< gic_irqs
; i
+= 4)
390 writel_relaxed(cpumask
, base
+ GIC_DIST_TARGET
+ i
* 4 / 4);
392 gic_dist_config(base
, gic_irqs
, NULL
);
394 writel_relaxed(GICD_ENABLE
, base
+ GIC_DIST_CTRL
);
397 static void gic_cpu_init(struct gic_chip_data
*gic
)
399 void __iomem
*dist_base
= gic_data_dist_base(gic
);
400 void __iomem
*base
= gic_data_cpu_base(gic
);
401 unsigned int cpu_mask
, cpu
= smp_processor_id();
405 * Get what the GIC says our CPU mask is.
407 BUG_ON(cpu
>= NR_GIC_CPU_IF
);
408 cpu_mask
= gic_get_cpumask(gic
);
409 gic_cpu_map
[cpu
] = cpu_mask
;
412 * Clear our mask from the other map entries in case they're
415 for (i
= 0; i
< NR_GIC_CPU_IF
; i
++)
417 gic_cpu_map
[i
] &= ~cpu_mask
;
419 gic_cpu_config(dist_base
, NULL
);
421 writel_relaxed(GICC_INT_PRI_THRESHOLD
, base
+ GIC_CPU_PRIMASK
);
425 void gic_cpu_if_down(void)
427 void __iomem
*cpu_base
= gic_data_cpu_base(&gic_data
[0]);
430 val
= readl(cpu_base
+ GIC_CPU_CTRL
);
432 writel_relaxed(val
, cpu_base
+ GIC_CPU_CTRL
);
437 * Saves the GIC distributor registers during suspend or idle. Must be called
438 * with interrupts disabled but before powering down the GIC. After calling
439 * this function, no interrupts will be delivered by the GIC, and another
440 * platform-specific wakeup source must be enabled.
442 static void gic_dist_save(unsigned int gic_nr
)
444 unsigned int gic_irqs
;
445 void __iomem
*dist_base
;
448 if (gic_nr
>= MAX_GIC_NR
)
451 gic_irqs
= gic_data
[gic_nr
].gic_irqs
;
452 dist_base
= gic_data_dist_base(&gic_data
[gic_nr
]);
457 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 16); i
++)
458 gic_data
[gic_nr
].saved_spi_conf
[i
] =
459 readl_relaxed(dist_base
+ GIC_DIST_CONFIG
+ i
* 4);
461 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 4); i
++)
462 gic_data
[gic_nr
].saved_spi_target
[i
] =
463 readl_relaxed(dist_base
+ GIC_DIST_TARGET
+ i
* 4);
465 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 32); i
++)
466 gic_data
[gic_nr
].saved_spi_enable
[i
] =
467 readl_relaxed(dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
471 * Restores the GIC distributor registers during resume or when coming out of
472 * idle. Must be called before enabling interrupts. If a level interrupt
473 * that occured while the GIC was suspended is still present, it will be
474 * handled normally, but any edge interrupts that occured will not be seen by
475 * the GIC and need to be handled by the platform-specific wakeup source.
477 static void gic_dist_restore(unsigned int gic_nr
)
479 unsigned int gic_irqs
;
481 void __iomem
*dist_base
;
483 if (gic_nr
>= MAX_GIC_NR
)
486 gic_irqs
= gic_data
[gic_nr
].gic_irqs
;
487 dist_base
= gic_data_dist_base(&gic_data
[gic_nr
]);
492 writel_relaxed(GICD_DISABLE
, dist_base
+ GIC_DIST_CTRL
);
494 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 16); i
++)
495 writel_relaxed(gic_data
[gic_nr
].saved_spi_conf
[i
],
496 dist_base
+ GIC_DIST_CONFIG
+ i
* 4);
498 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 4); i
++)
499 writel_relaxed(GICD_INT_DEF_PRI_X4
,
500 dist_base
+ GIC_DIST_PRI
+ i
* 4);
502 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 4); i
++)
503 writel_relaxed(gic_data
[gic_nr
].saved_spi_target
[i
],
504 dist_base
+ GIC_DIST_TARGET
+ i
* 4);
506 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 32); i
++)
507 writel_relaxed(gic_data
[gic_nr
].saved_spi_enable
[i
],
508 dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
510 writel_relaxed(GICD_ENABLE
, dist_base
+ GIC_DIST_CTRL
);
513 static void gic_cpu_save(unsigned int gic_nr
)
517 void __iomem
*dist_base
;
518 void __iomem
*cpu_base
;
520 if (gic_nr
>= MAX_GIC_NR
)
523 dist_base
= gic_data_dist_base(&gic_data
[gic_nr
]);
524 cpu_base
= gic_data_cpu_base(&gic_data
[gic_nr
]);
526 if (!dist_base
|| !cpu_base
)
529 ptr
= raw_cpu_ptr(gic_data
[gic_nr
].saved_ppi_enable
);
530 for (i
= 0; i
< DIV_ROUND_UP(32, 32); i
++)
531 ptr
[i
] = readl_relaxed(dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
533 ptr
= raw_cpu_ptr(gic_data
[gic_nr
].saved_ppi_conf
);
534 for (i
= 0; i
< DIV_ROUND_UP(32, 16); i
++)
535 ptr
[i
] = readl_relaxed(dist_base
+ GIC_DIST_CONFIG
+ i
* 4);
539 static void gic_cpu_restore(unsigned int gic_nr
)
543 void __iomem
*dist_base
;
544 void __iomem
*cpu_base
;
546 if (gic_nr
>= MAX_GIC_NR
)
549 dist_base
= gic_data_dist_base(&gic_data
[gic_nr
]);
550 cpu_base
= gic_data_cpu_base(&gic_data
[gic_nr
]);
552 if (!dist_base
|| !cpu_base
)
555 ptr
= raw_cpu_ptr(gic_data
[gic_nr
].saved_ppi_enable
);
556 for (i
= 0; i
< DIV_ROUND_UP(32, 32); i
++)
557 writel_relaxed(ptr
[i
], dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
559 ptr
= raw_cpu_ptr(gic_data
[gic_nr
].saved_ppi_conf
);
560 for (i
= 0; i
< DIV_ROUND_UP(32, 16); i
++)
561 writel_relaxed(ptr
[i
], dist_base
+ GIC_DIST_CONFIG
+ i
* 4);
563 for (i
= 0; i
< DIV_ROUND_UP(32, 4); i
++)
564 writel_relaxed(GICD_INT_DEF_PRI_X4
,
565 dist_base
+ GIC_DIST_PRI
+ i
* 4);
567 writel_relaxed(GICC_INT_PRI_THRESHOLD
, cpu_base
+ GIC_CPU_PRIMASK
);
571 static int gic_notifier(struct notifier_block
*self
, unsigned long cmd
, void *v
)
575 for (i
= 0; i
< MAX_GIC_NR
; i
++) {
576 #ifdef CONFIG_GIC_NON_BANKED
577 /* Skip over unused GICs */
578 if (!gic_data
[i
].get_base
)
585 case CPU_PM_ENTER_FAILED
:
589 case CPU_CLUSTER_PM_ENTER
:
592 case CPU_CLUSTER_PM_ENTER_FAILED
:
593 case CPU_CLUSTER_PM_EXIT
:
602 static struct notifier_block gic_notifier_block
= {
603 .notifier_call
= gic_notifier
,
606 static void __init
gic_pm_init(struct gic_chip_data
*gic
)
608 gic
->saved_ppi_enable
= __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
610 BUG_ON(!gic
->saved_ppi_enable
);
612 gic
->saved_ppi_conf
= __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
614 BUG_ON(!gic
->saved_ppi_conf
);
616 if (gic
== &gic_data
[0])
617 cpu_pm_register_notifier(&gic_notifier_block
);
620 static void __init
gic_pm_init(struct gic_chip_data
*gic
)
626 static void gic_raise_softirq(const struct cpumask
*mask
, unsigned int irq
)
629 unsigned long flags
, map
= 0;
631 raw_spin_lock_irqsave(&irq_controller_lock
, flags
);
633 /* Convert our logical CPU mask into a physical one. */
634 for_each_cpu(cpu
, mask
)
635 map
|= gic_cpu_map
[cpu
];
638 * Ensure that stores to Normal memory are visible to the
639 * other CPUs before they observe us issuing the IPI.
643 /* this always happens on GIC0 */
644 writel_relaxed(map
<< 16 | irq
, gic_data_dist_base(&gic_data
[0]) + GIC_DIST_SOFTINT
);
646 raw_spin_unlock_irqrestore(&irq_controller_lock
, flags
);
650 #ifdef CONFIG_BL_SWITCHER
652 * gic_send_sgi - send a SGI directly to given CPU interface number
654 * cpu_id: the ID for the destination CPU interface
655 * irq: the IPI number to send a SGI for
657 void gic_send_sgi(unsigned int cpu_id
, unsigned int irq
)
659 BUG_ON(cpu_id
>= NR_GIC_CPU_IF
);
660 cpu_id
= 1 << cpu_id
;
661 /* this always happens on GIC0 */
662 writel_relaxed((cpu_id
<< 16) | irq
, gic_data_dist_base(&gic_data
[0]) + GIC_DIST_SOFTINT
);
666 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
668 * @cpu: the logical CPU number to get the GIC ID for.
670 * Return the CPU interface ID for the given logical CPU number,
671 * or -1 if the CPU number is too large or the interface ID is
672 * unknown (more than one bit set).
674 int gic_get_cpu_id(unsigned int cpu
)
676 unsigned int cpu_bit
;
678 if (cpu
>= NR_GIC_CPU_IF
)
680 cpu_bit
= gic_cpu_map
[cpu
];
681 if (cpu_bit
& (cpu_bit
- 1))
683 return __ffs(cpu_bit
);
687 * gic_migrate_target - migrate IRQs to another CPU interface
689 * @new_cpu_id: the CPU target ID to migrate IRQs to
691 * Migrate all peripheral interrupts with a target matching the current CPU
692 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
693 * is also updated. Targets to other CPU interfaces are unchanged.
694 * This must be called with IRQs locally disabled.
696 void gic_migrate_target(unsigned int new_cpu_id
)
698 unsigned int cur_cpu_id
, gic_irqs
, gic_nr
= 0;
699 void __iomem
*dist_base
;
700 int i
, ror_val
, cpu
= smp_processor_id();
701 u32 val
, cur_target_mask
, active_mask
;
703 if (gic_nr
>= MAX_GIC_NR
)
706 dist_base
= gic_data_dist_base(&gic_data
[gic_nr
]);
709 gic_irqs
= gic_data
[gic_nr
].gic_irqs
;
711 cur_cpu_id
= __ffs(gic_cpu_map
[cpu
]);
712 cur_target_mask
= 0x01010101 << cur_cpu_id
;
713 ror_val
= (cur_cpu_id
- new_cpu_id
) & 31;
715 raw_spin_lock(&irq_controller_lock
);
717 /* Update the target interface for this logical CPU */
718 gic_cpu_map
[cpu
] = 1 << new_cpu_id
;
721 * Find all the peripheral interrupts targetting the current
722 * CPU interface and migrate them to the new CPU interface.
723 * We skip DIST_TARGET 0 to 7 as they are read-only.
725 for (i
= 8; i
< DIV_ROUND_UP(gic_irqs
, 4); i
++) {
726 val
= readl_relaxed(dist_base
+ GIC_DIST_TARGET
+ i
* 4);
727 active_mask
= val
& cur_target_mask
;
730 val
|= ror32(active_mask
, ror_val
);
731 writel_relaxed(val
, dist_base
+ GIC_DIST_TARGET
+ i
*4);
735 raw_spin_unlock(&irq_controller_lock
);
738 * Now let's migrate and clear any potential SGIs that might be
739 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
740 * is a banked register, we can only forward the SGI using
741 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
742 * doesn't use that information anyway.
744 * For the same reason we do not adjust SGI source information
745 * for previously sent SGIs by us to other CPUs either.
747 for (i
= 0; i
< 16; i
+= 4) {
749 val
= readl_relaxed(dist_base
+ GIC_DIST_SGI_PENDING_SET
+ i
);
752 writel_relaxed(val
, dist_base
+ GIC_DIST_SGI_PENDING_CLEAR
+ i
);
753 for (j
= i
; j
< i
+ 4; j
++) {
755 writel_relaxed((1 << (new_cpu_id
+ 16)) | j
,
756 dist_base
+ GIC_DIST_SOFTINT
);
763 * gic_get_sgir_physaddr - get the physical address for the SGI register
765 * REturn the physical address of the SGI register to be used
766 * by some early assembly code when the kernel is not yet available.
768 static unsigned long gic_dist_physaddr
;
770 unsigned long gic_get_sgir_physaddr(void)
772 if (!gic_dist_physaddr
)
774 return gic_dist_physaddr
+ GIC_DIST_SOFTINT
;
777 void __init
gic_init_physaddr(struct device_node
*node
)
780 if (of_address_to_resource(node
, 0, &res
) == 0) {
781 gic_dist_physaddr
= res
.start
;
782 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr
);
787 #define gic_init_physaddr(node) do { } while (0)
790 static int gic_irq_domain_map(struct irq_domain
*d
, unsigned int irq
,
794 irq_set_percpu_devid(irq
);
795 irq_domain_set_info(d
, irq
, hw
, &gic_chip
, d
->host_data
,
796 handle_percpu_devid_irq
, NULL
, NULL
);
797 set_irq_flags(irq
, IRQF_VALID
| IRQF_NOAUTOEN
);
799 irq_domain_set_info(d
, irq
, hw
, &gic_chip
, d
->host_data
,
800 handle_fasteoi_irq
, NULL
, NULL
);
801 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
806 static void gic_irq_domain_unmap(struct irq_domain
*d
, unsigned int irq
)
810 static int gic_irq_domain_xlate(struct irq_domain
*d
,
811 struct device_node
*controller
,
812 const u32
*intspec
, unsigned int intsize
,
813 unsigned long *out_hwirq
, unsigned int *out_type
)
815 unsigned long ret
= 0;
817 if (d
->of_node
!= controller
)
822 /* Get the interrupt number and add 16 to skip over SGIs */
823 *out_hwirq
= intspec
[1] + 16;
825 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
829 *out_type
= intspec
[2] & IRQ_TYPE_SENSE_MASK
;
835 static int gic_secondary_init(struct notifier_block
*nfb
, unsigned long action
,
838 if (action
== CPU_STARTING
|| action
== CPU_STARTING_FROZEN
)
839 gic_cpu_init(&gic_data
[0]);
844 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
845 * priority because the GIC needs to be up before the ARM generic timers.
847 static struct notifier_block gic_cpu_notifier
= {
848 .notifier_call
= gic_secondary_init
,
853 static int gic_irq_domain_alloc(struct irq_domain
*domain
, unsigned int virq
,
854 unsigned int nr_irqs
, void *arg
)
857 irq_hw_number_t hwirq
;
858 unsigned int type
= IRQ_TYPE_NONE
;
859 struct of_phandle_args
*irq_data
= arg
;
861 ret
= gic_irq_domain_xlate(domain
, irq_data
->np
, irq_data
->args
,
862 irq_data
->args_count
, &hwirq
, &type
);
866 for (i
= 0; i
< nr_irqs
; i
++)
867 gic_irq_domain_map(domain
, virq
+ i
, hwirq
+ i
);
872 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops
= {
873 .xlate
= gic_irq_domain_xlate
,
874 .alloc
= gic_irq_domain_alloc
,
875 .free
= irq_domain_free_irqs_top
,
878 static const struct irq_domain_ops gic_irq_domain_ops
= {
879 .map
= gic_irq_domain_map
,
880 .unmap
= gic_irq_domain_unmap
,
881 .xlate
= gic_irq_domain_xlate
,
884 void __init
gic_init_bases(unsigned int gic_nr
, int irq_start
,
885 void __iomem
*dist_base
, void __iomem
*cpu_base
,
886 u32 percpu_offset
, struct device_node
*node
)
888 irq_hw_number_t hwirq_base
;
889 struct gic_chip_data
*gic
;
890 int gic_irqs
, irq_base
, i
;
892 BUG_ON(gic_nr
>= MAX_GIC_NR
);
894 gic
= &gic_data
[gic_nr
];
895 #ifdef CONFIG_GIC_NON_BANKED
896 if (percpu_offset
) { /* Frankein-GIC without banked registers... */
899 gic
->dist_base
.percpu_base
= alloc_percpu(void __iomem
*);
900 gic
->cpu_base
.percpu_base
= alloc_percpu(void __iomem
*);
901 if (WARN_ON(!gic
->dist_base
.percpu_base
||
902 !gic
->cpu_base
.percpu_base
)) {
903 free_percpu(gic
->dist_base
.percpu_base
);
904 free_percpu(gic
->cpu_base
.percpu_base
);
908 for_each_possible_cpu(cpu
) {
909 u32 mpidr
= cpu_logical_map(cpu
);
910 u32 core_id
= MPIDR_AFFINITY_LEVEL(mpidr
, 0);
911 unsigned long offset
= percpu_offset
* core_id
;
912 *per_cpu_ptr(gic
->dist_base
.percpu_base
, cpu
) = dist_base
+ offset
;
913 *per_cpu_ptr(gic
->cpu_base
.percpu_base
, cpu
) = cpu_base
+ offset
;
916 gic_set_base_accessor(gic
, gic_get_percpu_base
);
919 { /* Normal, sane GIC... */
921 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
923 gic
->dist_base
.common_base
= dist_base
;
924 gic
->cpu_base
.common_base
= cpu_base
;
925 gic_set_base_accessor(gic
, gic_get_common_base
);
929 * Initialize the CPU interface map to all CPUs.
930 * It will be refined as each CPU probes its ID.
932 for (i
= 0; i
< NR_GIC_CPU_IF
; i
++)
933 gic_cpu_map
[i
] = 0xff;
936 * Find out how many interrupts are supported.
937 * The GIC only supports up to 1020 interrupt sources.
939 gic_irqs
= readl_relaxed(gic_data_dist_base(gic
) + GIC_DIST_CTR
) & 0x1f;
940 gic_irqs
= (gic_irqs
+ 1) * 32;
943 gic
->gic_irqs
= gic_irqs
;
945 if (node
) { /* DT case */
946 gic
->domain
= irq_domain_add_linear(node
, gic_irqs
,
947 &gic_irq_domain_hierarchy_ops
,
949 } else { /* Non-DT case */
951 * For primary GICs, skip over SGIs.
952 * For secondary GICs, skip over PPIs, too.
954 if (gic_nr
== 0 && (irq_start
& 31) > 0) {
957 irq_start
= (irq_start
& ~31) + 16;
962 gic_irqs
-= hwirq_base
; /* calculate # of irqs to allocate */
964 irq_base
= irq_alloc_descs(irq_start
, 16, gic_irqs
,
966 if (IS_ERR_VALUE(irq_base
)) {
967 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
969 irq_base
= irq_start
;
972 gic
->domain
= irq_domain_add_legacy(node
, gic_irqs
, irq_base
,
973 hwirq_base
, &gic_irq_domain_ops
, gic
);
976 if (WARN_ON(!gic
->domain
))
981 set_smp_cross_call(gic_raise_softirq
);
982 register_cpu_notifier(&gic_cpu_notifier
);
984 set_handle_irq(gic_handle_irq
);
993 static int gic_cnt __initdata
;
996 gic_of_init(struct device_node
*node
, struct device_node
*parent
)
998 void __iomem
*cpu_base
;
999 void __iomem
*dist_base
;
1006 dist_base
= of_iomap(node
, 0);
1007 WARN(!dist_base
, "unable to map gic dist registers\n");
1009 cpu_base
= of_iomap(node
, 1);
1010 WARN(!cpu_base
, "unable to map gic cpu registers\n");
1012 if (of_property_read_u32(node
, "cpu-offset", &percpu_offset
))
1015 gic_init_bases(gic_cnt
, -1, dist_base
, cpu_base
, percpu_offset
, node
);
1017 gic_init_physaddr(node
);
1020 irq
= irq_of_parse_and_map(node
, 0);
1021 gic_cascade_irq(gic_cnt
, irq
);
1024 if (IS_ENABLED(CONFIG_ARM_GIC_V2M
))
1025 gicv2m_of_init(node
, gic_data
[gic_cnt
].domain
);
1030 IRQCHIP_DECLARE(gic_400
, "arm,gic-400", gic_of_init
);
1031 IRQCHIP_DECLARE(arm11mp_gic
, "arm,arm11mp-gic", gic_of_init
);
1032 IRQCHIP_DECLARE(arm1176jzf_dc_gic
, "arm,arm1176jzf-devchip-gic", gic_of_init
);
1033 IRQCHIP_DECLARE(cortex_a15_gic
, "arm,cortex-a15-gic", gic_of_init
);
1034 IRQCHIP_DECLARE(cortex_a9_gic
, "arm,cortex-a9-gic", gic_of_init
);
1035 IRQCHIP_DECLARE(cortex_a7_gic
, "arm,cortex-a7-gic", gic_of_init
);
1036 IRQCHIP_DECLARE(msm_8660_qgic
, "qcom,msm-8660-qgic", gic_of_init
);
1037 IRQCHIP_DECLARE(msm_qgic2
, "qcom,msm-qgic2", gic_of_init
);
1042 static phys_addr_t dist_phy_base
, cpu_phy_base __initdata
;
1045 gic_acpi_parse_madt_cpu(struct acpi_subtable_header
*header
,
1046 const unsigned long end
)
1048 struct acpi_madt_generic_interrupt
*processor
;
1049 phys_addr_t gic_cpu_base
;
1050 static int cpu_base_assigned
;
1052 processor
= (struct acpi_madt_generic_interrupt
*)header
;
1054 if (BAD_MADT_GICC_ENTRY(processor
, end
))
1058 * There is no support for non-banked GICv1/2 register in ACPI spec.
1059 * All CPU interface addresses have to be the same.
1061 gic_cpu_base
= processor
->base_address
;
1062 if (cpu_base_assigned
&& gic_cpu_base
!= cpu_phy_base
)
1065 cpu_phy_base
= gic_cpu_base
;
1066 cpu_base_assigned
= 1;
1071 gic_acpi_parse_madt_distributor(struct acpi_subtable_header
*header
,
1072 const unsigned long end
)
1074 struct acpi_madt_generic_distributor
*dist
;
1076 dist
= (struct acpi_madt_generic_distributor
*)header
;
1078 if (BAD_MADT_ENTRY(dist
, end
))
1081 dist_phy_base
= dist
->base_address
;
1086 gic_v2_acpi_init(struct acpi_table_header
*table
)
1088 void __iomem
*cpu_base
, *dist_base
;
1091 /* Collect CPU base addresses */
1092 count
= acpi_parse_entries(ACPI_SIG_MADT
,
1093 sizeof(struct acpi_table_madt
),
1094 gic_acpi_parse_madt_cpu
, table
,
1095 ACPI_MADT_TYPE_GENERIC_INTERRUPT
, 0);
1097 pr_err("No valid GICC entries exist\n");
1102 * Find distributor base address. We expect one distributor entry since
1103 * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade.
1105 count
= acpi_parse_entries(ACPI_SIG_MADT
,
1106 sizeof(struct acpi_table_madt
),
1107 gic_acpi_parse_madt_distributor
, table
,
1108 ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR
, 0);
1110 pr_err("No valid GICD entries exist\n");
1112 } else if (count
> 1) {
1113 pr_err("More than one GICD entry detected\n");
1117 cpu_base
= ioremap(cpu_phy_base
, ACPI_GIC_CPU_IF_MEM_SIZE
);
1119 pr_err("Unable to map GICC registers\n");
1123 dist_base
= ioremap(dist_phy_base
, ACPI_GICV2_DIST_MEM_SIZE
);
1125 pr_err("Unable to map GICD registers\n");
1131 * Initialize zero GIC instance (no multi-GIC support). Also, set GIC
1132 * as default IRQ domain to allow for GSI registration and GSI to IRQ
1133 * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()).
1135 gic_init_bases(0, -1, dist_base
, cpu_base
, 0, NULL
);
1136 irq_set_default_host(gic_data
[0].domain
);
1138 acpi_irq_model
= ACPI_IRQ_MODEL_GIC
;