2 * linux/arch/arm/common/gic.c
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Interrupt architecture for the GIC:
12 * o There is one Interrupt Distributor, which receives interrupts
13 * from system devices and sends them to the Interrupt Controllers.
15 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * by the Distributor, and interrupts generated locally, to the
17 * associated CPU. The base address of the CPU interface is usually
18 * aliased so that the same address points to different chips depending
19 * on the CPU it is accessed from.
21 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * As such, the enable set/clear, pending set/clear and active bit
23 * registers are banked per-cpu for these sources.
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/err.h>
28 #include <linux/module.h>
29 #include <linux/list.h>
30 #include <linux/smp.h>
31 #include <linux/cpu.h>
32 #include <linux/cpu_pm.h>
33 #include <linux/cpumask.h>
36 #include <linux/of_address.h>
37 #include <linux/of_irq.h>
38 #include <linux/irqdomain.h>
39 #include <linux/interrupt.h>
40 #include <linux/percpu.h>
41 #include <linux/slab.h>
42 #include <linux/irqchip/chained_irq.h>
43 #include <linux/irqchip/arm-gic.h>
46 #include <asm/exception.h>
47 #include <asm/smp_plat.h>
52 void __iomem
*common_base
;
53 void __percpu __iomem
**percpu_base
;
56 struct gic_chip_data
{
57 union gic_base dist_base
;
58 union gic_base cpu_base
;
60 u32 saved_spi_enable
[DIV_ROUND_UP(1020, 32)];
61 u32 saved_spi_conf
[DIV_ROUND_UP(1020, 16)];
62 u32 saved_spi_target
[DIV_ROUND_UP(1020, 4)];
63 u32 __percpu
*saved_ppi_enable
;
64 u32 __percpu
*saved_ppi_conf
;
66 struct irq_domain
*domain
;
67 unsigned int gic_irqs
;
68 #ifdef CONFIG_GIC_NON_BANKED
69 void __iomem
*(*get_base
)(union gic_base
*);
73 static DEFINE_RAW_SPINLOCK(irq_controller_lock
);
76 * The GIC mapping of CPU interfaces does not necessarily match
77 * the logical CPU numbering. Let's use a mapping as returned
80 #define NR_GIC_CPU_IF 8
81 static u8 gic_cpu_map
[NR_GIC_CPU_IF
] __read_mostly
;
84 * Supported arch specific GIC irq extension.
85 * Default make them NULL.
87 struct irq_chip gic_arch_extn
= {
91 .irq_retrigger
= NULL
,
100 static struct gic_chip_data gic_data
[MAX_GIC_NR
] __read_mostly
;
102 #ifdef CONFIG_GIC_NON_BANKED
103 static void __iomem
*gic_get_percpu_base(union gic_base
*base
)
105 return *__this_cpu_ptr(base
->percpu_base
);
108 static void __iomem
*gic_get_common_base(union gic_base
*base
)
110 return base
->common_base
;
113 static inline void __iomem
*gic_data_dist_base(struct gic_chip_data
*data
)
115 return data
->get_base(&data
->dist_base
);
118 static inline void __iomem
*gic_data_cpu_base(struct gic_chip_data
*data
)
120 return data
->get_base(&data
->cpu_base
);
123 static inline void gic_set_base_accessor(struct gic_chip_data
*data
,
124 void __iomem
*(*f
)(union gic_base
*))
129 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
130 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
131 #define gic_set_base_accessor(d, f)
134 static inline void __iomem
*gic_dist_base(struct irq_data
*d
)
136 struct gic_chip_data
*gic_data
= irq_data_get_irq_chip_data(d
);
137 return gic_data_dist_base(gic_data
);
140 static inline void __iomem
*gic_cpu_base(struct irq_data
*d
)
142 struct gic_chip_data
*gic_data
= irq_data_get_irq_chip_data(d
);
143 return gic_data_cpu_base(gic_data
);
146 static inline unsigned int gic_irq(struct irq_data
*d
)
152 * Routines to acknowledge, disable and enable interrupts
154 static void gic_mask_irq(struct irq_data
*d
)
156 u32 mask
= 1 << (gic_irq(d
) % 32);
158 raw_spin_lock(&irq_controller_lock
);
159 writel_relaxed(mask
, gic_dist_base(d
) + GIC_DIST_ENABLE_CLEAR
+ (gic_irq(d
) / 32) * 4);
160 if (gic_arch_extn
.irq_mask
)
161 gic_arch_extn
.irq_mask(d
);
162 raw_spin_unlock(&irq_controller_lock
);
165 static void gic_unmask_irq(struct irq_data
*d
)
167 u32 mask
= 1 << (gic_irq(d
) % 32);
169 raw_spin_lock(&irq_controller_lock
);
170 if (gic_arch_extn
.irq_unmask
)
171 gic_arch_extn
.irq_unmask(d
);
172 writel_relaxed(mask
, gic_dist_base(d
) + GIC_DIST_ENABLE_SET
+ (gic_irq(d
) / 32) * 4);
173 raw_spin_unlock(&irq_controller_lock
);
176 static void gic_eoi_irq(struct irq_data
*d
)
178 if (gic_arch_extn
.irq_eoi
) {
179 raw_spin_lock(&irq_controller_lock
);
180 gic_arch_extn
.irq_eoi(d
);
181 raw_spin_unlock(&irq_controller_lock
);
184 writel_relaxed(gic_irq(d
), gic_cpu_base(d
) + GIC_CPU_EOI
);
187 static int gic_set_type(struct irq_data
*d
, unsigned int type
)
189 void __iomem
*base
= gic_dist_base(d
);
190 unsigned int gicirq
= gic_irq(d
);
191 u32 enablemask
= 1 << (gicirq
% 32);
192 u32 enableoff
= (gicirq
/ 32) * 4;
193 u32 confmask
= 0x2 << ((gicirq
% 16) * 2);
194 u32 confoff
= (gicirq
/ 16) * 4;
195 bool enabled
= false;
198 /* Interrupt configuration for SGIs can't be changed */
202 if (type
!= IRQ_TYPE_LEVEL_HIGH
&& type
!= IRQ_TYPE_EDGE_RISING
)
205 raw_spin_lock(&irq_controller_lock
);
207 if (gic_arch_extn
.irq_set_type
)
208 gic_arch_extn
.irq_set_type(d
, type
);
210 val
= readl_relaxed(base
+ GIC_DIST_CONFIG
+ confoff
);
211 if (type
== IRQ_TYPE_LEVEL_HIGH
)
213 else if (type
== IRQ_TYPE_EDGE_RISING
)
217 * As recommended by the spec, disable the interrupt before changing
220 if (readl_relaxed(base
+ GIC_DIST_ENABLE_SET
+ enableoff
) & enablemask
) {
221 writel_relaxed(enablemask
, base
+ GIC_DIST_ENABLE_CLEAR
+ enableoff
);
225 writel_relaxed(val
, base
+ GIC_DIST_CONFIG
+ confoff
);
228 writel_relaxed(enablemask
, base
+ GIC_DIST_ENABLE_SET
+ enableoff
);
230 raw_spin_unlock(&irq_controller_lock
);
235 static int gic_retrigger(struct irq_data
*d
)
237 if (gic_arch_extn
.irq_retrigger
)
238 return gic_arch_extn
.irq_retrigger(d
);
240 /* the genirq layer expects 0 if we can't retrigger in hardware */
245 static int gic_set_affinity(struct irq_data
*d
, const struct cpumask
*mask_val
,
248 void __iomem
*reg
= gic_dist_base(d
) + GIC_DIST_TARGET
+ (gic_irq(d
) & ~3);
249 unsigned int shift
= (gic_irq(d
) % 4) * 8;
250 unsigned int cpu
= cpumask_any_and(mask_val
, cpu_online_mask
);
253 if (cpu
>= NR_GIC_CPU_IF
|| cpu
>= nr_cpu_ids
)
256 mask
= 0xff << shift
;
257 bit
= gic_cpu_map
[cpu
] << shift
;
259 raw_spin_lock(&irq_controller_lock
);
260 val
= readl_relaxed(reg
) & ~mask
;
261 writel_relaxed(val
| bit
, reg
);
262 raw_spin_unlock(&irq_controller_lock
);
264 return IRQ_SET_MASK_OK
;
269 static int gic_set_wake(struct irq_data
*d
, unsigned int on
)
273 if (gic_arch_extn
.irq_set_wake
)
274 ret
= gic_arch_extn
.irq_set_wake(d
, on
);
280 #define gic_set_wake NULL
283 static asmlinkage
void __exception_irq_entry
gic_handle_irq(struct pt_regs
*regs
)
286 struct gic_chip_data
*gic
= &gic_data
[0];
287 void __iomem
*cpu_base
= gic_data_cpu_base(gic
);
290 irqstat
= readl_relaxed(cpu_base
+ GIC_CPU_INTACK
);
291 irqnr
= irqstat
& ~0x1c00;
293 if (likely(irqnr
> 15 && irqnr
< 1021)) {
294 irqnr
= irq_find_mapping(gic
->domain
, irqnr
);
295 handle_IRQ(irqnr
, regs
);
299 writel_relaxed(irqstat
, cpu_base
+ GIC_CPU_EOI
);
301 handle_IPI(irqnr
, regs
);
309 static void gic_handle_cascade_irq(unsigned int irq
, struct irq_desc
*desc
)
311 struct gic_chip_data
*chip_data
= irq_get_handler_data(irq
);
312 struct irq_chip
*chip
= irq_get_chip(irq
);
313 unsigned int cascade_irq
, gic_irq
;
314 unsigned long status
;
316 chained_irq_enter(chip
, desc
);
318 raw_spin_lock(&irq_controller_lock
);
319 status
= readl_relaxed(gic_data_cpu_base(chip_data
) + GIC_CPU_INTACK
);
320 raw_spin_unlock(&irq_controller_lock
);
322 gic_irq
= (status
& 0x3ff);
326 cascade_irq
= irq_find_mapping(chip_data
->domain
, gic_irq
);
327 if (unlikely(gic_irq
< 32 || gic_irq
> 1020))
328 handle_bad_irq(cascade_irq
, desc
);
330 generic_handle_irq(cascade_irq
);
333 chained_irq_exit(chip
, desc
);
336 static struct irq_chip gic_chip
= {
338 .irq_mask
= gic_mask_irq
,
339 .irq_unmask
= gic_unmask_irq
,
340 .irq_eoi
= gic_eoi_irq
,
341 .irq_set_type
= gic_set_type
,
342 .irq_retrigger
= gic_retrigger
,
344 .irq_set_affinity
= gic_set_affinity
,
346 .irq_set_wake
= gic_set_wake
,
349 void __init
gic_cascade_irq(unsigned int gic_nr
, unsigned int irq
)
351 if (gic_nr
>= MAX_GIC_NR
)
353 if (irq_set_handler_data(irq
, &gic_data
[gic_nr
]) != 0)
355 irq_set_chained_handler(irq
, gic_handle_cascade_irq
);
358 static u8
gic_get_cpumask(struct gic_chip_data
*gic
)
360 void __iomem
*base
= gic_data_dist_base(gic
);
363 for (i
= mask
= 0; i
< 32; i
+= 4) {
364 mask
= readl_relaxed(base
+ GIC_DIST_TARGET
+ i
);
372 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
377 static void __init
gic_dist_init(struct gic_chip_data
*gic
)
381 unsigned int gic_irqs
= gic
->gic_irqs
;
382 void __iomem
*base
= gic_data_dist_base(gic
);
384 writel_relaxed(0, base
+ GIC_DIST_CTRL
);
387 * Set all global interrupts to be level triggered, active low.
389 for (i
= 32; i
< gic_irqs
; i
+= 16)
390 writel_relaxed(0, base
+ GIC_DIST_CONFIG
+ i
* 4 / 16);
393 * Set all global interrupts to this CPU only.
395 cpumask
= gic_get_cpumask(gic
);
396 cpumask
|= cpumask
<< 8;
397 cpumask
|= cpumask
<< 16;
398 for (i
= 32; i
< gic_irqs
; i
+= 4)
399 writel_relaxed(cpumask
, base
+ GIC_DIST_TARGET
+ i
* 4 / 4);
402 * Set priority on all global interrupts.
404 for (i
= 32; i
< gic_irqs
; i
+= 4)
405 writel_relaxed(0xa0a0a0a0, base
+ GIC_DIST_PRI
+ i
* 4 / 4);
408 * Disable all interrupts. Leave the PPI and SGIs alone
409 * as these enables are banked registers.
411 for (i
= 32; i
< gic_irqs
; i
+= 32)
412 writel_relaxed(0xffffffff, base
+ GIC_DIST_ENABLE_CLEAR
+ i
* 4 / 32);
414 writel_relaxed(1, base
+ GIC_DIST_CTRL
);
417 static void __cpuinit
gic_cpu_init(struct gic_chip_data
*gic
)
419 void __iomem
*dist_base
= gic_data_dist_base(gic
);
420 void __iomem
*base
= gic_data_cpu_base(gic
);
421 unsigned int cpu_mask
, cpu
= smp_processor_id();
425 * Get what the GIC says our CPU mask is.
427 BUG_ON(cpu
>= NR_GIC_CPU_IF
);
428 cpu_mask
= gic_get_cpumask(gic
);
429 gic_cpu_map
[cpu
] = cpu_mask
;
432 * Clear our mask from the other map entries in case they're
435 for (i
= 0; i
< NR_GIC_CPU_IF
; i
++)
437 gic_cpu_map
[i
] &= ~cpu_mask
;
440 * Deal with the banked PPI and SGI interrupts - disable all
441 * PPI interrupts, ensure all SGI interrupts are enabled.
443 writel_relaxed(0xffff0000, dist_base
+ GIC_DIST_ENABLE_CLEAR
);
444 writel_relaxed(0x0000ffff, dist_base
+ GIC_DIST_ENABLE_SET
);
447 * Set priority on PPI and SGI interrupts
449 for (i
= 0; i
< 32; i
+= 4)
450 writel_relaxed(0xa0a0a0a0, dist_base
+ GIC_DIST_PRI
+ i
* 4 / 4);
452 writel_relaxed(0xf0, base
+ GIC_CPU_PRIMASK
);
453 writel_relaxed(1, base
+ GIC_CPU_CTRL
);
458 * Saves the GIC distributor registers during suspend or idle. Must be called
459 * with interrupts disabled but before powering down the GIC. After calling
460 * this function, no interrupts will be delivered by the GIC, and another
461 * platform-specific wakeup source must be enabled.
463 static void gic_dist_save(unsigned int gic_nr
)
465 unsigned int gic_irqs
;
466 void __iomem
*dist_base
;
469 if (gic_nr
>= MAX_GIC_NR
)
472 gic_irqs
= gic_data
[gic_nr
].gic_irqs
;
473 dist_base
= gic_data_dist_base(&gic_data
[gic_nr
]);
478 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 16); i
++)
479 gic_data
[gic_nr
].saved_spi_conf
[i
] =
480 readl_relaxed(dist_base
+ GIC_DIST_CONFIG
+ i
* 4);
482 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 4); i
++)
483 gic_data
[gic_nr
].saved_spi_target
[i
] =
484 readl_relaxed(dist_base
+ GIC_DIST_TARGET
+ i
* 4);
486 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 32); i
++)
487 gic_data
[gic_nr
].saved_spi_enable
[i
] =
488 readl_relaxed(dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
492 * Restores the GIC distributor registers during resume or when coming out of
493 * idle. Must be called before enabling interrupts. If a level interrupt
494 * that occured while the GIC was suspended is still present, it will be
495 * handled normally, but any edge interrupts that occured will not be seen by
496 * the GIC and need to be handled by the platform-specific wakeup source.
498 static void gic_dist_restore(unsigned int gic_nr
)
500 unsigned int gic_irqs
;
502 void __iomem
*dist_base
;
504 if (gic_nr
>= MAX_GIC_NR
)
507 gic_irqs
= gic_data
[gic_nr
].gic_irqs
;
508 dist_base
= gic_data_dist_base(&gic_data
[gic_nr
]);
513 writel_relaxed(0, dist_base
+ GIC_DIST_CTRL
);
515 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 16); i
++)
516 writel_relaxed(gic_data
[gic_nr
].saved_spi_conf
[i
],
517 dist_base
+ GIC_DIST_CONFIG
+ i
* 4);
519 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 4); i
++)
520 writel_relaxed(0xa0a0a0a0,
521 dist_base
+ GIC_DIST_PRI
+ i
* 4);
523 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 4); i
++)
524 writel_relaxed(gic_data
[gic_nr
].saved_spi_target
[i
],
525 dist_base
+ GIC_DIST_TARGET
+ i
* 4);
527 for (i
= 0; i
< DIV_ROUND_UP(gic_irqs
, 32); i
++)
528 writel_relaxed(gic_data
[gic_nr
].saved_spi_enable
[i
],
529 dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
531 writel_relaxed(1, dist_base
+ GIC_DIST_CTRL
);
534 static void gic_cpu_save(unsigned int gic_nr
)
538 void __iomem
*dist_base
;
539 void __iomem
*cpu_base
;
541 if (gic_nr
>= MAX_GIC_NR
)
544 dist_base
= gic_data_dist_base(&gic_data
[gic_nr
]);
545 cpu_base
= gic_data_cpu_base(&gic_data
[gic_nr
]);
547 if (!dist_base
|| !cpu_base
)
550 ptr
= __this_cpu_ptr(gic_data
[gic_nr
].saved_ppi_enable
);
551 for (i
= 0; i
< DIV_ROUND_UP(32, 32); i
++)
552 ptr
[i
] = readl_relaxed(dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
554 ptr
= __this_cpu_ptr(gic_data
[gic_nr
].saved_ppi_conf
);
555 for (i
= 0; i
< DIV_ROUND_UP(32, 16); i
++)
556 ptr
[i
] = readl_relaxed(dist_base
+ GIC_DIST_CONFIG
+ i
* 4);
560 static void gic_cpu_restore(unsigned int gic_nr
)
564 void __iomem
*dist_base
;
565 void __iomem
*cpu_base
;
567 if (gic_nr
>= MAX_GIC_NR
)
570 dist_base
= gic_data_dist_base(&gic_data
[gic_nr
]);
571 cpu_base
= gic_data_cpu_base(&gic_data
[gic_nr
]);
573 if (!dist_base
|| !cpu_base
)
576 ptr
= __this_cpu_ptr(gic_data
[gic_nr
].saved_ppi_enable
);
577 for (i
= 0; i
< DIV_ROUND_UP(32, 32); i
++)
578 writel_relaxed(ptr
[i
], dist_base
+ GIC_DIST_ENABLE_SET
+ i
* 4);
580 ptr
= __this_cpu_ptr(gic_data
[gic_nr
].saved_ppi_conf
);
581 for (i
= 0; i
< DIV_ROUND_UP(32, 16); i
++)
582 writel_relaxed(ptr
[i
], dist_base
+ GIC_DIST_CONFIG
+ i
* 4);
584 for (i
= 0; i
< DIV_ROUND_UP(32, 4); i
++)
585 writel_relaxed(0xa0a0a0a0, dist_base
+ GIC_DIST_PRI
+ i
* 4);
587 writel_relaxed(0xf0, cpu_base
+ GIC_CPU_PRIMASK
);
588 writel_relaxed(1, cpu_base
+ GIC_CPU_CTRL
);
591 static int gic_notifier(struct notifier_block
*self
, unsigned long cmd
, void *v
)
595 for (i
= 0; i
< MAX_GIC_NR
; i
++) {
596 #ifdef CONFIG_GIC_NON_BANKED
597 /* Skip over unused GICs */
598 if (!gic_data
[i
].get_base
)
605 case CPU_PM_ENTER_FAILED
:
609 case CPU_CLUSTER_PM_ENTER
:
612 case CPU_CLUSTER_PM_ENTER_FAILED
:
613 case CPU_CLUSTER_PM_EXIT
:
622 static struct notifier_block gic_notifier_block
= {
623 .notifier_call
= gic_notifier
,
626 static void __init
gic_pm_init(struct gic_chip_data
*gic
)
628 gic
->saved_ppi_enable
= __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
630 BUG_ON(!gic
->saved_ppi_enable
);
632 gic
->saved_ppi_conf
= __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
634 BUG_ON(!gic
->saved_ppi_conf
);
636 if (gic
== &gic_data
[0])
637 cpu_pm_register_notifier(&gic_notifier_block
);
640 static void __init
gic_pm_init(struct gic_chip_data
*gic
)
646 void gic_raise_softirq(const struct cpumask
*mask
, unsigned int irq
)
649 unsigned long map
= 0;
651 /* Convert our logical CPU mask into a physical one. */
652 for_each_cpu(cpu
, mask
)
653 map
|= gic_cpu_map
[cpu
];
656 * Ensure that stores to Normal memory are visible to the
657 * other CPUs before issuing the IPI.
661 /* this always happens on GIC0 */
662 writel_relaxed(map
<< 16 | irq
, gic_data_dist_base(&gic_data
[0]) + GIC_DIST_SOFTINT
);
666 static int gic_irq_domain_map(struct irq_domain
*d
, unsigned int irq
,
670 irq_set_percpu_devid(irq
);
671 irq_set_chip_and_handler(irq
, &gic_chip
,
672 handle_percpu_devid_irq
);
673 set_irq_flags(irq
, IRQF_VALID
| IRQF_NOAUTOEN
);
675 irq_set_chip_and_handler(irq
, &gic_chip
,
677 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
679 irq_set_chip_data(irq
, d
->host_data
);
683 static int gic_irq_domain_xlate(struct irq_domain
*d
,
684 struct device_node
*controller
,
685 const u32
*intspec
, unsigned int intsize
,
686 unsigned long *out_hwirq
, unsigned int *out_type
)
688 if (d
->of_node
!= controller
)
693 /* Get the interrupt number and add 16 to skip over SGIs */
694 *out_hwirq
= intspec
[1] + 16;
696 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
700 *out_type
= intspec
[2] & IRQ_TYPE_SENSE_MASK
;
705 static int __cpuinit
gic_secondary_init(struct notifier_block
*nfb
,
706 unsigned long action
, void *hcpu
)
708 if (action
== CPU_STARTING
|| action
== CPU_STARTING_FROZEN
)
709 gic_cpu_init(&gic_data
[0]);
714 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
715 * priority because the GIC needs to be up before the ARM generic timers.
717 static struct notifier_block __cpuinitdata gic_cpu_notifier
= {
718 .notifier_call
= gic_secondary_init
,
723 const struct irq_domain_ops gic_irq_domain_ops
= {
724 .map
= gic_irq_domain_map
,
725 .xlate
= gic_irq_domain_xlate
,
728 void __init
gic_init_bases(unsigned int gic_nr
, int irq_start
,
729 void __iomem
*dist_base
, void __iomem
*cpu_base
,
730 u32 percpu_offset
, struct device_node
*node
)
732 irq_hw_number_t hwirq_base
;
733 struct gic_chip_data
*gic
;
734 int gic_irqs
, irq_base
, i
;
736 BUG_ON(gic_nr
>= MAX_GIC_NR
);
738 gic
= &gic_data
[gic_nr
];
739 #ifdef CONFIG_GIC_NON_BANKED
740 if (percpu_offset
) { /* Frankein-GIC without banked registers... */
743 gic
->dist_base
.percpu_base
= alloc_percpu(void __iomem
*);
744 gic
->cpu_base
.percpu_base
= alloc_percpu(void __iomem
*);
745 if (WARN_ON(!gic
->dist_base
.percpu_base
||
746 !gic
->cpu_base
.percpu_base
)) {
747 free_percpu(gic
->dist_base
.percpu_base
);
748 free_percpu(gic
->cpu_base
.percpu_base
);
752 for_each_possible_cpu(cpu
) {
753 unsigned long offset
= percpu_offset
* cpu_logical_map(cpu
);
754 *per_cpu_ptr(gic
->dist_base
.percpu_base
, cpu
) = dist_base
+ offset
;
755 *per_cpu_ptr(gic
->cpu_base
.percpu_base
, cpu
) = cpu_base
+ offset
;
758 gic_set_base_accessor(gic
, gic_get_percpu_base
);
761 { /* Normal, sane GIC... */
763 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
765 gic
->dist_base
.common_base
= dist_base
;
766 gic
->cpu_base
.common_base
= cpu_base
;
767 gic_set_base_accessor(gic
, gic_get_common_base
);
771 * Initialize the CPU interface map to all CPUs.
772 * It will be refined as each CPU probes its ID.
774 for (i
= 0; i
< NR_GIC_CPU_IF
; i
++)
775 gic_cpu_map
[i
] = 0xff;
778 * For primary GICs, skip over SGIs.
779 * For secondary GICs, skip over PPIs, too.
781 if (gic_nr
== 0 && (irq_start
& 31) > 0) {
784 irq_start
= (irq_start
& ~31) + 16;
790 * Find out how many interrupts are supported.
791 * The GIC only supports up to 1020 interrupt sources.
793 gic_irqs
= readl_relaxed(gic_data_dist_base(gic
) + GIC_DIST_CTR
) & 0x1f;
794 gic_irqs
= (gic_irqs
+ 1) * 32;
797 gic
->gic_irqs
= gic_irqs
;
799 gic_irqs
-= hwirq_base
; /* calculate # of irqs to allocate */
800 irq_base
= irq_alloc_descs(irq_start
, 16, gic_irqs
, numa_node_id());
801 if (IS_ERR_VALUE(irq_base
)) {
802 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
804 irq_base
= irq_start
;
806 gic
->domain
= irq_domain_add_legacy(node
, gic_irqs
, irq_base
,
807 hwirq_base
, &gic_irq_domain_ops
, gic
);
808 if (WARN_ON(!gic
->domain
))
812 set_smp_cross_call(gic_raise_softirq
);
813 register_cpu_notifier(&gic_cpu_notifier
);
816 set_handle_irq(gic_handle_irq
);
818 gic_chip
.flags
|= gic_arch_extn
.flags
;
825 static int gic_cnt __initdata
;
827 int __init
gic_of_init(struct device_node
*node
, struct device_node
*parent
)
829 void __iomem
*cpu_base
;
830 void __iomem
*dist_base
;
837 dist_base
= of_iomap(node
, 0);
838 WARN(!dist_base
, "unable to map gic dist registers\n");
840 cpu_base
= of_iomap(node
, 1);
841 WARN(!cpu_base
, "unable to map gic cpu registers\n");
843 if (of_property_read_u32(node
, "cpu-offset", &percpu_offset
))
846 gic_init_bases(gic_cnt
, -1, dist_base
, cpu_base
, percpu_offset
, node
);
849 irq
= irq_of_parse_and_map(node
, 0);
850 gic_cascade_irq(gic_cnt
, irq
);
855 IRQCHIP_DECLARE(cortex_a15_gic
, "arm,cortex-a15-gic", gic_of_init
);
856 IRQCHIP_DECLARE(cortex_a9_gic
, "arm,cortex-a9-gic", gic_of_init
);
857 IRQCHIP_DECLARE(msm_8660_qgic
, "qcom,msm-8660-qgic", gic_of_init
);
858 IRQCHIP_DECLARE(msm_qgic2
, "qcom,msm-qgic2", gic_of_init
);