2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 #include <linux/bitmap.h>
10 #include <linux/clocksource.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip.h>
15 #include <linux/irqchip/mips-gic.h>
16 #include <linux/of_address.h>
17 #include <linux/sched.h>
18 #include <linux/smp.h>
20 #include <asm/mips-cm.h>
21 #include <asm/setup.h>
22 #include <asm/traps.h>
24 #include <dt-bindings/interrupt-controller/mips-gic.h>
26 unsigned int gic_present
;
28 struct gic_pcpu_mask
{
29 DECLARE_BITMAP(pcpu_mask
, GIC_MAX_INTRS
);
32 static void __iomem
*gic_base
;
33 static struct gic_pcpu_mask pcpu_masks
[NR_CPUS
];
34 static DEFINE_SPINLOCK(gic_lock
);
35 static struct irq_domain
*gic_irq_domain
;
36 static int gic_shared_intrs
;
38 static unsigned int gic_cpu_pin
;
39 static unsigned int timer_cpu_pin
;
40 static struct irq_chip gic_level_irq_controller
, gic_edge_irq_controller
;
42 static void __gic_irq_dispatch(void);
44 static inline u32
gic_read32(unsigned int reg
)
46 return __raw_readl(gic_base
+ reg
);
49 static inline u64
gic_read64(unsigned int reg
)
51 return __raw_readq(gic_base
+ reg
);
54 static inline unsigned long gic_read(unsigned int reg
)
57 return gic_read32(reg
);
59 return gic_read64(reg
);
62 static inline void gic_write32(unsigned int reg
, u32 val
)
64 return __raw_writel(val
, gic_base
+ reg
);
67 static inline void gic_write64(unsigned int reg
, u64 val
)
69 return __raw_writeq(val
, gic_base
+ reg
);
72 static inline void gic_write(unsigned int reg
, unsigned long val
)
75 return gic_write32(reg
, (u32
)val
);
77 return gic_write64(reg
, (u64
)val
);
80 static inline void gic_update_bits(unsigned int reg
, unsigned long mask
,
85 regval
= gic_read(reg
);
88 gic_write(reg
, regval
);
91 static inline void gic_reset_mask(unsigned int intr
)
93 gic_write(GIC_REG(SHARED
, GIC_SH_RMASK
) + GIC_INTR_OFS(intr
),
94 1ul << GIC_INTR_BIT(intr
));
97 static inline void gic_set_mask(unsigned int intr
)
99 gic_write(GIC_REG(SHARED
, GIC_SH_SMASK
) + GIC_INTR_OFS(intr
),
100 1ul << GIC_INTR_BIT(intr
));
103 static inline void gic_set_polarity(unsigned int intr
, unsigned int pol
)
105 gic_update_bits(GIC_REG(SHARED
, GIC_SH_SET_POLARITY
) +
106 GIC_INTR_OFS(intr
), 1ul << GIC_INTR_BIT(intr
),
107 (unsigned long)pol
<< GIC_INTR_BIT(intr
));
110 static inline void gic_set_trigger(unsigned int intr
, unsigned int trig
)
112 gic_update_bits(GIC_REG(SHARED
, GIC_SH_SET_TRIGGER
) +
113 GIC_INTR_OFS(intr
), 1ul << GIC_INTR_BIT(intr
),
114 (unsigned long)trig
<< GIC_INTR_BIT(intr
));
117 static inline void gic_set_dual_edge(unsigned int intr
, unsigned int dual
)
119 gic_update_bits(GIC_REG(SHARED
, GIC_SH_SET_DUAL
) + GIC_INTR_OFS(intr
),
120 1ul << GIC_INTR_BIT(intr
),
121 (unsigned long)dual
<< GIC_INTR_BIT(intr
));
124 static inline void gic_map_to_pin(unsigned int intr
, unsigned int pin
)
126 gic_write32(GIC_REG(SHARED
, GIC_SH_INTR_MAP_TO_PIN_BASE
) +
127 GIC_SH_MAP_TO_PIN(intr
), GIC_MAP_TO_PIN_MSK
| pin
);
130 static inline void gic_map_to_vpe(unsigned int intr
, unsigned int vpe
)
132 gic_write(GIC_REG(SHARED
, GIC_SH_INTR_MAP_TO_VPE_BASE
) +
133 GIC_SH_MAP_TO_VPE_REG_OFF(intr
, vpe
),
134 GIC_SH_MAP_TO_VPE_REG_BIT(vpe
));
137 #ifdef CONFIG_CLKSRC_MIPS_GIC
138 cycle_t
gic_read_count(void)
140 unsigned int hi
, hi2
, lo
;
143 return (cycle_t
)gic_read(GIC_REG(SHARED
, GIC_SH_COUNTER
));
146 hi
= gic_read32(GIC_REG(SHARED
, GIC_SH_COUNTER_63_32
));
147 lo
= gic_read32(GIC_REG(SHARED
, GIC_SH_COUNTER_31_00
));
148 hi2
= gic_read32(GIC_REG(SHARED
, GIC_SH_COUNTER_63_32
));
151 return (((cycle_t
) hi
) << 32) + lo
;
154 unsigned int gic_get_count_width(void)
156 unsigned int bits
, config
;
158 config
= gic_read(GIC_REG(SHARED
, GIC_SH_CONFIG
));
159 bits
= 32 + 4 * ((config
& GIC_SH_CONFIG_COUNTBITS_MSK
) >>
160 GIC_SH_CONFIG_COUNTBITS_SHF
);
165 void gic_write_compare(cycle_t cnt
)
168 gic_write(GIC_REG(VPE_LOCAL
, GIC_VPE_COMPARE
), cnt
);
170 gic_write32(GIC_REG(VPE_LOCAL
, GIC_VPE_COMPARE_HI
),
172 gic_write32(GIC_REG(VPE_LOCAL
, GIC_VPE_COMPARE_LO
),
173 (int)(cnt
& 0xffffffff));
177 void gic_write_cpu_compare(cycle_t cnt
, int cpu
)
181 local_irq_save(flags
);
183 gic_write(GIC_REG(VPE_LOCAL
, GIC_VPE_OTHER_ADDR
), cpu
);
186 gic_write(GIC_REG(VPE_OTHER
, GIC_VPE_COMPARE
), cnt
);
188 gic_write32(GIC_REG(VPE_OTHER
, GIC_VPE_COMPARE_HI
),
190 gic_write32(GIC_REG(VPE_OTHER
, GIC_VPE_COMPARE_LO
),
191 (int)(cnt
& 0xffffffff));
194 local_irq_restore(flags
);
197 cycle_t
gic_read_compare(void)
202 return (cycle_t
)gic_read(GIC_REG(VPE_LOCAL
, GIC_VPE_COMPARE
));
204 hi
= gic_read32(GIC_REG(VPE_LOCAL
, GIC_VPE_COMPARE_HI
));
205 lo
= gic_read32(GIC_REG(VPE_LOCAL
, GIC_VPE_COMPARE_LO
));
207 return (((cycle_t
) hi
) << 32) + lo
;
210 void gic_start_count(void)
214 /* Start the counter */
215 gicconfig
= gic_read(GIC_REG(SHARED
, GIC_SH_CONFIG
));
216 gicconfig
&= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF
);
217 gic_write(GIC_REG(SHARED
, GIC_SH_CONFIG
), gicconfig
);
220 void gic_stop_count(void)
224 /* Stop the counter */
225 gicconfig
= gic_read(GIC_REG(SHARED
, GIC_SH_CONFIG
));
226 gicconfig
|= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF
;
227 gic_write(GIC_REG(SHARED
, GIC_SH_CONFIG
), gicconfig
);
232 static bool gic_local_irq_is_routable(int intr
)
236 /* All local interrupts are routable in EIC mode. */
240 vpe_ctl
= gic_read32(GIC_REG(VPE_LOCAL
, GIC_VPE_CTL
));
242 case GIC_LOCAL_INT_TIMER
:
243 return vpe_ctl
& GIC_VPE_CTL_TIMER_RTBL_MSK
;
244 case GIC_LOCAL_INT_PERFCTR
:
245 return vpe_ctl
& GIC_VPE_CTL_PERFCNT_RTBL_MSK
;
246 case GIC_LOCAL_INT_FDC
:
247 return vpe_ctl
& GIC_VPE_CTL_FDC_RTBL_MSK
;
248 case GIC_LOCAL_INT_SWINT0
:
249 case GIC_LOCAL_INT_SWINT1
:
250 return vpe_ctl
& GIC_VPE_CTL_SWINT_RTBL_MSK
;
256 static void gic_bind_eic_interrupt(int irq
, int set
)
258 /* Convert irq vector # to hw int # */
259 irq
-= GIC_PIN_TO_VEC_OFFSET
;
261 /* Set irq to use shadow set */
262 gic_write(GIC_REG(VPE_LOCAL
, GIC_VPE_EIC_SHADOW_SET_BASE
) +
263 GIC_VPE_EIC_SS(irq
), set
);
266 void gic_send_ipi(unsigned int intr
)
268 gic_write(GIC_REG(SHARED
, GIC_SH_WEDGE
), GIC_SH_WEDGE_SET(intr
));
271 int gic_get_c0_compare_int(void)
273 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER
))
274 return MIPS_CPU_IRQ_BASE
+ cp0_compare_irq
;
275 return irq_create_mapping(gic_irq_domain
,
276 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER
));
279 int gic_get_c0_perfcount_int(void)
281 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR
)) {
282 /* Is the performance counter shared with the timer? */
283 if (cp0_perfcount_irq
< 0)
285 return MIPS_CPU_IRQ_BASE
+ cp0_perfcount_irq
;
287 return irq_create_mapping(gic_irq_domain
,
288 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR
));
291 int gic_get_c0_fdc_int(void)
293 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC
)) {
294 /* Is the FDC IRQ even present? */
297 return MIPS_CPU_IRQ_BASE
+ cp0_fdc_irq
;
300 return irq_create_mapping(gic_irq_domain
,
301 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC
));
304 static void gic_handle_shared_int(bool chained
)
306 unsigned int i
, intr
, virq
, gic_reg_step
= mips_cm_is64
? 8 : 4;
307 unsigned long *pcpu_mask
;
308 unsigned long pending_reg
, intrmask_reg
;
309 DECLARE_BITMAP(pending
, GIC_MAX_INTRS
);
310 DECLARE_BITMAP(intrmask
, GIC_MAX_INTRS
);
312 /* Get per-cpu bitmaps */
313 pcpu_mask
= pcpu_masks
[smp_processor_id()].pcpu_mask
;
315 pending_reg
= GIC_REG(SHARED
, GIC_SH_PEND
);
316 intrmask_reg
= GIC_REG(SHARED
, GIC_SH_MASK
);
318 for (i
= 0; i
< BITS_TO_LONGS(gic_shared_intrs
); i
++) {
319 pending
[i
] = gic_read(pending_reg
);
320 intrmask
[i
] = gic_read(intrmask_reg
);
321 pending_reg
+= gic_reg_step
;
322 intrmask_reg
+= gic_reg_step
;
325 bitmap_and(pending
, pending
, intrmask
, gic_shared_intrs
);
326 bitmap_and(pending
, pending
, pcpu_mask
, gic_shared_intrs
);
328 intr
= find_first_bit(pending
, gic_shared_intrs
);
329 while (intr
!= gic_shared_intrs
) {
330 virq
= irq_linear_revmap(gic_irq_domain
,
331 GIC_SHARED_TO_HWIRQ(intr
));
333 generic_handle_irq(virq
);
337 /* go to next pending bit */
338 bitmap_clear(pending
, intr
, 1);
339 intr
= find_first_bit(pending
, gic_shared_intrs
);
343 static void gic_mask_irq(struct irq_data
*d
)
345 gic_reset_mask(GIC_HWIRQ_TO_SHARED(d
->hwirq
));
348 static void gic_unmask_irq(struct irq_data
*d
)
350 gic_set_mask(GIC_HWIRQ_TO_SHARED(d
->hwirq
));
353 static void gic_ack_irq(struct irq_data
*d
)
355 unsigned int irq
= GIC_HWIRQ_TO_SHARED(d
->hwirq
);
357 gic_write(GIC_REG(SHARED
, GIC_SH_WEDGE
), GIC_SH_WEDGE_CLR(irq
));
360 static int gic_set_type(struct irq_data
*d
, unsigned int type
)
362 unsigned int irq
= GIC_HWIRQ_TO_SHARED(d
->hwirq
);
366 spin_lock_irqsave(&gic_lock
, flags
);
367 switch (type
& IRQ_TYPE_SENSE_MASK
) {
368 case IRQ_TYPE_EDGE_FALLING
:
369 gic_set_polarity(irq
, GIC_POL_NEG
);
370 gic_set_trigger(irq
, GIC_TRIG_EDGE
);
371 gic_set_dual_edge(irq
, GIC_TRIG_DUAL_DISABLE
);
374 case IRQ_TYPE_EDGE_RISING
:
375 gic_set_polarity(irq
, GIC_POL_POS
);
376 gic_set_trigger(irq
, GIC_TRIG_EDGE
);
377 gic_set_dual_edge(irq
, GIC_TRIG_DUAL_DISABLE
);
380 case IRQ_TYPE_EDGE_BOTH
:
381 /* polarity is irrelevant in this case */
382 gic_set_trigger(irq
, GIC_TRIG_EDGE
);
383 gic_set_dual_edge(irq
, GIC_TRIG_DUAL_ENABLE
);
386 case IRQ_TYPE_LEVEL_LOW
:
387 gic_set_polarity(irq
, GIC_POL_NEG
);
388 gic_set_trigger(irq
, GIC_TRIG_LEVEL
);
389 gic_set_dual_edge(irq
, GIC_TRIG_DUAL_DISABLE
);
392 case IRQ_TYPE_LEVEL_HIGH
:
394 gic_set_polarity(irq
, GIC_POL_POS
);
395 gic_set_trigger(irq
, GIC_TRIG_LEVEL
);
396 gic_set_dual_edge(irq
, GIC_TRIG_DUAL_DISABLE
);
402 irq_set_chip_handler_name_locked(d
, &gic_edge_irq_controller
,
403 handle_edge_irq
, NULL
);
405 irq_set_chip_handler_name_locked(d
, &gic_level_irq_controller
,
406 handle_level_irq
, NULL
);
407 spin_unlock_irqrestore(&gic_lock
, flags
);
413 static int gic_set_affinity(struct irq_data
*d
, const struct cpumask
*cpumask
,
416 unsigned int irq
= GIC_HWIRQ_TO_SHARED(d
->hwirq
);
417 cpumask_t tmp
= CPU_MASK_NONE
;
421 cpumask_and(&tmp
, cpumask
, cpu_online_mask
);
422 if (cpumask_empty(&tmp
))
425 /* Assumption : cpumask refers to a single CPU */
426 spin_lock_irqsave(&gic_lock
, flags
);
428 /* Re-route this IRQ */
429 gic_map_to_vpe(irq
, cpumask_first(&tmp
));
431 /* Update the pcpu_masks */
432 for (i
= 0; i
< NR_CPUS
; i
++)
433 clear_bit(irq
, pcpu_masks
[i
].pcpu_mask
);
434 set_bit(irq
, pcpu_masks
[cpumask_first(&tmp
)].pcpu_mask
);
436 cpumask_copy(irq_data_get_affinity_mask(d
), cpumask
);
437 spin_unlock_irqrestore(&gic_lock
, flags
);
439 return IRQ_SET_MASK_OK_NOCOPY
;
443 static struct irq_chip gic_level_irq_controller
= {
445 .irq_mask
= gic_mask_irq
,
446 .irq_unmask
= gic_unmask_irq
,
447 .irq_set_type
= gic_set_type
,
449 .irq_set_affinity
= gic_set_affinity
,
453 static struct irq_chip gic_edge_irq_controller
= {
455 .irq_ack
= gic_ack_irq
,
456 .irq_mask
= gic_mask_irq
,
457 .irq_unmask
= gic_unmask_irq
,
458 .irq_set_type
= gic_set_type
,
460 .irq_set_affinity
= gic_set_affinity
,
464 static void gic_handle_local_int(bool chained
)
466 unsigned long pending
, masked
;
467 unsigned int intr
, virq
;
469 pending
= gic_read32(GIC_REG(VPE_LOCAL
, GIC_VPE_PEND
));
470 masked
= gic_read32(GIC_REG(VPE_LOCAL
, GIC_VPE_MASK
));
472 bitmap_and(&pending
, &pending
, &masked
, GIC_NUM_LOCAL_INTRS
);
474 intr
= find_first_bit(&pending
, GIC_NUM_LOCAL_INTRS
);
475 while (intr
!= GIC_NUM_LOCAL_INTRS
) {
476 virq
= irq_linear_revmap(gic_irq_domain
,
477 GIC_LOCAL_TO_HWIRQ(intr
));
479 generic_handle_irq(virq
);
483 /* go to next pending bit */
484 bitmap_clear(&pending
, intr
, 1);
485 intr
= find_first_bit(&pending
, GIC_NUM_LOCAL_INTRS
);
489 static void gic_mask_local_irq(struct irq_data
*d
)
491 int intr
= GIC_HWIRQ_TO_LOCAL(d
->hwirq
);
493 gic_write32(GIC_REG(VPE_LOCAL
, GIC_VPE_RMASK
), 1 << intr
);
496 static void gic_unmask_local_irq(struct irq_data
*d
)
498 int intr
= GIC_HWIRQ_TO_LOCAL(d
->hwirq
);
500 gic_write32(GIC_REG(VPE_LOCAL
, GIC_VPE_SMASK
), 1 << intr
);
503 static struct irq_chip gic_local_irq_controller
= {
504 .name
= "MIPS GIC Local",
505 .irq_mask
= gic_mask_local_irq
,
506 .irq_unmask
= gic_unmask_local_irq
,
509 static void gic_mask_local_irq_all_vpes(struct irq_data
*d
)
511 int intr
= GIC_HWIRQ_TO_LOCAL(d
->hwirq
);
515 spin_lock_irqsave(&gic_lock
, flags
);
516 for (i
= 0; i
< gic_vpes
; i
++) {
517 gic_write(GIC_REG(VPE_LOCAL
, GIC_VPE_OTHER_ADDR
), i
);
518 gic_write32(GIC_REG(VPE_OTHER
, GIC_VPE_RMASK
), 1 << intr
);
520 spin_unlock_irqrestore(&gic_lock
, flags
);
523 static void gic_unmask_local_irq_all_vpes(struct irq_data
*d
)
525 int intr
= GIC_HWIRQ_TO_LOCAL(d
->hwirq
);
529 spin_lock_irqsave(&gic_lock
, flags
);
530 for (i
= 0; i
< gic_vpes
; i
++) {
531 gic_write(GIC_REG(VPE_LOCAL
, GIC_VPE_OTHER_ADDR
), i
);
532 gic_write32(GIC_REG(VPE_OTHER
, GIC_VPE_SMASK
), 1 << intr
);
534 spin_unlock_irqrestore(&gic_lock
, flags
);
537 static struct irq_chip gic_all_vpes_local_irq_controller
= {
538 .name
= "MIPS GIC Local",
539 .irq_mask
= gic_mask_local_irq_all_vpes
,
540 .irq_unmask
= gic_unmask_local_irq_all_vpes
,
543 static void __gic_irq_dispatch(void)
545 gic_handle_local_int(false);
546 gic_handle_shared_int(false);
549 static void gic_irq_dispatch(struct irq_desc
*desc
)
551 gic_handle_local_int(true);
552 gic_handle_shared_int(true);
555 #ifdef CONFIG_MIPS_GIC_IPI
556 static int gic_resched_int_base
;
557 static int gic_call_int_base
;
559 unsigned int plat_ipi_resched_int_xlate(unsigned int cpu
)
561 return gic_resched_int_base
+ cpu
;
564 unsigned int plat_ipi_call_int_xlate(unsigned int cpu
)
566 return gic_call_int_base
+ cpu
;
569 static irqreturn_t
ipi_resched_interrupt(int irq
, void *dev_id
)
576 static irqreturn_t
ipi_call_interrupt(int irq
, void *dev_id
)
578 generic_smp_call_function_interrupt();
583 static struct irqaction irq_resched
= {
584 .handler
= ipi_resched_interrupt
,
585 .flags
= IRQF_PERCPU
,
586 .name
= "IPI resched"
589 static struct irqaction irq_call
= {
590 .handler
= ipi_call_interrupt
,
591 .flags
= IRQF_PERCPU
,
595 static __init
void gic_ipi_init_one(unsigned int intr
, int cpu
,
596 struct irqaction
*action
)
598 int virq
= irq_create_mapping(gic_irq_domain
,
599 GIC_SHARED_TO_HWIRQ(intr
));
602 gic_map_to_vpe(intr
, cpu
);
603 for (i
= 0; i
< NR_CPUS
; i
++)
604 clear_bit(intr
, pcpu_masks
[i
].pcpu_mask
);
605 set_bit(intr
, pcpu_masks
[cpu
].pcpu_mask
);
607 irq_set_irq_type(virq
, IRQ_TYPE_EDGE_RISING
);
609 irq_set_handler(virq
, handle_percpu_irq
);
610 setup_irq(virq
, action
);
613 static __init
void gic_ipi_init(void)
617 /* Use last 2 * NR_CPUS interrupts as IPIs */
618 gic_resched_int_base
= gic_shared_intrs
- nr_cpu_ids
;
619 gic_call_int_base
= gic_resched_int_base
- nr_cpu_ids
;
621 for (i
= 0; i
< nr_cpu_ids
; i
++) {
622 gic_ipi_init_one(gic_call_int_base
+ i
, i
, &irq_call
);
623 gic_ipi_init_one(gic_resched_int_base
+ i
, i
, &irq_resched
);
627 static inline void gic_ipi_init(void)
632 static void __init
gic_basic_init(void)
636 board_bind_eic_interrupt
= &gic_bind_eic_interrupt
;
639 for (i
= 0; i
< gic_shared_intrs
; i
++) {
640 gic_set_polarity(i
, GIC_POL_POS
);
641 gic_set_trigger(i
, GIC_TRIG_LEVEL
);
645 for (i
= 0; i
< gic_vpes
; i
++) {
648 gic_write(GIC_REG(VPE_LOCAL
, GIC_VPE_OTHER_ADDR
), i
);
649 for (j
= 0; j
< GIC_NUM_LOCAL_INTRS
; j
++) {
650 if (!gic_local_irq_is_routable(j
))
652 gic_write32(GIC_REG(VPE_OTHER
, GIC_VPE_RMASK
), 1 << j
);
657 static int gic_local_irq_domain_map(struct irq_domain
*d
, unsigned int virq
,
660 int intr
= GIC_HWIRQ_TO_LOCAL(hw
);
665 if (!gic_local_irq_is_routable(intr
))
669 * HACK: These are all really percpu interrupts, but the rest
670 * of the MIPS kernel code does not use the percpu IRQ API for
671 * the CP0 timer and performance counter interrupts.
674 case GIC_LOCAL_INT_TIMER
:
675 case GIC_LOCAL_INT_PERFCTR
:
676 case GIC_LOCAL_INT_FDC
:
677 irq_set_chip_and_handler(virq
,
678 &gic_all_vpes_local_irq_controller
,
682 irq_set_chip_and_handler(virq
,
683 &gic_local_irq_controller
,
684 handle_percpu_devid_irq
);
685 irq_set_percpu_devid(virq
);
689 spin_lock_irqsave(&gic_lock
, flags
);
690 for (i
= 0; i
< gic_vpes
; i
++) {
691 u32 val
= GIC_MAP_TO_PIN_MSK
| gic_cpu_pin
;
693 gic_write(GIC_REG(VPE_LOCAL
, GIC_VPE_OTHER_ADDR
), i
);
696 case GIC_LOCAL_INT_WD
:
697 gic_write32(GIC_REG(VPE_OTHER
, GIC_VPE_WD_MAP
), val
);
699 case GIC_LOCAL_INT_COMPARE
:
700 gic_write32(GIC_REG(VPE_OTHER
, GIC_VPE_COMPARE_MAP
),
703 case GIC_LOCAL_INT_TIMER
:
704 /* CONFIG_MIPS_CMP workaround (see __gic_init) */
705 val
= GIC_MAP_TO_PIN_MSK
| timer_cpu_pin
;
706 gic_write32(GIC_REG(VPE_OTHER
, GIC_VPE_TIMER_MAP
),
709 case GIC_LOCAL_INT_PERFCTR
:
710 gic_write32(GIC_REG(VPE_OTHER
, GIC_VPE_PERFCTR_MAP
),
713 case GIC_LOCAL_INT_SWINT0
:
714 gic_write32(GIC_REG(VPE_OTHER
, GIC_VPE_SWINT0_MAP
),
717 case GIC_LOCAL_INT_SWINT1
:
718 gic_write32(GIC_REG(VPE_OTHER
, GIC_VPE_SWINT1_MAP
),
721 case GIC_LOCAL_INT_FDC
:
722 gic_write32(GIC_REG(VPE_OTHER
, GIC_VPE_FDC_MAP
), val
);
725 pr_err("Invalid local IRQ %d\n", intr
);
730 spin_unlock_irqrestore(&gic_lock
, flags
);
735 static int gic_shared_irq_domain_map(struct irq_domain
*d
, unsigned int virq
,
738 int intr
= GIC_HWIRQ_TO_SHARED(hw
);
741 irq_set_chip_and_handler(virq
, &gic_level_irq_controller
,
744 spin_lock_irqsave(&gic_lock
, flags
);
745 gic_map_to_pin(intr
, gic_cpu_pin
);
746 /* Map to VPE 0 by default */
747 gic_map_to_vpe(intr
, 0);
748 set_bit(intr
, pcpu_masks
[0].pcpu_mask
);
749 spin_unlock_irqrestore(&gic_lock
, flags
);
754 static int gic_irq_domain_map(struct irq_domain
*d
, unsigned int virq
,
757 if (GIC_HWIRQ_TO_LOCAL(hw
) < GIC_NUM_LOCAL_INTRS
)
758 return gic_local_irq_domain_map(d
, virq
, hw
);
759 return gic_shared_irq_domain_map(d
, virq
, hw
);
762 static int gic_irq_domain_xlate(struct irq_domain
*d
, struct device_node
*ctrlr
,
763 const u32
*intspec
, unsigned int intsize
,
764 irq_hw_number_t
*out_hwirq
,
765 unsigned int *out_type
)
770 if (intspec
[0] == GIC_SHARED
)
771 *out_hwirq
= GIC_SHARED_TO_HWIRQ(intspec
[1]);
772 else if (intspec
[0] == GIC_LOCAL
)
773 *out_hwirq
= GIC_LOCAL_TO_HWIRQ(intspec
[1]);
776 *out_type
= intspec
[2] & IRQ_TYPE_SENSE_MASK
;
781 static const struct irq_domain_ops gic_irq_domain_ops
= {
782 .map
= gic_irq_domain_map
,
783 .xlate
= gic_irq_domain_xlate
,
786 static void __init
__gic_init(unsigned long gic_base_addr
,
787 unsigned long gic_addrspace_size
,
788 unsigned int cpu_vec
, unsigned int irqbase
,
789 struct device_node
*node
)
791 unsigned int gicconfig
;
793 gic_base
= ioremap_nocache(gic_base_addr
, gic_addrspace_size
);
795 gicconfig
= gic_read(GIC_REG(SHARED
, GIC_SH_CONFIG
));
796 gic_shared_intrs
= (gicconfig
& GIC_SH_CONFIG_NUMINTRS_MSK
) >>
797 GIC_SH_CONFIG_NUMINTRS_SHF
;
798 gic_shared_intrs
= ((gic_shared_intrs
+ 1) * 8);
800 gic_vpes
= (gicconfig
& GIC_SH_CONFIG_NUMVPES_MSK
) >>
801 GIC_SH_CONFIG_NUMVPES_SHF
;
802 gic_vpes
= gic_vpes
+ 1;
805 /* Always use vector 1 in EIC mode */
807 timer_cpu_pin
= gic_cpu_pin
;
808 set_vi_handler(gic_cpu_pin
+ GIC_PIN_TO_VEC_OFFSET
,
811 gic_cpu_pin
= cpu_vec
- GIC_CPU_PIN_OFFSET
;
812 irq_set_chained_handler(MIPS_CPU_IRQ_BASE
+ cpu_vec
,
815 * With the CMP implementation of SMP (deprecated), other CPUs
816 * are started by the bootloader and put into a timer based
817 * waiting poll loop. We must not re-route those CPU's local
818 * timer interrupts as the wait instruction will never finish,
819 * so just handle whatever CPU interrupt it is routed to by
822 * This workaround should be removed when CMP support is
825 if (IS_ENABLED(CONFIG_MIPS_CMP
) &&
826 gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER
)) {
827 timer_cpu_pin
= gic_read32(GIC_REG(VPE_LOCAL
,
828 GIC_VPE_TIMER_MAP
)) &
830 irq_set_chained_handler(MIPS_CPU_IRQ_BASE
+
835 timer_cpu_pin
= gic_cpu_pin
;
839 gic_irq_domain
= irq_domain_add_simple(node
, GIC_NUM_LOCAL_INTRS
+
840 gic_shared_intrs
, irqbase
,
841 &gic_irq_domain_ops
, NULL
);
843 panic("Failed to add GIC IRQ domain");
850 void __init
gic_init(unsigned long gic_base_addr
,
851 unsigned long gic_addrspace_size
,
852 unsigned int cpu_vec
, unsigned int irqbase
)
854 __gic_init(gic_base_addr
, gic_addrspace_size
, cpu_vec
, irqbase
, NULL
);
857 static int __init
gic_of_init(struct device_node
*node
,
858 struct device_node
*parent
)
861 unsigned int cpu_vec
, i
= 0, reserved
= 0;
862 phys_addr_t gic_base
;
865 /* Find the first available CPU vector. */
866 while (!of_property_read_u32_index(node
, "mti,reserved-cpu-vectors",
868 reserved
|= BIT(cpu_vec
);
869 for (cpu_vec
= 2; cpu_vec
< 8; cpu_vec
++) {
870 if (!(reserved
& BIT(cpu_vec
)))
874 pr_err("No CPU vectors available for GIC\n");
878 if (of_address_to_resource(node
, 0, &res
)) {
880 * Probe the CM for the GIC base address if not specified
881 * in the device-tree.
883 if (mips_cm_present()) {
884 gic_base
= read_gcr_gic_base() &
885 ~CM_GCR_GIC_BASE_GICEN_MSK
;
888 pr_err("Failed to get GIC memory range\n");
892 gic_base
= res
.start
;
893 gic_len
= resource_size(&res
);
896 if (mips_cm_present())
897 write_gcr_gic_base(gic_base
| CM_GCR_GIC_BASE_GICEN_MSK
);
900 __gic_init(gic_base
, gic_len
, cpu_vec
, 0, node
);
904 IRQCHIP_DECLARE(mips_gic
, "mti,gic", gic_of_init
);