2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/irq.h>
16 #include <linux/irqchip.h>
17 #include <linux/irqdomain.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_address.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
25 struct mtk_sysirq_chip_data
{
27 void __iomem
*intpol_base
;
30 static int mtk_sysirq_set_type(struct irq_data
*data
, unsigned int type
)
32 irq_hw_number_t hwirq
= data
->hwirq
;
33 struct mtk_sysirq_chip_data
*chip_data
= data
->chip_data
;
34 u32 offset
, reg_index
, value
;
38 offset
= hwirq
& 0x1f;
39 reg_index
= hwirq
>> 5;
41 spin_lock_irqsave(&chip_data
->lock
, flags
);
42 value
= readl_relaxed(chip_data
->intpol_base
+ reg_index
* 4);
43 if (type
== IRQ_TYPE_LEVEL_LOW
|| type
== IRQ_TYPE_EDGE_FALLING
) {
44 if (type
== IRQ_TYPE_LEVEL_LOW
)
45 type
= IRQ_TYPE_LEVEL_HIGH
;
47 type
= IRQ_TYPE_EDGE_RISING
;
48 value
|= (1 << offset
);
50 value
&= ~(1 << offset
);
52 writel(value
, chip_data
->intpol_base
+ reg_index
* 4);
54 data
= data
->parent_data
;
55 ret
= data
->chip
->irq_set_type(data
, type
);
56 spin_unlock_irqrestore(&chip_data
->lock
, flags
);
60 static struct irq_chip mtk_sysirq_chip
= {
62 .irq_mask
= irq_chip_mask_parent
,
63 .irq_unmask
= irq_chip_unmask_parent
,
64 .irq_eoi
= irq_chip_eoi_parent
,
65 .irq_set_type
= mtk_sysirq_set_type
,
66 .irq_retrigger
= irq_chip_retrigger_hierarchy
,
67 .irq_set_affinity
= irq_chip_set_affinity_parent
,
70 static int mtk_sysirq_domain_xlate(struct irq_domain
*d
,
71 struct device_node
*controller
,
72 const u32
*intspec
, unsigned int intsize
,
73 unsigned long *out_hwirq
,
74 unsigned int *out_type
)
79 /* sysirq doesn't support PPI */
83 *out_hwirq
= intspec
[1];
84 *out_type
= intspec
[2] & IRQ_TYPE_SENSE_MASK
;
88 static int mtk_sysirq_domain_alloc(struct irq_domain
*domain
, unsigned int virq
,
89 unsigned int nr_irqs
, void *arg
)
92 irq_hw_number_t hwirq
;
93 struct of_phandle_args
*irq_data
= arg
;
94 struct of_phandle_args gic_data
= *irq_data
;
96 if (irq_data
->args_count
!= 3)
99 /* sysirq doesn't support PPI */
100 if (irq_data
->args
[0])
103 hwirq
= irq_data
->args
[1];
104 for (i
= 0; i
< nr_irqs
; i
++)
105 irq_domain_set_hwirq_and_chip(domain
, virq
+ i
, hwirq
+ i
,
109 gic_data
.np
= domain
->parent
->of_node
;
110 return irq_domain_alloc_irqs_parent(domain
, virq
, nr_irqs
, &gic_data
);
113 static const struct irq_domain_ops sysirq_domain_ops
= {
114 .xlate
= mtk_sysirq_domain_xlate
,
115 .alloc
= mtk_sysirq_domain_alloc
,
116 .free
= irq_domain_free_irqs_common
,
119 static int __init
mtk_sysirq_of_init(struct device_node
*node
,
120 struct device_node
*parent
)
122 struct irq_domain
*domain
, *domain_parent
;
123 struct mtk_sysirq_chip_data
*chip_data
;
124 int ret
, size
, intpol_num
;
127 domain_parent
= irq_find_host(parent
);
128 if (!domain_parent
) {
129 pr_err("mtk_sysirq: interrupt-parent not found\n");
133 ret
= of_address_to_resource(node
, 0, &res
);
137 chip_data
= kzalloc(sizeof(*chip_data
), GFP_KERNEL
);
141 size
= resource_size(&res
);
142 intpol_num
= size
* 8;
143 chip_data
->intpol_base
= ioremap(res
.start
, size
);
144 if (!chip_data
->intpol_base
) {
145 pr_err("mtk_sysirq: unable to map sysirq register\n");
150 domain
= irq_domain_add_hierarchy(domain_parent
, 0, intpol_num
, node
,
151 &sysirq_domain_ops
, chip_data
);
156 spin_lock_init(&chip_data
->lock
);
161 iounmap(chip_data
->intpol_base
);
166 IRQCHIP_DECLARE(mtk_sysirq
, "mediatek,mt6577-sysirq", mtk_sysirq_of_init
);