drivers/irqchip/irq-omap-intc.c

   1 /*
   2  * linux/arch/arm/mach-omap2/irq.c
   3  *
   4  * Interrupt handler for OMAP2 boards.
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License. See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/exception.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_irq.h>
  24
  25 #include "irqchip.h"
  26
  27 /* Define these here for now until we drop all board-files */
  28 #define OMAP24XX_IC_BASE        0x480fe000
  29 #define OMAP34XX_IC_BASE        0x48200000
  30
  31 /* selected INTC register offsets */
  32
  33 #define INTC_REVISION           0x0000
  34 #define INTC_SYSCONFIG          0x0010
  35 #define INTC_SYSSTATUS          0x0014
  36 #define INTC_SIR                0x0040
  37 #define INTC_CONTROL            0x0048
  38 #define INTC_PROTECTION         0x004C
  39 #define INTC_IDLE               0x0050
  40 #define INTC_THRESHOLD          0x0068
  41 #define INTC_MIR0               0x0084
  42 #define INTC_MIR_CLEAR0         0x0088
  43 #define INTC_MIR_SET0           0x008c
  44 #define INTC_PENDING_IRQ0       0x0098
  45 #define INTC_PENDING_IRQ1       0x00b8
  46 #define INTC_PENDING_IRQ2       0x00d8
  47 #define INTC_PENDING_IRQ3       0x00f8
  48 #define INTC_ILR0               0x0100
  49
  50 #define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
  51 #define INTCPS_NR_ILR_REGS      128
  52 #define INTCPS_NR_MIR_REGS      3
  53
  54 /*
  55  * OMAP2 has a number of different interrupt controllers, each interrupt
  56  * controller is identified as its own "bank". Register definitions are
  57  * fairly consistent for each bank, but not all registers are implemented
  58  * for each bank.. when in doubt, consult the TRM.
  59  */
  60
  61 /* Structure to save interrupt controller context */
  62 struct omap_intc_regs {
  63         u32 sysconfig;
  64         u32 protection;
  65         u32 idle;
  66         u32 threshold;
  67         u32 ilr[INTCPS_NR_ILR_REGS];
  68         u32 mir[INTCPS_NR_MIR_REGS];
  69 };
  70 static struct omap_intc_regs intc_context;
  71
  72 static struct irq_domain *domain;
  73 static void __iomem *omap_irq_base;
  74 static int omap_nr_pending = 3;
  75 static int omap_nr_irqs = 96;
  76
  77 /* INTC bank register get/set */
  78 static void intc_writel(u32 reg, u32 val)
  79 {
  80         writel_relaxed(val, omap_irq_base + reg);
  81 }
  82
  83 static u32 intc_readl(u32 reg)
  84 {
  85         return readl_relaxed(omap_irq_base + reg);
  86 }
  87
  88 void omap_intc_save_context(void)
  89 {
  90         int i;
  91
  92         intc_context.sysconfig =
  93                 intc_readl(INTC_SYSCONFIG);
  94         intc_context.protection =
  95                 intc_readl(INTC_PROTECTION);
  96         intc_context.idle =
  97                 intc_readl(INTC_IDLE);
  98         intc_context.threshold =
  99                 intc_readl(INTC_THRESHOLD);
 100
 101         for (i = 0; i < omap_nr_irqs; i++)
 102                 intc_context.ilr[i] =
 103                         intc_readl((INTC_ILR0 + 0x4 * i));
 104         for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
 105                 intc_context.mir[i] =
 106                         intc_readl(INTC_MIR0 + (0x20 * i));
 107 }
 108
 109 void omap_intc_restore_context(void)
 110 {
 111         int i;
 112
 113         intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
 114         intc_writel(INTC_PROTECTION, intc_context.protection);
 115         intc_writel(INTC_IDLE, intc_context.idle);
 116         intc_writel(INTC_THRESHOLD, intc_context.threshold);
 117
 118         for (i = 0; i < omap_nr_irqs; i++)
 119                 intc_writel(INTC_ILR0 + 0x4 * i,
 120                                 intc_context.ilr[i]);
 121
 122         for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
 123                 intc_writel(INTC_MIR0 + 0x20 * i,
 124                         intc_context.mir[i]);
 125         /* MIRs are saved and restore with other PRCM registers */
 126 }
 127
 128 void omap3_intc_prepare_idle(void)
 129 {
 130         /*
 131          * Disable autoidle as it can stall interrupt controller,
 132          * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
 133          */
 134         intc_writel(INTC_SYSCONFIG, 0);
 135 }
 136
 137 void omap3_intc_resume_idle(void)
 138 {
 139         /* Re-enable autoidle */
 140         intc_writel(INTC_SYSCONFIG, 1);
 141 }
 142
 143 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
 144 static void omap_ack_irq(struct irq_data *d)
 145 {
 146         intc_writel(INTC_CONTROL, 0x1);
 147 }
 148
 149 static void omap_mask_ack_irq(struct irq_data *d)
 150 {
 151         irq_gc_mask_disable_reg(d);
 152         omap_ack_irq(d);
 153 }
 154
 155 static void __init omap_irq_soft_reset(void)
 156 {
 157         unsigned long tmp;
 158
 159         tmp = intc_readl(INTC_REVISION) & 0xff;
 160
 161         pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
 162                 omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
 163
 164         tmp = intc_readl(INTC_SYSCONFIG);
 165         tmp |= 1 << 1;  /* soft reset */
 166         intc_writel(INTC_SYSCONFIG, tmp);
 167
 168         while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
 169                 /* Wait for reset to complete */;
 170
 171         /* Enable autoidle */
 172         intc_writel(INTC_SYSCONFIG, 1 << 0);
 173 }
 174
 175 int omap_irq_pending(void)
 176 {
 177         int i;
 178
 179         for (i = 0; i < omap_nr_pending; i++)
 180                 if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)))
 181                         return 1;
 182         return 0;
 183 }
 184
 185 void omap3_intc_suspend(void)
 186 {
 187         /* A pending interrupt would prevent OMAP from entering suspend */
 188         omap_ack_irq(NULL);
 189 }
 190
 191 static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
 192 {
 193         int ret;
 194         int i;
 195
 196         ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
 197                         handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
 198                         IRQ_LEVEL, 0);
 199         if (ret) {
 200                 pr_warn("Failed to allocate irq chips\n");
 201                 return ret;
 202         }
 203
 204         for (i = 0; i < omap_nr_pending; i++) {
 205                 struct irq_chip_generic *gc;
 206                 struct irq_chip_type *ct;
 207
 208                 gc = irq_get_domain_generic_chip(d, 32 * i);
 209                 gc->reg_base = base;
 210                 ct = gc->chip_types;
 211
 212                 ct->type = IRQ_TYPE_LEVEL_MASK;
 213                 ct->handler = handle_level_irq;
 214
 215                 ct->chip.irq_ack = omap_mask_ack_irq;
 216                 ct->chip.irq_mask = irq_gc_mask_disable_reg;
 217                 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 218
 219                 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
 220
 221                 ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
 222                 ct->regs.disable = INTC_MIR_SET0 + 32 * i;
 223         }
 224
 225         return 0;
 226 }
 227
 228 static void __init omap_alloc_gc_legacy(void __iomem *base,
 229                 unsigned int irq_start, unsigned int num)
 230 {
 231         struct irq_chip_generic *gc;
 232         struct irq_chip_type *ct;
 233
 234         gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
 235                         handle_level_irq);
 236         ct = gc->chip_types;
 237         ct->chip.irq_ack = omap_mask_ack_irq;
 238         ct->chip.irq_mask = irq_gc_mask_disable_reg;
 239         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 240         ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
 241
 242         ct->regs.enable = INTC_MIR_CLEAR0;
 243         ct->regs.disable = INTC_MIR_SET0;
 244         irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
 245                         IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 246 }
 247
 248 static int __init omap_init_irq_of(struct device_node *node)
 249 {
 250         int ret;
 251
 252         omap_irq_base = of_iomap(node, 0);
 253         if (WARN_ON(!omap_irq_base))
 254                 return -ENOMEM;
 255
 256         domain = irq_domain_add_linear(node, omap_nr_irqs,
 257                         &irq_generic_chip_ops, NULL);
 258
 259         omap_irq_soft_reset();
 260
 261         ret = omap_alloc_gc_of(domain, omap_irq_base);
 262         if (ret < 0)
 263                 irq_domain_remove(domain);
 264
 265         return ret;
 266 }
 267
 268 static int __init omap_init_irq_legacy(u32 base)
 269 {
 270         int j, irq_base;
 271
 272         omap_irq_base = ioremap(base, SZ_4K);
 273         if (WARN_ON(!omap_irq_base))
 274                 return -ENOMEM;
 275
 276         irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
 277         if (irq_base < 0) {
 278                 pr_warn("Couldn't allocate IRQ numbers\n");
 279                 irq_base = 0;
 280         }
 281
 282         domain = irq_domain_add_legacy(NULL, omap_nr_irqs, irq_base, 0,
 283                         &irq_domain_simple_ops, NULL);
 284
 285         omap_irq_soft_reset();
 286
 287         for (j = 0; j < omap_nr_irqs; j += 32)
 288                 omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);
 289
 290         return 0;
 291 }
 292
 293 static int __init omap_init_irq(u32 base, struct device_node *node)
 294 {
 295         if (node)
 296                 return omap_init_irq_of(node);
 297         else
 298                 return omap_init_irq_legacy(base);
 299 }
 300
 301 static asmlinkage void __exception_irq_entry
 302 omap_intc_handle_irq(struct pt_regs *regs)
 303 {
 304         u32 irqnr = 0;
 305         int handled_irq = 0;
 306         int i;
 307
 308         do {
 309                 for (i = 0; i < omap_nr_pending; i++) {
 310                         irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
 311                         if (irqnr)
 312                                 goto out;
 313                 }
 314
 315 out:
 316                 if (!irqnr)
 317                         break;
 318
 319                 irqnr = intc_readl(INTC_SIR);
 320                 irqnr &= ACTIVEIRQ_MASK;
 321
 322                 if (irqnr) {
 323                         irqnr = irq_find_mapping(domain, irqnr);
 324                         handle_IRQ(irqnr, regs);
 325                         handled_irq = 1;
 326                 }
 327         } while (irqnr);
 328
 329         /* If an irq is masked or deasserted while active, we will
 330          * keep ending up here with no irq handled. So remove it from
 331          * the INTC with an ack.*/
 332         if (!handled_irq)
 333                 omap_ack_irq(NULL);
 334 }
 335
 336 void __init omap2_init_irq(void)
 337 {
 338         omap_nr_irqs = 96;
 339         omap_nr_pending = 3;
 340         omap_init_irq(OMAP24XX_IC_BASE, NULL);
 341         set_handle_irq(omap_intc_handle_irq);
 342 }
 343
 344 void __init omap3_init_irq(void)
 345 {
 346         omap_nr_irqs = 96;
 347         omap_nr_pending = 3;
 348         omap_init_irq(OMAP34XX_IC_BASE, NULL);
 349         set_handle_irq(omap_intc_handle_irq);
 350 }
 351
 352 void __init ti81xx_init_irq(void)
 353 {
 354         omap_nr_irqs = 96;
 355         omap_nr_pending = 4;
 356         omap_init_irq(OMAP34XX_IC_BASE, NULL);
 357         set_handle_irq(omap_intc_handle_irq);
 358 }
 359
 360 static int __init intc_of_init(struct device_node *node,
 361                              struct device_node *parent)
 362 {
 363         struct resource res;
 364         int ret;
 365
 366         omap_nr_pending = 3;
 367         omap_nr_irqs = 96;
 368
 369         if (WARN_ON(!node))
 370                 return -ENODEV;
 371
 372         if (of_address_to_resource(node, 0, &res)) {
 373                 WARN(1, "unable to get intc registers\n");
 374                 return -EINVAL;
 375         }
 376
 377         if (of_device_is_compatible(node, "ti,am33xx-intc")) {
 378                 omap_nr_irqs = 128;
 379                 omap_nr_pending = 4;
 380         }
 381
 382         ret = omap_init_irq(-1, of_node_get(node));
 383         if (ret < 0)
 384                 return ret;
 385
 386         set_handle_irq(omap_intc_handle_irq);
 387
 388         return 0;
 389 }
 390
 391 IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
 392 IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
 393 IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);