drivers/irqchip/irq-renesas-irqc.c

   1 /*
   2  * Renesas IRQC Driver
   3  *
   4  *  Copyright (C) 2013 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/clk.h>
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/ioport.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/irqdomain.h>
  29 #include <linux/err.h>
  30 #include <linux/slab.h>
  31 #include <linux/module.h>
  32 #include <linux/platform_data/irq-renesas-irqc.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #define IRQC_IRQ_MAX    32      /* maximum 32 interrupts per driver instance */
  36
  37 #define IRQC_REQ_STS    0x00    /* Interrupt Request Status Register */
  38 #define IRQC_EN_STS     0x04    /* Interrupt Enable Status Register */
  39 #define IRQC_EN_SET     0x08    /* Interrupt Enable Set Register */
  40 #define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
  41                                 /* SYS-CPU vs. RT-CPU */
  42 #define DETECT_STATUS   0x100   /* IRQn Detect Status Register */
  43 #define MONITOR         0x104   /* IRQn Signal Level Monitor Register */
  44 #define HLVL_STS        0x108   /* IRQn High Level Detect Status Register */
  45 #define LLVL_STS        0x10c   /* IRQn Low Level Detect Status Register */
  46 #define S_R_EDGE_STS    0x110   /* IRQn Sync Rising Edge Detect Status Reg. */
  47 #define S_F_EDGE_STS    0x114   /* IRQn Sync Falling Edge Detect Status Reg. */
  48 #define A_R_EDGE_STS    0x118   /* IRQn Async Rising Edge Detect Status Reg. */
  49 #define A_F_EDGE_STS    0x11c   /* IRQn Async Falling Edge Detect Status Reg. */
  50 #define CHTEN_STS       0x120   /* Chattering Reduction Status Register */
  51 #define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
  52                                 /* IRQn Configuration Register */
  53
  54 struct irqc_irq {
  55         int hw_irq;
  56         int requested_irq;
  57         int domain_irq;
  58         struct irqc_priv *p;
  59 };
  60
  61 struct irqc_priv {
  62         void __iomem *iomem;
  63         void __iomem *cpu_int_base;
  64         struct irqc_irq irq[IRQC_IRQ_MAX];
  65         struct renesas_irqc_config config;
  66         unsigned int number_of_irqs;
  67         struct platform_device *pdev;
  68         struct irq_chip irq_chip;
  69         struct irq_domain *irq_domain;
  70         struct clk *clk;
  71 };
  72
  73 static void irqc_dbg(struct irqc_irq *i, char *str)
  74 {
  75         dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
  76                 str, i->requested_irq, i->hw_irq, i->domain_irq);
  77 }
  78
  79 static void irqc_irq_enable(struct irq_data *d)
  80 {
  81         struct irqc_priv *p = irq_data_get_irq_chip_data(d);
  82         int hw_irq = irqd_to_hwirq(d);
  83
  84         irqc_dbg(&p->irq[hw_irq], "enable");
  85         iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET);
  86 }
  87
  88 static void irqc_irq_disable(struct irq_data *d)
  89 {
  90         struct irqc_priv *p = irq_data_get_irq_chip_data(d);
  91         int hw_irq = irqd_to_hwirq(d);
  92
  93         irqc_dbg(&p->irq[hw_irq], "disable");
  94         iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
  95 }
  96
  97 static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
  98         [IRQ_TYPE_LEVEL_LOW]    = 0x01,
  99         [IRQ_TYPE_LEVEL_HIGH]   = 0x02,
 100         [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */
 101         [IRQ_TYPE_EDGE_RISING]  = 0x08, /* Synchronous */
 102         [IRQ_TYPE_EDGE_BOTH]    = 0x0c, /* Synchronous */
 103 };
 104
 105 static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
 106 {
 107         struct irqc_priv *p = irq_data_get_irq_chip_data(d);
 108         int hw_irq = irqd_to_hwirq(d);
 109         unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
 110         u32 tmp;
 111
 112         irqc_dbg(&p->irq[hw_irq], "sense");
 113
 114         if (!value)
 115                 return -EINVAL;
 116
 117         tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
 118         tmp &= ~0x3f;
 119         tmp |= value;
 120         iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
 121         return 0;
 122 }
 123
 124 static int irqc_irq_set_wake(struct irq_data *d, unsigned int on)
 125 {
 126         struct irqc_priv *p = irq_data_get_irq_chip_data(d);
 127
 128         if (!p->clk)
 129                 return 0;
 130
 131         if (on)
 132                 clk_enable(p->clk);
 133         else
 134                 clk_disable(p->clk);
 135
 136         return 0;
 137 }
 138
 139 static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
 140 {
 141         struct irqc_irq *i = dev_id;
 142         struct irqc_priv *p = i->p;
 143         u32 bit = BIT(i->hw_irq);
 144
 145         irqc_dbg(i, "demux1");
 146
 147         if (ioread32(p->iomem + DETECT_STATUS) & bit) {
 148                 iowrite32(bit, p->iomem + DETECT_STATUS);
 149                 irqc_dbg(i, "demux2");
 150                 generic_handle_irq(i->domain_irq);
 151                 return IRQ_HANDLED;
 152         }
 153         return IRQ_NONE;
 154 }
 155
 156 static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
 157                                irq_hw_number_t hw)
 158 {
 159         struct irqc_priv *p = h->host_data;
 160
 161         p->irq[hw].domain_irq = virq;
 162         p->irq[hw].hw_irq = hw;
 163
 164         irqc_dbg(&p->irq[hw], "map");
 165         irq_set_chip_data(virq, h->host_data);
 166         irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
 167         set_irq_flags(virq, IRQF_VALID); /* kill me now */
 168         return 0;
 169 }
 170
 171 static struct irq_domain_ops irqc_irq_domain_ops = {
 172         .map    = irqc_irq_domain_map,
 173         .xlate  = irq_domain_xlate_twocell,
 174 };
 175
 176 static int irqc_probe(struct platform_device *pdev)
 177 {
 178         struct renesas_irqc_config *pdata = pdev->dev.platform_data;
 179         struct irqc_priv *p;
 180         struct resource *io;
 181         struct resource *irq;
 182         struct irq_chip *irq_chip;
 183         const char *name = dev_name(&pdev->dev);
 184         int ret;
 185         int k;
 186
 187         p = kzalloc(sizeof(*p), GFP_KERNEL);
 188         if (!p) {
 189                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 190                 ret = -ENOMEM;
 191                 goto err0;
 192         }
 193
 194         /* deal with driver instance configuration */
 195         if (pdata)
 196                 memcpy(&p->config, pdata, sizeof(*pdata));
 197
 198         p->pdev = pdev;
 199         platform_set_drvdata(pdev, p);
 200
 201         p->clk = devm_clk_get(&pdev->dev, NULL);
 202         if (IS_ERR(p->clk)) {
 203                 dev_warn(&pdev->dev, "unable to get clock\n");
 204                 p->clk = NULL;
 205         }
 206
 207         pm_runtime_enable(&pdev->dev);
 208         pm_runtime_get_sync(&pdev->dev);
 209
 210         /* get hold of manadatory IOMEM */
 211         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 212         if (!io) {
 213                 dev_err(&pdev->dev, "not enough IOMEM resources\n");
 214                 ret = -EINVAL;
 215                 goto err1;
 216         }
 217
 218         /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
 219         for (k = 0; k < IRQC_IRQ_MAX; k++) {
 220                 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
 221                 if (!irq)
 222                         break;
 223
 224                 p->irq[k].p = p;
 225                 p->irq[k].requested_irq = irq->start;
 226         }
 227
 228         p->number_of_irqs = k;
 229         if (p->number_of_irqs < 1) {
 230                 dev_err(&pdev->dev, "not enough IRQ resources\n");
 231                 ret = -EINVAL;
 232                 goto err1;
 233         }
 234
 235         /* ioremap IOMEM and setup read/write callbacks */
 236         p->iomem = ioremap_nocache(io->start, resource_size(io));
 237         if (!p->iomem) {
 238                 dev_err(&pdev->dev, "failed to remap IOMEM\n");
 239                 ret = -ENXIO;
 240                 goto err2;
 241         }
 242
 243         p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
 244
 245         irq_chip = &p->irq_chip;
 246         irq_chip->name = name;
 247         irq_chip->irq_mask = irqc_irq_disable;
 248         irq_chip->irq_unmask = irqc_irq_enable;
 249         irq_chip->irq_set_type = irqc_irq_set_type;
 250         irq_chip->irq_set_wake = irqc_irq_set_wake;
 251         irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
 252
 253         p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
 254                                               p->number_of_irqs,
 255                                               p->config.irq_base,
 256                                               &irqc_irq_domain_ops, p);
 257         if (!p->irq_domain) {
 258                 ret = -ENXIO;
 259                 dev_err(&pdev->dev, "cannot initialize irq domain\n");
 260                 goto err2;
 261         }
 262
 263         /* request interrupts one by one */
 264         for (k = 0; k < p->number_of_irqs; k++) {
 265                 if (request_irq(p->irq[k].requested_irq, irqc_irq_handler,
 266                                 0, name, &p->irq[k])) {
 267                         dev_err(&pdev->dev, "failed to request IRQ\n");
 268                         ret = -ENOENT;
 269                         goto err3;
 270                 }
 271         }
 272
 273         dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
 274
 275         /* warn in case of mismatch if irq base is specified */
 276         if (p->config.irq_base) {
 277                 if (p->config.irq_base != p->irq[0].domain_irq)
 278                         dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
 279                                  p->config.irq_base, p->irq[0].domain_irq);
 280         }
 281
 282         return 0;
 283 err3:
 284         while (--k >= 0)
 285                 free_irq(p->irq[k].requested_irq, &p->irq[k]);
 286
 287         irq_domain_remove(p->irq_domain);
 288 err2:
 289         iounmap(p->iomem);
 290 err1:
 291         pm_runtime_put(&pdev->dev);
 292         pm_runtime_disable(&pdev->dev);
 293         kfree(p);
 294 err0:
 295         return ret;
 296 }
 297
 298 static int irqc_remove(struct platform_device *pdev)
 299 {
 300         struct irqc_priv *p = platform_get_drvdata(pdev);
 301         int k;
 302
 303         for (k = 0; k < p->number_of_irqs; k++)
 304                 free_irq(p->irq[k].requested_irq, &p->irq[k]);
 305
 306         irq_domain_remove(p->irq_domain);
 307         iounmap(p->iomem);
 308         pm_runtime_put(&pdev->dev);
 309         pm_runtime_disable(&pdev->dev);
 310         kfree(p);
 311         return 0;
 312 }
 313
 314 static const struct of_device_id irqc_dt_ids[] = {
 315         { .compatible = "renesas,irqc", },
 316         {},
 317 };
 318 MODULE_DEVICE_TABLE(of, irqc_dt_ids);
 319
 320 static struct platform_driver irqc_device_driver = {
 321         .probe          = irqc_probe,
 322         .remove         = irqc_remove,
 323         .driver         = {
 324                 .name   = "renesas_irqc",
 325                 .of_match_table = irqc_dt_ids,
 326         }
 327 };
 328
 329 static int __init irqc_init(void)
 330 {
 331         return platform_driver_register(&irqc_device_driver);
 332 }
 333 postcore_initcall(irqc_init);
 334
 335 static void __exit irqc_exit(void)
 336 {
 337         platform_driver_unregister(&irqc_device_driver);
 338 }
 339 module_exit(irqc_exit);
 340
 341 MODULE_AUTHOR("Magnus Damm");
 342 MODULE_DESCRIPTION("Renesas IRQC Driver");
 343 MODULE_LICENSE("GPL v2");