2 * Support for Versatile FPGA-based IRQ controllers
4 #include <linux/bitops.h>
7 #include <linux/irqchip.h>
8 #include <linux/irqchip/versatile-fpga.h>
9 #include <linux/irqdomain.h>
10 #include <linux/module.h>
12 #include <linux/of_address.h>
13 #include <linux/of_irq.h>
15 #include <asm/exception.h>
16 #include <asm/mach/irq.h>
18 #define IRQ_STATUS 0x00
19 #define IRQ_RAW_STATUS 0x04
20 #define IRQ_ENABLE_SET 0x08
21 #define IRQ_ENABLE_CLEAR 0x0c
22 #define INT_SOFT_SET 0x10
23 #define INT_SOFT_CLEAR 0x14
24 #define FIQ_STATUS 0x20
25 #define FIQ_RAW_STATUS 0x24
26 #define FIQ_ENABLE 0x28
27 #define FIQ_ENABLE_SET 0x28
28 #define FIQ_ENABLE_CLEAR 0x2C
30 #define PIC_ENABLES 0x20 /* set interrupt pass through bits */
33 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
34 * @base: memory offset in virtual memory
35 * @chip: chip container for this instance
36 * @domain: IRQ domain for this instance
37 * @valid: mask for valid IRQs on this controller
38 * @used_irqs: number of active IRQs on this controller
40 struct fpga_irq_data
{
44 struct irq_domain
*domain
;
48 /* we cannot allocate memory when the controllers are initially registered */
49 static struct fpga_irq_data fpga_irq_devices
[CONFIG_VERSATILE_FPGA_IRQ_NR
];
50 static int fpga_irq_id
;
52 static void fpga_irq_mask(struct irq_data
*d
)
54 struct fpga_irq_data
*f
= irq_data_get_irq_chip_data(d
);
55 u32 mask
= 1 << d
->hwirq
;
57 writel(mask
, f
->base
+ IRQ_ENABLE_CLEAR
);
60 static void fpga_irq_unmask(struct irq_data
*d
)
62 struct fpga_irq_data
*f
= irq_data_get_irq_chip_data(d
);
63 u32 mask
= 1 << d
->hwirq
;
65 writel(mask
, f
->base
+ IRQ_ENABLE_SET
);
68 static void fpga_irq_handle(unsigned int irq
, struct irq_desc
*desc
)
70 struct fpga_irq_data
*f
= irq_desc_get_handler_data(desc
);
71 u32 status
= readl(f
->base
+ IRQ_STATUS
);
74 do_bad_IRQ(irq
, desc
);
79 irq
= ffs(status
) - 1;
80 status
&= ~(1 << irq
);
81 generic_handle_irq(irq_find_mapping(f
->domain
, irq
));
86 * Handle each interrupt in a single FPGA IRQ controller. Returns non-zero
87 * if we've handled at least one interrupt. This does a single read of the
88 * status register and handles all interrupts in order from LSB first.
90 static int handle_one_fpga(struct fpga_irq_data
*f
, struct pt_regs
*regs
)
96 while ((status
= readl(f
->base
+ IRQ_STATUS
))) {
97 irq
= ffs(status
) - 1;
98 handle_domain_irq(f
->domain
, irq
, regs
);
106 * Keep iterating over all registered FPGA IRQ controllers until there are
107 * no pending interrupts.
109 asmlinkage
void __exception_irq_entry
fpga_handle_irq(struct pt_regs
*regs
)
114 for (i
= 0, handled
= 0; i
< fpga_irq_id
; ++i
)
115 handled
|= handle_one_fpga(&fpga_irq_devices
[i
], regs
);
119 static int fpga_irqdomain_map(struct irq_domain
*d
, unsigned int irq
,
120 irq_hw_number_t hwirq
)
122 struct fpga_irq_data
*f
= d
->host_data
;
124 /* Skip invalid IRQs, only register handlers for the real ones */
125 if (!(f
->valid
& BIT(hwirq
)))
127 irq_set_chip_data(irq
, f
);
128 irq_set_chip_and_handler(irq
, &f
->chip
,
130 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
134 static const struct irq_domain_ops fpga_irqdomain_ops
= {
135 .map
= fpga_irqdomain_map
,
136 .xlate
= irq_domain_xlate_onetwocell
,
139 void __init
fpga_irq_init(void __iomem
*base
, const char *name
, int irq_start
,
140 int parent_irq
, u32 valid
, struct device_node
*node
)
142 struct fpga_irq_data
*f
;
145 if (fpga_irq_id
>= ARRAY_SIZE(fpga_irq_devices
)) {
146 pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__
);
149 f
= &fpga_irq_devices
[fpga_irq_id
];
152 f
->chip
.irq_ack
= fpga_irq_mask
;
153 f
->chip
.irq_mask
= fpga_irq_mask
;
154 f
->chip
.irq_unmask
= fpga_irq_unmask
;
157 if (parent_irq
!= -1) {
158 irq_set_handler_data(parent_irq
, f
);
159 irq_set_chained_handler(parent_irq
, fpga_irq_handle
);
162 /* This will also allocate irq descriptors */
163 f
->domain
= irq_domain_add_simple(node
, fls(valid
), irq_start
,
164 &fpga_irqdomain_ops
, f
);
166 /* This will allocate all valid descriptors in the linear case */
167 for (i
= 0; i
< fls(valid
); i
++)
168 if (valid
& BIT(i
)) {
170 irq_create_mapping(f
->domain
, i
);
174 pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
175 fpga_irq_id
, name
, base
, f
->used_irqs
);
176 if (parent_irq
!= -1)
177 pr_cont(", parent IRQ: %d\n", parent_irq
);
185 int __init
fpga_irq_of_init(struct device_node
*node
,
186 struct device_node
*parent
)
196 base
= of_iomap(node
, 0);
197 WARN(!base
, "unable to map fpga irq registers\n");
199 if (of_property_read_u32(node
, "clear-mask", &clear_mask
))
202 if (of_property_read_u32(node
, "valid-mask", &valid_mask
))
205 /* Some chips are cascaded from a parent IRQ */
206 parent_irq
= irq_of_parse_and_map(node
, 0);
208 set_handle_irq(fpga_handle_irq
);
212 fpga_irq_init(base
, node
->name
, 0, parent_irq
, valid_mask
, node
);
214 writel(clear_mask
, base
+ IRQ_ENABLE_CLEAR
);
215 writel(clear_mask
, base
+ FIQ_ENABLE_CLEAR
);
218 * On Versatile AB/PB, some secondary interrupts have a direct
219 * pass-thru to the primary controller for IRQs 20 and 22-31 which need
220 * to be enabled. See section 3.10 of the Versatile AB user guide.
222 if (of_device_is_compatible(node
, "arm,versatile-sic"))
223 writel(0xffd00000, base
+ PIC_ENABLES
);
227 IRQCHIP_DECLARE(arm_fpga
, "arm,versatile-fpga-irq", fpga_irq_of_init
);
228 IRQCHIP_DECLARE(arm_fpga_sic
, "arm,versatile-sic", fpga_irq_of_init
);